diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
| commit | fce3433b2eb764d9519ffbc4c7e95049f3200ba3 (patch) | |
| tree | 26e90c5190c4751532683d1f4b5bf6094e6ba4b7 /tests/quick/se | |
| parent | c4898b15bcf5458e35f17cb0c3b4185cec0081aa (diff) | |
| download | gem5-fce3433b2eb764d9519ffbc4c7e95049f3200ba3.tar.xz | |
stats: Update stats for regressions using SimpleDDR3
This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
Diffstat (limited to 'tests/quick/se')
15 files changed, 6881 insertions, 6875 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index b21e4d084..9e62381ba 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18737000 # Number of ticks simulated -final_tick 18737000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19476000 # Number of ticks simulated +final_tick 19476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42684 # Simulator instruction rate (inst/s) -host_op_rate 42679 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 125129111 # Simulator tick rate (ticks/s) -host_mem_usage 269636 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 78389 # Simulator instruction rate (inst/s) +host_op_rate 78368 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 238789679 # Simulator tick rate (ticks/s) +host_mem_usage 223680 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19200 # Nu system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 468 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1024710466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 573837861 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1598548327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1024710466 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1024710466 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1024710466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 573837861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1598548327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 985828712 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 552064079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1537892791 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 985828712 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 985828712 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 985828712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 552064079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1537892791 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 469 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady @@ -37,21 +37,21 @@ system.physmem.bytesConsumedWr 0 # by system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 25 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 69 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 33 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 66 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 45 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 43 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 49 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 41 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 3 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 47 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 18722500 # Total gap between requests +system.physmem.totGap 19461500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,9 +98,9 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 138 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1862969 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11648969 # Sum of mem lat for all requests -system.physmem.totBusLat 1876000 # Total cycles spent in databus access -system.physmem.totBankLat 7910000 # Total cycles spent in bank access -system.physmem.avgQLat 3972.22 # Average queueing delay per request -system.physmem.avgBankLat 16865.67 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24837.89 # Average memory access latency -system.physmem.avgRdBW 1598.55 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2628216 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13374466 # Sum of mem lat for all requests +system.physmem.totBusLat 2345000 # Total cycles spent in databus access +system.physmem.totBankLat 8401250 # Total cycles spent in bank access +system.physmem.avgQLat 5603.87 # Average queueing delay per request +system.physmem.avgBankLat 17913.11 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 28516.99 # Average memory access latency +system.physmem.avgRdBW 1537.89 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1598.55 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1537.89 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.99 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.62 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 12.01 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.69 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 401 # Number of row buffer hits during reads +system.physmem.readRowHits 377 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.50 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.38 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 39920.04 # Average gap between requests +system.physmem.avgGap 41495.74 # Average gap between requests system.cpu.branchPred.lookups 1632 # Number of BP lookups system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect @@ -202,14 +202,14 @@ system.cpu.dtb.read_hits 1183 # DT system.cpu.dtb.read_misses 7 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 1190 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_hits 866 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2048 # DTB hits +system.cpu.dtb.write_accesses 869 # DTB write accesses +system.cpu.dtb.data_hits 2049 # DTB hits system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2058 # DTB accesses +system.cpu.dtb.data_accesses 2059 # DTB accesses system.cpu.itb.fetch_hits 915 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv @@ -227,18 +227,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 37475 # number of cpu cycles simulated +system.cpu.numCycles 38953 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 1130 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5202 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 5201 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4567 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9769 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9768 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 2948 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 2949 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 2152 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 325 # Number of Branches Incorrectly Predicted As Not Taken). @@ -249,12 +249,12 @@ system.cpu.execution_unit.executions 4448 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11520 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11544 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 498 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30101 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7374 # Number of cycles cpu stages are processed. -system.cpu.activity 19.677118 # Percentage of cycles cpu is active +system.cpu.timesIdled 503 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 31578 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7375 # Number of cycles cpu stages are processed. +system.cpu.activity 18.933073 # Percentage of cycles cpu is active system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed @@ -266,72 +266,72 @@ system.cpu.committedInsts 6390 # Nu system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) -system.cpu.cpi 5.864632 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.095931 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 5.864632 # CPI: Total CPI of All Threads -system.cpu.ipc 0.170514 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.095931 # CPI: Total CPI of All Threads +system.cpu.ipc 0.164044 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.170514 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 32551 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.164044 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 34029 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 13.139426 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 33582 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 12.640875 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 35060 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 10.388259 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33313 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 4162 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 11.106071 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 36170 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 1305 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.482322 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 32961 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 4514 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 12.045364 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.utilization 9.994095 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 34792 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4161 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 10.682104 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 37647 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 1306 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 3.352758 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 34441 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4512 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 11.583190 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 143.133594 # Cycle average of tags in use -system.cpu.icache.total_refs 561 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 142.957443 # Cycle average of tags in use +system.cpu.icache.total_refs 560 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.863787 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.860465 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 143.133594 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.069889 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.069889 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 561 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 561 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 561 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 561 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 561 # number of overall hits -system.cpu.icache.overall_hits::total 561 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 354 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 354 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 354 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 354 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 354 # number of overall misses -system.cpu.icache.overall_misses::total 354 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17402500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17402500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17402500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17402500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17402500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17402500 # number of overall miss cycles +system.cpu.icache.occ_blocks::cpu.inst 142.957443 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.069803 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.069803 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 560 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 560 # number of overall hits +system.cpu.icache.overall_hits::total 560 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 355 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 355 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 355 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses +system.cpu.icache.overall_misses::total 355 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18504000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18504000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18504000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18504000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18504000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18504000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 915 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 915 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 915 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.386885 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.386885 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.386885 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.386885 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.386885 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.386885 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49159.604520 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49159.604520 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49159.604520 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49159.604520 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49159.604520 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49159.604520 # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.387978 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.387978 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.387978 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52123.943662 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52123.943662 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52123.943662 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52123.943662 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52123.943662 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52123.943662 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -340,48 +340,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 48 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 52 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 52 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 52 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 53 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 53 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 53 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 53 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14751500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14751500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14751500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14751500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14751500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14751500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15862500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15862500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15862500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15862500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15862500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15862500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48846.026490 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48846.026490 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48846.026490 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48846.026490 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48846.026490 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48846.026490 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52524.834437 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52524.834437 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52524.834437 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52524.834437 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52524.834437 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52524.834437 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 200.167240 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 199.973805 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 143.234891 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.932349 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004371 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 143.049582 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.924223 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004366 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001737 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006109 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006103 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -399,17 +399,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14433000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4976500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19409500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3596000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3596000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14433000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8572500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23005500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14433000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8572500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23005500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15544000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5344500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 20888500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3558500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3558500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15544000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8903000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24447000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15544000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8903000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24447000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -432,17 +432,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47950.166113 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52384.210526 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49013.888889 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49260.273973 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49260.273973 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47950.166113 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51026.785714 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 49052.238806 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47950.166113 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51026.785714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 49052.238806 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51641.196013 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56257.894737 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52748.737374 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48746.575342 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48746.575342 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51641.196013 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52994.047619 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52125.799574 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51641.196013 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52994.047619 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52125.799574 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -462,17 +462,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10648000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3792120 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14440120 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2674096 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2674096 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10648000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6466216 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17114216 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10648000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6466216 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17114216 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11816499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4177366 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15993865 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2666348 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2666348 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11816499 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6843714 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18660213 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11816499 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6843714 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18660213 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -484,27 +484,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35375.415282 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39917.052632 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36464.949495 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36631.452055 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36631.452055 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35375.415282 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38489.380952 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36490.865672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35375.415282 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38489.380952 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36490.865672 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39257.471761 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43972.273684 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40388.547980 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36525.315068 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36525.315068 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39257.471761 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40736.392857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39787.234542 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39257.471761 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40736.392857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39787.234542 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 104.225653 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 104.433203 # Cycle average of tags in use system.cpu.dcache.total_refs 1601 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 9.529762 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 104.225653 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025446 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025446 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 104.433203 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025496 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025496 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits @@ -521,14 +521,14 @@ system.cpu.dcache.demand_misses::cpu.data 447 # n system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses system.cpu.dcache.overall_misses::total 447 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5353500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5353500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14913500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14913500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20267000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20267000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20267000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20267000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5722500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5722500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15380500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15380500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21103000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21103000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21103000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21103000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -545,19 +545,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55190.721649 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55190.721649 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42610 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42610 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45340.044743 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45340.044743 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45340.044743 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45340.044743 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 134 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58994.845361 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58994.845361 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43944.285714 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43944.285714 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47210.290828 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47210.290828 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47210.290828 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47210.290828 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 178 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 134 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 89 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -577,14 +577,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5078000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5078000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3673500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3673500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8751500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8751500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8751500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8751500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5446000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5446000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3636000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3636000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9082000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9082000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9082000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9082000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -593,14 +593,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53452.631579 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53452.631579 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50321.917808 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50321.917808 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52092.261905 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52092.261905 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52092.261905 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52092.261905 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57326.315789 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57326.315789 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49808.219178 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49808.219178 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54059.523810 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54059.523810 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54059.523810 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54059.523810 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index a295cf48e..d7bf6a6b9 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 15802500 # Number of ticks simulated -final_tick 15802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16030500 # Number of ticks simulated +final_tick 16030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36566 # Simulator instruction rate (inst/s) -host_op_rate 36562 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90663114 # Simulator tick rate (ticks/s) -host_mem_usage 270656 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 76258 # Simulator instruction rate (inst/s) +host_op_rate 76239 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 191753794 # Simulator tick rate (ticks/s) +host_mem_usage 225728 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory -system.physmem.bytes_read::total 31168 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 31104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory -system.physmem.num_reads::total 487 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1267647524 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 704698624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1972346148 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1267647524 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1267647524 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1267647524 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 704698624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1972346148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 487 # Total number of read requests seen +system.physmem.num_reads::total 486 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1245625526 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 694675774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1940301301 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1245625526 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1245625526 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1245625526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 694675774 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1940301301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 486 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 487 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 31168 # Total number of bytes read from memory +system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 31104 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 31104 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 67 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 73 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 67 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 47 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 44 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 3 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 45 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 15655000 # Total gap between requests +system.physmem.totGap 15817000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 487 # Categorize read packet sizes +system.physmem.readPktSize::6 486 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 247 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,56 +164,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3073487 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12819487 # Sum of mem lat for all requests -system.physmem.totBusLat 1948000 # Total cycles spent in databus access -system.physmem.totBankLat 7798000 # Total cycles spent in bank access -system.physmem.avgQLat 6311.06 # Average queueing delay per request -system.physmem.avgBankLat 16012.32 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26323.38 # Average memory access latency -system.physmem.avgRdBW 1972.35 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2909986 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13644986 # Sum of mem lat for all requests +system.physmem.totBusLat 2430000 # Total cycles spent in databus access +system.physmem.totBankLat 8305000 # Total cycles spent in bank access +system.physmem.avgQLat 5987.63 # Average queueing delay per request +system.physmem.avgBankLat 17088.48 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 28076.10 # Average memory access latency +system.physmem.avgRdBW 1940.30 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1972.35 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1940.30 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.33 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.81 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 15.16 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.85 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 416 # Number of row buffer hits during reads +system.physmem.readRowHits 396 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.42 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 32145.79 # Average gap between requests -system.cpu.branchPred.lookups 2927 # Number of BP lookups -system.cpu.branchPred.condPredicted 1718 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 517 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2238 # Number of BTB lookups -system.cpu.branchPred.BTBHits 757 # Number of BTB hits +system.physmem.avgGap 32545.27 # Average gap between requests +system.cpu.branchPred.lookups 2896 # Number of BP lookups +system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 513 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2200 # Number of BTB lookups +system.cpu.branchPred.BTBHits 746 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 33.824844 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 420 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 77 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 33.909091 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 416 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2068 # DTB read hits +system.cpu.dtb.read_hits 2071 # DTB read hits system.cpu.dtb.read_misses 50 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2118 # DTB read accesses -system.cpu.dtb.write_hits 1071 # DTB write hits -system.cpu.dtb.write_misses 29 # DTB write misses +system.cpu.dtb.read_accesses 2121 # DTB read accesses +system.cpu.dtb.write_hits 1069 # DTB write hits +system.cpu.dtb.write_misses 30 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1100 # DTB write accesses -system.cpu.dtb.data_hits 3139 # DTB hits -system.cpu.dtb.data_misses 79 # DTB misses +system.cpu.dtb.write_accesses 1099 # DTB write accesses +system.cpu.dtb.data_hits 3140 # DTB hits +system.cpu.dtb.data_misses 80 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3218 # DTB accesses -system.cpu.itb.fetch_hits 2370 # ITB hits -system.cpu.itb.fetch_misses 39 # ITB misses +system.cpu.dtb.data_accesses 3220 # DTB accesses +system.cpu.itb.fetch_hits 2349 # ITB hits +system.cpu.itb.fetch_misses 38 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2409 # ITB accesses +system.cpu.itb.fetch_accesses 2387 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -227,236 +227,236 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 31606 # number of cpu cycles simulated +system.cpu.numCycles 32062 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8266 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16744 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2927 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1177 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2985 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1897 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1074 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 762 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2370 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 362 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14416 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.161487 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.555904 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 8352 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16527 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2896 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1162 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2951 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1883 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1142 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2349 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 363 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14509 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.139086 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.536110 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11431 79.29% 79.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 317 2.20% 81.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 233 1.62% 83.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 212 1.47% 84.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 264 1.83% 86.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 229 1.59% 88.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 265 1.84% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 186 1.29% 91.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1279 8.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11558 79.66% 79.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 317 2.18% 81.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 230 1.59% 83.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 219 1.51% 84.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 255 1.76% 86.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 218 1.50% 88.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 264 1.82% 90.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 185 1.28% 91.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1263 8.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14416 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.092609 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.529773 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9179 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1146 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2779 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 90 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1222 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 249 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 14509 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.090325 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.515470 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9308 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1148 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2753 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1212 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 252 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15526 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 15363 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 231 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1222 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9389 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 326 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 477 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2653 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 349 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14793 # Number of instructions processed by rename +system.cpu.rename.SquashCycles 1212 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9517 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 459 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 372 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2631 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 318 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14679 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 317 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 11113 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18446 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18429 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 286 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 11023 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18314 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18297 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6543 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 32 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 26 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 811 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2756 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1363 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 6453 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 30 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 757 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2761 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1357 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 13069 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10819 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6341 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3614 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14416 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.750486 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.391653 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 13018 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10806 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 50 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6314 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3579 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14509 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.744779 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.389331 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9926 68.85% 68.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1619 11.23% 80.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1135 7.87% 87.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 768 5.33% 93.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 481 3.34% 96.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 285 1.98% 98.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 151 1.05% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 37 0.26% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10032 69.14% 69.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1598 11.01% 80.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1157 7.97% 88.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 759 5.23% 93.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 472 3.25% 96.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 281 1.94% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 159 1.10% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 38 0.26% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14416 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14509 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 14 11.97% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 64 54.70% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 39 33.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 16 13.56% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 63 53.39% 66.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 39 33.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7317 67.63% 67.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2355 21.77% 89.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1142 10.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7299 67.55% 67.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2362 21.86% 89.45% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1140 10.55% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10819 # Type of FU issued -system.cpu.iq.rate 0.342308 # Inst issue rate -system.cpu.iq.fu_busy_cnt 117 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010814 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 36206 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19446 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9723 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10806 # Type of FU issued +system.cpu.iq.rate 0.337034 # Inst issue rate +system.cpu.iq.fu_busy_cnt 118 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010920 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 36268 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19365 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9700 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10923 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10911 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 72 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1573 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1578 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 498 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 492 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 90 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 87 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1222 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 52 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13186 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 157 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2756 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1363 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 1212 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 151 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 13132 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 153 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2761 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1357 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 129 # Number of branches that were predicted taken incorrectly +system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 126 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 522 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10167 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed +system.cpu.iew.branchMispredicts 519 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10154 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2132 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 652 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 87 # number of nop insts executed -system.cpu.iew.exec_refs 3231 # number of memory reference insts executed -system.cpu.iew.exec_branches 1614 # Number of branches executed -system.cpu.iew.exec_stores 1102 # Number of stores executed -system.cpu.iew.exec_rate 0.321679 # Inst execution rate -system.cpu.iew.wb_sent 9882 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9733 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5145 # num instructions producing a value -system.cpu.iew.wb_consumers 6933 # num instructions consuming a value +system.cpu.iew.exec_nop 86 # number of nop insts executed +system.cpu.iew.exec_refs 3233 # number of memory reference insts executed +system.cpu.iew.exec_branches 1613 # Number of branches executed +system.cpu.iew.exec_stores 1101 # Number of stores executed +system.cpu.iew.exec_rate 0.316699 # Inst execution rate +system.cpu.iew.wb_sent 9857 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9710 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5134 # num instructions producing a value +system.cpu.iew.wb_consumers 6919 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.307948 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.742103 # average fanout of values written-back +system.cpu.iew.wb_rate 0.302851 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.742015 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6795 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6741 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 435 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13194 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.484235 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.303292 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13297 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.480484 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.303494 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10420 78.98% 78.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1475 11.18% 90.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 517 3.92% 94.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 247 1.87% 95.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 154 1.17% 97.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 92 0.70% 97.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 106 0.80% 98.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10548 79.33% 79.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1447 10.88% 90.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 514 3.87% 94.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 246 1.85% 95.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 153 1.15% 97.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 103 0.77% 97.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 101 0.76% 98.61% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 37 0.28% 98.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 146 1.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 148 1.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13194 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13297 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -467,70 +467,70 @@ system.cpu.commit.branches 1050 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6307 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 146 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 148 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 25881 # The number of ROB reads -system.cpu.rob.rob_writes 27599 # The number of ROB writes -system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17190 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 25928 # The number of ROB reads +system.cpu.rob.rob_writes 27481 # The number of ROB writes +system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17553 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 4.960138 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.960138 # CPI: Total CPI of All Threads -system.cpu.ipc 0.201607 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.201607 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12907 # number of integer regfile reads -system.cpu.int_regfile_writes 7365 # number of integer regfile writes +system.cpu.cpi 5.031701 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.031701 # CPI: Total CPI of All Threads +system.cpu.ipc 0.198740 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.198740 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12888 # number of integer regfile reads +system.cpu.int_regfile_writes 7343 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 160.479269 # Cycle average of tags in use -system.cpu.icache.total_refs 1894 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.031847 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 159.192237 # Cycle average of tags in use +system.cpu.icache.total_refs 1869 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.971246 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 160.479269 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.078359 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.078359 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1894 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1894 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1894 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1894 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1894 # number of overall hits -system.cpu.icache.overall_hits::total 1894 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 476 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 476 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 476 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 476 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 476 # number of overall misses -system.cpu.icache.overall_misses::total 476 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21386500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21386500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21386500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21386500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21386500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21386500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2370 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2370 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2370 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2370 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2370 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2370 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.200844 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.200844 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.200844 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.200844 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.200844 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.200844 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44929.621849 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44929.621849 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44929.621849 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44929.621849 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44929.621849 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44929.621849 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 159.192237 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.077731 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.077731 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1869 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1869 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1869 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1869 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1869 # number of overall hits +system.cpu.icache.overall_hits::total 1869 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 480 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 480 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 480 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses +system.cpu.icache.overall_misses::total 480 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 22202500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 22202500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 22202500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 22202500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 22202500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 22202500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2349 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2349 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2349 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2349 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2349 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2349 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204342 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.204342 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.204342 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.204342 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.204342 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.204342 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46255.208333 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46255.208333 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46255.208333 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46255.208333 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46255.208333 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46255.208333 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -539,109 +539,109 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 162 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 162 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 162 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 162 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 162 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 162 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15404000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15404000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15404000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15404000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15404000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15404000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.132489 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.132489 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.132489 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49057.324841 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49057.324841 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49057.324841 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49057.324841 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49057.324841 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49057.324841 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 167 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 167 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 167 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16102000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16102000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16102000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16102000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16102000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16102000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133248 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.133248 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.133248 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51444.089457 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51444.089457 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51444.089457 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51444.089457 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51444.089457 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51444.089457 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 220.902491 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 219.643453 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 414 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002415 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002421 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 160.626019 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 60.276472 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004902 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001839 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006741 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 159.327355 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 60.316098 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004862 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001841 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006703 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 313 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 312 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 414 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 413 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 313 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 487 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses +system.cpu.l2cache.demand_misses::total 486 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses -system.cpu.l2cache.overall_misses::total 487 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15078000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6210500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21288500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3737500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3737500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15078000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9948000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 25026000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15078000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9948000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 25026000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 314 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 486 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15777000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6080500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21857500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3687500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3687500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15777000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9768000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 25545000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15777000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9768000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 25545000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 313 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 414 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 314 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 313 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 488 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 314 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 487 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 313 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 488 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996815 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 487 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997590 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997585 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996815 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997951 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.997947 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997951 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48172.523962 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 61490.099010 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51421.497585 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51198.630137 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51198.630137 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48172.523962 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57172.413793 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51388.090349 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48172.523962 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57172.413793 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51388.090349 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997947 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50567.307692 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60202.970297 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52923.728814 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50513.698630 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50513.698630 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50567.307692 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52561.728395 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50567.307692 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52561.728395 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -650,68 +650,68 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 414 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 413 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 487 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 486 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 487 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11136994 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4966088 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16103082 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2842064 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2842064 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11136994 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7808152 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18945146 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11136994 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7808152 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18945146 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11907990 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4848832 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16756822 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2795812 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2795812 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11907990 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7644644 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19552634 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11907990 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7644644 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19552634 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997585 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35581.450479 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49169.188119 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38896.333333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38932.383562 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38932.383562 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35581.450479 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44874.436782 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38901.737166 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35581.450479 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44874.436782 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38901.737166 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38166.634615 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48008.237624 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40573.418886 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38298.794521 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38298.794521 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38166.634615 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43934.735632 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40231.757202 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38166.634615 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43934.735632 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40231.757202 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 107.834334 # Cycle average of tags in use -system.cpu.dcache.total_refs 2264 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 107.713176 # Cycle average of tags in use +system.cpu.dcache.total_refs 2262 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.011494 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 107.834334 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.026327 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.026327 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1758 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1758 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 107.713176 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.026297 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.026297 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1756 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1756 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2264 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2264 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2264 # number of overall hits -system.cpu.dcache.overall_hits::total 2264 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2262 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2262 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2262 # number of overall hits +system.cpu.dcache.overall_hits::total 2262 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses @@ -720,43 +720,43 @@ system.cpu.dcache.demand_misses::cpu.data 528 # n system.cpu.dcache.demand_misses::total 528 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 528 # number of overall misses system.cpu.dcache.overall_misses::total 528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9065500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9065500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15837484 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15837484 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24902984 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24902984 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24902984 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24902984 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1927 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9127000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9127000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15893487 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15893487 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 25020487 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 25020487 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 25020487 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 25020487 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1925 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1925 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2792 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2792 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2792 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2792 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087701 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.087701 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2790 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2790 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2790 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2790 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087792 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.087792 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.189112 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.189112 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.189112 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.189112 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53642.011834 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53642.011834 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44115.554318 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44115.554318 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47164.742424 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47164.742424 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47164.742424 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47164.742424 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 801 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.189247 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.189247 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.189247 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.189247 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54005.917160 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54005.917160 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44271.551532 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44271.551532 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47387.285985 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47387.285985 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47387.285985 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47387.285985 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 862 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.807692 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.478261 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -776,30 +776,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 174 system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6319000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6319000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3813500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3813500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10132500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10132500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10132500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10132500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052413 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052413 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6189000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6189000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3763500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3763500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9952500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9952500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9952500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9952500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052468 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052468 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062321 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.062321 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062321 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.062321 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62564.356436 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62564.356436 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52239.726027 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52239.726027 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58232.758621 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58232.758621 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58232.758621 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58232.758621 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062366 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.062366 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062366 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.062366 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61277.227723 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61277.227723 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51554.794521 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51554.794521 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57198.275862 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57198.275862 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57198.275862 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57198.275862 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 0c67bfe34..6b89534e6 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000009 # Number of seconds simulated -sim_ticks 9059000 # Number of ticks simulated -final_tick 9059000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 9350000 # Number of ticks simulated +final_tick 9350000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 18337 # Simulator instruction rate (inst/s) -host_op_rate 18335 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69572663 # Simulator tick rate (ticks/s) -host_mem_usage 270376 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 146 # Simulator instruction rate (inst/s) +host_op_rate 146 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 570039 # Simulator tick rate (ticks/s) +host_mem_usage 224412 # Number of bytes of host memory used +host_seconds 16.40 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1321117121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 600507782 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1921624903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1321117121 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1321117121 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1321117121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 600507782 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1921624903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1280000000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 581818182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1861818182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1280000000 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1280000000 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1280000000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 581818182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1861818182 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 272 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 272 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 17408 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 38 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 9 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 18 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 21 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 8990500 # Total gap between requests +system.physmem.totGap 9280500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 87 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,56 +164,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1180771 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6930771 # Sum of mem lat for all requests -system.physmem.totBusLat 1088000 # Total cycles spent in databus access -system.physmem.totBankLat 4662000 # Total cycles spent in bank access -system.physmem.avgQLat 4341.07 # Average queueing delay per request -system.physmem.avgBankLat 17139.71 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25480.78 # Average memory access latency -system.physmem.avgRdBW 1921.62 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 1329022 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7872772 # Sum of mem lat for all requests +system.physmem.totBusLat 1360000 # Total cycles spent in databus access +system.physmem.totBankLat 5183750 # Total cycles spent in bank access +system.physmem.avgQLat 4886.11 # Average queueing delay per request +system.physmem.avgBankLat 19057.90 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 28944.01 # Average memory access latency +system.physmem.avgRdBW 1861.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1921.62 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1861.82 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.01 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.77 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 14.55 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.84 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 228 # Number of row buffer hits during reads +system.physmem.readRowHits 207 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.10 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33053.31 # Average gap between requests -system.cpu.branchPred.lookups 1180 # Number of BP lookups -system.cpu.branchPred.condPredicted 594 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 261 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 806 # Number of BTB lookups -system.cpu.branchPred.BTBHits 235 # Number of BTB hits +system.physmem.avgGap 34119.49 # Average gap between requests +system.cpu.branchPred.lookups 1154 # Number of BP lookups +system.cpu.branchPred.condPredicted 581 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 258 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 791 # Number of BTB lookups +system.cpu.branchPred.BTBHits 226 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 29.156328 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 227 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 28.571429 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 39 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 717 # DTB read hits -system.cpu.dtb.read_misses 25 # DTB read misses +system.cpu.dtb.read_hits 708 # DTB read hits +system.cpu.dtb.read_misses 28 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 742 # DTB read accesses -system.cpu.dtb.write_hits 359 # DTB write hits -system.cpu.dtb.write_misses 19 # DTB write misses +system.cpu.dtb.read_accesses 736 # DTB read accesses +system.cpu.dtb.write_hits 357 # DTB write hits +system.cpu.dtb.write_misses 20 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 378 # DTB write accesses -system.cpu.dtb.data_hits 1076 # DTB hits -system.cpu.dtb.data_misses 44 # DTB misses +system.cpu.dtb.write_accesses 377 # DTB write accesses +system.cpu.dtb.data_hits 1065 # DTB hits +system.cpu.dtb.data_misses 48 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1120 # DTB accesses -system.cpu.itb.fetch_hits 1063 # ITB hits +system.cpu.dtb.data_accesses 1113 # DTB accesses +system.cpu.itb.fetch_hits 1043 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1093 # ITB accesses +system.cpu.itb.fetch_accesses 1073 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -227,237 +227,237 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 18119 # number of cpu cycles simulated +system.cpu.numCycles 18701 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4211 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 7069 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1180 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 462 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1219 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 881 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 344 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 4189 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6947 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1154 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 450 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1194 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 869 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 306 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 959 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1024 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1063 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 190 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7350 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.961769 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.375037 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1043 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 182 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7320 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.949044 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.362722 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6131 83.41% 83.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 57 0.78% 84.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 120 1.63% 85.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 95 1.29% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 168 2.29% 89.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 73 0.99% 90.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 67 0.91% 91.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 64 0.87% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 575 7.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6126 83.69% 83.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 54 0.74% 84.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 114 1.56% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 92 1.26% 87.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 168 2.30% 89.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 73 1.00% 90.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 64 0.87% 91.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 64 0.87% 92.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 565 7.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7350 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.065125 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.390143 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5296 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 369 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1168 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 510 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 170 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 7320 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.061708 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.371477 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5332 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 332 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1148 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 500 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6269 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 6173 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 510 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5398 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 91 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 250 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1075 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 26 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5981 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu.rename.SquashCycles 500 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5432 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 109 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 186 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1056 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 37 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5903 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 16 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4351 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6729 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6717 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 4293 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6642 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6630 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2583 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2525 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 121 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 979 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 463 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 133 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 964 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 466 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 5055 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 5010 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4086 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2501 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1445 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 4065 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2458 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1421 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7350 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.555918 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.264810 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7320 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.555328 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.267026 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5719 77.81% 77.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 555 7.55% 85.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 404 5.50% 90.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 261 3.55% 94.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 214 2.91% 97.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 126 1.71% 99.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 50 0.68% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14 0.19% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5695 77.80% 77.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 561 7.66% 85.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 397 5.42% 90.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 261 3.57% 94.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 207 2.83% 97.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 126 1.72% 99.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 50 0.68% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15 0.20% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 8 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7350 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7320 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19 43.18% 50.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 22 50.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2 4.35% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 21 45.65% 50.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 50.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2910 71.22% 71.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 789 19.31% 90.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 386 9.45% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2890 71.09% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 787 19.36% 90.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 387 9.52% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4086 # Type of FU issued -system.cpu.iq.rate 0.225509 # Inst issue rate -system.cpu.iq.fu_busy_cnt 44 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010768 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15607 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7560 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3685 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 4065 # Type of FU issued +system.cpu.iq.rate 0.217368 # Inst issue rate +system.cpu.iq.fu_busy_cnt 46 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011316 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15536 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7472 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3658 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4123 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4104 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 36 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 564 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 549 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 169 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 172 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 10 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 510 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 82 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 500 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 100 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5405 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 124 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 979 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 463 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 5355 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 129 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 964 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 466 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 57 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 161 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 218 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3887 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 743 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 199 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 159 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 215 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3852 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 737 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 213 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 344 # number of nop insts executed -system.cpu.iew.exec_refs 1121 # number of memory reference insts executed -system.cpu.iew.exec_branches 656 # Number of branches executed -system.cpu.iew.exec_stores 378 # Number of stores executed -system.cpu.iew.exec_rate 0.214526 # Inst execution rate -system.cpu.iew.wb_sent 3770 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3691 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1735 # num instructions producing a value -system.cpu.iew.wb_consumers 2218 # num instructions consuming a value +system.cpu.iew.exec_nop 339 # number of nop insts executed +system.cpu.iew.exec_refs 1114 # number of memory reference insts executed +system.cpu.iew.exec_branches 649 # Number of branches executed +system.cpu.iew.exec_stores 377 # Number of stores executed +system.cpu.iew.exec_rate 0.205978 # Inst execution rate +system.cpu.iew.wb_sent 3743 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3664 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1730 # num instructions producing a value +system.cpu.iew.wb_consumers 2229 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.203709 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.782236 # average fanout of values written-back +system.cpu.iew.wb_rate 0.195925 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.776133 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2808 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2758 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 183 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6840 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.376608 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.234221 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6820 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.377713 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.238824 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5975 87.35% 87.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 201 2.94% 90.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 309 4.52% 94.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 115 1.68% 96.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 68 0.99% 97.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 49 0.72% 98.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 33 0.48% 98.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23 0.34% 99.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 67 0.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5956 87.33% 87.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 201 2.95% 90.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 310 4.55% 94.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 116 1.70% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 63 0.92% 97.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 50 0.73% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 32 0.47% 98.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23 0.34% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69 1.01% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6840 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6820 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -468,119 +468,119 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 67 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11910 # The number of ROB reads -system.cpu.rob.rob_writes 11291 # The number of ROB writes -system.cpu.timesIdled 164 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10769 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 11838 # The number of ROB reads +system.cpu.rob.rob_writes 11181 # The number of ROB writes +system.cpu.timesIdled 163 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11381 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 7.590700 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.590700 # CPI: Total CPI of All Threads -system.cpu.ipc 0.131740 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.131740 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4685 # number of integer regfile reads -system.cpu.int_regfile_writes 2864 # number of integer regfile writes +system.cpu.cpi 7.834520 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.834520 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127640 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127640 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4649 # number of integer regfile reads +system.cpu.int_regfile_writes 2842 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 92.986102 # Cycle average of tags in use -system.cpu.icache.total_refs 813 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 90.926534 # Cycle average of tags in use +system.cpu.icache.total_refs 794 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.347594 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.245989 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 92.986102 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.045403 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.045403 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 813 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 813 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 813 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 813 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 813 # number of overall hits -system.cpu.icache.overall_hits::total 813 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses -system.cpu.icache.overall_misses::total 250 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11955999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11955999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11955999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11955999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11955999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11955999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1063 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1063 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1063 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1063 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1063 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1063 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235183 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.235183 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.235183 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.235183 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.235183 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.235183 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47823.996000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47823.996000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47823.996000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47823.996000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47823.996000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47823.996000 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 102 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 90.926534 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.044398 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.044398 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 794 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 794 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 794 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 794 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 794 # number of overall hits +system.cpu.icache.overall_hits::total 794 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 249 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 249 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 249 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses +system.cpu.icache.overall_misses::total 249 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12422499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12422499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12422499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12422499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12422499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12422499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1043 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1043 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1043 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1043 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1043 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1043 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.238734 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.238734 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.238734 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.238734 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.238734 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.238734 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49889.554217 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49889.554217 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49889.554217 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49889.554217 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49889.554217 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49889.554217 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 160 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 53.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 62 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 62 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 62 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9236999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9236999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9236999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9236999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9236999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9236999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.175917 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.175917 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.175917 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.175917 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.175917 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.175917 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49395.716578 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49395.716578 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49395.716578 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49395.716578 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49395.716578 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49395.716578 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9626999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9626999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9626999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9626999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9626999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9626999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.179291 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.179291 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.179291 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.179291 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.179291 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.179291 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51481.278075 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51481.278075 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51481.278075 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51481.278075 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51481.278075 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51481.278075 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 121.901566 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 119.099628 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 248 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 93.245260 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.656305 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002846 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000875 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003720 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 91.174739 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 27.924890 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002782 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000852 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003635 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 187 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 248 # number of ReadReq misses @@ -592,17 +592,17 @@ system.cpu.l2cache.demand_misses::total 272 # nu system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 272 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9049000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3265500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12314500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1324000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1324000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9049000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4589500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13638500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9049000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4589500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13638500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9439000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3587500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13026500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1408000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1408000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9439000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4995500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14434500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9439000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4995500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14434500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 187 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 248 # number of ReadReq accesses(hits+misses) @@ -625,17 +625,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48390.374332 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53532.786885 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49655.241935 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55166.666667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55166.666667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48390.374332 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53994.117647 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 50141.544118 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48390.374332 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53994.117647 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 50141.544118 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50475.935829 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58811.475410 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52526.209677 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58666.666667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58666.666667 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50475.935829 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58770.588235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53068.014706 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50475.935829 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58770.588235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53068.014706 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -655,17 +655,17 @@ system.cpu.l2cache.demand_mshr_misses::total 272 system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6701279 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2512062 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9213341 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1027024 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1027024 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6701279 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3539086 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10240365 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6701279 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3539086 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10240365 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7118288 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2838816 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9957104 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1114024 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1114024 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7118288 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3952840 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11071128 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7118288 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3952840 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11071128 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -677,91 +677,91 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35835.716578 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41181.344262 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37150.568548 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42792.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42792.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35835.716578 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41636.305882 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37648.400735 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35835.716578 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41636.305882 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37648.400735 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38065.711230 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46537.967213 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40149.612903 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46417.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46417.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38065.711230 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46504 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40702.676471 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38065.711230 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46504 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40702.676471 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 45.425217 # Cycle average of tags in use -system.cpu.dcache.total_refs 774 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 44.507812 # Cycle average of tags in use +system.cpu.dcache.total_refs 763 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.105882 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.976471 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 45.425217 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011090 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011090 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 561 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 561 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 44.507812 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.010866 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.010866 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 550 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 550 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 774 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 774 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 774 # number of overall hits -system.cpu.dcache.overall_hits::total 774 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 763 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 763 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 763 # number of overall hits +system.cpu.dcache.overall_hits::total 763 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 112 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 112 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 192 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 192 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 192 # number of overall misses -system.cpu.dcache.overall_misses::total 192 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5152500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5152500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4115500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4115500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9268000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9268000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9268000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9268000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 672 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 672 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 193 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 193 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 193 # number of overall misses +system.cpu.dcache.overall_misses::total 193 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5526500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5526500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4429500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4429500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9956000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9956000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9956000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9956000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 662 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 662 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 966 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 966 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 966 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 966 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.165179 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.165179 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 956 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 956 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 956 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 956 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169184 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.169184 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.198758 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.198758 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.198758 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.198758 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46418.918919 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 46418.918919 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50808.641975 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 50808.641975 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48270.833333 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48270.833333 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48270.833333 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48270.833333 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 69 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.201883 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.201883 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.201883 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.201883 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49343.750000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49343.750000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54685.185185 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54685.185185 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 51585.492228 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 51585.492228 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 51585.492228 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 51585.492228 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 88 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 23 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.333333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 107 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 107 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 107 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 107 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 108 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 108 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 108 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -770,30 +770,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3326500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3326500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1349500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1349500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4676000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4676000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4676000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4676000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.090774 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.090774 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3648500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3648500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1433500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1433500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5082000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5082000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5082000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5082000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092145 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092145 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087992 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.087992 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087992 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.087992 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54532.786885 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54532.786885 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56229.166667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56229.166667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55011.764706 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 55011.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55011.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 55011.764706 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.088912 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.088912 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.088912 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.088912 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59811.475410 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59811.475410 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59729.166667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59729.166667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59788.235294 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59788.235294 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59788.235294 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59788.235294 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index cbe7a8e01..80cf199ee 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13354000 # Number of ticks simulated -final_tick 13354000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000014 # Number of seconds simulated +sim_ticks 13709000 # Number of ticks simulated +final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 22763 # Simulator instruction rate (inst/s) -host_op_rate 28403 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66199618 # Simulator tick rate (ticks/s) -host_mem_usage 285296 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 51480 # Simulator instruction rate (inst/s) +host_op_rate 64222 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 153638426 # Simulator tick rate (ticks/s) +host_mem_usage 239936 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17408 # Nu system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 394 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1303579452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 584693725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1888273177 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1303579452 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1303579452 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1303579452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 584693725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1888273177 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1269822744 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 569552848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1839375593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1269822744 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1269822744 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1269822744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 569552848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1839375593 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 394 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 25216 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 43 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 18 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 43 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 15 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13296500 # Total gap between requests +system.physmem.totGap 13651500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2460894 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10560894 # Sum of mem lat for all requests -system.physmem.totBusLat 1576000 # Total cycles spent in databus access -system.physmem.totBankLat 6524000 # Total cycles spent in bank access -system.physmem.avgQLat 6245.92 # Average queueing delay per request -system.physmem.avgBankLat 16558.38 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26804.30 # Average memory access latency -system.physmem.avgRdBW 1888.27 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2508144 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11751894 # Sum of mem lat for all requests +system.physmem.totBusLat 1970000 # Total cycles spent in databus access +system.physmem.totBankLat 7273750 # Total cycles spent in bank access +system.physmem.avgQLat 6365.85 # Average queueing delay per request +system.physmem.avgBankLat 18461.29 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 29827.14 # Average memory access latency +system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1888.27 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.80 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.79 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 14.37 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.86 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 319 # Number of row buffer hits during reads +system.physmem.readRowHits 294 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33747.46 # Average gap between requests +system.physmem.avgGap 34648.48 # Average gap between requests system.cpu.branchPred.lookups 2501 # Number of BP lookups system.cpu.branchPred.condPredicted 1795 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 485 # Number of conditional branches incorrect @@ -282,50 +282,50 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 26709 # number of cpu cycles simulated +system.cpu.numCycles 27419 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6895 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 994 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2651 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1627 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2216 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 2253 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1956 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12880 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.183618 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.594570 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.172963 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.585283 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10229 79.42% 79.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 225 1.75% 81.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.58% 82.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 224 1.74% 84.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 223 1.73% 86.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 273 2.12% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 95 0.74% 89.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 149 1.16% 90.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1259 9.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10346 79.60% 79.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 225 1.73% 81.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.56% 82.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 224 1.72% 84.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 223 1.72% 86.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 273 2.10% 88.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 95 0.73% 89.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 149 1.15% 90.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1259 9.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12880 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.093639 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.449661 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6875 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2529 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2444 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 12997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.091214 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.438017 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2562 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2445 # Number of cycles decode is running system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 389 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13347 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13349 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7140 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 7224 # Number of cycles rename is idle system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1992 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 2025 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2245 # Number of cycles rename is running system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 12580 # Number of instructions processed by rename @@ -347,28 +347,28 @@ system.cpu.memDep0.conflictingLoads 37 # Nu system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 11260 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8988 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8986 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 5240 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 14437 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12880 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.697826 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.403354 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12997 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.691390 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.397883 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9299 72.20% 72.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1308 10.16% 82.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 806 6.26% 88.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 539 4.18% 92.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 466 3.62% 96.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 270 2.10% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 122 0.95% 99.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9412 72.42% 72.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1312 10.09% 82.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 811 6.24% 88.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 535 4.12% 92.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 465 3.58% 96.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 270 2.08% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 122 0.94% 99.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.42% 99.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12880 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12997 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available @@ -404,50 +404,50 @@ system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5406 60.15% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5406 60.16% 60.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2347 26.12% 86.39% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1223 13.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8988 # Type of FU issued -system.cpu.iq.rate 0.336516 # Inst issue rate +system.cpu.iq.FU_type_0::total 8986 # Type of FU issued +system.cpu.iq.rate 0.327729 # Inst issue rate system.cpu.iq.fu_busy_cnt 228 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31164 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_rate 0.025373 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31277 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 16519 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8089 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 8090 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9196 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9194 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -475,42 +475,42 @@ system.cpu.iew.predictedTakenIncorrect 109 # Nu system.cpu.iew.predictedNotTakenIncorrect 275 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 8563 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 425 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 423 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3303 # number of memory reference insts executed -system.cpu.iew.exec_branches 1443 # Number of branches executed +system.cpu.iew.exec_refs 3302 # number of memory reference insts executed +system.cpu.iew.exec_branches 1444 # Number of branches executed system.cpu.iew.exec_stores 1167 # Number of stores executed -system.cpu.iew.exec_rate 0.320604 # Inst execution rate -system.cpu.iew.wb_sent 8264 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8105 # cumulative count of insts written-back +system.cpu.iew.exec_rate 0.312302 # Inst execution rate +system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8106 # cumulative count of insts written-back system.cpu.iew.wb_producers 3904 # num instructions producing a value system.cpu.iew.wb_consumers 7842 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.303456 # insts written-back per cycle +system.cpu.iew.wb_rate 0.295634 # insts written-back per cycle system.cpu.iew.wb_fanout 0.497832 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 5585 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 330 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11917 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.480742 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.314534 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12034 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.476068 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.308850 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9632 80.83% 80.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1071 8.99% 89.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 396 3.32% 93.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 259 2.17% 95.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 183 1.54% 96.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.44% 98.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 50 0.42% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.29% 99.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 119 1.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9748 81.00% 81.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1072 8.91% 89.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 397 3.30% 93.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 258 2.14% 95.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 183 1.52% 96.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.43% 98.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 50 0.42% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 119 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11917 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12034 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -523,117 +523,117 @@ system.cpu.commit.int_insts 4976 # Nu system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22955 # The number of ROB reads +system.cpu.rob.rob_reads 23072 # The number of ROB reads system.cpu.rob.rob_writes 23605 # The number of ROB writes system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 14422 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 5.817687 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.817687 # CPI: Total CPI of All Threads -system.cpu.ipc 0.171890 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.171890 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39368 # number of integer regfile reads -system.cpu.int_regfile_writes 8018 # number of integer regfile writes +system.cpu.cpi 5.972337 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.972337 # CPI: Total CPI of All Threads +system.cpu.ipc 0.167439 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.167439 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39366 # number of integer regfile reads +system.cpu.int_regfile_writes 8019 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.misc_regfile_reads 2982 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 147.647008 # Cycle average of tags in use -system.cpu.icache.total_refs 1597 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 146.913425 # Cycle average of tags in use +system.cpu.icache.total_refs 1596 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.487973 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.484536 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 147.647008 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072093 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072093 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1597 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1597 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1597 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1597 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1597 # number of overall hits -system.cpu.icache.overall_hits::total 1597 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses -system.cpu.icache.overall_misses::total 359 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17287500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17287500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17287500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17287500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17287500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17287500 # number of overall miss cycles +system.cpu.icache.occ_blocks::cpu.inst 146.913425 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071735 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071735 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1596 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1596 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1596 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1596 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1596 # number of overall hits +system.cpu.icache.overall_hits::total 1596 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses +system.cpu.icache.overall_misses::total 360 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17745500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17745500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17745500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17745500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17745500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17745500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1956 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1956 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 1956 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 1956 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1956 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183538 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.183538 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.183538 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.183538 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.183538 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.183538 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48154.596100 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48154.596100 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48154.596100 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48154.596100 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184049 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.184049 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.184049 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.184049 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.184049 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.184049 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49293.055556 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49293.055556 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49293.055556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49293.055556 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 124 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 62 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14218500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14218500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14218500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14218500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14218500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14218500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14592500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14592500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14592500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14592500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14592500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14592500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148773 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.148773 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.148773 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48860.824742 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48860.824742 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50146.048110 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50146.048110 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 185.926666 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 185.063220 # Cycle average of tags in use system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 139.061385 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.865282 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004244 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001430 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005674 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 138.360527 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.702693 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004222 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001425 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005648 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits @@ -654,17 +654,17 @@ system.cpu.l2cache.demand_misses::total 399 # nu system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 399 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13736500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18412500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13736500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6947500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20684000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13736500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6947500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20684000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14110500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4968000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19078500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2402500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2402500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14110500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7370500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21481000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14110500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7370500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21481000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -687,17 +687,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.910959 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.934708 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.910959 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50501.838235 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54372.093023 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51431.564246 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51839.598997 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51839.598997 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51876.838235 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57767.441860 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53291.899441 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58597.560976 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58597.560976 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53837.092732 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53837.092732 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -723,17 +723,17 @@ system.cpu.l2cache.demand_mshr_misses::total 394 system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319902 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455564 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13775466 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319902 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5220104 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15540006 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319902 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5220104 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15540006 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10736168 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756318 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492486 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896792 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896792 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10736168 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653110 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16389278 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10736168 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653110 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16389278 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses @@ -745,109 +745,109 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37940.816176 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42661.283951 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39023.983003 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39471.205882 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46374.296296 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41055.201133 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46263.219512 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46263.219512 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.800851 # Cycle average of tags in use -system.cpu.dcache.total_refs 2395 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use +system.cpu.dcache.total_refs 2392 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.404110 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.383562 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.800851 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021192 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021192 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.502557 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021119 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021119 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1764 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1764 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits -system.cpu.dcache.overall_hits::total 2373 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2370 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2370 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2370 # number of overall hits +system.cpu.dcache.overall_hits::total 2370 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 193 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 193 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses -system.cpu.dcache.overall_misses::total 498 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8139500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8139500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses +system.cpu.dcache.overall_misses::total 500 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8675500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8675500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14874500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14874500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23047000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1958 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1958 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 23550000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23550000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23550000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23550000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1957 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1957 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2871 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2871 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2871 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2871 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097549 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097549 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2870 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2870 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2870 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2870 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098620 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098620 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173459 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173459 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173459 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173459 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.174216 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.174216 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.174216 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.174216 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44950.777202 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 44950.777202 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.140065 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48451.140065 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47100 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47100 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 87 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 353 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 353 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 353 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 353 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -856,30 +856,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4926000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4926000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7239500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7239500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7239500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7239500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054137 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054137 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5218000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5218000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2444500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2444500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7662500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7662500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7662500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7662500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054165 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054165 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051202 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051202 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46471.698113 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46471.698113 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051220 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051220 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49226.415094 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49226.415094 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59621.951220 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59621.951220 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index a9f3432ad..13489057c 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13354000 # Number of ticks simulated -final_tick 13354000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000014 # Number of seconds simulated +sim_ticks 13709000 # Number of ticks simulated +final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 20035 # Simulator instruction rate (inst/s) -host_op_rate 24999 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58267208 # Simulator tick rate (ticks/s) -host_mem_usage 285296 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_inst_rate 58002 # Simulator instruction rate (inst/s) +host_op_rate 72354 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 173086159 # Simulator tick rate (ticks/s) +host_mem_usage 238920 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17408 # Nu system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 394 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1303579452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 584693725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1888273177 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1303579452 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1303579452 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1303579452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 584693725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1888273177 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1269822744 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 569552848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1839375593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1269822744 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1269822744 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1269822744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 569552848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1839375593 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 394 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 25216 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 43 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 18 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 43 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 15 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13296500 # Total gap between requests +system.physmem.totGap 13651500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2460894 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10560894 # Sum of mem lat for all requests -system.physmem.totBusLat 1576000 # Total cycles spent in databus access -system.physmem.totBankLat 6524000 # Total cycles spent in bank access -system.physmem.avgQLat 6245.92 # Average queueing delay per request -system.physmem.avgBankLat 16558.38 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26804.30 # Average memory access latency -system.physmem.avgRdBW 1888.27 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2508144 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11751894 # Sum of mem lat for all requests +system.physmem.totBusLat 1970000 # Total cycles spent in databus access +system.physmem.totBankLat 7273750 # Total cycles spent in bank access +system.physmem.avgQLat 6365.85 # Average queueing delay per request +system.physmem.avgBankLat 18461.29 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 29827.14 # Average memory access latency +system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1888.27 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.80 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.79 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 14.37 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.86 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 319 # Number of row buffer hits during reads +system.physmem.readRowHits 294 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33747.46 # Average gap between requests +system.physmem.avgGap 34648.48 # Average gap between requests system.cpu.branchPred.lookups 2501 # Number of BP lookups system.cpu.branchPred.condPredicted 1795 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 485 # Number of conditional branches incorrect @@ -237,50 +237,50 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 26709 # number of cpu cycles simulated +system.cpu.numCycles 27419 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6895 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 994 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2651 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1627 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2216 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 2253 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1956 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12880 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.183618 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.594570 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.172963 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.585283 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10229 79.42% 79.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 225 1.75% 81.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.58% 82.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 224 1.74% 84.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 223 1.73% 86.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 273 2.12% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 95 0.74% 89.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 149 1.16% 90.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1259 9.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10346 79.60% 79.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 225 1.73% 81.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.56% 82.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 224 1.72% 84.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 223 1.72% 86.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 273 2.10% 88.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 95 0.73% 89.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 149 1.15% 90.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1259 9.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12880 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.093639 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.449661 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6875 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2529 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2444 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 12997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.091214 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.438017 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2562 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2445 # Number of cycles decode is running system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 389 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13347 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13349 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7140 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 7224 # Number of cycles rename is idle system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1992 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 2025 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2245 # Number of cycles rename is running system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 12580 # Number of instructions processed by rename @@ -302,28 +302,28 @@ system.cpu.memDep0.conflictingLoads 37 # Nu system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 11260 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8988 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8986 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 5240 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 14437 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12880 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.697826 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.403354 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12997 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.691390 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.397883 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9299 72.20% 72.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1308 10.16% 82.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 806 6.26% 88.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 539 4.18% 92.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 466 3.62% 96.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 270 2.10% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 122 0.95% 99.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9412 72.42% 72.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1312 10.09% 82.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 811 6.24% 88.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 535 4.12% 92.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 465 3.58% 96.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 270 2.08% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 122 0.94% 99.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.42% 99.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12880 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12997 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available @@ -359,50 +359,50 @@ system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5406 60.15% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5406 60.16% 60.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2347 26.12% 86.39% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1223 13.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8988 # Type of FU issued -system.cpu.iq.rate 0.336516 # Inst issue rate +system.cpu.iq.FU_type_0::total 8986 # Type of FU issued +system.cpu.iq.rate 0.327729 # Inst issue rate system.cpu.iq.fu_busy_cnt 228 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31164 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_rate 0.025373 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31277 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 16519 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8089 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 8090 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9196 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9194 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -430,42 +430,42 @@ system.cpu.iew.predictedTakenIncorrect 109 # Nu system.cpu.iew.predictedNotTakenIncorrect 275 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 8563 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 425 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 423 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3303 # number of memory reference insts executed -system.cpu.iew.exec_branches 1443 # Number of branches executed +system.cpu.iew.exec_refs 3302 # number of memory reference insts executed +system.cpu.iew.exec_branches 1444 # Number of branches executed system.cpu.iew.exec_stores 1167 # Number of stores executed -system.cpu.iew.exec_rate 0.320604 # Inst execution rate -system.cpu.iew.wb_sent 8264 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8105 # cumulative count of insts written-back +system.cpu.iew.exec_rate 0.312302 # Inst execution rate +system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8106 # cumulative count of insts written-back system.cpu.iew.wb_producers 3904 # num instructions producing a value system.cpu.iew.wb_consumers 7842 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.303456 # insts written-back per cycle +system.cpu.iew.wb_rate 0.295634 # insts written-back per cycle system.cpu.iew.wb_fanout 0.497832 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 5585 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 330 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11917 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.480742 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.314534 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12034 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.476068 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.308850 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9632 80.83% 80.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1071 8.99% 89.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 396 3.32% 93.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 259 2.17% 95.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 183 1.54% 96.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.44% 98.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 50 0.42% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.29% 99.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 119 1.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9748 81.00% 81.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1072 8.91% 89.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 397 3.30% 93.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 258 2.14% 95.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 183 1.52% 96.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.43% 98.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 50 0.42% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 119 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11917 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12034 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -478,117 +478,117 @@ system.cpu.commit.int_insts 4976 # Nu system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22955 # The number of ROB reads +system.cpu.rob.rob_reads 23072 # The number of ROB reads system.cpu.rob.rob_writes 23605 # The number of ROB writes system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 14422 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 5.817687 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.817687 # CPI: Total CPI of All Threads -system.cpu.ipc 0.171890 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.171890 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39368 # number of integer regfile reads -system.cpu.int_regfile_writes 8018 # number of integer regfile writes +system.cpu.cpi 5.972337 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.972337 # CPI: Total CPI of All Threads +system.cpu.ipc 0.167439 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.167439 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39366 # number of integer regfile reads +system.cpu.int_regfile_writes 8019 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.misc_regfile_reads 2982 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 147.647008 # Cycle average of tags in use -system.cpu.icache.total_refs 1597 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 146.913425 # Cycle average of tags in use +system.cpu.icache.total_refs 1596 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.487973 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.484536 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 147.647008 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072093 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072093 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1597 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1597 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1597 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1597 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1597 # number of overall hits -system.cpu.icache.overall_hits::total 1597 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses -system.cpu.icache.overall_misses::total 359 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17287500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17287500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17287500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17287500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17287500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17287500 # number of overall miss cycles +system.cpu.icache.occ_blocks::cpu.inst 146.913425 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071735 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071735 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1596 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1596 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1596 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1596 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1596 # number of overall hits +system.cpu.icache.overall_hits::total 1596 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses +system.cpu.icache.overall_misses::total 360 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17745500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17745500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17745500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17745500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17745500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17745500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1956 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1956 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 1956 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 1956 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1956 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183538 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.183538 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.183538 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.183538 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.183538 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.183538 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48154.596100 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48154.596100 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48154.596100 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48154.596100 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184049 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.184049 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.184049 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.184049 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.184049 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.184049 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49293.055556 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49293.055556 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49293.055556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49293.055556 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 124 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 62 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14218500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14218500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14218500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14218500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14218500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14218500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14592500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14592500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14592500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14592500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14592500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14592500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148773 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.148773 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.148773 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48860.824742 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48860.824742 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50146.048110 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50146.048110 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 185.926666 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 185.063220 # Cycle average of tags in use system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 139.061385 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.865282 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004244 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001430 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005674 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 138.360527 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.702693 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004222 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001425 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005648 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits @@ -609,17 +609,17 @@ system.cpu.l2cache.demand_misses::total 399 # nu system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 399 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13736500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18412500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13736500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6947500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20684000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13736500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6947500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20684000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14110500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4968000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19078500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2402500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2402500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14110500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7370500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21481000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14110500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7370500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21481000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -642,17 +642,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.910959 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.934708 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.910959 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50501.838235 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54372.093023 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51431.564246 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51839.598997 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51839.598997 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51876.838235 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57767.441860 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53291.899441 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58597.560976 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58597.560976 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53837.092732 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53837.092732 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -678,17 +678,17 @@ system.cpu.l2cache.demand_mshr_misses::total 394 system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319902 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455564 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13775466 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319902 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5220104 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15540006 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319902 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5220104 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15540006 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10736168 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756318 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492486 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896792 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896792 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10736168 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653110 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16389278 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10736168 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653110 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16389278 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses @@ -700,109 +700,109 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37940.816176 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42661.283951 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39023.983003 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39471.205882 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46374.296296 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41055.201133 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46263.219512 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46263.219512 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.800851 # Cycle average of tags in use -system.cpu.dcache.total_refs 2395 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use +system.cpu.dcache.total_refs 2392 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.404110 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.383562 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.800851 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021192 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021192 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.502557 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021119 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021119 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1764 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1764 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits -system.cpu.dcache.overall_hits::total 2373 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2370 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2370 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2370 # number of overall hits +system.cpu.dcache.overall_hits::total 2370 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 193 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 193 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses -system.cpu.dcache.overall_misses::total 498 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8139500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8139500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses +system.cpu.dcache.overall_misses::total 500 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8675500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8675500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14874500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14874500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23047000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1958 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1958 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 23550000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23550000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23550000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23550000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1957 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1957 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2871 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2871 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2871 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2871 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097549 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097549 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2870 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2870 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2870 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2870 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098620 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098620 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173459 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173459 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173459 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173459 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.174216 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.174216 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.174216 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.174216 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44950.777202 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 44950.777202 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.140065 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48451.140065 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47100 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47100 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 87 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 353 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 353 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 353 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 353 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -811,30 +811,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4926000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4926000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7239500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7239500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7239500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7239500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054137 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054137 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5218000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5218000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2444500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2444500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7662500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7662500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7662500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7662500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054165 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054165 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051202 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051202 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46471.698113 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46471.698113 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051220 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051220 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49226.415094 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49226.415094 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59621.951220 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59621.951220 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 7f0e6e36f..4baa76c40 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18578000 # Number of ticks simulated -final_tick 18578000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19339000 # Number of ticks simulated +final_tick 19339000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49489 # Simulator instruction rate (inst/s) -host_op_rate 49481 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 158085302 # Simulator tick rate (ticks/s) -host_mem_usage 270352 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 100636 # Simulator instruction rate (inst/s) +host_op_rate 100592 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 334460805 # Simulator tick rate (ticks/s) +host_mem_usage 224316 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20288 # Nu system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1092044354 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 475401012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1567445365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1092044354 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1092044354 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1092044354 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 475401012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1567445365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1049071824 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 456693728 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1505765551 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1049071824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1049071824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1049071824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 456693728 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1505765551 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 455 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 29120 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 60 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 53 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 5 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 89 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 45 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 5 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 37 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 18503000 # Total gap between requests +system.physmem.totGap 19292000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,9 +98,9 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 293 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2354454 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12658454 # Sum of mem lat for all requests -system.physmem.totBusLat 1820000 # Total cycles spent in databus access -system.physmem.totBankLat 8484000 # Total cycles spent in bank access -system.physmem.avgQLat 5174.62 # Average queueing delay per request -system.physmem.avgBankLat 18646.15 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27820.78 # Average memory access latency -system.physmem.avgRdBW 1567.45 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2650454 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13959204 # Sum of mem lat for all requests +system.physmem.totBusLat 2275000 # Total cycles spent in databus access +system.physmem.totBankLat 9033750 # Total cycles spent in bank access +system.physmem.avgQLat 5825.17 # Average queueing delay per request +system.physmem.avgBankLat 19854.40 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 30679.57 # Average memory access latency +system.physmem.avgRdBW 1505.77 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1567.45 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1505.77 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.80 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.68 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 11.76 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.72 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 357 # Number of row buffer hits during reads +system.physmem.readRowHits 334 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.46 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.41 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 40665.93 # Average gap between requests +system.physmem.avgGap 42400.00 # Average gap between requests system.cpu.branchPred.lookups 1154 # Number of BP lookups system.cpu.branchPred.condPredicted 858 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 603 # Number of conditional branches incorrect @@ -213,7 +213,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 37157 # number of cpu cycles simulated +system.cpu.numCycles 38679 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 429 # Number of Branches Predicted As Taken (True). @@ -235,12 +235,12 @@ system.cpu.execution_unit.executions 3135 # Nu system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9462 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9463 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 477 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 31782 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 5375 # Number of cycles cpu stages are processed. -system.cpu.activity 14.465646 # Percentage of cycles cpu is active +system.cpu.idleCycles 33303 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 5376 # Number of cycles cpu stages are processed. +system.cpu.activity 13.899015 # Percentage of cycles cpu is active system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed @@ -252,36 +252,36 @@ system.cpu.committedInsts 5814 # Nu system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) -system.cpu.cpi 6.390953 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.652735 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.390953 # CPI: Total CPI of All Threads -system.cpu.ipc 0.156471 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.652735 # CPI: Total CPI of All Threads +system.cpu.ipc 0.150314 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.156471 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 33508 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.150314 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 35030 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 3649 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 9.820491 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34341 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 9.434060 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 35863 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 2816 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.578653 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 34392 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.280436 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 35914 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 2765 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.441397 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 35931 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 7.148582 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 37453 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1226 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.299513 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 34255 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 3.169679 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 35777 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 2902 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.810103 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 7.502779 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 149.849185 # Cycle average of tags in use +system.cpu.icache.tagsinuse 149.398891 # Cycle average of tags in use system.cpu.icache.total_refs 428 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1.341693 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 149.849185 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.073169 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.073169 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 149.398891 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072949 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072949 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits @@ -294,12 +294,12 @@ system.cpu.icache.demand_misses::cpu.inst 346 # n system.cpu.icache.demand_misses::total 346 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 346 # number of overall misses system.cpu.icache.overall_misses::total 346 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18063500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18063500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18063500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18063500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18063500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18063500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18937500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18937500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18937500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18937500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18937500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18937500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 774 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 774 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 774 # number of demand (read+write) accesses @@ -312,12 +312,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.447028 system.cpu.icache.demand_miss_rate::total 0.447028 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.447028 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.447028 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52206.647399 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52206.647399 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52206.647399 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52206.647399 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52206.647399 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52206.647399 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54732.658960 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54732.658960 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54732.658960 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54732.658960 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54732.658960 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54732.658960 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -338,36 +338,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319 system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16468000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16468000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16468000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16468000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16468000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16468000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17329000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17329000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17329000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17329000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17329000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17329000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.412145 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.412145 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.412145 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51623.824451 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51623.824451 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51623.824451 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51623.824451 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51623.824451 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51623.824451 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54322.884013 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54322.884013 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54322.884013 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54322.884013 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54322.884013 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54322.884013 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 207.484772 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 206.866516 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 151.598539 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 55.886233 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004626 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001706 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006332 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 151.045976 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 55.820540 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001704 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006313 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -385,17 +385,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16122500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5062000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21184500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2564500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2564500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16122500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7626500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23749000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16122500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7626500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23749000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16983500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5162000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 22145500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2560500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2560500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16983500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7722500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24706000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16983500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7722500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24706000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -418,17 +418,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50859.621451 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58183.908046 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52436.881188 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50284.313725 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50284.313725 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50859.621451 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55264.492754 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52195.604396 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50859.621451 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55264.492754 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52195.604396 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53575.709779 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59333.333333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54815.594059 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50205.882353 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50205.882353 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53575.709779 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55960.144928 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54298.901099 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53575.709779 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55960.144928 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54298.901099 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -448,17 +448,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12118017 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3982594 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16100611 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1929572 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1929572 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12118017 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5912166 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18030183 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12118017 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5912166 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18030183 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13055529 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4090608 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17146137 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1925076 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1925076 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13055529 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6015684 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19071213 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13055529 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6015684 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19071213 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -470,27 +470,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38227.182965 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45776.942529 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39852.997525 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37834.745098 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37834.745098 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38227.182965 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42841.782609 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39626.775824 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38227.182965 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42841.782609 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39626.775824 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41184.634069 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47018.482759 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42440.933168 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37746.588235 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37746.588235 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41184.634069 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43591.913043 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41914.753846 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41184.634069 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43591.913043 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41914.753846 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.859083 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 89.917113 # Cycle average of tags in use system.cpu.dcache.total_refs 1644 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11.913043 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 89.859083 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021938 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021938 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 89.917113 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021952 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021952 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1070 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1070 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 574 # number of WriteReq hits @@ -507,14 +507,14 @@ system.cpu.dcache.demand_misses::cpu.data 444 # n system.cpu.dcache.demand_misses::total 444 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 444 # number of overall misses system.cpu.dcache.overall_misses::total 444 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5589500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5589500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14659500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14659500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20249000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20249000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20249000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20249000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5626500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5626500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14767500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14767500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20394000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20394000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20394000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20394000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -531,14 +531,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.212644 system.cpu.dcache.demand_miss_rate::total 0.212644 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.212644 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.212644 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60102.150538 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60102.150538 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41764.957265 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41764.957265 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45605.855856 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45605.855856 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45605.855856 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45605.855856 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60500 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60500 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42072.649573 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42072.649573 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45932.432432 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45932.432432 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45932.432432 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45932.432432 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -563,14 +563,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5155500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5155500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2618500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2618500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7774000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7774000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7774000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7774000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5255500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5255500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2614500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2614500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7870000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7870000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7870000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7870000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -579,14 +579,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59258.620690 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59258.620690 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51343.137255 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51343.137255 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56333.333333 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56333.333333 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56333.333333 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56333.333333 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60408.045977 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60408.045977 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51264.705882 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51264.705882 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57028.985507 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57028.985507 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57028.985507 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57028.985507 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 8a152a960..7feba62df 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16532500 # Number of ticks simulated -final_tick 16532500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17026500 # Number of ticks simulated +final_tick 17026500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36398 # Simulator instruction rate (inst/s) -host_op_rate 36393 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 116675957 # Simulator tick rate (ticks/s) -host_mem_usage 271376 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 76348 # Simulator instruction rate (inst/s) +host_op_rate 76319 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 251939378 # Simulator tick rate (ticks/s) +host_mem_usage 226380 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory -system.physmem.bytes_read::total 30464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1296839558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 545833963 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1842673522 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1296839558 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1296839558 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1296839558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 545833963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1842673522 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory +system.physmem.bytes_read::total 30592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory +system.physmem.num_reads::total 478 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1262972425 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 533756204 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1796728629 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1262972425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1262972425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1262972425 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 533756204 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1796728629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 478 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 476 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30464 # Total number of bytes read from memory +system.physmem.cpureqs 478 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30592 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30464 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30592 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 64 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 54 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 38 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 40 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 93 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 51 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 38 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 5 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 38 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16453500 # Total gap between requests +system.physmem.totGap 16967000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 476 # Categorize read packet sizes +system.physmem.readPktSize::6 478 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,36 +164,36 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2530972 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13086972 # Sum of mem lat for all requests -system.physmem.totBusLat 1904000 # Total cycles spent in databus access -system.physmem.totBankLat 8652000 # Total cycles spent in bank access -system.physmem.avgQLat 5317.17 # Average queueing delay per request -system.physmem.avgBankLat 18176.47 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27493.64 # Average memory access latency -system.physmem.avgRdBW 1842.67 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2863474 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 14617224 # Sum of mem lat for all requests +system.physmem.totBusLat 2390000 # Total cycles spent in databus access +system.physmem.totBankLat 9363750 # Total cycles spent in bank access +system.physmem.avgQLat 5990.53 # Average queueing delay per request +system.physmem.avgBankLat 19589.44 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 30579.97 # Average memory access latency +system.physmem.avgRdBW 1796.73 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1842.67 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1796.73 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.52 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.79 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 14.04 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.86 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 376 # Number of row buffer hits during reads +system.physmem.readRowHits 351 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.99 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.43 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34566.18 # Average gap between requests -system.cpu.branchPred.lookups 2120 # Number of BP lookups -system.cpu.branchPred.condPredicted 1453 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1651 # Number of BTB lookups -system.cpu.branchPred.BTBHits 517 # Number of BTB hits +system.physmem.avgGap 35495.82 # Average gap between requests +system.cpu.branchPred.lookups 2222 # Number of BP lookups +system.cpu.branchPred.condPredicted 1502 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 439 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1693 # Number of BTB lookups +system.cpu.branchPred.BTBHits 508 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.314355 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 258 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 30.005907 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 271 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -213,235 +213,236 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 33066 # number of cpu cycles simulated +system.cpu.numCycles 34054 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8642 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12896 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2120 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 775 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3199 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1339 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1070 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8765 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13389 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2222 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3272 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1401 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1014 # Number of cycles fetch has spent blocked system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1949 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 271 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13947 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.924643 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.229674 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2013 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14126 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.947827 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.258648 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10748 77.06% 77.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1351 9.69% 86.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 103 0.74% 87.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 137 0.98% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 291 2.09% 90.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 93 0.67% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 169 1.21% 92.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 155 1.11% 93.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 900 6.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10854 76.84% 76.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1348 9.54% 86.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 105 0.74% 87.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 135 0.96% 88.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 305 2.16% 90.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 118 0.84% 91.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 156 1.10% 92.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 160 1.13% 93.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 945 6.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13947 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064114 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.390008 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8777 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1236 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3037 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 46 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 851 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 137 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12081 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 166 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 851 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8957 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 360 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 762 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2904 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 113 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11654 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full -system.cpu.rename.LSQFullEvents 97 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7041 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13857 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13853 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 14126 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.065249 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.393170 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8860 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1239 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3094 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 44 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 889 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 168 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 44 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12497 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 889 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9042 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 324 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 804 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2958 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 109 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11987 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 93 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 7237 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14212 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 14208 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3643 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 17 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 265 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2476 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1198 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3839 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 276 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2483 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1201 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9172 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8209 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 55 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3542 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2140 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13947 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.588585 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.249847 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 9303 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 14 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8325 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3645 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2172 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14126 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.589339 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.255776 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10394 74.52% 74.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1403 10.06% 84.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 889 6.37% 90.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 554 3.97% 94.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 357 2.56% 97.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 219 1.57% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 88 0.63% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 29 0.21% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10546 74.66% 74.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1398 9.90% 84.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 898 6.36% 90.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 564 3.99% 94.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 360 2.55% 97.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 226 1.60% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 87 0.62% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 29 0.21% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 18 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13947 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14126 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 3.73% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 100 62.11% 65.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 55 34.16% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5 3.14% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 100 62.89% 66.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 54 33.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4835 58.90% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.06% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 58.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2260 27.53% 86.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1105 13.46% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4947 59.42% 59.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2263 27.18% 86.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1106 13.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8209 # Type of FU issued -system.cpu.iq.rate 0.248261 # Inst issue rate -system.cpu.iq.fu_busy_cnt 161 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019613 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30577 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12735 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7402 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8325 # Type of FU issued +system.cpu.iq.rate 0.244465 # Inst issue rate +system.cpu.iq.fu_busy_cnt 159 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019099 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30977 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12971 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7469 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8368 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8482 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1313 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1320 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 273 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 276 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 32 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 851 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 242 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10697 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2476 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1198 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 889 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 223 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10864 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 83 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2483 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1201 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 103 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 330 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 433 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7849 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2119 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 360 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 106 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 359 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7936 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2125 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 389 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1512 # number of nop insts executed -system.cpu.iew.exec_refs 3196 # number of memory reference insts executed -system.cpu.iew.exec_branches 1341 # Number of branches executed -system.cpu.iew.exec_stores 1077 # Number of stores executed -system.cpu.iew.exec_rate 0.237374 # Inst execution rate -system.cpu.iew.wb_sent 7488 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7404 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2925 # num instructions producing a value -system.cpu.iew.wb_consumers 4228 # num instructions consuming a value +system.cpu.iew.exec_nop 1547 # number of nop insts executed +system.cpu.iew.exec_refs 3203 # number of memory reference insts executed +system.cpu.iew.exec_branches 1355 # Number of branches executed +system.cpu.iew.exec_stores 1078 # Number of stores executed +system.cpu.iew.exec_rate 0.233042 # Inst execution rate +system.cpu.iew.wb_sent 7560 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7471 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2950 # num instructions producing a value +system.cpu.iew.wb_consumers 4259 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.223916 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.691816 # average fanout of values written-back +system.cpu.iew.wb_rate 0.219387 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692651 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4876 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5043 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 377 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13096 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.443876 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.229358 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13237 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.439148 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.223024 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10722 81.87% 81.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 944 7.21% 89.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 654 4.99% 94.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 320 2.44% 96.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 142 1.08% 97.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 103 0.79% 98.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 65 0.50% 98.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 40 0.31% 99.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106 0.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10853 81.99% 81.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 966 7.30% 89.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 635 4.80% 94.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 328 2.48% 96.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 148 1.12% 97.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 96 0.73% 98.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 63 0.48% 98.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.31% 99.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 107 0.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13096 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13237 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -452,69 +453,69 @@ system.cpu.commit.branches 915 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5111 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23666 # The number of ROB reads -system.cpu.rob.rob_writes 22238 # The number of ROB writes -system.cpu.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19119 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23973 # The number of ROB reads +system.cpu.rob.rob_writes 22610 # The number of ROB writes +system.cpu.timesIdled 288 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19928 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated -system.cpu.cpi 6.413111 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.413111 # CPI: Total CPI of All Threads -system.cpu.ipc 0.155931 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.155931 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10670 # number of integer regfile reads -system.cpu.int_regfile_writes 5185 # number of integer regfile writes +system.cpu.cpi 6.604732 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.604732 # CPI: Total CPI of All Threads +system.cpu.ipc 0.151407 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.151407 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10756 # number of integer regfile reads +system.cpu.int_regfile_writes 5239 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 147 # number of misc regfile reads +system.cpu.misc_regfile_reads 150 # number of misc regfile reads system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 163.159030 # Cycle average of tags in use -system.cpu.icache.total_refs 1502 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.443787 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 162.249914 # Cycle average of tags in use +system.cpu.icache.total_refs 1566 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.619469 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 163.159030 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.079667 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.079667 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1502 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1502 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1502 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1502 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1502 # number of overall hits -system.cpu.icache.overall_hits::total 1502 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 162.249914 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.079224 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.079224 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1566 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1566 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1566 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1566 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1566 # number of overall hits +system.cpu.icache.overall_hits::total 1566 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 447 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 447 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 447 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 447 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 447 # number of overall misses system.cpu.icache.overall_misses::total 447 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21475500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21475500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21475500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21475500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21475500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21475500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1949 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1949 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1949 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1949 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1949 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1949 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229348 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.229348 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.229348 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.229348 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.229348 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.229348 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48043.624161 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48043.624161 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48043.624161 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48043.624161 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48043.624161 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48043.624161 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 22381500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 22381500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 22381500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 22381500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 22381500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 22381500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2013 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2013 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2013 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2013 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2013 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2013 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.222057 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.222057 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.222057 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.222057 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.222057 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.222057 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50070.469799 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 50070.469799 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 50070.469799 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 50070.469799 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 50070.469799 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 50070.469799 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -523,109 +524,109 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 6 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 109 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 109 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 109 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 109 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 109 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 109 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16956000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16956000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16956000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16956000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16956000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16956000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.173422 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.173422 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.173422 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.173422 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.173422 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.173422 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50165.680473 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50165.680473 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50165.680473 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50165.680473 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50165.680473 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50165.680473 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 339 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 339 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17822000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17822000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17822000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17822000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17822000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17822000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.168405 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.168405 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.168405 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.168405 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.168405 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.168405 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52572.271386 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52572.271386 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52572.271386 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52572.271386 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52572.271386 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52572.271386 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 223.797313 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 222.426618 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 425 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.007059 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 427 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.007026 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 165.672562 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 58.124752 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005056 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001774 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006830 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 164.638321 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 57.788297 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005024 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001764 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006788 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits system.cpu.l2cache.overall_hits::total 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 90 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 425 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 336 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 427 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 476 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses -system.cpu.l2cache.overall_misses::total 476 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16588000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5450000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 22038000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2702000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2702000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16588000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8152000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24740000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16588000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8152000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24740000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 428 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 336 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 478 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 336 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses +system.cpu.l2cache.overall_misses::total 478 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17452500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5919000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 23371500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2657000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2657000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 17452500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8576000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 26028500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 17452500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8576000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26028500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 339 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 430 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 479 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 338 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 479 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991124 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 339 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 481 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 339 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 481 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991150 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.992991 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.993023 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991124 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991150 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.993737 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.993763 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991150 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.993737 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49516.417910 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60555.555556 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51854.117647 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52980.392157 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52980.392157 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49516.417910 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57815.602837 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51974.789916 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49516.417910 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57815.602837 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51974.789916 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.993763 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51941.964286 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65043.956044 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54734.192037 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52098.039216 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52098.039216 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51941.964286 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60394.366197 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54452.928870 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51941.964286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60394.366197 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54452.928870 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -634,156 +635,156 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 336 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 427 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 476 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 476 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12365045 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4341573 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16706618 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2071054 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2071054 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12365045 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6412627 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18777672 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12365045 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6412627 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18777672 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 336 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 478 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 478 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13273303 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4804087 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18077390 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2032056 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2032056 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13273303 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6836143 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20109446 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13273303 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6836143 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20109446 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.992991 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993023 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.993737 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.993763 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.993737 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36910.582090 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48239.700000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39309.689412 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40608.901961 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40608.901961 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36910.582090 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 45479.624113 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39448.890756 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36910.582090 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 45479.624113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39448.890756 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.993763 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39503.877976 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52792.164835 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42335.807963 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39844.235294 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39844.235294 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39503.877976 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48141.852113 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42069.970711 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39503.877976 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48141.852113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42069.970711 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 92.017211 # Cycle average of tags in use -system.cpu.dcache.total_refs 2420 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 17.163121 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 91.642501 # Cycle average of tags in use +system.cpu.dcache.total_refs 2424 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 17.070423 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 92.017211 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022465 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022465 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1848 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1848 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 91.642501 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022374 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022374 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1852 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1852 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 572 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2420 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2420 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2420 # number of overall hits -system.cpu.dcache.overall_hits::total 2420 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 151 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 151 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2424 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2424 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2424 # number of overall hits +system.cpu.dcache.overall_hits::total 2424 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 353 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 353 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 504 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 504 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 504 # number of overall misses -system.cpu.dcache.overall_misses::total 504 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8905500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8905500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15603499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15603499 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24508999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24508999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24508999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24508999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1999 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1999 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 501 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 501 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 501 # number of overall misses +system.cpu.dcache.overall_misses::total 501 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9019500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9019500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15098999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15098999 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24118499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24118499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24118499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24118499 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2000 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2000 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2924 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2924 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2924 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2924 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075538 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.075538 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2925 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2925 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2925 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2925 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074000 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.074000 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.172367 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.172367 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.172367 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.172367 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58976.821192 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58976.821192 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44202.546742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44202.546742 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48628.966270 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48628.966270 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48628.966270 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48628.966270 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.171282 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.171282 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.171282 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.171282 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60942.567568 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60942.567568 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42773.368272 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42773.368272 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 48140.716567 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 48140.716567 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 48140.716567 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 48140.716567 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 488 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.636364 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.363636 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 363 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 363 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 363 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 363 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 359 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 359 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 359 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 359 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5543500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5543500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2753999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2753999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8297499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8297499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8297499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8297499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6013500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6013500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2708999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2708999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8722499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8722499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8722499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8722499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045500 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045500 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048222 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048222 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048222 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048222 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61594.444444 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61594.444444 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53999.980392 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53999.980392 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58847.510638 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58847.510638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58847.510638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58847.510638 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048547 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048547 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048547 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048547 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66082.417582 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66082.417582 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53117.627451 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53117.627451 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61426.049296 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61426.049296 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61426.049296 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61426.049296 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 2fa72cd37..ccc0289be 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 14065500 # Number of ticks simulated -final_tick 14065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000015 # Number of seconds simulated +sim_ticks 14724500 # Number of ticks simulated +final_tick 14724500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 44313 # Simulator instruction rate (inst/s) -host_op_rate 44306 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 107578636 # Simulator tick rate (ticks/s) -host_mem_usage 267272 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 87376 # Simulator instruction rate (inst/s) +host_op_rate 87343 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 221965921 # Simulator tick rate (ticks/s) +host_mem_usage 222644 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 22080 # Nu system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1569798443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 459564182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2029362625 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1569798443 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1569798443 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1569798443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 459564182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2029362625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1499541580 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 438996231 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1938537811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1499541580 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1499541580 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1499541580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 438996231 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1938537811 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 446 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 446 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 28544 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 64 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 49 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 38 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 56 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 18 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 52 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 19 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13958000 # Total gap between requests +system.physmem.totGap 14617000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,34 +164,34 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1923944 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11085944 # Sum of mem lat for all requests -system.physmem.totBusLat 1784000 # Total cycles spent in databus access -system.physmem.totBankLat 7378000 # Total cycles spent in bank access -system.physmem.avgQLat 4313.78 # Average queueing delay per request -system.physmem.avgBankLat 16542.60 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24856.38 # Average memory access latency -system.physmem.avgRdBW 2029.36 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2286195 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12779945 # Sum of mem lat for all requests +system.physmem.totBusLat 2230000 # Total cycles spent in databus access +system.physmem.totBankLat 8263750 # Total cycles spent in bank access +system.physmem.avgQLat 5126.00 # Average queueing delay per request +system.physmem.avgBankLat 18528.59 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 28654.59 # Average memory access latency +system.physmem.avgRdBW 1938.54 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2029.36 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1938.54 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.68 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.79 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 15.14 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.87 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 369 # Number of row buffer hits during reads +system.physmem.readRowHits 338 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.74 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.78 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 31295.96 # Average gap between requests -system.cpu.branchPred.lookups 2247 # Number of BP lookups -system.cpu.branchPred.condPredicted 1810 # Number of conditional branches predicted +system.physmem.avgGap 32773.54 # Average gap between requests +system.cpu.branchPred.lookups 2226 # Number of BP lookups +system.cpu.branchPred.condPredicted 1794 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1863 # Number of BTB lookups -system.cpu.branchPred.BTBHits 602 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1842 # Number of BTB lookups +system.cpu.branchPred.BTBHits 599 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.313473 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 32.519001 # BTB Hit Percentage system.cpu.branchPred.usedRAS 198 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits @@ -213,234 +213,234 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 28132 # number of cpu cycles simulated +system.cpu.numCycles 29450 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7398 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13218 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2247 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 800 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2267 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1136 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1813 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 307 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11663 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.133328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.550093 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7445 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13075 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2226 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 797 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2246 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1279 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1007 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1802 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 309 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11548 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.132231 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.547600 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9396 80.56% 80.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 175 1.50% 82.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 176 1.51% 83.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 142 1.22% 84.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 227 1.95% 86.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 132 1.13% 87.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 257 2.20% 90.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 109 0.93% 91.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1049 8.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9302 80.55% 80.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 175 1.52% 82.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 174 1.51% 83.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 140 1.21% 84.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 227 1.97% 86.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 132 1.14% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 256 2.22% 90.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 108 0.94% 91.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1034 8.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11663 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.079873 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.469856 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7468 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1305 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2099 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 709 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 342 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 156 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11753 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 11548 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.075586 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.443973 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7511 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1178 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2083 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 697 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 338 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 11641 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 431 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7658 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 585 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 451 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1983 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 277 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11310 # Number of instructions processed by rename +system.cpu.rename.SquashCycles 697 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7696 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 476 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 449 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1969 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 261 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11203 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 233 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 9699 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18197 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18142 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 218 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 9614 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18041 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17986 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4701 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4616 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 580 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2014 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1829 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10303 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 553 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1993 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 53 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10211 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8959 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 188 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4243 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3419 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8907 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 171 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4167 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3342 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11663 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.768156 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.499073 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11548 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.771302 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.502142 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8296 71.13% 71.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1090 9.35% 80.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 795 6.82% 87.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 496 4.25% 91.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 466 4.00% 95.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 308 2.64% 98.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 133 1.14% 99.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 43 0.37% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 36 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8209 71.09% 71.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1071 9.27% 80.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 791 6.85% 87.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 496 4.30% 91.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 466 4.04% 95.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 302 2.62% 98.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 134 1.16% 99.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 44 0.38% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 35 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11663 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11548 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 4.60% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 71 40.80% 45.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 95 54.60% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 4.68% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 69 40.35% 45.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 94 54.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5501 61.40% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1805 20.15% 81.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1651 18.43% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5470 61.41% 61.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1795 20.15% 81.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1640 18.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8959 # Type of FU issued -system.cpu.iq.rate 0.318463 # Inst issue rate -system.cpu.iq.fu_busy_cnt 174 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019422 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29881 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14574 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8164 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8907 # Type of FU issued +system.cpu.iq.rate 0.302445 # Inst issue rate +system.cpu.iq.fu_busy_cnt 171 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019198 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29642 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14405 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8122 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9099 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9044 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1053 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1032 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 783 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 757 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 709 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 370 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10360 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 697 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 276 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10268 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 55 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2014 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1829 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 1993 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 264 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 330 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8539 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1683 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 420 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 329 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8492 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1673 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 415 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3224 # number of memory reference insts executed -system.cpu.iew.exec_branches 1354 # Number of branches executed -system.cpu.iew.exec_stores 1541 # Number of stores executed -system.cpu.iew.exec_rate 0.303533 # Inst execution rate -system.cpu.iew.wb_sent 8307 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8191 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4222 # num instructions producing a value -system.cpu.iew.wb_consumers 6683 # num instructions consuming a value +system.cpu.iew.exec_refs 3204 # number of memory reference insts executed +system.cpu.iew.exec_branches 1349 # Number of branches executed +system.cpu.iew.exec_stores 1531 # Number of stores executed +system.cpu.iew.exec_rate 0.288353 # Inst execution rate +system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8149 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4198 # num instructions producing a value +system.cpu.iew.wb_consumers 6619 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.291163 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.631752 # average fanout of values written-back +system.cpu.iew.wb_rate 0.276706 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.634235 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4574 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4482 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10954 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.528757 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.330367 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 10851 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.533776 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.333108 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8576 78.29% 78.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1000 9.13% 87.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 620 5.66% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 265 2.42% 95.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 172 1.57% 97.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 106 0.97% 98.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 68 0.62% 98.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 45 0.41% 99.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102 0.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8471 78.07% 78.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 999 9.21% 87.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 620 5.71% 92.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 267 2.46% 95.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 174 1.60% 97.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 109 1.00% 98.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 67 0.62% 98.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 43 0.40% 99.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101 0.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10954 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10851 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -451,118 +451,118 @@ system.cpu.commit.branches 1037 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5698 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21218 # The number of ROB reads -system.cpu.rob.rob_writes 21442 # The number of ROB writes -system.cpu.timesIdled 246 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16469 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21024 # The number of ROB reads +system.cpu.rob.rob_writes 21246 # The number of ROB writes +system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17902 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated -system.cpu.cpi 4.857044 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.857044 # CPI: Total CPI of All Threads -system.cpu.ipc 0.205887 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.205887 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13537 # number of integer regfile reads -system.cpu.int_regfile_writes 7068 # number of integer regfile writes +system.cpu.cpi 5.084599 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.084599 # CPI: Total CPI of All Threads +system.cpu.ipc 0.196672 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.196672 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13466 # number of integer regfile reads +system.cpu.int_regfile_writes 7036 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 168.326770 # Cycle average of tags in use -system.cpu.icache.total_refs 1375 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 167.837630 # Cycle average of tags in use +system.cpu.icache.total_refs 1361 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.917379 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.877493 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 168.326770 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.082191 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.082191 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1375 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1375 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1375 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1375 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1375 # number of overall hits -system.cpu.icache.overall_hits::total 1375 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 438 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 438 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 438 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 438 # number of overall misses -system.cpu.icache.overall_misses::total 438 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20259000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20259000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20259000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20259000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20259000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20259000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1813 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1813 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1813 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1813 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1813 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1813 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.241589 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.241589 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.241589 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.241589 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.241589 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.241589 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46253.424658 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46253.424658 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46253.424658 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46253.424658 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46253.424658 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46253.424658 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 208 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 167.837630 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.081952 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.081952 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1361 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1361 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1361 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1361 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1361 # number of overall hits +system.cpu.icache.overall_hits::total 1361 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 441 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 441 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 441 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 441 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 441 # number of overall misses +system.cpu.icache.overall_misses::total 441 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21881500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21881500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21881500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21881500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21881500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21881500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1802 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1802 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1802 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1802 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1802 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1802 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.244728 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.244728 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.244728 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.244728 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.244728 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.244728 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49617.913832 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49617.913832 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49617.913832 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49617.913832 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49617.913832 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49617.913832 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 210 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 52 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 52.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 87 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 87 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 87 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 87 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 90 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 90 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 90 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16770000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16770000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16770000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16770000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16770000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16770000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193602 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.193602 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.193602 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47777.777778 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47777.777778 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47777.777778 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 47777.777778 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47777.777778 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 47777.777778 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17781500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17781500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17781500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17781500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17781500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17781500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.194784 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.194784 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.194784 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.194784 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.194784 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.194784 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50659.544160 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50659.544160 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50659.544160 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50659.544160 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50659.544160 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50659.544160 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 198.645596 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 198.145802 # Cycle average of tags in use system.cpu.l2cache.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.017544 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 167.286173 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.359424 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005105 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 166.786148 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.359654 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005090 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000957 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006062 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006047 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits @@ -583,17 +583,17 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16358500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2981000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19339500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2766000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2766000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16358500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 5747000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22105500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16358500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 5747000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22105500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17370000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3170500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 20540500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2908000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2908000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 17370000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6078500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23448500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 17370000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6078500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23448500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -616,17 +616,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.984547 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47415.942029 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55203.703704 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 48469.924812 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58851.063830 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58851.063830 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47415.942029 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56900.990099 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 49563.901345 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47415.942029 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56900.990099 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 49563.901345 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50347.826087 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58712.962963 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51479.949875 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61872.340426 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61872.340426 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50347.826087 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60183.168317 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52575.112108 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50347.826087 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60183.168317 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52575.112108 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -646,17 +646,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12035515 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2315048 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14350563 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2187044 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2187044 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12035515 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4502092 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16537607 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12035515 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4502092 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16537607 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13081037 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2509304 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15590341 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2332794 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2332794 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13081037 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4842098 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17923135 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13081037 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4842098 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17923135 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses @@ -668,91 +668,91 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34885.550725 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42871.259259 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35966.323308 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46532.851064 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46532.851064 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34885.550725 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44575.168317 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37079.836323 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34885.550725 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44575.168317 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37079.836323 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37916.049275 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46468.592593 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39073.536341 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49633.914894 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49633.914894 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37916.049275 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47941.564356 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40186.401345 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37916.049275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47941.564356 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40186.401345 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 63.407702 # Cycle average of tags in use -system.cpu.dcache.total_refs 2190 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 63.324462 # Cycle average of tags in use +system.cpu.dcache.total_refs 2181 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 21.470588 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 21.382353 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 63.407702 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.015480 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.015480 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1475 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1475 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2190 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2190 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2190 # number of overall hits -system.cpu.dcache.overall_hits::total 2190 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 435 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses -system.cpu.dcache.overall_misses::total 435 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5222000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5222000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14128997 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14128997 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19350997 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19350997 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19350997 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19350997 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1579 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1579 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 63.324462 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.015460 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.015460 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1472 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1472 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 709 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 709 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2181 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2181 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2181 # number of overall hits +system.cpu.dcache.overall_hits::total 2181 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 101 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 101 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 337 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 337 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 438 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 438 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 438 # number of overall misses +system.cpu.dcache.overall_misses::total 438 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5160500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5160500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14813997 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14813997 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19974497 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19974497 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19974497 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19974497 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1573 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1573 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2625 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2625 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2625 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2625 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065864 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.065864 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.165714 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.165714 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.165714 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.165714 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50211.538462 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50211.538462 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42685.791541 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42685.791541 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 44485.050575 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 44485.050575 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 44485.050575 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 44485.050575 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 414 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2619 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2619 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2619 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2619 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064209 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.064209 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.322180 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.322180 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.167239 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.167239 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.167239 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.167239 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51094.059406 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51094.059406 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43958.448071 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43958.448071 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45603.874429 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45603.874429 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45603.874429 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45603.874429 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 419 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 82.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.800000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 46 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 290 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 290 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 336 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 336 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 336 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 336 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses @@ -761,30 +761,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3046500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3046500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2815499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2815499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5861999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5861999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5861999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5861999 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034832 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034832 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3236000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3236000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2957499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2957499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6193499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6193499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6193499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6193499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034965 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034965 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038857 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.038857 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038857 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.038857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55390.909091 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55390.909091 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59904.234043 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59904.234043 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57470.578431 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57470.578431 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57470.578431 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57470.578431 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038946 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.038946 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038946 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.038946 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58836.363636 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58836.363636 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62925.510638 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62925.510638 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60720.578431 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60720.578431 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60720.578431 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60720.578431 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 0a19f6727..a586f3039 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16286500 # Number of ticks simulated -final_tick 16286500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 16783500 # Number of ticks simulated +final_tick 16783500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 32843 # Simulator instruction rate (inst/s) -host_op_rate 32839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 100387600 # Simulator tick rate (ticks/s) -host_mem_usage 278524 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 84096 # Simulator instruction rate (inst/s) +host_op_rate 84062 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 264753473 # Simulator tick rate (ticks/s) +host_mem_usage 230292 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1135664507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 526571086 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1662235594 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1135664507 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1135664507 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1135664507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 526571086 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1662235594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1102034736 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 510978044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1613012780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1102034736 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1102034736 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1102034736 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 510978044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1613012780 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 423 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 27072 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 37 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 5 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 11 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 5 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 40 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 59 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 62 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 25 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 54 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 46 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 46 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 14 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 34 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 71 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16235000 # Total gap between requests +system.physmem.totGap 16708000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 254 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2302422 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11302422 # Sum of mem lat for all requests -system.physmem.totBusLat 1692000 # Total cycles spent in databus access -system.physmem.totBankLat 7308000 # Total cycles spent in bank access -system.physmem.avgQLat 5443.08 # Average queueing delay per request -system.physmem.avgBankLat 17276.60 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26719.67 # Average memory access latency -system.physmem.avgRdBW 1662.24 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2673172 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12996922 # Sum of mem lat for all requests +system.physmem.totBusLat 2115000 # Total cycles spent in databus access +system.physmem.totBankLat 8208750 # Total cycles spent in bank access +system.physmem.avgQLat 6319.56 # Average queueing delay per request +system.physmem.avgBankLat 19406.03 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 30725.58 # Average memory access latency +system.physmem.avgRdBW 1613.01 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1662.24 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1613.01 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 10.39 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.69 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 12.60 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.77 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 336 # Number of row buffer hits during reads +system.physmem.readRowHits 300 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.43 # Row buffer hit rate for reads +system.physmem.readRowHitRate 70.92 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 38380.61 # Average gap between requests +system.physmem.avgGap 39498.82 # Average gap between requests system.cpu.branchPred.lookups 1636 # Number of BP lookups system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect @@ -195,14 +195,14 @@ system.cpu.branchPred.BTBHitPct 43.484736 # BT system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 32574 # number of cpu cycles simulated +system.cpu.numCycles 33568 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 985 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5612 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 5611 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9600 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9599 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File @@ -217,12 +217,12 @@ system.cpu.execution_unit.executions 3957 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9655 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9656 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 478 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26327 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6247 # Number of cycles cpu stages are processed. -system.cpu.activity 19.177872 # Percentage of cycles cpu is active +system.cpu.timesIdled 481 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27323 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6245 # Number of cycles cpu stages are processed. +system.cpu.activity 18.604028 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -234,36 +234,36 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 6.114886 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.301483 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.114886 # CPI: Total CPI of All Threads -system.cpu.ipc 0.163535 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.301483 # CPI: Total CPI of All Threads +system.cpu.ipc 0.158693 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.163535 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27935 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.158693 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 28929 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4639 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 14.241420 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 29377 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 13.819709 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 30371 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3197 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 9.814576 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 29541 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 9.523951 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 30535 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.311107 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 31599 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 9.035391 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 32593 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.993185 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29417 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.904552 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 30411 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 9.691779 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 9.404790 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 143.423519 # Cycle average of tags in use +system.cpu.icache.tagsinuse 141.185042 # Cycle average of tags in use system.cpu.icache.total_refs 895 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 3.075601 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 143.423519 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.070031 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.070031 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 141.185042 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.068938 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.068938 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 895 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 895 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 895 # number of demand (read+write) hits @@ -276,12 +276,12 @@ system.cpu.icache.demand_misses::cpu.inst 362 # n system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses system.cpu.icache.overall_misses::total 362 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18347500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18347500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18347500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18347500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18347500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18347500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18996500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18996500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18996500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18996500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18996500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18996500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1257 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1257 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1257 # number of demand (read+write) accesses @@ -294,12 +294,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.287987 system.cpu.icache.demand_miss_rate::total 0.287987 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.287987 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.287987 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50683.701657 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 50683.701657 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 50683.701657 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 50683.701657 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 50683.701657 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 50683.701657 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52476.519337 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52476.519337 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52476.519337 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52476.519337 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52476.519337 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52476.519337 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -320,36 +320,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15194000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15194000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15194000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15194000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15194000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15194000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15423000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15423000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15423000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15423000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15423000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15423000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231504 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.231504 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.231504 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52213.058419 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52213.058419 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52213.058419 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52213.058419 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 170.006396 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 167.397199 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 142.886606 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 27.119790 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004361 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000828 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005188 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 140.660988 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.736211 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004293 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000816 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005109 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -370,17 +370,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14875500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2872500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17748000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4069000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4069000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14875500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6941500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21817000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14875500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6941500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21817000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15104500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3320000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18424500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4710000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4710000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15104500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8030000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23134500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15104500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8030000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23134500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -403,17 +403,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51472.318339 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54198.113208 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51894.736842 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50234.567901 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50234.567901 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51472.318339 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51802.238806 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51576.832151 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51472.318339 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51802.238806 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51576.832151 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52264.705882 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62641.509434 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53872.807018 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58148.148148 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58148.148148 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52264.705882 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59925.373134 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54691.489362 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52264.705882 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59925.373134 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54691.489362 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -433,17 +433,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11236437 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2207572 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13444009 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3066068 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3066068 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11236437 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5273640 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16510077 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11236437 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5273640 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16510077 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11527456 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2665331 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14192787 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3719824 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3719824 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11527456 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6385155 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17912611 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11527456 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6385155 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17912611 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -455,27 +455,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38880.404844 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41652.301887 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39309.967836 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37852.691358 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37852.691358 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38880.404844 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39355.522388 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39030.914894 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38880.404844 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39355.522388 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39030.914894 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39887.391003 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50289.264151 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41499.377193 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45923.753086 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45923.753086 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39887.391003 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47650.410448 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42346.598109 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39887.391003 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47650.410448 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42346.598109 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 85.216900 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 84.137936 # Cycle average of tags in use system.cpu.dcache.total_refs 914 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 6.770370 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 85.216900 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020805 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020805 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 84.137936 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020541 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020541 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits @@ -492,14 +492,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3347000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3347000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19183000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19183000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22530000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22530000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22530000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22530000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3818500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3818500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21812000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21812000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 25630500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 25630500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 25630500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 25630500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -516,19 +516,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54868.852459 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54868.852459 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46447.941889 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46447.941889 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47531.645570 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47531.645570 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 405 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62598.360656 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62598.360656 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52813.559322 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52813.559322 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54072.784810 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54072.784810 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54072.784810 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54072.784810 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 557 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.656250 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.406250 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -548,14 +548,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2939000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2939000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4152500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4152500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7091500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7091500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7091500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7091500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3386500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3386500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4793500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4793500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8180000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8180000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8180000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8180000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -564,14 +564,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54425.925926 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54425.925926 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51265.432099 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51265.432099 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62712.962963 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62712.962963 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59179.012346 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59179.012346 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60592.592593 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60592.592593 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60592.592593 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60592.592593 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 44632e460..b6a3a3279 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000015 # Number of seconds simulated -sim_ticks 15014000 # Number of ticks simulated -final_tick 15014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 15468000 # Number of ticks simulated +final_tick 15468000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24822 # Simulator instruction rate (inst/s) -host_op_rate 44962 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69258779 # Simulator tick rate (ticks/s) -host_mem_usage 286624 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 31666 # Simulator instruction rate (inst/s) +host_op_rate 57357 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 91020367 # Simulator tick rate (ticks/s) +host_mem_usage 241544 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9746 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory @@ -19,39 +19,39 @@ system.physmem.bytes_inst_read::total 19392 # Nu system.physmem.num_reads::cpu.inst 303 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory system.physmem.num_reads::total 449 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1291594512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 622352471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1913946983 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1291594512 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1291594512 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1291594512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 622352471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1913946983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 450 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 1253685027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 604085855 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1857770882 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1253685027 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1253685027 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1253685027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 604085855 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1857770882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 451 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 450 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 451 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 28736 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 28736 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 41 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 55 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 52 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 49 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 14 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 34 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 41 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 5 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 26 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 14993500 # Total gap between requests +system.physmem.totGap 15452000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 450 # Categorize read packet sizes +system.physmem.readPktSize::6 451 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,10 +98,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 231 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -164,266 +164,266 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1656450 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12024450 # Sum of mem lat for all requests -system.physmem.totBusLat 1800000 # Total cycles spent in databus access -system.physmem.totBankLat 8568000 # Total cycles spent in bank access -system.physmem.avgQLat 3681.00 # Average queueing delay per request -system.physmem.avgBankLat 19040.00 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26721.00 # Average memory access latency -system.physmem.avgRdBW 1913.95 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 1899951 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13161201 # Sum of mem lat for all requests +system.physmem.totBusLat 2255000 # Total cycles spent in databus access +system.physmem.totBankLat 9006250 # Total cycles spent in bank access +system.physmem.avgQLat 4212.75 # Average queueing delay per request +system.physmem.avgBankLat 19969.51 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 29182.26 # Average memory access latency +system.physmem.avgRdBW 1857.77 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1913.95 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1857.77 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.96 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.80 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 14.51 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.85 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 352 # Number of row buffer hits during reads +system.physmem.readRowHits 333 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.22 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33318.89 # Average gap between requests -system.cpu.branchPred.lookups 3018 # Number of BP lookups -system.cpu.branchPred.condPredicted 3018 # Number of conditional branches predicted +system.physmem.avgGap 34261.64 # Average gap between requests +system.cpu.branchPred.lookups 2995 # Number of BP lookups +system.cpu.branchPred.condPredicted 2995 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 546 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2500 # Number of BTB lookups -system.cpu.branchPred.BTBHits 796 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2485 # Number of BTB lookups +system.cpu.branchPred.BTBHits 793 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.840000 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 31.911469 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 30029 # number of cpu cycles simulated +system.cpu.numCycles 30937 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8963 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14512 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3018 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 796 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3937 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2417 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3663 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 144 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 8904 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14405 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2995 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 793 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3911 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2416 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3684 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 178 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1881 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 288 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 18583 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.378787 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.879591 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1874 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 18552 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.371173 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.873073 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 14745 79.35% 79.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 189 1.02% 80.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 157 0.84% 81.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 193 1.04% 82.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 162 0.87% 83.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 171 0.92% 84.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 265 1.43% 85.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 161 0.87% 86.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2540 13.67% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 14740 79.45% 79.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 189 1.02% 80.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 154 0.83% 81.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 193 1.04% 82.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 163 0.88% 83.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 168 0.91% 84.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 265 1.43% 85.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 160 0.86% 86.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2520 13.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 18583 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.100503 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.483266 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9455 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3616 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3547 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1830 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24452 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1830 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9798 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2386 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 485 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3325 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 759 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22970 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 18552 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.096810 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.465624 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9434 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3628 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3523 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 144 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1823 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24308 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1823 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9778 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2398 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 477 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3309 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 767 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22819 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 39 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 640 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 25107 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 55203 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 55187 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 651 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 24896 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 54742 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 54726 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11061 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14046 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 13835 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 31 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2021 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2205 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1757 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 2054 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2204 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1750 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20458 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 20351 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 35 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17350 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 213 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9975 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13877 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 17307 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 209 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9863 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13657 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 23 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 18583 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.933649 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.794423 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 18552 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.932891 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.792260 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13202 71.04% 71.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1385 7.45% 78.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1043 5.61% 84.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 691 3.72% 87.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 742 3.99% 91.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 623 3.35% 95.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 598 3.22% 98.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 257 1.38% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13164 70.96% 70.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1399 7.54% 78.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1053 5.68% 84.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 693 3.74% 87.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 728 3.92% 91.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 621 3.35% 95.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 594 3.20% 98.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 258 1.39% 99.77% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 42 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 18583 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 18552 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 138 77.53% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19 10.67% 88.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 21 11.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 134 76.57% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 20 11.43% 88.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 21 12.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13964 80.48% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1899 10.95% 91.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1483 8.55% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13916 80.41% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1905 11.01% 91.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1482 8.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17350 # Type of FU issued -system.cpu.iq.rate 0.577775 # Inst issue rate -system.cpu.iq.fu_busy_cnt 178 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010259 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 53666 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 30475 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16004 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17307 # Type of FU issued +system.cpu.iq.rate 0.559427 # Inst issue rate +system.cpu.iq.fu_busy_cnt 175 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010112 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 53542 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 30256 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15949 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17520 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17474 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 158 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 160 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1153 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1152 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 822 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 815 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1830 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1703 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1823 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1705 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20493 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 20386 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 33 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2205 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1757 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2204 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1750 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 601 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 657 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16426 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1777 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 924 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 607 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 663 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16378 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1780 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 929 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3141 # number of memory reference insts executed -system.cpu.iew.exec_branches 1630 # Number of branches executed -system.cpu.iew.exec_stores 1364 # Number of stores executed -system.cpu.iew.exec_rate 0.547005 # Inst execution rate -system.cpu.iew.wb_sent 16198 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16008 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10179 # num instructions producing a value -system.cpu.iew.wb_consumers 15729 # num instructions consuming a value +system.cpu.iew.exec_refs 3145 # number of memory reference insts executed +system.cpu.iew.exec_branches 1625 # Number of branches executed +system.cpu.iew.exec_stores 1365 # Number of stores executed +system.cpu.iew.exec_rate 0.529398 # Inst execution rate +system.cpu.iew.wb_sent 16147 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15953 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10136 # num instructions producing a value +system.cpu.iew.wb_consumers 15661 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.533085 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.647149 # average fanout of values written-back +system.cpu.iew.wb_rate 0.515661 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.647213 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10746 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10639 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 566 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 16753 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.581747 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.458276 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 572 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 16729 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.582581 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.458500 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 13224 78.94% 78.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1319 7.87% 86.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 595 3.55% 90.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 710 4.24% 94.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 351 2.10% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 138 0.82% 97.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 120 0.72% 98.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 75 0.45% 98.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 13195 78.88% 78.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1327 7.93% 86.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 594 3.55% 90.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 704 4.21% 94.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 355 2.12% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 141 0.84% 97.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 118 0.71% 98.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 74 0.44% 98.68% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 221 1.32% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 16753 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 16729 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9746 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -436,71 +436,71 @@ system.cpu.commit.int_insts 9652 # Nu system.cpu.commit.function_calls 0 # Number of function calls committed. system.cpu.commit.bw_lim_events 221 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 37024 # The number of ROB reads -system.cpu.rob.rob_writes 42843 # The number of ROB writes -system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11446 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 36893 # The number of ROB reads +system.cpu.rob.rob_writes 42622 # The number of ROB writes +system.cpu.timesIdled 155 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 12385 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9746 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 5.581599 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.581599 # CPI: Total CPI of All Threads -system.cpu.ipc 0.179160 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.179160 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 28877 # number of integer regfile reads -system.cpu.int_regfile_writes 17233 # number of integer regfile writes +system.cpu.cpi 5.750372 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.750372 # CPI: Total CPI of All Threads +system.cpu.ipc 0.173902 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.173902 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 28821 # number of integer regfile reads +system.cpu.int_regfile_writes 17168 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7157 # number of misc regfile reads +system.cpu.misc_regfile_reads 7143 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 144.838495 # Cycle average of tags in use -system.cpu.icache.total_refs 1482 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 144.824422 # Cycle average of tags in use +system.cpu.icache.total_refs 1475 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.875000 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.851974 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 144.838495 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.070722 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.070722 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1482 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1482 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1482 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1482 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1482 # number of overall hits -system.cpu.icache.overall_hits::total 1482 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 144.824422 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.070715 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.070715 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1475 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1475 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1475 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1475 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1475 # number of overall hits +system.cpu.icache.overall_hits::total 1475 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 399 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 399 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 399 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 399 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 399 # number of overall misses system.cpu.icache.overall_misses::total 399 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19371000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19371000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19371000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19371000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19371000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19371000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1881 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1881 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1881 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1881 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1881 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1881 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212121 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.212121 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.212121 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.212121 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.212121 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.212121 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48548.872180 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48548.872180 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48548.872180 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48548.872180 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48548.872180 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48548.872180 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20611500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20611500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20611500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20611500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20611500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20611500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1874 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1874 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1874 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1874 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1874 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1874 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212914 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.212914 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.212914 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.212914 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.212914 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.212914 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51657.894737 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51657.894737 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 51657.894737 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51657.894737 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 51657.894737 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51657.894737 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 312 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 44.571429 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -516,36 +516,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 304 system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15461500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15461500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15461500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15461500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15461500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15461500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161616 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161616 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161616 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.161616 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161616 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.161616 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50860.197368 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50860.197368 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16157000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16157000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16157000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16157000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16157000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16157000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.162220 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.162220 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.162220 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53148.026316 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53148.026316 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53148.026316 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53148.026316 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53148.026316 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53148.026316 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 178.021458 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 177.982441 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 144.985394 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 33.036064 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004425 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 144.961595 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 33.020847 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004424 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005433 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005432 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -553,60 +553,60 @@ system.cpu.l2cache.demand_hits::total 1 # nu system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 71 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 374 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 72 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 375 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 303 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 147 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 450 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 451 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 303 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses -system.cpu.l2cache.overall_misses::total 450 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15146500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3811500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18958000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3992500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3992500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15146500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7804000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22950500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15146500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7804000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22950500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses +system.cpu.l2cache.overall_misses::total 451 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15842000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3892500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19734500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3990500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3990500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15842000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7883000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23725000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15842000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7883000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23725000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 71 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 375 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 72 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 376 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 451 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 452 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 451 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 452 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996711 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997333 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997340 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996711 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997783 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997788 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996711 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997783 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49988.448845 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53683.098592 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 50689.839572 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52532.894737 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52532.894737 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53088.435374 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51001.111111 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53088.435374 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51001.111111 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997788 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52283.828383 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54062.500000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52625.333333 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52506.578947 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52506.578947 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52283.828383 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53263.513514 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52605.321508 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52283.828383 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53263.513514 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52605.321508 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -616,59 +616,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 374 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 72 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 375 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 450 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 451 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 450 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11336952 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2944072 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14281024 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3029110 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3029110 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11336952 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5973182 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17310134 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11336952 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5973182 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17310134 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12092212 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3030082 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15122294 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3058112 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3058112 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12092212 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6088194 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18180406 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12092212 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6088194 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18180406 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997333 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997340 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997783 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997788 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997783 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37415.683168 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41465.802817 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38184.556150 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39856.710526 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39856.710526 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37415.683168 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38466.964444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37415.683168 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38466.964444 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997788 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39908.290429 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42084.472222 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40326.117333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40238.315789 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40238.315789 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39908.290429 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41136.445946 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40311.321508 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39908.290429 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41136.445946 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40311.321508 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.281408 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 83.496642 # Cycle average of tags in use system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.861111 # Average number of references to valid blocks. +system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.643836 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.281408 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020332 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020332 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 83.496642 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020385 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020385 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1425 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1425 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits @@ -677,51 +677,51 @@ system.cpu.dcache.demand_hits::cpu.data 2284 # nu system.cpu.dcache.demand_hits::total 2284 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 2284 # number of overall hits system.cpu.dcache.overall_hits::total 2284 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 127 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 127 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses -system.cpu.dcache.overall_misses::total 202 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6336500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6336500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4220500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4220500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10557000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10557000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10557000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10557000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1551 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1551 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 203 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 203 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 203 # number of overall misses +system.cpu.dcache.overall_misses::total 203 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6648000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6648000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4218500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4218500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10866500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10866500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10866500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10866500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1552 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1552 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2486 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2486 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2486 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2486 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081238 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.081238 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2487 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2487 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2487 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2487 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081830 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081830 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.081255 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.081255 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.081255 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.081255 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50289.682540 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50289.682540 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55532.894737 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55532.894737 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52262.376238 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52262.376238 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52262.376238 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52262.376238 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.081624 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081624 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081624 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081624 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52346.456693 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 52346.456693 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55506.578947 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55506.578947 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53529.556650 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53529.556650 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53529.556650 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53529.556650 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 103 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.600000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -731,38 +731,38 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 55 system.cpu.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 72 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 72 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3735500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3735500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4068500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4068500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7804000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7804000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7804000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7804000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045777 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045777 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3962500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3962500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4066500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4066500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8029000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8029000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8029000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8029000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046392 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046392 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059131 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.059131 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52612.676056 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52612.676056 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53532.894737 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53532.894737 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53088.435374 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53088.435374 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53088.435374 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53088.435374 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059509 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059509 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059509 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.059509 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55034.722222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55034.722222 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53506.578947 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53506.578947 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54250 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54250 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54250 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54250 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 18c747e94..329680740 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19857000 # Number of ticks simulated -final_tick 19857000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000024 # Number of seconds simulated +sim_ticks 24473000 # Number of ticks simulated +final_tick 24473000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38427 # Simulator instruction rate (inst/s) -host_op_rate 38425 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59863252 # Simulator tick rate (ticks/s) -host_mem_usage 271256 # Number of bytes of host memory used -host_seconds 0.33 # Real time elapsed on the host +host_inst_rate 4068 # Simulator instruction rate (inst/s) +host_op_rate 4068 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7811345 # Simulator tick rate (ticks/s) +host_mem_usage 226312 # Number of bytes of host memory used +host_seconds 3.13 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22400 # Number of bytes read from this memory -system.physmem.bytes_read::total 62208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22272 # Number of bytes read from this memory +system.physmem.bytes_read::total 62080 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 39808 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 39808 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 622 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 350 # Number of read requests responded to by this memory -system.physmem.num_reads::total 972 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2004733847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1128065670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3132799517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2004733847 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2004733847 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2004733847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1128065670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3132799517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 972 # Total number of read requests seen +system.physmem.num_reads::cpu.data 348 # Number of read requests responded to by this memory +system.physmem.num_reads::total 970 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1626608916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 910064152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2536673068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1626608916 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1626608916 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1626608916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 910064152 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2536673068 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 970 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 972 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 62208 # Total number of bytes read from memory +system.physmem.cpureqs 970 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 62080 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62208 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 62080 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 73 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 70 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 122 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 80 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 74 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 74 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 71 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 100 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 74 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 76 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 101 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 34 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 45 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 100 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 103 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 116 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 66 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 88 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 60 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 91 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 19816500 # Total gap between requests +system.physmem.totGap 24326500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 972 # Categorize read packet sizes +system.physmem.readPktSize::6 970 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 215 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,56 +164,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 11651972 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 34145972 # Sum of mem lat for all requests -system.physmem.totBusLat 3888000 # Total cycles spent in databus access -system.physmem.totBankLat 18606000 # Total cycles spent in bank access -system.physmem.avgQLat 11987.63 # Average queueing delay per request -system.physmem.avgBankLat 19141.98 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 35129.60 # Average memory access latency -system.physmem.avgRdBW 3132.80 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 22646466 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 53470216 # Sum of mem lat for all requests +system.physmem.totBusLat 4850000 # Total cycles spent in databus access +system.physmem.totBankLat 25973750 # Total cycles spent in bank access +system.physmem.avgQLat 23346.87 # Average queueing delay per request +system.physmem.avgBankLat 26777.06 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 55123.93 # Average memory access latency +system.physmem.avgRdBW 2536.67 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3132.80 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2536.67 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 19.58 # Data bus utilization in percentage -system.physmem.avgRdQLen 1.72 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 19.82 # Data bus utilization in percentage +system.physmem.avgRdQLen 2.18 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 733 # Number of row buffer hits during reads +system.physmem.readRowHits 450 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.41 # Row buffer hit rate for reads +system.physmem.readRowHitRate 46.39 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 20387.35 # Average gap between requests -system.cpu.branchPred.lookups 6348 # Number of BP lookups -system.cpu.branchPred.condPredicted 3569 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1446 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 4530 # Number of BTB lookups -system.cpu.branchPred.BTBHits 874 # Number of BTB hits +system.physmem.avgGap 25078.87 # Average gap between requests +system.cpu.branchPred.lookups 6101 # Number of BP lookups +system.cpu.branchPred.condPredicted 3457 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1231 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 4432 # Number of BTB lookups +system.cpu.branchPred.BTBHits 1023 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 19.293598 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 898 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 184 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 23.082130 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 800 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 163 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4359 # DTB read hits -system.cpu.dtb.read_misses 96 # DTB read misses +system.cpu.dtb.read_hits 4461 # DTB read hits +system.cpu.dtb.read_misses 100 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4455 # DTB read accesses -system.cpu.dtb.write_hits 2014 # DTB write hits -system.cpu.dtb.write_misses 72 # DTB write misses +system.cpu.dtb.read_accesses 4561 # DTB read accesses +system.cpu.dtb.write_hits 2022 # DTB write hits +system.cpu.dtb.write_misses 83 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2086 # DTB write accesses -system.cpu.dtb.data_hits 6373 # DTB hits -system.cpu.dtb.data_misses 168 # DTB misses +system.cpu.dtb.write_accesses 2105 # DTB write accesses +system.cpu.dtb.data_hits 6483 # DTB hits +system.cpu.dtb.data_misses 183 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6541 # DTB accesses -system.cpu.itb.fetch_hits 5250 # ITB hits -system.cpu.itb.fetch_misses 57 # ITB misses +system.cpu.dtb.data_accesses 6666 # DTB accesses +system.cpu.itb.fetch_hits 4836 # ITB hits +system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5307 # ITB accesses +system.cpu.itb.fetch_accesses 4885 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -228,350 +228,351 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 39715 # number of cpu cycles simulated +system.cpu.numCycles 48947 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 1539 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 35371 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6348 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1772 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5994 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1779 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 370 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5250 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 858 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 26295 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.345161 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.748208 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 1376 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 33899 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6101 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1823 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 5733 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1590 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 519 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 4836 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 811 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 28070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.207659 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.639587 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20301 77.20% 77.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 545 2.07% 79.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 388 1.48% 80.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 414 1.57% 82.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 431 1.64% 83.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 401 1.53% 85.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 440 1.67% 87.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 561 2.13% 89.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2814 10.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 22337 79.58% 79.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 523 1.86% 81.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 359 1.28% 82.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 389 1.39% 84.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 440 1.57% 85.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 399 1.42% 87.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 440 1.57% 88.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 368 1.31% 89.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2815 10.03% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 26295 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.159839 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.890621 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 37128 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7028 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5161 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 465 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2623 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 533 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 326 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 31237 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 663 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2623 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37789 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3807 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1133 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4855 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2198 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 28851 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 56 # Number of times rename has blocked due to ROB full -system.cpu.rename.LSQFullEvents 2210 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 21669 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 35547 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 35513 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 28070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.124645 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.692565 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 38855 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9028 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 4956 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 477 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2426 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 492 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 289 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 30419 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 546 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2426 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 39473 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6021 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 969 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4731 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2122 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 28264 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 57 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2059 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 21243 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 34749 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 34715 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 12529 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 51 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 39 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 6010 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2907 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1363 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 12103 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 49 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 5573 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2924 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1330 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2775 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1297 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.insertedLoads 2736 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1292 # Number of stores inserted to the mem dependence unit. system.cpu.memDep1.conflictingLoads 6 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 25429 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 70 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21088 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 110 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11668 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7282 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 36 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 26295 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.801978 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.371425 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 25104 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 73 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 20875 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 70 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11589 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7157 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 28070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.743677 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.323333 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17201 65.42% 65.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3228 12.28% 77.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2604 9.90% 87.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1566 5.96% 93.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 907 3.45% 97.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 493 1.87% 98.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 226 0.86% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.21% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 15 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18893 67.31% 67.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3427 12.21% 79.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2538 9.04% 88.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1546 5.51% 94.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 945 3.37% 97.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 459 1.64% 99.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 189 0.67% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 59 0.21% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 26295 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 28070 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11 5.67% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 117 60.31% 65.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 66 34.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 3.64% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 98 59.39% 63.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 61 36.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6973 65.93% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2492 23.56% 89.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1106 10.46% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 6970 65.71% 65.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2525 23.81% 89.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1107 10.44% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10576 # Type of FU issued +system.cpu.iq.FU_type_0::total 10607 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7011 66.70% 66.71% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.72% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2403 22.86% 89.60% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1093 10.40% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 6762 65.86% 65.87% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.88% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2394 23.32% 89.22% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1107 10.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 10512 # Type of FU issued +system.cpu.iq.FU_type_1::total 10268 # Type of FU issued system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type::IntAlu 13984 66.31% 66.33% # Type of FU issued -system.cpu.iq.FU_type::IntMult 2 0.01% 66.34% # Type of FU issued -system.cpu.iq.FU_type::IntDiv 0 0.00% 66.34% # Type of FU issued -system.cpu.iq.FU_type::FloatAdd 4 0.02% 66.36% # Type of FU issued -system.cpu.iq.FU_type::FloatCmp 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::FloatCvt 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::FloatMult 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::FloatDiv 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::FloatSqrt 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdAdd 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdAlu 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdCmp 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdCvt 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdMisc 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdMult 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdShift 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdSqrt 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::MemRead 4895 23.21% 89.57% # Type of FU issued -system.cpu.iq.FU_type::MemWrite 2199 10.43% 100.00% # Type of FU issued +system.cpu.iq.FU_type::IntAlu 13732 65.78% 65.80% # Type of FU issued +system.cpu.iq.FU_type::IntMult 2 0.01% 65.81% # Type of FU issued +system.cpu.iq.FU_type::IntDiv 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type::FloatAdd 4 0.02% 65.83% # Type of FU issued +system.cpu.iq.FU_type::FloatCmp 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::FloatCvt 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::FloatMult 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::FloatDiv 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::FloatSqrt 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdAdd 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdAlu 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdCmp 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdCvt 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdMisc 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdMult 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdShift 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdSqrt 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::MemRead 4919 23.56% 89.39% # Type of FU issued +system.cpu.iq.FU_type::MemWrite 2214 10.61% 100.00% # Type of FU issued system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::total 21088 # Type of FU issued -system.cpu.iq.rate 0.530983 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 94 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 100 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 194 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.004458 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.004742 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.009200 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 68733 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 37173 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 18381 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads +system.cpu.iq.FU_type::total 20875 # Type of FU issued +system.cpu.iq.rate 0.426482 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 83 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 82 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 165 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.003976 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.003928 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.007904 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 70014 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 36770 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 18228 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 41 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21256 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 21015 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 21 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1724 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 498 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1741 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 465 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 355 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 427 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread1.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1592 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.squashedLoads 1553 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 432 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedStores 427 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 238 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 302 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2623 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 887 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 25678 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 656 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 5682 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2660 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 70 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 31 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 235 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1060 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1295 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 19629 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2279 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2190 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4469 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1459 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 2426 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2850 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 25356 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 534 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 5660 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2622 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 73 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 218 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 905 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1123 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 19630 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2348 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2224 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4572 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1245 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 110 # number of nop insts executed -system.cpu.iew.exec_nop::1 69 # number of nop insts executed +system.cpu.iew.exec_nop::0 98 # number of nop insts executed +system.cpu.iew.exec_nop::1 81 # number of nop insts executed system.cpu.iew.exec_nop::total 179 # number of nop insts executed -system.cpu.iew.exec_refs::0 3341 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3226 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6567 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1545 # Number of branches executed -system.cpu.iew.exec_branches::1 1563 # Number of branches executed -system.cpu.iew.exec_branches::total 3108 # Number of branches executed -system.cpu.iew.exec_stores::0 1062 # Number of stores executed -system.cpu.iew.exec_stores::1 1036 # Number of stores executed -system.cpu.iew.exec_stores::total 2098 # Number of stores executed -system.cpu.iew.exec_rate 0.494247 # Inst execution rate -system.cpu.iew.wb_sent::0 9363 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9308 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 18671 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9223 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9178 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 18401 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 4724 # num instructions producing a value -system.cpu.iew.wb_producers::1 4736 # num instructions producing a value -system.cpu.iew.wb_producers::total 9460 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6156 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6184 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 12340 # num instructions consuming a value +system.cpu.iew.exec_refs::0 3414 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3275 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6689 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1527 # Number of branches executed +system.cpu.iew.exec_branches::1 1521 # Number of branches executed +system.cpu.iew.exec_branches::total 3048 # Number of branches executed +system.cpu.iew.exec_stores::0 1066 # Number of stores executed +system.cpu.iew.exec_stores::1 1051 # Number of stores executed +system.cpu.iew.exec_stores::total 2117 # Number of stores executed +system.cpu.iew.exec_rate 0.401046 # Inst execution rate +system.cpu.iew.wb_sent::0 9349 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9181 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 18530 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9210 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9038 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 18248 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 4725 # num instructions producing a value +system.cpu.iew.wb_producers::1 4632 # num instructions producing a value +system.cpu.iew.wb_producers::total 9357 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6193 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6064 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 12257 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.232230 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.231097 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.463326 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.767381 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.765847 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.766613 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.188163 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.184649 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.372811 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.762958 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.763852 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.763401 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 12926 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 12589 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1134 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 26218 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.487413 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.275738 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 957 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 28025 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.455986 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.237353 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20568 78.45% 78.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2989 11.40% 89.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1062 4.05% 93.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 514 1.96% 95.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 342 1.30% 97.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 238 0.91% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 201 0.77% 98.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 72 0.27% 99.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 232 0.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22265 79.45% 79.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3171 11.31% 90.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1034 3.69% 94.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 483 1.72% 96.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 332 1.18% 97.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 227 0.81% 98.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 200 0.71% 98.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 76 0.27% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 237 0.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 26218 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 28025 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6389 # Number of instructions committed system.cpu.commit.committedInsts::1 6390 # Number of instructions committed system.cpu.commit.committedInsts::total 12779 # Number of instructions committed @@ -602,191 +603,191 @@ system.cpu.commit.int_insts::total 12614 # Nu system.cpu.commit.function_calls::0 127 # Number of function calls committed. system.cpu.commit.function_calls::1 127 # Number of function calls committed. system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.bw_lim_events 232 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 237 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 123093 # The number of ROB reads -system.cpu.rob.rob_writes 54044 # The number of ROB writes -system.cpu.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13420 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 126869 # The number of ROB reads +system.cpu.rob.rob_writes 53172 # The number of ROB writes +system.cpu.timesIdled 388 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20877 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6372 # Number of Instructions Simulated system.cpu.committedInsts::1 6373 # Number of Instructions Simulated system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 12745 # Number of Instructions Simulated -system.cpu.cpi::0 6.232737 # CPI: Cycles Per Instruction -system.cpu.cpi::1 6.231759 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.116124 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.160443 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.160468 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.320911 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 24691 # number of integer regfile reads -system.cpu.int_regfile_writes 13868 # number of integer regfile writes +system.cpu.cpi::0 7.681576 # CPI: Cycles Per Instruction +system.cpu.cpi::1 7.680370 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.840486 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.130182 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.130202 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.260384 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 24701 # number of integer regfile reads +system.cpu.int_regfile_writes 13755 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.icache.replacements::0 7 # number of replacements +system.cpu.icache.replacements::0 6 # number of replacements system.cpu.icache.replacements::1 0 # number of replacements -system.cpu.icache.replacements::total 7 # number of replacements -system.cpu.icache.tagsinuse 306.891389 # Cycle average of tags in use -system.cpu.icache.total_refs 4214 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 625 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.742400 # Average number of references to valid blocks. +system.cpu.icache.replacements::total 6 # number of replacements +system.cpu.icache.tagsinuse 292.522712 # Cycle average of tags in use +system.cpu.icache.total_refs 3780 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 624 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6.057692 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 306.891389 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.149849 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.149849 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4214 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4214 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4214 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4214 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4214 # number of overall hits -system.cpu.icache.overall_hits::total 4214 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1030 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1030 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1030 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1030 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1030 # number of overall misses -system.cpu.icache.overall_misses::total 1030 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 56718997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 56718997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 56718997 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 56718997 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 56718997 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 56718997 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5244 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5244 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5244 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5244 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5244 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5244 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196415 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.196415 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.196415 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.196415 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.196415 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.196415 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55066.987379 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55066.987379 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55066.987379 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55066.987379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55066.987379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55066.987379 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2360 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 292.522712 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.142833 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.142833 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 3780 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3780 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3780 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3780 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3780 # number of overall hits +system.cpu.icache.overall_hits::total 3780 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1049 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1049 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1049 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1049 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1049 # number of overall misses +system.cpu.icache.overall_misses::total 1049 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 78577996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 78577996 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 78577996 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 78577996 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 78577996 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 78577996 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 4829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 4829 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4829 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 4829 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4829 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217229 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.217229 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.217229 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.217229 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.217229 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.217229 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74907.527169 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74907.527169 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74907.527169 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74907.527169 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74907.527169 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74907.527169 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3158 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 56 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 66 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42.142857 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 47.848485 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 405 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 405 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 405 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 405 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 405 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 405 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 625 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 625 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 625 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 625 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 625 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38021997 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 38021997 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38021997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 38021997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38021997 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 38021997 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.119184 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.119184 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.119184 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.119184 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.119184 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.119184 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60835.195200 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60835.195200 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60835.195200 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60835.195200 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60835.195200 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60835.195200 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 425 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 425 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 425 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 425 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 425 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 425 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 624 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 624 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 624 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 624 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 624 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 624 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 48453998 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 48453998 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 48453998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 48453998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 48453998 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 48453998 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.129219 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.129219 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.129219 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.129219 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.129219 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.129219 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77650.637821 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77650.637821 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77650.637821 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 77650.637821 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77650.637821 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 77650.637821 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements::0 0 # number of replacements system.cpu.l2cache.replacements::1 0 # number of replacements system.cpu.l2cache.replacements::total 0 # number of replacements -system.cpu.l2cache.tagsinuse 425.528507 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 826 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.003632 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 407.828883 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 824 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002427 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 307.423460 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 118.105047 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.009382 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.003604 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.012986 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits -system.cpu.l2cache.overall_hits::total 3 # number of overall hits +system.cpu.l2cache.occ_blocks::cpu.inst 293.011617 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 114.817266 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.008942 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.003504 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.012446 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits +system.cpu.l2cache.overall_hits::total 2 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 622 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 204 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 826 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 202 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 824 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 622 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 350 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 972 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 348 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 970 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 622 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 350 # number of overall misses -system.cpu.l2cache.overall_misses::total 972 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37362500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13955000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 51317500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8555000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8555000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 37362500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22510000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 59872500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 37362500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22510000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 59872500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 625 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 204 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 829 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 348 # number of overall misses +system.cpu.l2cache.overall_misses::total 970 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 47808000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 18056500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 65864500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12124000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12124000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 47808000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 30180500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 77988500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 47808000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 30180500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 77988500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 624 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 202 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 826 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 625 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 350 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 975 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 625 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 350 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 975 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995200 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 624 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 348 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 972 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 624 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 348 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 972 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996795 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.996381 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997579 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995200 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996795 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.996923 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995200 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.997942 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996795 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.996923 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60068.327974 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68406.862745 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 62127.723971 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58595.890411 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58595.890411 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60068.327974 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64314.285714 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 61597.222222 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60068.327974 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64314.285714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 61597.222222 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997942 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76861.736334 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 89388.613861 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 79932.645631 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83041.095890 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83041.095890 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76861.736334 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86725.574713 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80400.515464 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76861.736334 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86725.574713 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80400.515464 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -796,157 +797,157 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 622 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 826 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 824 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 622 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 972 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 348 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 970 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 622 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 972 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29639174 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11445162 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41084336 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6748648 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6748648 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29639174 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18193810 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 47832984 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29639174 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18193810 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 47832984 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995200 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.data 348 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 970 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40142034 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15600631 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55742665 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10339864 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10339864 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40142034 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25940495 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 66082529 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40142034 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25940495 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 66082529 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996381 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997579 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995200 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.996923 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995200 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.996923 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47651.405145 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56103.735294 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 49738.905569 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46223.616438 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46223.616438 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47651.405145 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51982.314286 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49210.888889 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47651.405145 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51982.314286 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49210.888889 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64537.032154 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77230.846535 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67648.865291 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70820.986301 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70820.986301 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64537.032154 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74541.652299 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68126.318557 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64537.032154 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74541.652299 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68126.318557 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements::0 0 # number of replacements system.cpu.dcache.replacements::1 0 # number of replacements system.cpu.dcache.replacements::total 0 # number of replacements -system.cpu.dcache.tagsinuse 210.613846 # Cycle average of tags in use -system.cpu.dcache.total_refs 4387 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 349 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.570201 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 202.984846 # Cycle average of tags in use +system.cpu.dcache.total_refs 4338 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 348 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.465517 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 210.613846 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.051419 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.051419 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3369 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3369 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1018 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1018 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4387 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4387 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4387 # number of overall hits -system.cpu.dcache.overall_hits::total 4387 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 323 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 323 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 712 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 712 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1035 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1035 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1035 # number of overall misses -system.cpu.dcache.overall_misses::total 1035 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 19559500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 19559500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33573958 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33573958 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 53133458 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 53133458 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 53133458 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 53133458 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3692 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3692 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 202.984846 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.049557 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.049557 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3316 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3316 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1022 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 4338 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4338 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4338 # number of overall hits +system.cpu.dcache.overall_hits::total 4338 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 320 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 320 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 708 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 708 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1028 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1028 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1028 # number of overall misses +system.cpu.dcache.overall_misses::total 1028 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26222500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26222500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 53389967 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 53389967 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 79612467 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 79612467 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 79612467 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 79612467 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3636 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3636 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5422 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5422 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5422 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5422 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087486 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.087486 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.190889 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.190889 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.190889 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.190889 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60555.727554 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60555.727554 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47154.435393 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47154.435393 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51336.674396 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 51336.674396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51336.674396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 51336.674396 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3056 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 5366 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5366 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5366 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5366 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.088009 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.088009 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409249 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.409249 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.191577 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.191577 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.191577 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.191577 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81945.312500 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 81945.312500 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75409.557910 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75409.557910 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77444.034047 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77444.034047 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77444.034047 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77444.034047 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4583 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 103 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 91 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.669903 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.362637 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 119 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 566 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 566 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 685 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 685 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 685 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 685 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 118 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 118 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 562 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 562 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 680 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 680 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 680 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 680 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14127500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 14127500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8703496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8703496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22830996 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22830996 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22830996 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22830996 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055255 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055255 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 348 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 348 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 348 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 348 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18267500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 18267500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12271498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12271498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30538998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 30538998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30538998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 30538998 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055556 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055556 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064552 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.064552 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064552 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.064552 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69252.450980 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69252.450980 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59612.986301 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59612.986301 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65231.417143 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65231.417143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65231.417143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65231.417143 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064853 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.064853 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064853 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.064853 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 90433.168317 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 90433.168317 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84051.356164 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84051.356164 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87755.741379 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 87755.741379 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87755.741379 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 87755.741379 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 3353b4aad..3cd467a4b 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 22838500 # Number of ticks simulated -final_tick 22838500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 23146500 # Number of ticks simulated +final_tick 23146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 21741 # Simulator instruction rate (inst/s) -host_op_rate 21740 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32746771 # Simulator tick rate (ticks/s) -host_mem_usage 278448 # Number of bytes of host memory used -host_seconds 0.70 # Real time elapsed on the host +host_inst_rate 62448 # Simulator instruction rate (inst/s) +host_op_rate 62442 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 95315643 # Simulator tick rate (ticks/s) +host_mem_usage 230224 # Number of bytes of host memory used +host_seconds 0.24 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19072 # Nu system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 436 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 835081113 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 386715415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1221796528 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 835081113 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 835081113 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 835081113 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 386715415 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1221796528 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 823969067 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 381569568 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1205538634 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 823969067 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 823969067 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 823969067 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 381569568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1205538634 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 436 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 27904 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 69 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 25 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 5 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 37 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 11 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 76 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 43 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 84 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 24 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 22805000 # Total gap between requests +system.physmem.totGap 23113000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,10 +98,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 279 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -164,41 +164,41 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2325934 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11335934 # Sum of mem lat for all requests -system.physmem.totBusLat 1744000 # Total cycles spent in databus access -system.physmem.totBankLat 7266000 # Total cycles spent in bank access -system.physmem.avgQLat 5334.71 # Average queueing delay per request -system.physmem.avgBankLat 16665.14 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25999.85 # Average memory access latency -system.physmem.avgRdBW 1221.80 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2156686 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12064186 # Sum of mem lat for all requests +system.physmem.totBusLat 2180000 # Total cycles spent in databus access +system.physmem.totBankLat 7727500 # Total cycles spent in bank access +system.physmem.avgQLat 4946.53 # Average queueing delay per request +system.physmem.avgBankLat 17723.62 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 27670.15 # Average memory access latency +system.physmem.avgRdBW 1205.54 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1221.80 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1205.54 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 7.64 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.50 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 9.42 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.52 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 359 # Number of row buffer hits during reads +system.physmem.readRowHits 339 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.75 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 52305.05 # Average gap between requests -system.cpu.branchPred.lookups 5147 # Number of BP lookups +system.physmem.avgGap 53011.47 # Average gap between requests +system.cpu.branchPred.lookups 5146 # Number of BP lookups system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 2366 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 4101 # Number of BTB lookups -system.cpu.branchPred.BTBHits 2720 # Number of BTB hits +system.cpu.branchPred.BTBLookups 4100 # Number of BTB lookups +system.cpu.branchPred.BTBHits 2719 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 66.325287 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 66.317073 # BTB Hit Percentage system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 45678 # number of cpu cycles simulated +system.cpu.numCycles 46294 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 2894 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 2253 # Number of Branches Predicted As Not Taken (False). system.cpu.regfile_manager.intRegFileReads 14397 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 11099 # Number of Writes to Int. Register File @@ -217,12 +217,12 @@ system.cpu.execution_unit.executions 11045 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 21903 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 21905 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 502 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 28109 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 17569 # Number of cycles cpu stages are processed. -system.cpu.activity 38.462717 # Percentage of cycles cpu is active +system.cpu.timesIdled 505 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 28726 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 17568 # Number of cycles cpu stages are processed. +system.cpu.activity 37.948762 # Percentage of cycles cpu is active system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed @@ -234,36 +234,36 @@ system.cpu.committedInsts 15162 # Nu system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) -system.cpu.cpi 3.012663 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.053291 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 3.012663 # CPI: Total CPI of All Threads -system.cpu.ipc 0.331932 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.053291 # CPI: Total CPI of All Threads +system.cpu.ipc 0.327515 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.331932 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 32252 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.327515 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 32868 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 29.392705 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 36324 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 9354 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 20.478130 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 36874 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 8804 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 19.274049 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 42800 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 29.001598 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 36941 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 20.203482 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 37491 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 19.015423 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 43416 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 6.300626 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 36369 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 6.216788 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 36985 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 20.379614 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 20.108437 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 172.574474 # Cycle average of tags in use +system.cpu.icache.tagsinuse 172.164652 # Cycle average of tags in use system.cpu.icache.total_refs 3004 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 10.046823 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 172.574474 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.084265 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.084265 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 172.164652 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.084065 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.084065 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits @@ -276,12 +276,12 @@ system.cpu.icache.demand_misses::cpu.inst 381 # n system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses system.cpu.icache.overall_misses::total 381 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18868500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18868500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18868500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18868500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18868500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18868500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18686000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18686000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18686000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18686000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18686000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18686000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses @@ -294,12 +294,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.112555 system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49523.622047 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49523.622047 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49523.622047 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49523.622047 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49523.622047 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49523.622047 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49044.619423 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49044.619423 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49044.619423 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49044.619423 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49044.619423 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49044.619423 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -320,36 +320,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301 system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15157500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15157500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15157500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15157500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15157500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15157500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14960000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14960000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14960000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14960000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14960000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14960000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50357.142857 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50357.142857 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50357.142857 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50357.142857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50357.142857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50357.142857 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49700.996678 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49700.996678 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49700.996678 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49700.996678 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49700.996678 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49700.996678 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 204.083022 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 203.582900 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005698 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 171.933146 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 32.149876 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005247 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000981 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006228 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 171.517590 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 32.065310 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005234 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000979 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006213 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -367,17 +367,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14874500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2846000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17720500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4426000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4426000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14874500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7272000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22146500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14874500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7272000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22146500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14678000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3230000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17908000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4625000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4625000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14678000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7855000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22533000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14678000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7855000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22533000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -400,17 +400,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49747.491639 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53698.113208 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 50342.329545 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52070.588235 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52070.588235 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49747.491639 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52695.652174 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 50678.489703 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49747.491639 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52695.652174 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 50678.489703 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49090.301003 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60943.396226 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 50875 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54411.764706 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54411.764706 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49090.301003 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56920.289855 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51562.929062 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49090.301003 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56920.289855 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51562.929062 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -430,17 +430,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11105481 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2181568 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13287049 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3382064 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3382064 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11105481 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5563632 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16669113 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11105481 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5563632 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16669113 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10987236 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2575826 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13563062 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3583070 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3583070 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10987236 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6158896 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17146132 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10987236 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6158896 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17146132 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -452,27 +452,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37142.076923 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41161.660377 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37747.298295 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39788.988235 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39788.988235 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37142.076923 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38144.423341 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37142.076923 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38144.423341 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36746.608696 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48600.490566 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38531.426136 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42153.764706 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42153.764706 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36746.608696 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44629.681159 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39236 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36746.608696 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44629.681159 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39236 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 99.519804 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 99.212064 # Cycle average of tags in use system.cpu.dcache.total_refs 3193 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 23.137681 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 99.519804 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.024297 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.024297 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 99.212064 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.024222 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.024222 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits @@ -491,14 +491,14 @@ system.cpu.dcache.demand_misses::cpu.data 480 # n system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses system.cpu.dcache.overall_misses::total 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3301000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3301000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19263500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19263500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22564500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22564500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22564500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22564500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3686000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3686000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19969500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19969500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23655500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23655500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23655500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23655500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -517,19 +517,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56913.793103 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56913.793103 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45648.104265 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45648.104265 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47009.375000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47009.375000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47009.375000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47009.375000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 680 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63551.724138 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63551.724138 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47321.090047 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47321.090047 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 49282.291667 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 49282.291667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 49282.291667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 49282.291667 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 760 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.352941 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -549,14 +549,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2900500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2900500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4514000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4514000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7414500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7414500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7414500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7414500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3284500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3284500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4713000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4713000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7997500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7997500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7997500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7997500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -565,14 +565,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54726.415094 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54726.415094 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53105.882353 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53105.882353 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53728.260870 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53728.260870 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53728.260870 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53728.260870 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61971.698113 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61971.698113 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55447.058824 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55447.058824 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57952.898551 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57952.898551 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57952.898551 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57952.898551 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 368690106..cd86d7e47 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 23180500 # Number of ticks simulated -final_tick 23180500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000024 # Number of seconds simulated +sim_ticks 23775500 # Number of ticks simulated +final_tick 23775500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 20805 # Simulator instruction rate (inst/s) -host_op_rate 20805 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33406458 # Simulator tick rate (ticks/s) -host_mem_usage 278444 # Number of bytes of host memory used -host_seconds 0.69 # Real time elapsed on the host +host_inst_rate 69212 # Simulator instruction rate (inst/s) +host_op_rate 69204 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 113962469 # Simulator tick rate (ticks/s) +host_mem_usage 232268 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 21504 # Nu system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory system.physmem.num_reads::total 483 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 927676280 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 405858372 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1333534652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 927676280 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 927676280 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 927676280 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 405858372 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1333534652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 904460474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 395701457 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1300161931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 904460474 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 904460474 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 904460474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 395701457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1300161931 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 483 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 483 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 30912 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 13 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 80 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 46 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 75 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 37 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 91 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 41 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 28 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23120500 # Total gap between requests +system.physmem.totGap 23715500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,9 +98,9 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -164,121 +164,121 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3040483 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12980483 # Sum of mem lat for all requests -system.physmem.totBusLat 1932000 # Total cycles spent in databus access -system.physmem.totBankLat 8008000 # Total cycles spent in bank access -system.physmem.avgQLat 6295.00 # Average queueing delay per request -system.physmem.avgBankLat 16579.71 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26874.71 # Average memory access latency -system.physmem.avgRdBW 1333.53 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 4632480 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 15613730 # Sum of mem lat for all requests +system.physmem.totBusLat 2415000 # Total cycles spent in databus access +system.physmem.totBankLat 8566250 # Total cycles spent in bank access +system.physmem.avgQLat 9591.06 # Average queueing delay per request +system.physmem.avgBankLat 17735.51 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 32326.56 # Average memory access latency +system.physmem.avgRdBW 1300.16 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1333.53 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1300.16 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 8.33 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.56 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 10.16 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.66 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 394 # Number of row buffer hits during reads +system.physmem.readRowHits 369 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.40 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47868.53 # Average gap between requests -system.cpu.branchPred.lookups 6759 # Number of BP lookups -system.cpu.branchPred.condPredicted 4517 # Number of conditional branches predicted +system.physmem.avgGap 49100.41 # Average gap between requests +system.cpu.branchPred.lookups 6770 # Number of BP lookups +system.cpu.branchPred.condPredicted 4525 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1074 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 4658 # Number of BTB lookups -system.cpu.branchPred.BTBHits 2448 # Number of BTB hits +system.cpu.branchPred.BTBLookups 4668 # Number of BTB lookups +system.cpu.branchPred.BTBHits 2447 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 52.554745 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 52.420737 # BTB Hit Percentage system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 46362 # number of cpu cycles simulated +system.cpu.numCycles 47552 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12203 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 31435 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6759 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2890 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9181 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3076 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 8341 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 12219 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 31483 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6770 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2889 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9186 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3077 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 8389 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 908 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5338 # Number of cache lines fetched +system.cpu.fetch.PendingTrapStallCycles 1048 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 5341 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 446 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 32543 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.965953 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.157796 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 32753 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.961225 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.154417 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 23362 71.79% 71.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4525 13.90% 85.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 464 1.43% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 371 1.14% 88.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 671 2.06% 90.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 764 2.35% 92.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 234 0.72% 93.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 255 0.78% 94.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1897 5.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23567 71.95% 71.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4524 13.81% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 464 1.42% 87.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 371 1.13% 88.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 671 2.05% 90.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 764 2.33% 92.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 234 0.71% 93.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 254 0.78% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1904 5.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 32543 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.145787 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.678034 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12825 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9216 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8405 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 191 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1906 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 29374 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1906 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13470 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 359 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8350 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 8008 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 450 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 26929 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 32753 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.142370 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.662075 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12949 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9302 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8402 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 193 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1907 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 29379 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1907 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13599 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 381 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8397 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 8002 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 467 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 26943 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 128 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 24166 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 49969 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 49969 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 138 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 24189 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 49982 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 49982 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10347 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 10370 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 691 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 693 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2734 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3540 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2331 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 2748 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3537 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2327 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 22748 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 22737 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 650 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21285 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8188 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5672 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 21278 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 107 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8171 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5645 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 175 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 32543 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.654058 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.275967 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 32753 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.649650 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.272846 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23299 71.59% 71.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3475 10.68% 82.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2346 7.21% 89.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1731 5.32% 94.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 922 2.83% 97.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 467 1.44% 99.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 238 0.73% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 46 0.14% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23497 71.74% 71.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3507 10.71% 82.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2330 7.11% 89.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1726 5.27% 94.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 921 2.81% 97.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 469 1.43% 99.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 236 0.72% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 48 0.15% 99.94% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 32543 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 32753 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 45 29.41% 29.41% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 29.41% # attempts to use FU when none available @@ -314,69 +314,69 @@ system.cpu.iq.fu_full::MemWrite 81 52.94% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 15766 74.07% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3371 15.84% 89.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2148 10.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 15764 74.09% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3369 15.83% 89.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2145 10.08% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21285 # Type of FU issued -system.cpu.iq.rate 0.459104 # Inst issue rate +system.cpu.iq.FU_type_0::total 21278 # Type of FU issued +system.cpu.iq.rate 0.447468 # Inst issue rate system.cpu.iq.fu_busy_cnt 153 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007188 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 75371 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 31612 # Number of integer instruction queue writes +system.cpu.iq.fu_busy_rate 0.007191 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 75569 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 31584 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 19647 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21438 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21431 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1315 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1312 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 883 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 879 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1906 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1907 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 246 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 24537 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 24523 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 379 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3540 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2331 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 3537 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2327 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 650 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -384,43 +384,43 @@ system.cpu.iew.memOrderViolationEvents 26 # Nu system.cpu.iew.predictedTakenIncorrect 254 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 945 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1199 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20207 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3221 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1078 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 20204 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3219 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1074 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1139 # number of nop insts executed -system.cpu.iew.exec_refs 5276 # number of memory reference insts executed -system.cpu.iew.exec_branches 4247 # Number of branches executed -system.cpu.iew.exec_stores 2055 # Number of stores executed -system.cpu.iew.exec_rate 0.435853 # Inst execution rate -system.cpu.iew.wb_sent 19873 # cumulative count of insts sent to commit +system.cpu.iew.exec_nop 1136 # number of nop insts executed +system.cpu.iew.exec_refs 5272 # number of memory reference insts executed +system.cpu.iew.exec_branches 4246 # Number of branches executed +system.cpu.iew.exec_stores 2053 # Number of stores executed +system.cpu.iew.exec_rate 0.424882 # Inst execution rate +system.cpu.iew.wb_sent 19870 # cumulative count of insts sent to commit system.cpu.iew.wb_count 19647 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9210 # num instructions producing a value -system.cpu.iew.wb_consumers 11373 # num instructions consuming a value +system.cpu.iew.wb_producers 9208 # num instructions producing a value +system.cpu.iew.wb_consumers 11364 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.423774 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.809813 # average fanout of values written-back +system.cpu.iew.wb_rate 0.413169 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.810278 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9300 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9288 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1074 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 30637 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.494892 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.191683 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 30846 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.491539 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.188551 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23339 76.18% 76.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4026 13.14% 89.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1377 4.49% 93.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 766 2.50% 96.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 357 1.17% 97.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 269 0.88% 98.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 324 1.06% 99.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 65 0.21% 99.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23538 76.31% 76.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4051 13.13% 89.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1362 4.42% 93.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 765 2.48% 96.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 357 1.16% 97.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 268 0.87% 98.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 325 1.05% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 66 0.21% 99.63% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 114 0.37% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 30637 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 30846 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -433,66 +433,66 @@ system.cpu.commit.int_insts 12174 # Nu system.cpu.commit.function_calls 187 # Number of function calls committed. system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 54162 # The number of ROB reads -system.cpu.rob.rob_writes 50836 # The number of ROB writes +system.cpu.rob.rob_reads 54359 # The number of ROB reads +system.cpu.rob.rob_writes 50813 # The number of ROB writes system.cpu.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13819 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 14799 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14436 # Number of Instructions Simulated -system.cpu.cpi 3.211554 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.211554 # CPI: Total CPI of All Threads -system.cpu.ipc 0.311376 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.311376 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 32290 # number of integer regfile reads +system.cpu.cpi 3.293987 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.293987 # CPI: Total CPI of All Threads +system.cpu.ipc 0.303583 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.303583 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 32289 # number of integer regfile reads system.cpu.int_regfile_writes 17967 # number of integer regfile writes -system.cpu.misc_regfile_reads 6967 # number of misc regfile reads +system.cpu.misc_regfile_reads 6962 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 191.466325 # Cycle average of tags in use -system.cpu.icache.total_refs 4845 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 190.534927 # Cycle average of tags in use +system.cpu.icache.total_refs 4850 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14.334320 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 14.349112 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 191.466325 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.093489 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.093489 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4845 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4845 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4845 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4845 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4845 # number of overall hits -system.cpu.icache.overall_hits::total 4845 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 493 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 493 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 493 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 493 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 493 # number of overall misses -system.cpu.icache.overall_misses::total 493 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23383000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23383000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23383000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23383000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23383000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23383000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5338 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5338 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5338 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5338 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5338 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5338 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092357 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092357 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092357 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092357 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092357 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092357 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47430.020284 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47430.020284 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47430.020284 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47430.020284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47430.020284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47430.020284 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 190.534927 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.093035 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.093035 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4850 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4850 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4850 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4850 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4850 # number of overall hits +system.cpu.icache.overall_hits::total 4850 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 491 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 491 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 491 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 491 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 491 # number of overall misses +system.cpu.icache.overall_misses::total 491 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24328000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24328000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24328000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24328000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24328000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24328000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5341 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5341 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5341 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5341 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5341 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5341 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091930 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.091930 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.091930 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.091930 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.091930 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.091930 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49547.861507 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49547.861507 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49547.861507 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49547.861507 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49547.861507 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49547.861507 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -501,48 +501,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 155 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 155 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 155 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 155 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 155 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 155 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 153 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 153 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 153 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 153 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 153 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 153 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17113500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17113500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17113500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17113500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17113500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17113500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063320 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063320 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063320 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.063320 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063320 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.063320 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50631.656805 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50631.656805 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50631.656805 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50631.656805 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50631.656805 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50631.656805 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17616000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17616000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17616000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17616000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17616000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17616000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063284 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063284 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063284 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.063284 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063284 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.063284 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52118.343195 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52118.343195 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52118.343195 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52118.343195 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52118.343195 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52118.343195 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 225.767373 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 224.642209 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005000 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 190.872097 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 34.895277 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005825 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001065 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006890 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 189.932225 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 34.709984 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005796 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001059 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006856 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -560,17 +560,17 @@ system.cpu.l2cache.demand_misses::total 483 # nu system.cpu.l2cache.overall_misses::cpu.inst 336 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses system.cpu.l2cache.overall_misses::total 483 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16755500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3772000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 20527500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4421500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4421500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16755500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8193500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24949000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16755500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8193500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24949000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17258000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4829500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 22087500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5160500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5160500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 17258000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9990000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 27248000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 17258000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9990000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 27248000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses) @@ -593,17 +593,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995876 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994083 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995876 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49867.559524 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58937.500000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51318.750000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53271.084337 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53271.084337 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49867.559524 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55738.095238 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51654.244306 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49867.559524 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55738.095238 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51654.244306 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51363.095238 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75460.937500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 55218.750000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 62174.698795 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 62174.698795 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51363.095238 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67959.183673 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 56414.078675 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51363.095238 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67959.183673 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 56414.078675 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -623,17 +623,17 @@ system.cpu.l2cache.demand_mshr_misses::total 483 system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12529012 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2980062 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15509074 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3397062 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3397062 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12529012 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6377124 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18906136 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12529012 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6377124 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18906136 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13099526 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4042315 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17141841 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4145826 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4145826 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13099526 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8188141 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21287667 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13099526 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8188141 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21287667 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses @@ -645,95 +645,95 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37288.726190 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46563.468750 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38772.685000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40928.457831 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40928.457831 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37288.726190 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43381.795918 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39143.138716 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37288.726190 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43381.795918 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39143.138716 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38986.684524 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63161.171875 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42854.602500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49949.710843 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49949.710843 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38986.684524 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55701.639456 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44073.844720 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38986.684524 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55701.639456 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44073.844720 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 99.943036 # Cycle average of tags in use -system.cpu.dcache.total_refs 4019 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 99.563734 # Cycle average of tags in use +system.cpu.dcache.total_refs 4017 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27.340136 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 27.326531 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 99.943036 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.024400 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.024400 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 2980 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 2980 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 99.563734 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.024308 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.024308 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 2978 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 2978 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4013 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4013 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4013 # number of overall hits -system.cpu.dcache.overall_hits::total 4013 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 130 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 130 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 4011 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4011 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4011 # number of overall hits +system.cpu.dcache.overall_hits::total 4011 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 131 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 131 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 539 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 539 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 539 # number of overall misses -system.cpu.dcache.overall_misses::total 539 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6943000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6943000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19544474 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19544474 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 26487474 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 26487474 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 26487474 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 26487474 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3110 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3110 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 540 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 540 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 540 # number of overall misses +system.cpu.dcache.overall_misses::total 540 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8999000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8999000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21053474 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21053474 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30052474 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30052474 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30052474 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30052474 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3109 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3109 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4552 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4552 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4552 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4552 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.041801 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.041801 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 4551 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4551 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4551 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4551 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042136 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.042136 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118409 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118409 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118409 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118409 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53407.692308 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53407.692308 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47786 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47786 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 49141.881262 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 49141.881262 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 49141.881262 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 49141.881262 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 378 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.118655 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118655 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118655 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118655 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68694.656489 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68694.656489 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51475.486553 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 51475.486553 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55652.729630 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55652.729630 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55652.729630 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55652.729630 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 429 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.321429 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 392 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 392 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 392 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 392 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 393 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 393 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 393 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 393 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses @@ -742,30 +742,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3836500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3836500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8342000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8342000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8342000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8342000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020579 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020579 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4894000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4894000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5244500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5244500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10138500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10138500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10138500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10138500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020585 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020585 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032293 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032293 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032293 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032293 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59945.312500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59945.312500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54283.132530 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54283.132530 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56748.299320 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56748.299320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56748.299320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56748.299320 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032301 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032301 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032301 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032301 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76468.750000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76468.750000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63186.746988 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63186.746988 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68969.387755 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68969.387755 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68969.387755 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68969.387755 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 3f4fe5ffb..3dd8cecd5 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,87 +1,87 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000105 # Number of seconds simulated -sim_ticks 104832500 # Number of ticks simulated -final_tick 104832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000106 # Number of seconds simulated +sim_ticks 105801500 # Number of ticks simulated +final_tick 105801500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81452 # Simulator instruction rate (inst/s) -host_op_rate 81452 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8250764 # Simulator tick rate (ticks/s) -host_mem_usage 293492 # Number of bytes of host memory used -host_seconds 12.71 # Real time elapsed on the host -sim_insts 1034907 # Number of instructions simulated -sim_ops 1034907 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory +host_inst_rate 99938 # Simulator instruction rate (inst/s) +host_op_rate 99937 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10207562 # Simulator tick rate (ticks/s) +host_mem_usage 247464 # Number of bytes of host memory used +host_seconds 10.37 # Real time elapsed on the host +sim_insts 1035849 # Number of instructions simulated +sim_ops 1035849 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 22848 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 28416 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 42240 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 22848 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 28544 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 357 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 81 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 658 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 217337181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 102563613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 49450314 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 12209954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 1831493 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7936470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 2441991 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7936470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 401707486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 217337181 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 49450314 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 1831493 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 2441991 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 271060978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 217337181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 102563613 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 49450314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 12209954 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 1831493 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7936470 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 2441991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7936470 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 401707486 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 659 # Total number of read requests seen +system.physmem.num_reads::total 660 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 215951570 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 101624268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 48392509 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 12098127 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 3629438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7863783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1814719 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7863783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 399238196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 215951570 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 48392509 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 3629438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1814719 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269788236 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 215951570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 101624268 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 48392509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 12098127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 3629438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7863783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1814719 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7863783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 399238196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 661 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 980 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 42112 # Total number of bytes read from memory +system.physmem.cpureqs 978 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 42240 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 42112 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 42240 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 72 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 71 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 53 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 54 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 71 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 60 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 5 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 78 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 44 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 71 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 74 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 69 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 58 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 38 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 14 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 13 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 37 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 60 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 74 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 23 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -100,14 +100,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 104804500 # Total gap between requests +system.physmem.totGap 105773500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 659 # Categorize read packet sizes +system.physmem.readPktSize::6 661 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -125,14 +125,14 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 72 # categorize neither packet sizes +system.physmem.neitherpktsize::6 71 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 377 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 205 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -194,336 +194,336 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2976655 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 17750655 # Sum of mem lat for all requests -system.physmem.totBusLat 2636000 # Total cycles spent in databus access -system.physmem.totBankLat 12138000 # Total cycles spent in bank access -system.physmem.avgQLat 4516.93 # Average queueing delay per request -system.physmem.avgBankLat 18418.82 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26935.74 # Average memory access latency -system.physmem.avgRdBW 401.71 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 4077160 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 20692160 # Sum of mem lat for all requests +system.physmem.totBusLat 3305000 # Total cycles spent in databus access +system.physmem.totBankLat 13310000 # Total cycles spent in bank access +system.physmem.avgQLat 6168.17 # Average queueing delay per request +system.physmem.avgBankLat 20136.16 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 31304.33 # Average memory access latency +system.physmem.avgRdBW 399.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 401.71 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 399.24 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.51 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.17 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.12 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.20 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 506 # Number of row buffer hits during reads +system.physmem.readRowHits 465 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.78 # Row buffer hit rate for reads +system.physmem.readRowHitRate 70.35 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 159035.66 # Average gap between requests -system.cpu0.branchPred.lookups 82004 # Number of BP lookups -system.cpu0.branchPred.condPredicted 79765 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 79291 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 77227 # Number of BTB hits +system.physmem.avgGap 160020.42 # Average gap between requests +system.cpu0.branchPred.lookups 82232 # Number of BP lookups +system.cpu0.branchPred.condPredicted 80005 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1236 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 79512 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 77444 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 97.396930 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 516 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.BTBHitPct 97.399135 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 525 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 209666 # number of cpu cycles simulated +system.cpu0.numCycles 211604 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 16910 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 486703 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 82004 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 77743 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 159637 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3804 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 12561 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 16980 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 488068 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 82232 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 77969 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 160105 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3869 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 13032 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1361 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 5871 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 483 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 192912 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.522928 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.215898 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1378 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 5906 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 485 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 193984 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.516022 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.216359 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33275 17.25% 17.25% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 79042 40.97% 58.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 584 0.30% 58.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 987 0.51% 59.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 454 0.24% 59.27% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 75108 38.93% 98.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 578 0.30% 98.51% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 364 0.19% 98.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2520 1.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33879 17.46% 17.46% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 79263 40.86% 58.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 605 0.31% 58.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 997 0.51% 59.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 467 0.24% 59.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 75310 38.82% 98.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 571 0.29% 98.51% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 376 0.19% 98.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2516 1.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 192912 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.391117 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.321325 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17503 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 14019 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 158668 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 284 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2438 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 483730 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2438 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18159 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 648 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12784 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 158332 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 551 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 480873 # Number of instructions processed by rename +system.cpu0.fetch.rateDist::total 193984 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.388613 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.306516 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17628 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 14487 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 159104 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 281 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2484 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 484973 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2484 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18279 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 710 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13181 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 158767 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 563 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 482144 # Number of instructions processed by rename system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 153 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 329027 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 958899 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 958899 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 315995 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13032 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 877 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 903 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3595 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 153720 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 77689 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 74928 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 74758 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 402151 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 922 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 399553 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10756 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 9264 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 363 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 192912 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.071167 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.088883 # Number of insts issued each cycle +system.cpu0.rename.LSQFullEvents 156 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 329947 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 961518 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 961518 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 316491 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13456 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 888 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 909 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 3585 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 154112 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 77863 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 75108 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 74923 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 403093 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 921 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 400275 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11012 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 9891 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 362 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 193984 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.063443 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.093968 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 32280 16.73% 16.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4842 2.51% 19.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 76824 39.82% 59.07% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 76328 39.57% 98.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1590 0.82% 99.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 686 0.36% 99.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 263 0.14% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 81 0.04% 99.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 18 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33040 17.03% 17.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4899 2.53% 19.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 76941 39.66% 59.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 76443 39.41% 98.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1604 0.83% 99.46% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 703 0.36% 99.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 261 0.13% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 76 0.04% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 192912 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 193984 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 57 25.45% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 53 23.66% 49.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 114 50.89% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 51 22.67% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 62 27.56% 50.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 112 49.78% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 169105 42.32% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 153315 38.37% 80.70% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 77133 19.30% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 169361 42.31% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 153636 38.38% 80.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 77278 19.31% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 399553 # Type of FU issued -system.cpu0.iq.rate 1.905664 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 224 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000561 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 992374 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 413873 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 397773 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 400275 # Type of FU issued +system.cpu0.iq.rate 1.891623 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 225 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000562 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 994851 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 415081 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 398443 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 399777 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 400500 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 74515 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 74634 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2133 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1389 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2277 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 55 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1439 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2438 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 389 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 34 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 478542 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 300 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 153720 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 77689 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 806 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 35 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 2484 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 441 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 479665 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 304 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 154112 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 77863 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 809 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 327 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1115 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1442 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 398478 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 152978 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1075 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 55 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 346 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1112 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1458 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 399178 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 153293 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1097 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 75469 # number of nop insts executed -system.cpu0.iew.exec_refs 230010 # number of memory reference insts executed -system.cpu0.iew.exec_branches 79152 # Number of branches executed -system.cpu0.iew.exec_stores 77032 # Number of stores executed -system.cpu0.iew.exec_rate 1.900537 # Inst execution rate -system.cpu0.iew.wb_sent 398087 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 397773 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 235728 # num instructions producing a value -system.cpu0.iew.wb_consumers 238247 # num instructions consuming a value +system.cpu0.iew.exec_nop 75651 # number of nop insts executed +system.cpu0.iew.exec_refs 230462 # number of memory reference insts executed +system.cpu0.iew.exec_branches 79264 # Number of branches executed +system.cpu0.iew.exec_stores 77169 # Number of stores executed +system.cpu0.iew.exec_rate 1.886439 # Inst execution rate +system.cpu0.iew.wb_sent 398782 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 398443 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 236156 # num instructions producing a value +system.cpu0.iew.wb_consumers 238721 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.897175 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.989427 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.882965 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.989255 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 12164 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 12542 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 190474 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.448334 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.135304 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1236 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 191500 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.439102 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.136121 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 32805 17.22% 17.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 78740 41.34% 58.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2339 1.23% 59.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 693 0.36% 60.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 545 0.29% 60.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 74329 39.02% 99.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 456 0.24% 99.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 250 0.13% 99.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 317 0.17% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 33551 17.52% 17.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 78896 41.20% 58.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2340 1.22% 59.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 696 0.36% 60.30% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 545 0.28% 60.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 74448 38.88% 99.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 466 0.24% 99.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 256 0.13% 99.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 302 0.16% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 190474 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 466344 # Number of instructions committed -system.cpu0.commit.committedOps 466344 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 191500 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 467088 # Number of instructions committed +system.cpu0.commit.committedOps 467088 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 227887 # Number of memory references committed -system.cpu0.commit.loads 151587 # Number of loads committed +system.cpu0.commit.refs 228259 # Number of memory references committed +system.cpu0.commit.loads 151835 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 78187 # Number of branches committed +system.cpu0.commit.branches 78311 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 314326 # Number of committed integer instructions. +system.cpu0.commit.int_insts 314822 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 317 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 302 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 667504 # The number of ROB reads -system.cpu0.rob.rob_writes 959472 # The number of ROB writes -system.cpu0.timesIdled 316 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 16754 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 391341 # Number of Instructions Simulated -system.cpu0.committedOps 391341 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 391341 # Number of Instructions Simulated -system.cpu0.cpi 0.535763 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.535763 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.866497 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.866497 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 712766 # number of integer regfile reads -system.cpu0.int_regfile_writes 321389 # number of integer regfile writes +system.cpu0.rob.rob_reads 669667 # The number of ROB reads +system.cpu0.rob.rob_writes 961765 # The number of ROB writes +system.cpu0.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 17620 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 391961 # Number of Instructions Simulated +system.cpu0.committedOps 391961 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 391961 # Number of Instructions Simulated +system.cpu0.cpi 0.539860 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.539860 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.852333 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.852333 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 714059 # number of integer regfile reads +system.cpu0.int_regfile_writes 321926 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 231850 # number of misc regfile reads +system.cpu0.misc_regfile_reads 232286 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.replacements 297 # number of replacements -system.cpu0.icache.tagsinuse 245.463196 # Cycle average of tags in use -system.cpu0.icache.total_refs 5129 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 587 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.737649 # Average number of references to valid blocks. +system.cpu0.icache.replacements 298 # number of replacements +system.cpu0.icache.tagsinuse 245.557795 # Cycle average of tags in use +system.cpu0.icache.total_refs 5162 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 589 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.764007 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 245.463196 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.479420 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.479420 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5129 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5129 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5129 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5129 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5129 # number of overall hits -system.cpu0.icache.overall_hits::total 5129 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 742 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 742 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 742 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 742 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 742 # number of overall misses -system.cpu0.icache.overall_misses::total 742 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 25596000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 25596000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 25596000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 25596000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 25596000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 25596000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5871 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 5871 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5871 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 5871 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5871 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 5871 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.126384 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.126384 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.126384 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.126384 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.126384 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.126384 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 34495.956873 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 34495.956873 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 34495.956873 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 34495.956873 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 34495.956873 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 34495.956873 # average overall miss latency +system.cpu0.icache.occ_blocks::cpu0.inst 245.557795 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.479605 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.479605 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5162 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5162 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5162 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5162 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5162 # number of overall hits +system.cpu0.icache.overall_hits::total 5162 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 744 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 744 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 744 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 744 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 744 # number of overall misses +system.cpu0.icache.overall_misses::total 744 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 26547500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 26547500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 26547500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 26547500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 26547500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 26547500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5906 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 5906 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5906 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 5906 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5906 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 5906 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125974 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.125974 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125974 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.125974 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125974 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.125974 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 35682.123656 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 35682.123656 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 35682.123656 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 35682.123656 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 35682.123656 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 35682.123656 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,468 +538,469 @@ system.cpu0.icache.demand_mshr_hits::cpu0.inst 154 system.cpu0.icache.demand_mshr_hits::total 154 # number of demand (read+write) MSHR hits system.cpu0.icache.overall_mshr_hits::cpu0.inst 154 # number of overall MSHR hits system.cpu0.icache.overall_mshr_hits::total 154 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 20466000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 20466000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 20466000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 20466000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 20466000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 20466000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100153 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.100153 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.100153 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34806.122449 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 34806.122449 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 34806.122449 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 34806.122449 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 34806.122449 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 34806.122449 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 590 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 590 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 590 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 590 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 590 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 590 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21154500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 21154500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21154500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 21154500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21154500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 21154500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.099898 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.099898 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.099898 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.099898 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.099898 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.099898 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 35855.084746 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 35855.084746 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 35855.084746 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 35855.084746 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 35855.084746 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 35855.084746 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 143.865824 # Cycle average of tags in use -system.cpu0.dcache.total_refs 153562 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 143.429999 # Cycle average of tags in use +system.cpu0.dcache.total_refs 153854 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 903.305882 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 905.023529 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 143.865824 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.280988 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.280988 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 77931 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 77931 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 75708 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 75708 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 22 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 22 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 153639 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 153639 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 153639 # number of overall hits -system.cpu0.dcache.overall_hits::total 153639 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 471 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 471 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 550 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 550 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 20 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 20 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1021 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1021 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1021 # number of overall misses -system.cpu0.dcache.overall_misses::total 1021 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11085500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11085500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 23032998 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 23032998 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 390000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 390000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 34118498 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 34118498 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 34118498 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 34118498 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 78402 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 78402 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 76258 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 76258 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.occ_blocks::cpu0.data 143.429999 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.280137 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.280137 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 78105 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 78105 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 75839 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 75839 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 153944 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 153944 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 153944 # number of overall hits +system.cpu0.dcache.overall_hits::total 153944 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 475 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 543 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 543 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1018 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1018 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1018 # number of overall misses +system.cpu0.dcache.overall_misses::total 1018 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11909000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11909000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24675495 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24675495 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 605500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 605500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 36584495 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 36584495 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 36584495 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 36584495 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 78580 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 78580 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 76382 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 76382 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 154660 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 154660 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 154660 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 154660 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006007 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006007 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007212 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007212 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.476190 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006602 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006602 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006602 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006602 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23536.093418 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 23536.093418 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41878.178182 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 41878.178182 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19500 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 19500 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33416.746327 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33416.746327 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33416.746327 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33416.746327 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked +system.cpu0.dcache.demand_accesses::cpu0.data 154962 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 154962 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 154962 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 154962 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006045 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006045 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007109 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007109 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006569 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006569 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006569 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006569 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25071.578947 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25071.578947 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45442.900552 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45442.900552 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 28833.333333 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 28833.333333 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35937.617878 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 35937.617878 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35937.617878 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 35937.617878 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 184 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.142857 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 277 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 277 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 384 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 384 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 661 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 661 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 661 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 661 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 194 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 194 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 166 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 166 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 20 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 20 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4894000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4894000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5613000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5613000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 350000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 350000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10507000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10507000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10507000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10507000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002474 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002474 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002177 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002177 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.476190 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002328 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002328 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002328 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002328 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25226.804124 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25226.804124 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33813.253012 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33813.253012 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17500 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17500 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29186.111111 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29186.111111 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29186.111111 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29186.111111 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 287 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 373 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 373 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 660 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 660 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 660 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 660 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 170 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 170 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 358 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 358 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 358 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 358 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5409500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5409500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5718500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5718500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 563500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 563500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11128000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11128000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11128000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11128000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002392 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002226 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002226 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002310 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002310 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002310 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002310 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28773.936170 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28773.936170 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33638.235294 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33638.235294 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26833.333333 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26833.333333 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31083.798883 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31083.798883 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31083.798883 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31083.798883 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 52905 # Number of BP lookups -system.cpu1.branchPred.condPredicted 50239 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1268 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 46829 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 46139 # Number of BTB hits +system.cpu1.branchPred.lookups 58098 # Number of BP lookups +system.cpu1.branchPred.condPredicted 55415 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1271 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 51986 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 51313 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 98.526554 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 659 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 98.705421 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 648 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.numCycles 174086 # number of cpu cycles simulated +system.cpu1.numCycles 174790 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 27344 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 297404 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 52905 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 46798 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 103837 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3694 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 29303 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 6120 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 727 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 18660 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 169684 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.752693 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.165174 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 24349 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 331605 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 58098 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 51961 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 112635 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3690 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 23829 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.NoActiveThreadStallCycles 6397 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 795 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 15584 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 170350 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.946610 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.217345 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 65847 38.81% 38.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 52567 30.98% 69.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 5632 3.32% 73.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3204 1.89% 74.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 655 0.39% 75.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 36567 21.55% 96.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1212 0.71% 97.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 766 0.45% 98.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3234 1.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 57715 33.88% 33.88% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 56197 32.99% 66.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 4087 2.40% 69.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3199 1.88% 71.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 641 0.38% 71.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 43239 25.38% 96.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1271 0.75% 97.65% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 756 0.44% 98.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3245 1.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 169684 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.303902 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.708374 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 31981 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 26238 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 98390 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 4607 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2348 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 293931 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2348 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 32683 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 13600 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11856 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 94084 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 8993 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 291897 # Number of instructions processed by rename -system.cpu1.rename.LSQFullEvents 40 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 205023 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 562534 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 562534 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 192188 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 12835 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1091 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1214 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 11554 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 83198 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 39823 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 39558 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 34786 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 242793 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 5818 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 244436 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 88 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10755 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10381 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 573 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 169684 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.440537 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.314007 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 170350 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.332387 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.897162 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 27574 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 22245 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 108585 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3208 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2341 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 328108 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2341 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 28283 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 9804 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11660 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 105676 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 6189 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 325946 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 43 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 230320 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 636644 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 636644 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 217343 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 12977 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1083 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1203 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8803 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 95013 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 46485 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 44692 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 41453 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 273191 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 4270 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 273407 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10726 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10333 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 504 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 170350 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.604972 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.301874 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 63215 37.25% 37.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 21011 12.38% 49.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 39931 23.53% 73.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 40651 23.96% 97.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3306 1.95% 99.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1205 0.71% 99.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 253 0.15% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 54964 32.27% 32.27% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 16569 9.73% 41.99% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 46599 27.35% 69.35% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 47325 27.78% 97.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3328 1.95% 99.08% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1208 0.71% 99.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 245 0.14% 99.93% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 169684 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 170350 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 17 5.76% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 68 23.05% 28.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 71.19% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 17 5.69% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 72 24.08% 29.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 70.23% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 118250 48.38% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 87046 35.61% 83.99% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 39140 16.01% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 130168 47.61% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 97443 35.64% 83.25% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 45796 16.75% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 244436 # Type of FU issued -system.cpu1.iq.rate 1.404111 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 295 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001207 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 658939 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 259411 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 242683 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 273407 # Type of FU issued +system.cpu1.iq.rate 1.564203 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 299 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001094 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 717543 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 288232 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 271609 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 244731 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 273706 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 34550 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 41212 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2395 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2369 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1432 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedStores 1440 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2348 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 954 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 69 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 289064 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 345 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 83198 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 39823 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1054 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 70 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2341 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 1392 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 323061 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 370 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 95013 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 46485 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1042 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 67 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 455 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 930 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 243277 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 82228 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1159 # Number of squashed instructions skipped in execute +system.cpu1.iew.predictedTakenIncorrect 456 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 928 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1384 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 272209 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 94088 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1198 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 40453 # number of nop insts executed -system.cpu1.iew.exec_refs 121292 # number of memory reference insts executed -system.cpu1.iew.exec_branches 49718 # Number of branches executed -system.cpu1.iew.exec_stores 39064 # Number of stores executed -system.cpu1.iew.exec_rate 1.397453 # Inst execution rate -system.cpu1.iew.wb_sent 242950 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 242683 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 138076 # num instructions producing a value -system.cpu1.iew.wb_consumers 142766 # num instructions consuming a value +system.cpu1.iew.exec_nop 45600 # number of nop insts executed +system.cpu1.iew.exec_refs 139806 # number of memory reference insts executed +system.cpu1.iew.exec_branches 54914 # Number of branches executed +system.cpu1.iew.exec_stores 45718 # Number of stores executed +system.cpu1.iew.exec_rate 1.557349 # Inst execution rate +system.cpu1.iew.wb_sent 271881 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 271609 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 156621 # num instructions producing a value +system.cpu1.iew.wb_consumers 161297 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.394041 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.967149 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.553916 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.971010 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 12362 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 5245 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1268 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 161216 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.716349 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.045856 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 12317 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 3766 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1271 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 161612 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.922772 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.097017 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 62245 38.61% 38.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 47765 29.63% 68.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6052 3.75% 71.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 6179 3.83% 75.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1571 0.97% 76.80% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 35063 21.75% 98.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 510 0.32% 98.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1010 0.63% 99.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 821 0.51% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 52280 32.35% 32.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 52948 32.76% 65.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6058 3.75% 68.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 4700 2.91% 71.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1571 0.97% 72.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 41692 25.80% 98.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 528 0.33% 98.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1013 0.63% 99.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 161216 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 276703 # Number of instructions committed -system.cpu1.commit.committedOps 276703 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 161612 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 310743 # Number of instructions committed +system.cpu1.commit.committedOps 310743 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 119194 # Number of memory references committed -system.cpu1.commit.loads 80803 # Number of loads committed -system.cpu1.commit.membars 4532 # Number of memory barriers committed -system.cpu1.commit.branches 48886 # Number of branches committed +system.cpu1.commit.refs 137689 # Number of memory references committed +system.cpu1.commit.loads 92644 # Number of loads committed +system.cpu1.commit.membars 3055 # Number of memory barriers committed +system.cpu1.commit.branches 54067 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 190203 # Number of committed integer instructions. +system.cpu1.commit.int_insts 213879 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 821 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 822 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 448873 # The number of ROB reads -system.cpu1.rob.rob_writes 580482 # The number of ROB writes -system.cpu1.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 4402 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 35578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 232494 # Number of Instructions Simulated -system.cpu1.committedOps 232494 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 232494 # Number of Instructions Simulated -system.cpu1.cpi 0.748776 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.748776 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.335512 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.335512 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 422524 # number of integer regfile reads -system.cpu1.int_regfile_writes 197153 # number of integer regfile writes +system.cpu1.rob.rob_reads 483263 # The number of ROB reads +system.cpu1.rob.rob_writes 648465 # The number of ROB writes +system.cpu1.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 4440 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 36812 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 262828 # Number of Instructions Simulated +system.cpu1.committedOps 262828 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 262828 # Number of Instructions Simulated +system.cpu1.cpi 0.665036 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.665036 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.503679 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.503679 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 478110 # number of integer regfile reads +system.cpu1.int_regfile_writes 222397 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 122878 # number of misc regfile reads +system.cpu1.misc_regfile_reads 141404 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.icache.replacements 317 # number of replacements -system.cpu1.icache.tagsinuse 85.782711 # Cycle average of tags in use -system.cpu1.icache.total_refs 18178 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 85.239071 # Cycle average of tags in use +system.cpu1.icache.total_refs 15102 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 42.771765 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 35.534118 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 85.782711 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.167544 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.167544 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 18178 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 18178 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 18178 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 18178 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 18178 # number of overall hits -system.cpu1.icache.overall_hits::total 18178 # number of overall hits +system.cpu1.icache.occ_blocks::cpu1.inst 85.239071 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.166483 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.166483 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 15102 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 15102 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 15102 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 15102 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 15102 # number of overall hits +system.cpu1.icache.overall_hits::total 15102 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 482 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 482 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 482 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 482 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 482 # number of overall misses system.cpu1.icache.overall_misses::total 482 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9897000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 9897000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 9897000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 9897000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 9897000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 9897000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 18660 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 18660 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 18660 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 18660 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 18660 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 18660 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.025831 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.025831 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025831 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.025831 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025831 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.025831 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20533.195021 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 20533.195021 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20533.195021 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 20533.195021 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20533.195021 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 20533.195021 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10460500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 10460500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 10460500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 10460500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 10460500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 10460500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 15584 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 15584 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 15584 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 15584 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 15584 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 15584 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030929 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.030929 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030929 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.030929 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030929 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.030929 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21702.282158 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 21702.282158 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21702.282158 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 21702.282158 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21702.282158 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 21702.282158 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 44 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1020,94 +1021,94 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 425 system.cpu1.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 425 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 425 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8054000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8054000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8054000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8054000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8054000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8054000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022776 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.022776 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.022776 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18950.588235 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18950.588235 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18950.588235 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 18950.588235 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18950.588235 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 18950.588235 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8302000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8302000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8302000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8302000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8302000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8302000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027272 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027272 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027272 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.027272 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027272 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.027272 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 19534.117647 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 19534.117647 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19534.117647 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 19534.117647 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19534.117647 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 19534.117647 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 27.224520 # Cycle average of tags in use -system.cpu1.dcache.total_refs 44407 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 27.071497 # Cycle average of tags in use +system.cpu1.dcache.total_refs 51063 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1585.964286 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 1823.678571 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 27.224520 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.053173 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.053173 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 47255 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 47255 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 38187 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 38187 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 85442 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 85442 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 85442 # number of overall hits -system.cpu1.dcache.overall_hits::total 85442 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 407 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 407 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 137 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 137 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 53 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 53 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 544 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 544 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 544 # number of overall misses -system.cpu1.dcache.overall_misses::total 544 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6159500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6159500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2641000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2641000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 528500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 528500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8800500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8800500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8800500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8800500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 47662 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 47662 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 38324 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 38324 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 67 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 85986 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 85986 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 85986 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 85986 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008539 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.008539 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003575 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003575 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.791045 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.791045 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006327 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.006327 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006327 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.006327 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15133.906634 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15133.906634 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19277.372263 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 19277.372263 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9971.698113 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 9971.698113 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16177.389706 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16177.389706 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16177.389706 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16177.389706 # average overall miss latency +system.cpu1.dcache.occ_blocks::cpu1.data 27.071497 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.052874 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.052874 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 52421 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 52421 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 44839 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 44839 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 97260 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 97260 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 97260 # number of overall hits +system.cpu1.dcache.overall_hits::total 97260 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 438 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 438 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 141 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 141 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 54 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 54 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 579 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 579 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 579 # number of overall misses +system.cpu1.dcache.overall_misses::total 579 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8533500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 8533500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3160000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3160000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 510000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 510000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 11693500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 11693500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 11693500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 11693500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 52859 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 52859 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 44980 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 44980 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 65 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 97839 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 97839 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 97839 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 97839 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008286 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.008286 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003135 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.003135 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.830769 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.830769 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005918 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005918 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005918 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005918 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19482.876712 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19482.876712 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22411.347518 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22411.347518 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9444.444444 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 9444.444444 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20196.027634 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20196.027634 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20196.027634 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20196.027634 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1116,365 +1117,365 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 252 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 252 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 284 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 284 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 284 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 284 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 155 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 53 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 260 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 260 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1530000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1530000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1381000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1381000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 422500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 422500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2911000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2911000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2911000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2911000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003252 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003252 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002740 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002740 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.791045 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.791045 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003024 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003024 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003024 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003024 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9870.967742 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9870.967742 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13152.380952 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13152.380952 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7971.698113 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7971.698113 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11196.153846 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11196.153846 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11196.153846 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11196.153846 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 286 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 286 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 320 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 320 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 320 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 320 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 152 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 54 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 259 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 259 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1798500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1798500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1487000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1487000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 402000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 402000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3285500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3285500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3285500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3285500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002876 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002876 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002379 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002379 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.830769 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.830769 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002647 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.002647 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002647 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.002647 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11832.236842 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11832.236842 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13897.196262 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13897.196262 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7444.444444 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7444.444444 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12685.328185 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12685.328185 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12685.328185 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12685.328185 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 43658 # Number of BP lookups -system.cpu2.branchPred.condPredicted 40905 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1282 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 37514 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 36718 # Number of BTB hits +system.cpu2.branchPred.lookups 45099 # Number of BP lookups +system.cpu2.branchPred.condPredicted 42400 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1262 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 39025 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 38304 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.878125 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 654 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 98.152466 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 646 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.numCycles 173761 # number of cpu cycles simulated +system.cpu2.numCycles 174459 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 33388 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 235313 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 43658 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 37372 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 88227 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 3786 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 41181 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 6111 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 690 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 25041 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 172028 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.367876 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.005593 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 32669 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 244823 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 45099 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 38950 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 90929 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 3703 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 39674 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.NoActiveThreadStallCycles 6379 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 712 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 24269 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 265 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 172730 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.417374 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.028063 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 83801 48.71% 48.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 46271 26.90% 75.61% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 8744 5.08% 80.69% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3171 1.84% 82.54% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 732 0.43% 82.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 24119 14.02% 96.98% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1119 0.65% 97.63% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 764 0.44% 98.08% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3307 1.92% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 81801 47.36% 47.36% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 47495 27.50% 74.85% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 8404 4.87% 79.72% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3201 1.85% 81.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 675 0.39% 81.96% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 25947 15.02% 96.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1207 0.70% 97.68% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 760 0.44% 98.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3240 1.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 172028 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.251253 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.354234 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 40935 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 35179 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 79843 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 7534 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2426 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 231751 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2426 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 41648 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 22387 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12001 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 72579 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 14876 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 229374 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 35 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 158064 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 425055 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 425055 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 145196 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12868 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1106 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1225 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 17601 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 61347 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 27349 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 30218 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 22307 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 186544 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 8963 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 190992 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 109 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 11059 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10957 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 650 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 172028 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.110238 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.273778 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 172730 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.258508 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.403327 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 39762 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 34129 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 82888 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 7209 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2363 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 241309 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2363 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 40462 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 21352 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11989 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 75976 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 14209 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 239275 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 36 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 165256 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 446077 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 446077 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 152520 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 12736 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1091 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1215 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 16777 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 64738 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 29196 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 31698 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 24168 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 195168 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 8612 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 199473 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 72 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 10767 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10430 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 654 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 172730 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.154825 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.283743 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 81447 47.35% 47.35% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 30126 17.51% 64.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 27409 15.93% 80.79% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 28202 16.39% 97.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3303 1.92% 99.10% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1178 0.68% 99.79% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 256 0.15% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 79387 45.96% 45.96% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 29099 16.85% 62.81% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 29295 16.96% 79.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 30090 17.42% 97.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3300 1.91% 99.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1204 0.70% 99.79% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 247 0.14% 99.94% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 56 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 172028 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 172730 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 11 3.83% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 66 23.00% 26.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 73.17% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 16 5.67% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 56 19.86% 25.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 74.47% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 96218 50.38% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 68109 35.66% 86.04% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 26665 13.96% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 99688 49.98% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 71251 35.72% 85.70% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 28534 14.30% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 190992 # Type of FU issued -system.cpu2.iq.rate 1.099165 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 287 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001503 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 554408 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 206613 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 189211 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 199473 # Type of FU issued +system.cpu2.iq.rate 1.143380 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 282 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001414 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 572030 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 214590 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 197726 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 191279 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 199755 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 22028 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 23953 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2518 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2414 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1460 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1398 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2426 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 904 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 226591 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 328 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 61347 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 27349 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1066 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 54 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2363 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 870 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 45 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 236415 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 392 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 64738 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 29196 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1054 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 47 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 929 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1394 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 189819 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 60231 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1173 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 43 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 913 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1372 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 198312 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 63718 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1161 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 31084 # number of nop insts executed -system.cpu2.iew.exec_refs 86815 # number of memory reference insts executed -system.cpu2.iew.exec_branches 40244 # Number of branches executed -system.cpu2.iew.exec_stores 26584 # Number of stores executed -system.cpu2.iew.exec_rate 1.092414 # Inst execution rate -system.cpu2.iew.wb_sent 189481 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 189211 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 103581 # num instructions producing a value -system.cpu2.iew.wb_consumers 108246 # num instructions consuming a value +system.cpu2.iew.exec_nop 32635 # number of nop insts executed +system.cpu2.iew.exec_refs 92179 # number of memory reference insts executed +system.cpu2.iew.exec_branches 41831 # Number of branches executed +system.cpu2.iew.exec_stores 28461 # Number of stores executed +system.cpu2.iew.exec_rate 1.136726 # Inst execution rate +system.cpu2.iew.wb_sent 197998 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 197726 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 108943 # num instructions producing a value +system.cpu2.iew.wb_consumers 113613 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.088915 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.956904 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.133367 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.958896 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 12701 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 8313 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1282 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 163491 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.308145 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.875240 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 12414 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 7958 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1262 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 163988 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.365838 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.905647 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 83403 51.01% 51.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 38322 23.44% 74.45% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6091 3.73% 78.18% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 9201 5.63% 83.81% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1555 0.95% 84.76% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 22612 13.83% 98.59% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 481 0.29% 98.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1011 0.62% 99.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 815 0.50% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 80806 49.28% 49.28% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 39854 24.30% 73.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6054 3.69% 77.27% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 8882 5.42% 82.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1574 0.96% 83.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 24481 14.93% 98.57% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 507 0.31% 98.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1010 0.62% 99.50% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 820 0.50% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 163491 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 213870 # Number of instructions committed -system.cpu2.commit.committedOps 213870 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 163988 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 223981 # Number of instructions committed +system.cpu2.commit.committedOps 223981 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 84718 # Number of memory references committed -system.cpu2.commit.loads 58829 # Number of loads committed -system.cpu2.commit.membars 7592 # Number of memory barriers committed -system.cpu2.commit.branches 39438 # Number of branches committed +system.cpu2.commit.refs 90122 # Number of memory references committed +system.cpu2.commit.loads 62324 # Number of loads committed +system.cpu2.commit.membars 7244 # Number of memory barriers committed +system.cpu2.commit.branches 41003 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 146274 # Number of committed integer instructions. +system.cpu2.commit.int_insts 153248 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 815 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 820 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 388660 # The number of ROB reads -system.cpu2.rob.rob_writes 455572 # The number of ROB writes -system.cpu2.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1733 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 35903 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 176057 # Number of Instructions Simulated -system.cpu2.committedOps 176057 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 176057 # Number of Instructions Simulated -system.cpu2.cpi 0.986959 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.986959 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.013214 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.013214 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 319023 # number of integer regfile reads -system.cpu2.int_regfile_writes 150022 # number of integer regfile writes +system.cpu2.rob.rob_reads 398976 # The number of ROB reads +system.cpu2.rob.rob_writes 475157 # The number of ROB writes +system.cpu2.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1729 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 37143 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 184944 # Number of Instructions Simulated +system.cpu2.committedOps 184944 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 184944 # Number of Instructions Simulated +system.cpu2.cpi 0.943307 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.943307 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.060100 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.060100 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 335090 # number of integer regfile reads +system.cpu2.int_regfile_writes 157371 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 88368 # number of misc regfile reads +system.cpu2.misc_regfile_reads 93758 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.icache.replacements 319 # number of replacements -system.cpu2.icache.tagsinuse 80.119801 # Cycle average of tags in use -system.cpu2.icache.total_refs 24566 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 429 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 57.263403 # Average number of references to valid blocks. +system.cpu2.icache.tagsinuse 83.416337 # Cycle average of tags in use +system.cpu2.icache.total_refs 23791 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 430 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 55.327907 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 80.119801 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.156484 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.156484 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 24566 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 24566 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 24566 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 24566 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 24566 # number of overall hits -system.cpu2.icache.overall_hits::total 24566 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 475 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 475 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 475 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 475 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 475 # number of overall misses -system.cpu2.icache.overall_misses::total 475 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6355000 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 6355000 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 6355000 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 6355000 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 6355000 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 6355000 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 25041 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 25041 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 25041 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 25041 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 25041 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 25041 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.018969 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.018969 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.018969 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.018969 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.018969 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.018969 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13378.947368 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 13378.947368 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13378.947368 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 13378.947368 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13378.947368 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 13378.947368 # average overall miss latency +system.cpu2.icache.occ_blocks::cpu2.inst 83.416337 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.162923 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.162923 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 23791 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 23791 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 23791 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 23791 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 23791 # number of overall hits +system.cpu2.icache.overall_hits::total 23791 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 478 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 478 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 478 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 478 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 478 # number of overall misses +system.cpu2.icache.overall_misses::total 478 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6751000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 6751000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 6751000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 6751000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 6751000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 6751000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 24269 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 24269 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 24269 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 24269 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 24269 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 24269 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.019696 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.019696 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.019696 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.019696 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.019696 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.019696 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14123.430962 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 14123.430962 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14123.430962 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 14123.430962 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14123.430962 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 14123.430962 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1483,106 +1484,106 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 46 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 46 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 46 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 46 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 429 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 429 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 429 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 429 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5129000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 5129000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5129000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 5129000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5129000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 5129000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.017132 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.017132 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.017132 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11955.710956 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 11955.710956 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11955.710956 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 11955.710956 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11955.710956 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 11955.710956 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 48 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 48 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 48 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 48 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 430 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 430 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 430 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 430 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5435000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 5435000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5435000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 5435000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5435000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 5435000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.017718 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.017718 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.017718 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.017718 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.017718 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.017718 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12639.534884 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12639.534884 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12639.534884 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 12639.534884 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12639.534884 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 12639.534884 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 24.751060 # Cycle average of tags in use -system.cpu2.dcache.total_refs 32016 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 25.649065 # Cycle average of tags in use +system.cpu2.dcache.total_refs 33911 # Total number of references to valid blocks. system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1104 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 1169.344828 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 24.751060 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.048342 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.048342 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 37788 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 37788 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 25681 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 25681 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 16 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 63469 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 63469 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 63469 # number of overall hits -system.cpu2.dcache.overall_hits::total 63469 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 397 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 397 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 133 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 133 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 59 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 59 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 530 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 530 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 530 # number of overall misses -system.cpu2.dcache.overall_misses::total 530 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5134500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 5134500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2352000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2352000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 565000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 565000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 7486500 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 7486500 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 7486500 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 7486500 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 38185 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 38185 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 25814 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 25814 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 75 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 75 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 63999 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 63999 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 63999 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 63999 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010397 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.010397 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.005152 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.005152 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.786667 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.786667 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008281 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.008281 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008281 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.008281 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12933.249370 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 12933.249370 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17684.210526 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 17684.210526 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9576.271186 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 9576.271186 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14125.471698 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 14125.471698 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14125.471698 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 14125.471698 # average overall miss latency +system.cpu2.dcache.occ_blocks::cpu2.data 25.649065 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.050096 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.050096 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 39345 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 39345 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 27592 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 27592 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 15 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 15 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 66937 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 66937 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 66937 # number of overall hits +system.cpu2.dcache.overall_hits::total 66937 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 402 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 402 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 138 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 138 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 53 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 53 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 540 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 540 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 540 # number of overall misses +system.cpu2.dcache.overall_misses::total 540 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5276000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 5276000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2759500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2759500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 558000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 558000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 8035500 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 8035500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 8035500 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 8035500 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 39747 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 39747 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 27730 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 27730 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 67477 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 67477 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 67477 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 67477 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010114 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.010114 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004977 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004977 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.779412 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.779412 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008003 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.008003 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008003 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.008003 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13124.378109 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 13124.378109 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19996.376812 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 19996.376812 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10528.301887 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 10528.301887 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14880.555556 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 14880.555556 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14880.555556 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 14880.555556 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1591,365 +1592,365 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 227 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 227 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 32 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 259 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 259 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 259 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 259 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 170 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 59 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1408000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1408000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1144000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1144000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 447000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 447000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2552000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 2552000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2552000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 2552000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004452 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004452 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003913 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003913 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.786667 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.786667 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004234 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004234 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004234 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004234 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8282.352941 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8282.352941 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 11326.732673 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 11326.732673 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7576.271186 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7576.271186 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9416.974170 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9416.974170 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9416.974170 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9416.974170 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 241 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 241 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 274 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 274 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 274 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 274 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 53 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 266 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 266 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1358500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1358500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1350500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1350500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 452000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 452000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2709000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 2709000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2709000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 2709000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004051 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004051 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003787 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003787 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.779412 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.779412 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003942 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003942 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003942 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003942 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8437.888199 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8437.888199 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 12861.904762 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 12861.904762 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8528.301887 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8528.301887 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 10184.210526 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 10184.210526 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 10184.210526 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 10184.210526 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 53689 # Number of BP lookups -system.cpu3.branchPred.condPredicted 50963 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1276 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 47522 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 46772 # Number of BTB hits +system.cpu3.branchPred.lookups 47073 # Number of BP lookups +system.cpu3.branchPred.condPredicted 44334 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1289 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 40998 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 40129 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 98.421784 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 661 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 97.880384 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 665 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.numCycles 173451 # number of cpu cycles simulated +system.cpu3.numCycles 174149 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 27478 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 301364 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 53689 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 47433 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 105433 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 3739 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 29902 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 31334 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 257802 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 47073 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 40794 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 94093 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 3784 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 37693 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 6129 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 699 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 19205 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 172033 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.751780 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.162655 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 6388 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 691 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 23091 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 274 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 172622 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.493448 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.066617 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 66600 38.71% 38.71% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 53421 31.05% 69.77% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 5840 3.39% 73.16% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3208 1.86% 75.03% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 724 0.42% 75.45% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 37060 21.54% 96.99% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1114 0.65% 97.64% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 769 0.45% 98.08% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3297 1.92% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 78529 45.49% 45.49% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 48697 28.21% 73.70% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 7780 4.51% 78.21% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3181 1.84% 80.05% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 739 0.43% 80.48% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 28510 16.52% 97.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1109 0.64% 97.64% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 774 0.45% 98.09% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3303 1.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 172033 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.309534 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.737459 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 32330 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 26595 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 99740 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 4852 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2387 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 297875 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2387 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 33042 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 14161 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 11648 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 95160 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 9506 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 295501 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 42 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 206976 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 568781 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 568781 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 194055 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 12921 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1094 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1213 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 12164 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 84323 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 40264 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 40234 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 35231 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 245467 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 6061 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 247268 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 84 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 10933 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 10571 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 569 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 172033 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.437329 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.311411 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 172622 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.270303 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.480353 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 38095 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 32492 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 86590 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 6639 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2418 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 254216 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2418 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 38798 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 19631 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 12074 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 80231 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 13082 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 251848 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 33 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 174600 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 473869 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 473869 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 161804 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 12796 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1100 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1222 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 15769 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 69165 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 31749 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 33643 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 26714 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 206536 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 7999 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 210100 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 110 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 10964 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10853 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 623 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 172622 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.217110 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.294923 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 63997 37.20% 37.20% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 21775 12.66% 49.86% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 40282 23.42% 73.27% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 41064 23.87% 97.14% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3352 1.95% 99.09% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1207 0.70% 99.79% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 253 0.15% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 48 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 76068 44.07% 44.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 27297 15.81% 59.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 31861 18.46% 78.34% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 32569 18.87% 97.20% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3286 1.90% 99.11% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1177 0.68% 99.79% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 258 0.15% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 51 0.03% 99.97% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 172033 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 172622 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 11 3.83% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 66 23.00% 26.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 73.17% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 11 3.79% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 69 23.79% 27.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 72.41% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 119306 48.25% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 88375 35.74% 83.99% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 39587 16.01% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 104024 49.51% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 75016 35.70% 85.22% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 31060 14.78% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 247268 # Type of FU issued -system.cpu3.iq.rate 1.425578 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 287 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001161 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 666940 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 262506 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 245488 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 210100 # Type of FU issued +system.cpu3.iq.rate 1.206438 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 290 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001380 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 593222 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 225545 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 208328 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 247555 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 210390 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 34962 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 26418 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2463 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2499 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1469 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1475 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2387 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 786 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 292672 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 339 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 84323 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 40264 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2418 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 854 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 249047 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 315 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 69165 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 31749 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1065 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 58 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 45 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 463 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 932 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1395 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 246092 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 83308 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1176 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 46 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 473 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 935 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1408 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 208934 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 68077 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1166 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 41144 # number of nop insts executed -system.cpu3.iew.exec_refs 122814 # number of memory reference insts executed -system.cpu3.iew.exec_branches 50378 # Number of branches executed -system.cpu3.iew.exec_stores 39506 # Number of stores executed -system.cpu3.iew.exec_rate 1.418798 # Inst execution rate -system.cpu3.iew.wb_sent 245754 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 245488 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 139611 # num instructions producing a value -system.cpu3.iew.wb_consumers 144276 # num instructions consuming a value +system.cpu3.iew.exec_nop 34512 # number of nop insts executed +system.cpu3.iew.exec_refs 99056 # number of memory reference insts executed +system.cpu3.iew.exec_branches 43690 # Number of branches executed +system.cpu3.iew.exec_stores 30979 # Number of stores executed +system.cpu3.iew.exec_rate 1.199743 # Inst execution rate +system.cpu3.iew.wb_sent 208597 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 208328 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 115832 # num instructions producing a value +system.cpu3.iew.wb_consumers 120507 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.415316 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.967666 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.196263 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.961206 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 12526 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 5492 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1276 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 163517 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.713131 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.043728 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 12582 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7376 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1289 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 163816 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.443357 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.942306 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 63246 38.68% 38.68% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 48405 29.60% 68.28% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6092 3.73% 72.01% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 6399 3.91% 75.92% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1556 0.95% 76.87% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 35438 21.67% 98.54% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 553 0.34% 98.88% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1016 0.62% 99.50% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 76810 46.89% 46.89% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 41800 25.52% 72.40% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6086 3.72% 76.12% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8257 5.04% 81.16% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1545 0.94% 82.10% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 27022 16.50% 98.60% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 472 0.29% 98.89% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1012 0.62% 99.50% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::8 812 0.50% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 163517 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 280126 # Number of instructions committed -system.cpu3.commit.committedOps 280126 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 163816 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 236445 # Number of instructions committed +system.cpu3.commit.committedOps 236445 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 120655 # Number of memory references committed -system.cpu3.commit.loads 81860 # Number of loads committed -system.cpu3.commit.membars 4779 # Number of memory barriers committed -system.cpu3.commit.branches 49541 # Number of branches committed +system.cpu3.commit.refs 96940 # Number of memory references committed +system.cpu3.commit.loads 66666 # Number of loads committed +system.cpu3.commit.membars 6656 # Number of memory barriers committed +system.cpu3.commit.branches 42889 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 192316 # Number of committed integer instructions. +system.cpu3.commit.int_insts 161946 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. system.cpu3.commit.bw_lim_events 812 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 454770 # The number of ROB reads -system.cpu3.rob.rob_writes 587696 # The number of ROB writes -system.cpu3.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1418 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 36213 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 235015 # Number of Instructions Simulated -system.cpu3.committedOps 235015 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 235015 # Number of Instructions Simulated -system.cpu3.cpi 0.738042 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.738042 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.354936 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.354936 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 427046 # number of integer regfile reads -system.cpu3.int_regfile_writes 198986 # number of integer regfile writes +system.cpu3.rob.rob_reads 411444 # The number of ROB reads +system.cpu3.rob.rob_writes 500477 # The number of ROB writes +system.cpu3.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1527 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 37453 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 196116 # Number of Instructions Simulated +system.cpu3.committedOps 196116 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 196116 # Number of Instructions Simulated +system.cpu3.cpi 0.887990 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.887990 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.126139 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.126139 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 355696 # number of integer regfile reads +system.cpu3.int_regfile_writes 166589 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 124374 # number of misc regfile reads +system.cpu3.misc_regfile_reads 100584 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.icache.replacements 318 # number of replacements -system.cpu3.icache.tagsinuse 83.494084 # Cycle average of tags in use -system.cpu3.icache.total_refs 18731 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 428 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 43.764019 # Average number of references to valid blocks. +system.cpu3.icache.tagsinuse 80.204482 # Cycle average of tags in use +system.cpu3.icache.total_refs 22614 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 429 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 52.713287 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 83.494084 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.163074 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.163074 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 18731 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 18731 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 18731 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 18731 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 18731 # number of overall hits -system.cpu3.icache.overall_hits::total 18731 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 474 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 474 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 474 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 474 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 474 # number of overall misses -system.cpu3.icache.overall_misses::total 474 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6189500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6189500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6189500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6189500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6189500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6189500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 19205 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 19205 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 19205 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 19205 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 19205 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 19205 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.024681 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.024681 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.024681 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.024681 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.024681 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.024681 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13058.016878 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13058.016878 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13058.016878 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13058.016878 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13058.016878 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13058.016878 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 80.204482 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.156649 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.156649 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 22614 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 22614 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 22614 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 22614 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 22614 # number of overall hits +system.cpu3.icache.overall_hits::total 22614 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 477 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 477 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 477 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 477 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 477 # number of overall misses +system.cpu3.icache.overall_misses::total 477 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6252000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6252000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6252000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6252000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6252000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6252000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 23091 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 23091 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 23091 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 23091 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 23091 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 23091 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020657 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.020657 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020657 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.020657 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020657 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.020657 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13106.918239 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13106.918239 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13106.918239 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13106.918239 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13106.918239 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13106.918239 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1958,106 +1959,106 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 46 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 46 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 46 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 46 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 428 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 428 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 428 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 428 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4969500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4969500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4969500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4969500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4969500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4969500 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.022286 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.022286 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.022286 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.022286 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.022286 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.022286 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11610.981308 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11610.981308 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11610.981308 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 11610.981308 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11610.981308 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 11610.981308 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 48 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 48 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 48 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 48 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 429 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 429 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 429 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 429 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4992500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4992500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4992500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4992500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4992500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4992500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.018579 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.018579 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.018579 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.018579 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.018579 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.018579 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11637.529138 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11637.529138 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11637.529138 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 11637.529138 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11637.529138 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 11637.529138 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 0 # number of replacements -system.cpu3.dcache.tagsinuse 25.854191 # Cycle average of tags in use -system.cpu3.dcache.total_refs 44812 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 24.557568 # Cycle average of tags in use +system.cpu3.dcache.total_refs 36284 # Total number of references to valid blocks. system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1600.428571 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 1295.857143 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 25.854191 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.050496 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.050496 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 47902 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 47902 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 38586 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 38586 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 86488 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 86488 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 86488 # number of overall hits -system.cpu3.dcache.overall_hits::total 86488 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 426 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 426 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 142 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 142 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 568 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 568 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 568 # number of overall misses -system.cpu3.dcache.overall_misses::total 568 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 5341000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 5341000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2325000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2325000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 555000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 555000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 7666000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 7666000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 7666000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 7666000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 48328 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 48328 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 38728 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 38728 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 87056 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 87056 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 87056 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 87056 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.008815 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.008815 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003667 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.003667 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.835821 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.835821 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006525 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.006525 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006525 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.006525 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12537.558685 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 12537.558685 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16373.239437 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 16373.239437 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9910.714286 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 9910.714286 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 13496.478873 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 13496.478873 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 13496.478873 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 13496.478873 # average overall miss latency +system.cpu3.dcache.occ_blocks::cpu3.data 24.557568 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.047964 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.047964 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 41265 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41265 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 30070 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 30070 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 71335 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 71335 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 71335 # number of overall hits +system.cpu3.dcache.overall_hits::total 71335 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 376 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 376 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 130 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 130 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 59 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 59 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 506 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 506 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 506 # number of overall misses +system.cpu3.dcache.overall_misses::total 506 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4881500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 4881500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2539500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2539500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 546000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 546000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 7421000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 7421000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 7421000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 7421000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41641 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41641 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 30200 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 30200 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 74 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 74 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 71841 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 71841 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 71841 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 71841 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009030 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.009030 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004305 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.004305 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.797297 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.797297 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007043 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.007043 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007043 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.007043 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12982.712766 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 12982.712766 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19534.615385 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 19534.615385 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9254.237288 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 9254.237288 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14666.007905 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 14666.007905 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14666.007905 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 14666.007905 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2066,288 +2067,288 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 273 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 273 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 306 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 306 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 306 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 306 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 153 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 109 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 262 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 262 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1264000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1264000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1158000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1158000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 443000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 443000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2422000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2422000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2422000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2422000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003166 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003166 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002815 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002815 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.835821 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.835821 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003010 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003010 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003010 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003010 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 8261.437908 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 8261.437908 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 10623.853211 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 10623.853211 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7910.714286 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7910.714286 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9244.274809 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9244.274809 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9244.274809 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9244.274809 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 218 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 218 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 30 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 30 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 248 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 248 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 248 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 158 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 100 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 59 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 258 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 258 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 258 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 258 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1328000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1328000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1243000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1243000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 428000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 428000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2571000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2571000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2571000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2571000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003794 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003794 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003311 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003311 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.797297 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.797297 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003591 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003591 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003591 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003591 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 8405.063291 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 8405.063291 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12430 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12430 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7254.237288 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7254.237288 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9965.116279 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9965.116279 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9965.116279 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9965.116279 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 425.291959 # Cycle average of tags in use -system.l2c.total_refs 1448 # Total number of references to valid blocks. -system.l2c.sampled_refs 525 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.758095 # Average number of references to valid blocks. +system.l2c.tagsinuse 425.230692 # Cycle average of tags in use +system.l2c.total_refs 1445 # Total number of references to valid blocks. +system.l2c.sampled_refs 527 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.741935 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 0.828889 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 289.887816 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 59.267955 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 63.508377 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 5.639601 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 2.310233 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.728238 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 2.354132 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.766718 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 0.824596 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 289.832857 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 59.073855 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 61.730806 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 5.603647 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 4.388881 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 0.760374 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 2.293580 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 0.722095 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.004423 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.000904 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.000969 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.004422 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.000901 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.000942 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.000086 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000035 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.000036 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.000067 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.000012 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.inst 0.000035 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.006489 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 230 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 342 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 421 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 418 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 424 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 423 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1448 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1445 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 230 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 342 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 421 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 418 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 424 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 423 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 1448 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 229 # number of overall hits +system.l2c.demand_hits::total 1445 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 230 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits system.l2c.overall_hits::cpu1.inst 342 # number of overall hits system.l2c.overall_hits::cpu1.data 5 # number of overall hits -system.l2c.overall_hits::cpu2.inst 421 # number of overall hits +system.l2c.overall_hits::cpu2.inst 418 # number of overall hits system.l2c.overall_hits::cpu2.data 11 # number of overall hits -system.l2c.overall_hits::cpu3.inst 424 # number of overall hits +system.l2c.overall_hits::cpu3.inst 423 # number of overall hits system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 1448 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses +system.l2c.overall_hits::total 1445 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 360 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 83 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 8 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 4 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.inst 6 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 537 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 72 # number of UpgradeReq misses +system.l2c.ReadReq_misses::total 544 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 18 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 71 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 359 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 360 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 83 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 8 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 4 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 6 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::total 668 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 359 # number of overall misses +system.l2c.demand_misses::total 675 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 360 # number of overall misses system.l2c.overall_misses::cpu0.data 168 # number of overall misses system.l2c.overall_misses::cpu1.inst 83 # number of overall misses system.l2c.overall_misses::cpu1.data 20 # number of overall misses -system.l2c.overall_misses::cpu2.inst 8 # number of overall misses +system.l2c.overall_misses::cpu2.inst 12 # number of overall misses system.l2c.overall_misses::cpu2.data 13 # number of overall misses -system.l2c.overall_misses::cpu3.inst 4 # number of overall misses +system.l2c.overall_misses::cpu3.inst 6 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses -system.l2c.overall_misses::total 668 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 17552500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 4069000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 4145500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 381000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 395000 # number of ReadReq miss cycles +system.l2c.overall_misses::total 675 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 18237500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 4615000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 4399500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 666000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 728500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.data 68500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 232000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 248500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.data 68500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 26912000 # number of ReadReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5008000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 878500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 701000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 660000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7247500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 17552500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 9077000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 4145500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1259500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 395000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 769500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 232000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 728500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 34159500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 17552500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 9077000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 4145500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1259500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 395000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 769500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 232000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 728500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 34159500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_miss_latency::total 29032000 # number of ReadReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5403000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 996000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 869000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 756000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 8024000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 18237500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 10018000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 4399500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1662000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 728500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 937500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 248500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 824500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 37056000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 18237500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 10018000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 4399500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1662000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 728500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 937500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 248500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 824500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 37056000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 590 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 425 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 429 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 430 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 428 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 429 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1985 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1989 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 22 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 75 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 21 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 74 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 588 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 590 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 425 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 429 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 430 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 428 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 429 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2116 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 588 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2120 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 590 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 425 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 429 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 430 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 428 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 429 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2116 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.610544 # miss rate for ReadReq accesses +system.l2c.overall_accesses::total 2120 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.610169 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.195294 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.018648 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.027907 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.009346 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.013986 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.270529 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.863636 # miss rate for UpgradeReq accesses +system.l2c.ReadReq_miss_rate::total 0.273504 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.857143 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.960000 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.959459 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.610544 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.610169 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.195294 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.018648 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.027907 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.009346 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.013986 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.315690 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.610544 # miss rate for overall accesses +system.l2c.demand_miss_rate::total 0.318396 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.610169 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.195294 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.018648 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.027907 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.009346 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.013986 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.315690 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 48892.757660 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 54986.486486 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49945.783133 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 54428.571429 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49375 # average ReadReq miss latency +system.l2c.overall_miss_rate::total 0.318396 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 50659.722222 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 62364.864865 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53006.024096 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 95142.857143 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 60708.333333 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.data 68500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 58000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 41416.666667 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.data 68500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 50115.456238 # average ReadReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53276.595745 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 67576.923077 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 58416.666667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 55000 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 55324.427481 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 48892.757660 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 54029.761905 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 49945.783133 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 62975 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 49375 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 59192.307692 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 58000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 56038.461538 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 51136.976048 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 48892.757660 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 54029.761905 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 49945.783133 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 62975 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 49375 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 59192.307692 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 58000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 56038.461538 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 51136.976048 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::total 53367.647059 # average ReadReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 57478.723404 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76615.384615 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 72416.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 63000 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 61251.908397 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 50659.722222 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 59630.952381 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 53006.024096 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 83100 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 60708.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 72115.384615 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 41416.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 63423.076923 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 54897.777778 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 50659.722222 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 59630.952381 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 53006.024096 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 83100 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 60708.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 72115.384615 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 41416.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 63423.076923 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 54897.777778 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2357,165 +2358,168 @@ system.l2c.avg_blocked_cycles::no_targets nan # a system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.inst 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.inst 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3.inst 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 6 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 357 # number of ReadReq MSHR misses +system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 6 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 14 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.inst 358 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 81 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 80 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 3 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 6 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.inst 4 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.inst 3 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 528 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 19 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 18 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 15 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 72 # number of UpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 530 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 18 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 19 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 18 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 71 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 357 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 358 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 81 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 80 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 3 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 6 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.inst 4 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.inst 3 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 659 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 357 # number of overall MSHR misses +system.l2c.demand_mshr_misses::total 661 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 358 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 81 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 80 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 3 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 6 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.inst 4 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.inst 3 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 659 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13005059 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3150576 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3026126 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 293010 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 103002 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 56002 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 180507 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.data 56002 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 19870284 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 193013 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 181515 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 153009 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 200519 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 728056 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3834610 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 717513 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 550018 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 510018 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5612159 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 13005059 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 6985186 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 3026126 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1010523 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 103002 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 606020 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 180507 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 566020 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 25482443 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 13005059 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 6985186 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 3026126 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1010523 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 103002 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 606020 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 180507 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 566020 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 25482443 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_misses::total 661 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13753074 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3705088 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3257128 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 578261 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 230760 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 56252 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 86256 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.data 56252 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 21723071 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 184010 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 190518 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 161513 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 191511 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 727552 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4247116 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 838760 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 720020 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 607520 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 6413416 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 13753074 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 7952204 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 3257128 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1417021 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 230760 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 776272 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 86256 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 663772 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 28136487 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 13753074 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 7952204 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 3257128 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1417021 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 230760 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 776272 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 86256 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 663772 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 28136487 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.190588 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.006993 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.013953 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.009346 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.265995 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.863636 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.266466 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.857143 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.960000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.959459 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.190588 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006993 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.013953 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.009346 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.311437 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::total 0.311792 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.190588 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006993 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.013953 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.009346 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.311437 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 36428.736695 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 42575.351351 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 37359.580247 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41858.571429 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 34334 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56002 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 45126.750000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56002 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 37633.113636 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10158.578947 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10084.166667 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10200.600000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10025.950000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10111.888889 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40793.723404 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55193.307692 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 45834.833333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42501.500000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 42840.908397 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 36428.736695 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41578.488095 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 37359.580247 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50526.150000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 34334 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 46616.923077 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 45126.750000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 43540 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 38668.350531 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36428.736695 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41578.488095 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 37359.580247 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50526.150000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 34334 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 46616.923077 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 45126.750000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 43540 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 38668.350531 # average overall mshr miss latency +system.l2c.overall_mshr_miss_rate::total 0.311792 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50068.756757 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82608.714286 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 38460 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56252 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 28752 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56252 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40986.926415 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10222.777778 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.263158 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10094.562500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10639.500000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10247.211268 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 45182.085106 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64520 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60001.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50626.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 48957.374046 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47334.547619 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70851.050000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 38460 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59713.230769 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 28752 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51059.384615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42566.546142 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47334.547619 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70851.050000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 38460 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59713.230769 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 28752 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51059.384615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42566.546142 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt index eb01eb1c6..e7866c92f 100644 --- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt +++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 18434818132 # Simulator tick rate (ticks/s) -host_mem_usage 219256 # Number of bytes of host memory used -host_seconds 5.42 # Real time elapsed on the host +host_tick_rate 29045358432 # Simulator tick rate (ticks/s) +host_mem_usage 222412 # Number of bytes of host memory used +host_seconds 3.44 # Real time elapsed on the host system.physmem.bytes_read::cpu 213337536 # Number of bytes read from this memory system.physmem.bytes_read::total 213337536 # Number of bytes read from this memory system.physmem.num_reads::cpu 3333399 # Number of read requests responded to by this memory @@ -25,21 +25,21 @@ system.physmem.bytesConsumedWr 0 # by system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 210200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 204800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 210200 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 208000 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -86,18 +86,18 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 3267797 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 52471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1602 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1074 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1074 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 804 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 274 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3200711 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 105371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 4811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3752 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3205 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1602 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1076 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 546 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see @@ -152,25 +152,25 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2980562702 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 63351670702 # Sum of mem lat for all requests -system.physmem.totBusLat 13333600000 # Total cycles spent in databus access -system.physmem.totBankLat 47037508000 # Total cycles spent in bank access -system.physmem.avgQLat 894.15 # Average queueing delay per request -system.physmem.avgBankLat 14110.97 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 19005.12 # Average memory access latency +system.physmem.totQLat 6115686626 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 69505296626 # Sum of mem lat for all requests +system.physmem.totBusLat 16667000000 # Total cycles spent in databus access +system.physmem.totBankLat 46722610000 # Total cycles spent in bank access +system.physmem.avgQLat 1834.67 # Average queueing delay per request +system.physmem.avgBankLat 14016.50 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 20851.17 # Average memory access latency system.physmem.avgRdBW 2133.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2133.38 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 13.33 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.63 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 16.67 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.70 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 3281300 # Number of row buffer hits during reads +system.physmem.readRowHits 3229200 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 98.44 # Row buffer hit rate for reads +system.physmem.readRowHitRate 96.87 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 29999.40 # Average gap between requests system.monitor.readBurstLengthHist::samples 3333400 # Histogram of burst lengths of transmitted packets @@ -278,20 +278,20 @@ system.monitor.writeBandwidthHist::total 100 # Hi system.monitor.averageWriteBandwidth 0 # Average write bandwidth (bytes/s) system.monitor.totalWrittenBytes 0 # Number of bytes written system.monitor.readLatencyHist::samples 3333399 # Read request-response latency -system.monitor.readLatencyHist::mean 19061.873685 # Read request-response latency -system.monitor.readLatencyHist::gmean 18381.352509 # Read request-response latency -system.monitor.readLatencyHist::stdev 11230.520439 # Read request-response latency -system.monitor.readLatencyHist::0-32767 3267631 98.03% 98.03% # Read request-response latency -system.monitor.readLatencyHist::32768-65535 52364 1.57% 99.60% # Read request-response latency -system.monitor.readLatencyHist::65536-98303 2680 0.08% 99.68% # Read request-response latency -system.monitor.readLatencyHist::98304-131071 2415 0.07% 99.75% # Read request-response latency -system.monitor.readLatencyHist::131072-163839 2133 0.06% 99.81% # Read request-response latency -system.monitor.readLatencyHist::163840-196607 1602 0.05% 99.86% # Read request-response latency -system.monitor.readLatencyHist::196608-229375 1620 0.05% 99.91% # Read request-response latency -system.monitor.readLatencyHist::229376-262143 1066 0.03% 99.94% # Read request-response latency -system.monitor.readLatencyHist::262144-294911 802 0.02% 99.97% # Read request-response latency -system.monitor.readLatencyHist::294912-327679 812 0.02% 99.99% # Read request-response latency -system.monitor.readLatencyHist::327680-360447 274 0.01% 100.00% # Read request-response latency +system.monitor.readLatencyHist::mean 20879.051770 # Read request-response latency +system.monitor.readLatencyHist::gmean 19622.150808 # Read request-response latency +system.monitor.readLatencyHist::stdev 15688.008500 # Read request-response latency +system.monitor.readLatencyHist::0-32767 3201881 96.05% 96.05% # Read request-response latency +system.monitor.readLatencyHist::32768-65535 104731 3.14% 99.20% # Read request-response latency +system.monitor.readLatencyHist::65536-98303 5355 0.16% 99.36% # Read request-response latency +system.monitor.readLatencyHist::98304-131071 4826 0.14% 99.50% # Read request-response latency +system.monitor.readLatencyHist::131072-163839 4267 0.13% 99.63% # Read request-response latency +system.monitor.readLatencyHist::163840-196607 3205 0.10% 99.73% # Read request-response latency +system.monitor.readLatencyHist::196608-229375 3236 0.10% 99.82% # Read request-response latency +system.monitor.readLatencyHist::229376-262143 2130 0.06% 99.89% # Read request-response latency +system.monitor.readLatencyHist::262144-294911 1602 0.05% 99.94% # Read request-response latency +system.monitor.readLatencyHist::294912-327679 1620 0.05% 99.98% # Read request-response latency +system.monitor.readLatencyHist::327680-360447 546 0.02% 100.00% # Read request-response latency system.monitor.readLatencyHist::360448-393215 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::393216-425983 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::425984-458751 0 0.00% 100.00% # Read request-response latency |