diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-06-06 17:16:44 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-06-06 17:16:44 +0100 |
| commit | 85997e66a08b71d701e5b41462d1cfd42660b0c7 (patch) | |
| tree | bc242f1a2bfc3a92b18da04805d9ebd8864b5320 /tests/quick/se | |
| parent | 21b66f45422bc449d4a8b86ab452d6b6ae5838bf (diff) | |
| download | gem5-85997e66a08b71d701e5b41462d1cfd42660b0c7.tar.xz | |
stats: Add power stats to test references
Change-Id: Ic827213134b199446822f128b81d4a480e777fee
Diffstat (limited to 'tests/quick/se')
90 files changed, 1674 insertions, 384 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index 6544ab634..7fa71daaa 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000037 # Nu sim_ticks 37494000 # Number of ticks simulated final_tick 37494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 176621 # Simulator instruction rate (inst/s) -host_op_rate 176529 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1031613588 # Simulator tick rate (ticks/s) -host_mem_usage 248004 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 200557 # Simulator instruction rate (inst/s) +host_op_rate 200498 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1171902214 # Simulator tick rate (ticks/s) +host_mem_usage 294520 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 6413 # Number of instructions simulated sim_ops 6413 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory system.physmem.bytes_read::total 34048 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 1040000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 28986000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 2009 # Number of BP lookups system.cpu.branchPred.condPredicted 1241 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect @@ -297,6 +299,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 37494000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 74988 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -343,6 +346,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 6413 # Class of committed instruction system.cpu.tickCycles 12653 # Number of cycles that the object actually ticked system.cpu.idleCycles 62335 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 104.135823 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1980 # Total number of references to valid blocks. @@ -358,6 +362,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4583 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4583 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1240 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1240 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits @@ -452,6 +457,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77565.088757 system.cpu.dcache.demand_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77565.088757 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 175.312988 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2323 # Total number of references to valid blocks. @@ -467,6 +473,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 258 system.cpu.icache.tags.occ_task_id_percent::1024 0.177734 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 5738 # Number of tag accesses system.cpu.icache.tags.data_accesses 5738 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 2323 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2323 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2323 # number of demand (read+write) hits @@ -533,6 +540,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75280.219780 system.cpu.icache.demand_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75280.219780 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 233.336913 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. @@ -550,6 +558,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 337 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014008 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4796 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4796 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -676,6 +685,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 460 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution @@ -705,6 +715,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 546000 # La system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 253500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 459 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index ead74abf4..8d95bb8b7 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000022 # Nu sim_ticks 22019000 # Number of ticks simulated final_tick 22019000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115969 # Simulator instruction rate (inst/s) -host_op_rate 115940 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 399737091 # Simulator tick rate (ticks/s) -host_mem_usage 249288 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 117755 # Simulator instruction rate (inst/s) +host_op_rate 117735 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 405950936 # Simulator tick rate (ticks/s) +host_mem_usage 294524 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 6385 # Number of instructions simulated sim_ops 6385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory system.physmem.bytes_read::total 31040 # Number of bytes read from this memory @@ -249,6 +250,7 @@ system.physmem_1.memoryStateTime::REF 520000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 14308250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 2849 # Number of BP lookups system.cpu.branchPred.condPredicted 1676 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 481 # Number of conditional branches incorrect @@ -296,6 +298,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 22019000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 44039 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -587,6 +590,7 @@ system.cpu.fp_regfile_reads 8 # nu system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 109.409218 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2405 # Total number of references to valid blocks. @@ -602,6 +606,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 129 system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1899 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1899 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits @@ -696,6 +701,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81858.381503 system.cpu.dcache.demand_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81858.381503 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 158.432951 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1836 # Total number of references to valid blocks. @@ -711,6 +717,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 174 system.cpu.icache.tags.occ_task_id_percent::1024 0.152832 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4899 # Number of tag accesses system.cpu.icache.tags.data_accesses 4899 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1836 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1836 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1836 # number of demand (read+write) hits @@ -783,6 +790,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78180.511182 system.cpu.icache.demand_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78180.511182 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 220.994877 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. @@ -800,6 +808,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 241 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012604 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4373 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4373 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -926,6 +935,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution @@ -955,6 +965,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 469500 # La system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 413 # Transaction distribution system.membus.trans_dist::ReadExReq 72 # Transaction distribution system.membus.trans_dist::ReadExResp 72 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt index 9a58520d3..281db070e 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000003 # Nu sim_ticks 3214500 # Number of ticks simulated final_tick 3214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1011674 # Simulator instruction rate (inst/s) -host_op_rate 1009913 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 506215370 # Simulator tick rate (ticks/s) -host_mem_usage 237756 # Number of bytes of host memory used +host_inst_rate 879431 # Simulator instruction rate (inst/s) +host_op_rate 878309 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 440397606 # Simulator tick rate (ticks/s) +host_mem_usage 282472 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 3214500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 25652 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory system.physmem.bytes_read::total 34456 # Number of bytes read from this memory @@ -35,6 +36,7 @@ system.physmem.bw_write::total 2083061129 # Wr system.physmem.bw_total::cpu.inst 7980090216 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4821900762 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 12801990978 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 3214500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -69,6 +71,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 3214500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 6430 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -127,6 +130,7 @@ system.cpu.op_class::MemWrite 868 13.54% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6413 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 3214500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7598 # Transaction distribution system.membus.trans_dist::ReadResp 7598 # Transaction distribution system.membus.trans_dist::WriteReq 865 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt index e07863c49..d17f0dc2a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000122 # Nu sim_ticks 121535 # Number of ticks simulated final_tick 121535 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 71837 # Simulator instruction rate (inst/s) -host_op_rate 71828 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1363198 # Simulator tick rate (ticks/s) -host_mem_usage 407704 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 67126 # Simulator instruction rate (inst/s) +host_op_rate 67120 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1273887 # Simulator tick rate (ticks/s) +host_mem_usage 453732 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 93504 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 93504 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 17728 # Number of bytes written to this memory @@ -265,6 +266,7 @@ system.mem_ctrls_1.memoryStateTime::REF 3900 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 111353 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -299,6 +301,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 121535 # Cumulative time (in ticks) in various power states system.cpu.numCycles 121535 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -358,6 +361,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6413 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 9652 # delay histogram for all message @@ -395,6 +399,7 @@ system.ruby.miss_latency_hist_seqr::gmean 66.961050 system.ruby.miss_latency_hist_seqr::stdev 30.103565 system.ruby.miss_latency_hist_seqr | 331 22.20% 22.20% | 1141 76.53% 98.73% | 4 0.27% 98.99% | 1 0.07% 99.06% | 8 0.54% 99.60% | 6 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1491 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 1250 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 800 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses @@ -410,10 +415,14 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 1461 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 1491 # Number of cache demand accesses +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 4.310281 system.ruby.network.routers0.msg_count.Control::0 1491 system.ruby.network.routers0.msg_count.Request_Control::2 1041 @@ -431,6 +440,7 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 6400 system.ruby.network.routers0.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers0.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 2336 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 8.369194 system.ruby.network.routers1.msg_count.Control::0 2952 system.ruby.network.routers1.msg_count.Request_Control::2 1041 @@ -448,6 +458,7 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2 6400 system.ruby.network.routers1.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers1.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers1.msg_bytes.Writeback_Control::0 2336 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 4.058913 system.ruby.network.routers2.msg_count.Control::0 1461 system.ruby.network.routers2.msg_count.Response_Data::1 1738 @@ -455,6 +466,7 @@ system.ruby.network.routers2.msg_count.Response_Control::1 2629 system.ruby.network.routers2.msg_bytes.Control::0 11688 system.ruby.network.routers2.msg_bytes.Response_Data::1 125136 system.ruby.network.routers2.msg_bytes.Response_Control::1 21032 +system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states system.ruby.network.routers3.percent_links_utilized 5.579463 system.ruby.network.routers3.msg_count.Control::0 2952 system.ruby.network.routers3.msg_count.Request_Control::2 1041 @@ -472,6 +484,7 @@ system.ruby.network.routers3.msg_bytes.Response_Control::2 6400 system.ruby.network.routers3.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers3.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers3.msg_bytes.Writeback_Control::0 2336 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 8856 system.ruby.network.msg_count.Request_Control 3123 system.ruby.network.msg_count.Response_Data 9687 @@ -484,6 +497,7 @@ system.ruby.network.msg_byte.Response_Data 697464 system.ruby.network.msg_byte.Response_Control 114384 system.ruby.network.msg_byte.Writeback_Data 61776 system.ruby.network.msg_byte.Writeback_Control 7008 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.throttle0.link_utilization 6.128687 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 1041 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1491 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 86b91c7c5..99bf8d33d 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000109 # Nu sim_ticks 108878 # Number of ticks simulated final_tick 108878 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 68389 # Simulator instruction rate (inst/s) -host_op_rate 68380 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1162621 # Simulator tick rate (ticks/s) -host_mem_usage 413676 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 66441 # Simulator instruction rate (inst/s) +host_op_rate 66435 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1129573 # Simulator tick rate (ticks/s) +host_mem_usage 461124 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75712 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 75712 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 12416 # Number of bytes written to this memory @@ -265,6 +266,7 @@ system.mem_ctrls_1.memoryStateTime::REF 3380 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 96382 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -299,6 +301,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 108878 # Cumulative time (in ticks) in various power states system.cpu.numCycles 108878 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -358,6 +361,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6413 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 system.ruby.outstanding_req_hist_seqr::samples 8464 @@ -388,16 +392,21 @@ system.ruby.miss_latency_hist_seqr::gmean 57.123275 system.ruby.miss_latency_hist_seqr::stdev 33.791401 system.ruby.miss_latency_hist_seqr | 412 28.97% 28.97% | 995 69.97% 98.95% | 2 0.14% 99.09% | 0 0.00% 99.09% | 9 0.63% 99.72% | 4 0.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1422 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 1274 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 776 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states system.ruby.l2_cntrl0.L2cache.demand_hits 239 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 1183 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 1422 # Number of cache demand accesses +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 6.929545 system.ruby.network.routers0.msg_count.Request_Control::0 1422 system.ruby.network.routers0.msg_count.Response_Data::2 1183 @@ -411,6 +420,7 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 17208 system.ruby.network.routers0.msg_bytes.Writeback_Data::2 94248 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 21680 system.ruby.network.routers0.msg_bytes.Unblock_Control::2 11744 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 10.407520 system.ruby.network.routers1.msg_count.Request_Control::0 1422 system.ruby.network.routers1.msg_count.Request_Control::1 1183 @@ -428,6 +438,7 @@ system.ruby.network.routers1.msg_bytes.Writeback_Data::2 108216 system.ruby.network.routers1.msg_bytes.Writeback_Control::0 21680 system.ruby.network.routers1.msg_bytes.Writeback_Control::1 3104 system.ruby.network.routers1.msg_bytes.Unblock_Control::2 21208 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 3.477975 system.ruby.network.routers2.msg_count.Request_Control::1 1183 system.ruby.network.routers2.msg_count.Response_Data::2 1183 @@ -439,6 +450,7 @@ system.ruby.network.routers2.msg_bytes.Response_Data::2 85176 system.ruby.network.routers2.msg_bytes.Writeback_Data::2 13968 system.ruby.network.routers2.msg_bytes.Writeback_Control::1 3104 system.ruby.network.routers2.msg_bytes.Unblock_Control::2 9464 +system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states system.ruby.network.routers3.percent_links_utilized 6.938347 system.ruby.network.routers3.msg_count.Request_Control::0 1422 system.ruby.network.routers3.msg_count.Request_Control::1 1183 @@ -456,6 +468,7 @@ system.ruby.network.routers3.msg_bytes.Writeback_Data::2 108216 system.ruby.network.routers3.msg_bytes.Writeback_Control::0 21680 system.ruby.network.routers3.msg_bytes.Writeback_Control::1 3104 system.ruby.network.routers3.msg_bytes.Unblock_Control::2 21208 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Request_Control 7815 system.ruby.network.msg_count.Response_Data 7098 system.ruby.network.msg_count.ResponseL2hit_Data 717 @@ -468,6 +481,7 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 51624 system.ruby.network.msg_byte.Writeback_Data 324648 system.ruby.network.msg_byte.Writeback_Control 74352 system.ruby.network.msg_byte.Unblock_Control 63624 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.throttle0.link_utilization 6.499476 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1183 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 239 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index bdd21635f..e5f292184 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000108 # Nu sim_ticks 108253 # Number of ticks simulated final_tick 108253 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 4411 # Simulator instruction rate (inst/s) -host_op_rate 4411 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 74577 # Simulator tick rate (ticks/s) -host_mem_usage 409256 # Number of bytes of host memory used -host_seconds 1.45 # Real time elapsed on the host +host_inst_rate 94410 # Simulator instruction rate (inst/s) +host_op_rate 94397 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1595747 # Simulator tick rate (ticks/s) +host_mem_usage 455808 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75456 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 75456 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14656 # Number of bytes written to this memory @@ -264,6 +265,7 @@ system.mem_ctrls_1.memoryStateTime::REF 3380 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 95729 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -298,6 +300,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 108253 # Cumulative time (in ticks) in various power states system.cpu.numCycles 108253 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -357,6 +360,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6413 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 system.ruby.outstanding_req_hist_seqr::samples 8464 @@ -389,16 +393,21 @@ system.ruby.miss_latency_hist_seqr::stdev 28.099799 system.ruby.miss_latency_hist_seqr | 162 13.74% 13.74% | 996 84.48% 98.22% | 8 0.68% 98.90% | 4 0.34% 99.24% | 5 0.42% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1179 system.ruby.Directory.incomplete_times_seqr 1178 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 1313 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 737 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states system.ruby.l2_cntrl0.L2cache.demand_hits 187 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 1196 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 1383 # Number of cache demand accesses +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 6.022466 system.ruby.network.routers0.msg_count.Request_Control::1 1383 system.ruby.network.routers0.msg_count.Response_Data::4 1179 @@ -412,6 +421,7 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 14688 system.ruby.network.routers0.msg_bytes.Response_Control::4 8 system.ruby.network.routers0.msg_bytes.Writeback_Data::4 97560 system.ruby.network.routers0.msg_bytes.Persistent_Control::3 416 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 4.541676 system.ruby.network.routers1.msg_count.Request_Control::1 1383 system.ruby.network.routers1.msg_count.Request_Control::2 1196 @@ -427,6 +437,7 @@ system.ruby.network.routers1.msg_bytes.Response_Control::4 8 system.ruby.network.routers1.msg_bytes.Writeback_Data::4 114048 system.ruby.network.routers1.msg_bytes.Writeback_Control::4 7744 system.ruby.network.routers1.msg_bytes.Persistent_Control::3 208 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 3.432237 system.ruby.network.routers2.msg_count.Request_Control::2 1196 system.ruby.network.routers2.msg_count.Response_Data::4 1179 @@ -438,6 +449,7 @@ system.ruby.network.routers2.msg_bytes.Response_Data::4 84888 system.ruby.network.routers2.msg_bytes.Writeback_Data::4 16488 system.ruby.network.routers2.msg_bytes.Writeback_Control::4 7744 system.ruby.network.routers2.msg_bytes.Persistent_Control::3 208 +system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states system.ruby.network.routers3.percent_links_utilized 4.665460 system.ruby.network.routers3.msg_count.Request_Control::1 1383 system.ruby.network.routers3.msg_count.Request_Control::2 1196 @@ -455,6 +467,7 @@ system.ruby.network.routers3.msg_bytes.Response_Control::4 8 system.ruby.network.routers3.msg_bytes.Writeback_Data::4 114048 system.ruby.network.routers3.msg_bytes.Writeback_Control::4 7744 system.ruby.network.routers3.msg_bytes.Persistent_Control::3 416 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Request_Control 7737 system.ruby.network.msg_count.Response_Data 3537 system.ruby.network.msg_count.ResponseL2hit_Data 612 @@ -469,6 +482,7 @@ system.ruby.network.msg_byte.Response_Control 24 system.ruby.network.msg_byte.Writeback_Data 342144 system.ruby.network.msg_byte.Writeback_Control 23232 system.ruby.network.msg_byte.Persistent_Control 1248 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.throttle0.link_utilization 5.761503 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1179 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 204 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index 463ba3cfb..9d52394d3 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000087 # Nu sim_ticks 86770 # Number of ticks simulated final_tick 86770 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 99240 # Simulator instruction rate (inst/s) -host_op_rate 99218 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1344283 # Simulator tick rate (ticks/s) -host_mem_usage 407932 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 95809 # Simulator instruction rate (inst/s) +host_op_rate 95795 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1297998 # Simulator tick rate (ticks/s) +host_mem_usage 453692 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 74240 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 74240 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14080 # Number of bytes written to this memory @@ -264,6 +265,7 @@ system.mem_ctrls_1.memoryStateTime::REF 2860 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 82150 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -298,6 +300,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 86770 # Cumulative time (in ticks) in various power states system.cpu.numCycles 86770 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -357,6 +360,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6413 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 system.ruby.outstanding_req_hist_seqr::samples 8464 @@ -392,6 +396,7 @@ system.ruby.Directory.incomplete_times_seqr 1159 system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 1333 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 717 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses @@ -401,8 +406,11 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 system.ruby.l1_cntrl0.L2cache.demand_hits 203 # Number of cache demand hits system.ruby.l1_cntrl0.L2cache.demand_misses 1160 # Number of cache demand misses system.ruby.l1_cntrl0.L2cache.demand_accesses 1363 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.fully_busy_cycles 7 # cycles for which number of transistions == max transitions system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 5.172295 system.ruby.network.routers0.msg_count.Request_Control::2 1160 system.ruby.network.routers0.msg_count.Response_Data::4 1160 @@ -418,6 +426,7 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2 9152 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9152 system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7392 system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9280 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 5.172006 system.ruby.network.routers1.msg_count.Request_Control::2 1160 system.ruby.network.routers1.msg_count.Response_Data::4 1160 @@ -433,6 +442,7 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::2 9152 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9152 system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7392 system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9272 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 5.172295 system.ruby.network.routers2.msg_count.Request_Control::2 1160 system.ruby.network.routers2.msg_count.Response_Data::4 1160 @@ -448,6 +458,7 @@ system.ruby.network.routers2.msg_bytes.Writeback_Control::2 9152 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 9152 system.ruby.network.routers2.msg_bytes.Writeback_Control::5 7392 system.ruby.network.routers2.msg_bytes.Unblock_Control::5 9280 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Request_Control 3480 system.ruby.network.msg_count.Response_Data 3480 system.ruby.network.msg_count.Writeback_Data 660 @@ -458,6 +469,7 @@ system.ruby.network.msg_byte.Response_Data 250560 system.ruby.network.msg_byte.Writeback_Data 47520 system.ruby.network.msg_byte.Writeback_Control 77088 system.ruby.network.msg_byte.Unblock_Control 27832 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.throttle0.link_utilization 6.675118 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1160 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1144 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index d5526ad82..a33abfe97 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000107 # Nu sim_ticks 107065 # Number of ticks simulated final_tick 107065 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 109103 # Simulator instruction rate (inst/s) -host_op_rate 109072 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1823360 # Simulator tick rate (ticks/s) -host_mem_usage 411068 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 58028 # Simulator instruction rate (inst/s) +host_op_rate 58023 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 970128 # Simulator tick rate (ticks/s) +host_mem_usage 456600 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 110784 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 110784 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 110528 # Number of bytes written to this memory @@ -267,6 +268,7 @@ system.mem_ctrls_1.memoryStateTime::REF 3380 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 92641 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -301,6 +303,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 107065 # Cumulative time (in ticks) in various power states system.cpu.numCycles 107065 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -360,6 +363,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6413 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 3458 # delay histogram for all message @@ -396,10 +400,14 @@ system.ruby.miss_latency_hist_seqr::stdev 32.911544 system.ruby.miss_latency_hist_seqr | 1488 85.96% 85.96% | 190 10.98% 96.94% | 41 2.37% 99.31% | 1 0.06% 99.36% | 6 0.35% 99.71% | 4 0.23% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1731 system.ruby.Directory.incomplete_times_seqr 1730 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 6732 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1731 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8463 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 8.074534 system.ruby.network.routers0.msg_count.Control::2 1731 system.ruby.network.routers0.msg_count.Data::2 1727 @@ -409,6 +417,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 13848 system.ruby.network.routers0.msg_bytes.Data::2 124344 system.ruby.network.routers0.msg_bytes.Response_Data::4 124632 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13816 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 8.074534 system.ruby.network.routers1.msg_count.Control::2 1731 system.ruby.network.routers1.msg_count.Data::2 1727 @@ -418,6 +427,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 13848 system.ruby.network.routers1.msg_bytes.Data::2 124344 system.ruby.network.routers1.msg_bytes.Response_Data::4 124632 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13816 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 8.074534 system.ruby.network.routers2.msg_count.Control::2 1731 system.ruby.network.routers2.msg_count.Data::2 1727 @@ -427,6 +437,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 13848 system.ruby.network.routers2.msg_bytes.Data::2 124344 system.ruby.network.routers2.msg_bytes.Response_Data::4 124632 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13816 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 5193 system.ruby.network.msg_count.Data 5181 system.ruby.network.msg_count.Response_Data 5193 @@ -435,6 +446,7 @@ system.ruby.network.msg_byte.Control 41544 system.ruby.network.msg_byte.Data 373032 system.ruby.network.msg_byte.Response_Data 373896 system.ruby.network.msg_byte.Writeback_Control 41448 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.throttle0.link_utilization 8.082006 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1731 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1727 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index 4c1b7f48d..0b95c7449 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000036 # Nu sim_ticks 35682500 # Number of ticks simulated final_tick 35682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 581025 # Simulator instruction rate (inst/s) -host_op_rate 580437 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3231677275 # Simulator tick rate (ticks/s) -host_mem_usage 247496 # Number of bytes of host memory used +host_inst_rate 516760 # Simulator instruction rate (inst/s) +host_op_rate 516348 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2875227341 # Simulator tick rate (ticks/s) +host_mem_usage 291440 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory system.physmem.bytes_read::total 28544 # Number of bytes read from this memory @@ -29,6 +30,7 @@ system.physmem.bw_inst_read::total 498619772 # In system.physmem.bw_total::cpu.inst 498619772 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 301324179 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 799943950 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -63,6 +65,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 35682500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 71365 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -121,6 +124,7 @@ system.cpu.op_class::MemWrite 868 13.54% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6413 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 103.763836 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1882 # Total number of references to valid blocks. @@ -136,6 +140,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 143 system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4268 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4268 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits @@ -222,6 +227,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 127.232065 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6135 # Total number of references to valid blocks. @@ -237,6 +243,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 184 system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 13107 # Number of tag accesses system.cpu.icache.tags.data_accesses 13107 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 6135 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6135 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6135 # number of demand (read+write) hits @@ -303,6 +310,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60829.749104 system.cpu.icache.demand_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 184.000496 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. @@ -320,6 +328,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -446,6 +455,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution @@ -475,6 +485,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 418500 # La system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 373 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index f75116dfd..b5156559e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000020 # Nu sim_ticks 20320000 # Number of ticks simulated final_tick 20320000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 154508 # Simulator instruction rate (inst/s) -host_op_rate 154391 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1212791416 # Simulator tick rate (ticks/s) -host_mem_usage 246696 # Number of bytes of host memory used +host_inst_rate 171591 # Simulator instruction rate (inst/s) +host_op_rate 171481 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1347191282 # Simulator tick rate (ticks/s) +host_mem_usage 293200 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 20320000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory system.physmem.bytes_read::total 19840 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 520000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 14869250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 20320000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 794 # Number of BP lookups system.cpu.branchPred.condPredicted 395 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 170 # Number of conditional branches incorrect @@ -297,6 +299,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 20320000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 40640 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -343,6 +346,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 2585 # Class of committed instruction system.cpu.tickCycles 5416 # Number of cycles that the object actually ticked system.cpu.idleCycles 35224 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20320000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 48.513757 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 693 # Total number of references to valid blocks. @@ -358,6 +362,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1679 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1679 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20320000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 442 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 442 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits @@ -452,6 +457,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76000 system.cpu.dcache.demand_avg_mshr_miss_latency::total 76000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 76000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20320000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 119.123012 # Cycle average of tags in use system.cpu.icache.tags.total_refs 750 # Total number of references to valid blocks. @@ -467,6 +473,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 125 system.cpu.icache.tags.occ_task_id_percent::1024 0.109863 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 2175 # Number of tag accesses system.cpu.icache.tags.data_accesses 2175 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20320000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 750 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 750 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 750 # number of demand (read+write) hits @@ -533,6 +540,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75457.777778 system.cpu.icache.demand_avg_mshr_miss_latency::total 75457.777778 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75457.777778 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 75457.777778 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20320000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 147.162900 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. @@ -550,6 +558,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 152 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008636 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2790 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2790 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20320000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 225 # number of ReadCleanReq misses @@ -670,6 +679,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20320000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution @@ -699,6 +709,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 337500 # La system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 20320000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 283 # Transaction distribution system.membus.trans_dist::ReadExReq 27 # Transaction distribution system.membus.trans_dist::ReadExResp 27 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 92634ef37..006581ce2 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000012 # Nu sim_ticks 12409500 # Number of ticks simulated final_tick 12409500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87055 # Simulator instruction rate (inst/s) -host_op_rate 87008 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 452104980 # Simulator tick rate (ticks/s) -host_mem_usage 247976 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 52563 # Simulator instruction rate (inst/s) +host_op_rate 52553 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 273157641 # Simulator tick rate (ticks/s) +host_mem_usage 293200 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory system.physmem.bytes_read::total 17408 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 260000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 7371500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 1003 # Number of BP lookups system.cpu.branchPred.condPredicted 492 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 213 # Number of conditional branches incorrect @@ -297,6 +299,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 12409500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 24820 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -586,6 +589,7 @@ system.cpu.int_regfile_writes 2640 # nu system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 45.439304 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 735 # Total number of references to valid blocks. @@ -601,6 +605,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1919 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1919 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 522 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 522 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits @@ -695,6 +700,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78211.764706 system.cpu.dcache.demand_avg_mshr_miss_latency::total 78211.764706 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78211.764706 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 78211.764706 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 90.399218 # Cycle average of tags in use system.cpu.icache.tags.total_refs 625 # Total number of references to valid blocks. @@ -710,6 +716,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 29 system.cpu.icache.tags.occ_task_id_percent::1024 0.091309 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1943 # Number of tag accesses system.cpu.icache.tags.data_accesses 1943 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 625 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 625 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 625 # number of demand (read+write) hits @@ -782,6 +789,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75724.593583 system.cpu.icache.demand_avg_mshr_miss_latency::total 75724.593583 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75724.593583 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 75724.593583 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 119.261302 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. @@ -799,6 +807,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007568 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2448 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2448 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 187 # number of ReadCleanReq misses @@ -919,6 +928,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution @@ -948,6 +958,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 280500 # La system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 248 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution system.membus.trans_dist::ReadExResp 24 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index 8171db450..fe81a2b88 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000001 # Nu sim_ticks 1297500 # Number of ticks simulated final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 461545 # Simulator instruction rate (inst/s) -host_op_rate 460635 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 231518490 # Simulator tick rate (ticks/s) -host_mem_usage 237472 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 615280 # Simulator instruction rate (inst/s) +host_op_rate 613973 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 308554926 # Simulator tick rate (ticks/s) +host_mem_usage 281160 # Number of bytes of host memory used +host_seconds 0.00 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 1297500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory system.physmem.bytes_read::total 13356 # Number of bytes read from this memory @@ -35,6 +36,7 @@ system.physmem.bw_write::total 1586127168 # Wr system.physmem.bw_total::cpu.inst 7969171484 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3910597303 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11879768786 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 1297500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -69,6 +71,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 1297500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 2596 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -127,6 +130,7 @@ system.cpu.op_class::MemWrite 298 11.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 1297500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 3000 # Transaction distribution system.membus.trans_dist::ReadResp 3000 # Transaction distribution system.membus.trans_dist::WriteReq 294 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt index cb06e619e..5ca935512 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000046 # Nu sim_ticks 45733 # Number of ticks simulated final_tick 45733 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 63739 # Simulator instruction rate (inst/s) -host_op_rate 63721 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1130531 # Simulator tick rate (ticks/s) -host_mem_usage 407420 # Number of bytes of host memory used +host_inst_rate 61876 # Simulator instruction rate (inst/s) +host_op_rate 61863 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1097622 # Simulator tick rate (ticks/s) +host_mem_usage 452416 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 35008 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 35008 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 6592 # Number of bytes written to this memory @@ -260,6 +261,7 @@ system.mem_ctrls_1.memoryStateTime::REF 1300 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 37150 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -294,6 +296,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 45733 # Cumulative time (in ticks) in various power states system.cpu.numCycles 45733 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -353,6 +356,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 3612 # delay histogram for all message @@ -390,6 +394,7 @@ system.ruby.miss_latency_hist_seqr::gmean 64.604000 system.ruby.miss_latency_hist_seqr::stdev 30.458568 system.ruby.miss_latency_hist_seqr | 134 23.43% 23.43% | 432 75.52% 98.95% | 1 0.17% 99.13% | 0 0.00% 99.13% | 1 0.17% 99.30% | 4 0.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 572 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 437 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 272 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses @@ -405,10 +410,14 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states system.ruby.l2_cntrl0.L2cache.demand_hits 25 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 547 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 572 # Number of cache demand accesses +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 4.350250 system.ruby.network.routers0.msg_count.Control::0 572 system.ruby.network.routers0.msg_count.Request_Control::2 431 @@ -426,6 +435,7 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 2176 system.ruby.network.routers0.msg_bytes.Writeback_Data::0 3240 system.ruby.network.routers0.msg_bytes.Writeback_Data::1 4464 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 632 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 8.380163 system.ruby.network.routers1.msg_count.Control::0 1119 system.ruby.network.routers1.msg_count.Request_Control::2 431 @@ -443,6 +453,7 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2 2176 system.ruby.network.routers1.msg_bytes.Writeback_Data::0 3240 system.ruby.network.routers1.msg_bytes.Writeback_Data::1 4464 system.ruby.network.routers1.msg_bytes.Writeback_Control::0 632 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 4.029913 system.ruby.network.routers2.msg_count.Control::0 547 system.ruby.network.routers2.msg_count.Response_Data::1 650 @@ -450,6 +461,7 @@ system.ruby.network.routers2.msg_count.Response_Control::1 975 system.ruby.network.routers2.msg_bytes.Control::0 4376 system.ruby.network.routers2.msg_bytes.Response_Data::1 46800 system.ruby.network.routers2.msg_bytes.Response_Control::1 7800 +system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states system.ruby.network.routers3.percent_links_utilized 5.586775 system.ruby.network.routers3.msg_count.Control::0 1119 system.ruby.network.routers3.msg_count.Request_Control::2 431 @@ -467,6 +479,7 @@ system.ruby.network.routers3.msg_bytes.Response_Control::2 2176 system.ruby.network.routers3.msg_bytes.Writeback_Data::0 3240 system.ruby.network.routers3.msg_bytes.Writeback_Data::1 4464 system.ruby.network.routers3.msg_bytes.Writeback_Control::0 632 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 3357 system.ruby.network.msg_count.Request_Control 1293 system.ruby.network.msg_count.Response_Data 3666 @@ -479,6 +492,7 @@ system.ruby.network.msg_byte.Response_Data 263952 system.ruby.network.msg_byte.Response_Control 41760 system.ruby.network.msg_byte.Writeback_Data 23112 system.ruby.network.msg_byte.Writeback_Control 1896 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.throttle0.link_utilization 6.235104 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 431 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 572 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index f80632a35..1d68008a1 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000042 # Nu sim_ticks 41712 # Number of ticks simulated final_tick 41712 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 64355 # Simulator instruction rate (inst/s) -host_op_rate 64336 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1041083 # Simulator tick rate (ticks/s) -host_mem_usage 410320 # Number of bytes of host memory used +host_inst_rate 62826 # Simulator instruction rate (inst/s) +host_op_rate 62813 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1016484 # Simulator tick rate (ticks/s) +host_mem_usage 457644 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 29696 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 29696 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 4992 # Number of bytes written to this memory @@ -260,6 +261,7 @@ system.mem_ctrls_1.memoryStateTime::REF 1300 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 37281 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -294,6 +296,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 41712 # Cumulative time (in ticks) in various power states system.cpu.numCycles 41712 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -353,6 +356,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 system.ruby.outstanding_req_hist_seqr::samples 3295 @@ -383,16 +387,21 @@ system.ruby.miss_latency_hist_seqr::gmean 57.783054 system.ruby.miss_latency_hist_seqr::stdev 31.323348 system.ruby.miss_latency_hist_seqr | 80 14.71% 14.71% | 80 14.71% 29.41% | 359 65.99% 95.40% | 18 3.31% 98.71% | 2 0.37% 99.08% | 0 0.00% 99.08% | 1 0.18% 99.26% | 0 0.00% 99.26% | 1 0.18% 99.45% | 3 0.55% 100.00% system.ruby.miss_latency_hist_seqr::total 544 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 435 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 274 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states system.ruby.l2_cntrl0.L2cache.demand_hits 80 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 464 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 544 # Number of cache demand accesses +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 6.800201 system.ruby.network.routers0.msg_count.Request_Control::0 544 system.ruby.network.routers0.msg_count.Response_Data::2 464 @@ -406,6 +415,7 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 5760 system.ruby.network.routers0.msg_bytes.Writeback_Data::2 34704 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 8032 system.ruby.network.routers0.msg_bytes.Unblock_Control::2 4512 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 10.372914 system.ruby.network.routers1.msg_count.Request_Control::0 544 system.ruby.network.routers1.msg_count.Request_Control::1 464 @@ -423,6 +433,7 @@ system.ruby.network.routers1.msg_bytes.Writeback_Data::2 40320 system.ruby.network.routers1.msg_bytes.Writeback_Control::0 8032 system.ruby.network.routers1.msg_bytes.Writeback_Control::1 1248 system.ruby.network.routers1.msg_bytes.Unblock_Control::2 8216 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 3.572713 system.ruby.network.routers2.msg_count.Request_Control::1 464 system.ruby.network.routers2.msg_count.Response_Data::2 464 @@ -434,6 +445,7 @@ system.ruby.network.routers2.msg_bytes.Response_Data::2 33408 system.ruby.network.routers2.msg_bytes.Writeback_Data::2 5616 system.ruby.network.routers2.msg_bytes.Writeback_Control::1 1248 system.ruby.network.routers2.msg_bytes.Unblock_Control::2 3704 +system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states system.ruby.network.routers3.percent_links_utilized 6.915276 system.ruby.network.routers3.msg_count.Request_Control::0 544 system.ruby.network.routers3.msg_count.Request_Control::1 464 @@ -451,6 +463,7 @@ system.ruby.network.routers3.msg_bytes.Writeback_Data::2 40320 system.ruby.network.routers3.msg_bytes.Writeback_Control::0 8032 system.ruby.network.routers3.msg_bytes.Writeback_Control::1 1248 system.ruby.network.routers3.msg_bytes.Unblock_Control::2 8216 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Request_Control 3024 system.ruby.network.msg_count.Response_Data 2784 system.ruby.network.msg_count.ResponseL2hit_Data 240 @@ -463,6 +476,7 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 17280 system.ruby.network.msg_byte.Writeback_Data 120960 system.ruby.network.msg_byte.Writeback_Control 27840 system.ruby.network.msg_byte.Unblock_Control 24648 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.throttle0.link_utilization 6.470560 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 464 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 80 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index 03e04136e..20325d4b9 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000041 # Nu sim_ticks 40527 # Number of ticks simulated final_tick 40527 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 1955 # Simulator instruction rate (inst/s) -host_op_rate 1955 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30751 # Simulator tick rate (ticks/s) -host_mem_usage 407948 # Number of bytes of host memory used -host_seconds 1.32 # Real time elapsed on the host +host_inst_rate 89328 # Simulator instruction rate (inst/s) +host_op_rate 89293 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1403832 # Simulator tick rate (ticks/s) +host_mem_usage 454496 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 28672 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 28672 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 5376 # Number of bytes written to this memory @@ -260,6 +261,7 @@ system.mem_ctrls_1.memoryStateTime::REF 1300 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 37083 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -294,6 +296,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 40527 # Cumulative time (in ticks) in various power states system.cpu.numCycles 40527 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -353,6 +356,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 system.ruby.outstanding_req_hist_seqr::samples 3295 @@ -385,16 +389,21 @@ system.ruby.miss_latency_hist_seqr::stdev 29.782878 system.ruby.miss_latency_hist_seqr | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 0 0.00% 98.88% | 3 0.67% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 448 system.ruby.Directory.incomplete_times_seqr 447 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 461 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 248 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states system.ruby.l2_cntrl0.L2cache.demand_hits 64 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 454 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 518 # Number of cache demand accesses +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 5.992918 system.ruby.network.routers0.msg_count.Request_Control::1 518 system.ruby.network.routers0.msg_count.Response_Data::4 448 @@ -408,6 +417,7 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 5040 system.ruby.network.routers0.msg_bytes.Response_Control::4 8 system.ruby.network.routers0.msg_bytes.Writeback_Data::4 36144 system.ruby.network.routers0.msg_bytes.Persistent_Control::3 128 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 4.472327 system.ruby.network.routers1.msg_count.Request_Control::1 518 system.ruby.network.routers1.msg_count.Request_Control::2 454 @@ -423,6 +433,7 @@ system.ruby.network.routers1.msg_bytes.Response_Control::4 8 system.ruby.network.routers1.msg_bytes.Writeback_Data::4 42192 system.ruby.network.routers1.msg_bytes.Writeback_Control::4 2920 system.ruby.network.routers1.msg_bytes.Persistent_Control::3 64 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 3.463740 system.ruby.network.routers2.msg_count.Request_Control::2 454 system.ruby.network.routers2.msg_count.Response_Data::4 448 @@ -434,6 +445,7 @@ system.ruby.network.routers2.msg_bytes.Response_Data::4 32256 system.ruby.network.routers2.msg_bytes.Writeback_Data::4 6048 system.ruby.network.routers2.msg_bytes.Writeback_Control::4 2920 system.ruby.network.routers2.msg_bytes.Persistent_Control::3 64 +system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states system.ruby.network.routers3.percent_links_utilized 4.642995 system.ruby.network.routers3.msg_count.Request_Control::1 518 system.ruby.network.routers3.msg_count.Request_Control::2 454 @@ -451,6 +463,7 @@ system.ruby.network.routers3.msg_bytes.Response_Control::4 8 system.ruby.network.routers3.msg_bytes.Writeback_Data::4 42192 system.ruby.network.routers3.msg_bytes.Writeback_Control::4 2920 system.ruby.network.routers3.msg_bytes.Persistent_Control::3 128 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Request_Control 2916 system.ruby.network.msg_count.Response_Data 1344 system.ruby.network.msg_count.ResponseL2hit_Data 210 @@ -465,6 +478,7 @@ system.ruby.network.msg_byte.Response_Control 24 system.ruby.network.msg_byte.Writeback_Data 126576 system.ruby.network.msg_byte.Writeback_Control 8760 system.ruby.network.msg_byte.Persistent_Control 384 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.throttle0.link_utilization 5.762825 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 448 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 70 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index 2707b659f..71e93d920 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000033 # Nu sim_ticks 32936 # Number of ticks simulated final_tick 32936 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 83066 # Simulator instruction rate (inst/s) -host_op_rate 82987 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1059779 # Simulator tick rate (ticks/s) -host_mem_usage 407644 # Number of bytes of host memory used +host_inst_rate 91605 # Simulator instruction rate (inst/s) +host_op_rate 91573 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1170024 # Simulator tick rate (ticks/s) +host_mem_usage 453424 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 28224 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 28224 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 5184 # Number of bytes written to this memory @@ -260,6 +261,7 @@ system.mem_ctrls_1.memoryStateTime::REF 1040 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 29634 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -294,6 +296,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 32936 # Cumulative time (in ticks) in various power states system.cpu.numCycles 32936 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -353,6 +356,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 system.ruby.outstanding_req_hist_seqr::samples 3295 @@ -388,6 +392,7 @@ system.ruby.Directory.incomplete_times_seqr 440 system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 469 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 240 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses @@ -397,8 +402,11 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 system.ruby.l1_cntrl0.L2cache.demand_hits 69 # Number of cache demand hits system.ruby.l1_cntrl0.L2cache.demand_misses 441 # Number of cache demand misses system.ruby.l1_cntrl0.L2cache.demand_accesses 510 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.fully_busy_cycles 5 # cycles for which number of transistions == max transitions system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 5.141031 system.ruby.network.routers0.msg_count.Request_Control::2 441 system.ruby.network.routers0.msg_count.Response_Data::4 441 @@ -414,6 +422,7 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2 3400 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 3400 system.ruby.network.routers0.msg_bytes.Writeback_Control::5 2752 system.ruby.network.routers0.msg_bytes.Unblock_Control::5 3520 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 5.141031 system.ruby.network.routers1.msg_count.Request_Control::2 441 system.ruby.network.routers1.msg_count.Response_Data::4 441 @@ -429,6 +438,7 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::2 3400 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 3400 system.ruby.network.routers1.msg_bytes.Writeback_Control::5 2752 system.ruby.network.routers1.msg_bytes.Unblock_Control::5 3520 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 5.141031 system.ruby.network.routers2.msg_count.Request_Control::2 441 system.ruby.network.routers2.msg_count.Response_Data::4 441 @@ -444,6 +454,7 @@ system.ruby.network.routers2.msg_bytes.Writeback_Control::2 3400 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 3400 system.ruby.network.routers2.msg_bytes.Writeback_Control::5 2752 system.ruby.network.routers2.msg_bytes.Unblock_Control::5 3520 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Request_Control 1323 system.ruby.network.msg_count.Response_Data 1323 system.ruby.network.msg_count.Writeback_Data 243 @@ -454,6 +465,7 @@ system.ruby.network.msg_byte.Response_Data 95256 system.ruby.network.msg_byte.Writeback_Data 17496 system.ruby.network.msg_byte.Writeback_Control 28656 system.ruby.network.msg_byte.Unblock_Control 10560 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.throttle0.link_utilization 6.670513 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 441 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 425 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index 15c5cf0e9..f97a14626 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000042 # Nu sim_ticks 41659 # Number of ticks simulated final_tick 41659 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 92225 # Simulator instruction rate (inst/s) -host_op_rate 92177 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1489374 # Simulator tick rate (ticks/s) -host_mem_usage 407716 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 54027 # Simulator instruction rate (inst/s) +host_op_rate 54016 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 873053 # Simulator tick rate (ticks/s) +host_mem_usage 453224 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 40064 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 40064 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 39808 # Number of bytes written to this memory @@ -266,6 +267,7 @@ system.mem_ctrls_1.memoryStateTime::REF 1300 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 37357 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -300,6 +302,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 41659 # Cumulative time (in ticks) in various power states system.cpu.numCycles 41659 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -359,6 +362,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 1248 # delay histogram for all message @@ -395,10 +399,14 @@ system.ruby.miss_latency_hist_seqr::stdev 32.986607 system.ruby.miss_latency_hist_seqr | 517 82.59% 82.59% | 90 14.38% 96.96% | 14 2.24% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 626 system.ruby.Directory.incomplete_times_seqr 625 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 7.489378 system.ruby.network.routers0.msg_count.Control::2 626 system.ruby.network.routers0.msg_count.Data::2 622 @@ -408,6 +416,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 5008 system.ruby.network.routers0.msg_bytes.Data::2 44784 system.ruby.network.routers0.msg_bytes.Response_Data::4 45072 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 4976 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 7.489378 system.ruby.network.routers1.msg_count.Control::2 626 system.ruby.network.routers1.msg_count.Data::2 622 @@ -417,6 +426,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 5008 system.ruby.network.routers1.msg_bytes.Data::2 44784 system.ruby.network.routers1.msg_bytes.Response_Data::4 45072 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 4976 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 7.489378 system.ruby.network.routers2.msg_count.Control::2 626 system.ruby.network.routers2.msg_count.Data::2 622 @@ -426,6 +436,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 5008 system.ruby.network.routers2.msg_bytes.Data::2 44784 system.ruby.network.routers2.msg_bytes.Response_Data::4 45072 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 4976 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 1878 system.ruby.network.msg_count.Data 1866 system.ruby.network.msg_count.Response_Data 1878 @@ -434,6 +445,7 @@ system.ruby.network.msg_byte.Control 15024 system.ruby.network.msg_byte.Data 134352 system.ruby.network.msg_byte.Response_Data 135216 system.ruby.network.msg_byte.Writeback_Control 14928 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.throttle0.link_utilization 7.508582 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 626 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 622 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 9736e3d18..a94783b9b 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000018 # Nu sim_ticks 18239500 # Number of ticks simulated final_tick 18239500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 339288 # Simulator instruction rate (inst/s) -host_op_rate 338780 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2394585777 # Simulator tick rate (ticks/s) -host_mem_usage 246188 # Number of bytes of host memory used +host_inst_rate 346390 # Simulator instruction rate (inst/s) +host_op_rate 345952 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2445638693 # Simulator tick rate (ticks/s) +host_mem_usage 291156 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5248 # Number of bytes read from this memory system.physmem.bytes_read::total 15680 # Number of bytes read from this memory @@ -29,6 +30,7 @@ system.physmem.bw_inst_read::total 571945503 # In system.physmem.bw_total::cpu.inst 571945503 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 287727186 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 859672688 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -63,6 +65,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 18239500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 36479 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -121,6 +124,7 @@ system.cpu.op_class::MemWrite 298 11.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 47.277997 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. @@ -136,6 +140,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 49 system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits @@ -222,6 +227,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 79.677134 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks. @@ -237,6 +243,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 69 system.cpu.icache.tags.occ_task_id_percent::1024 0.079590 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 5335 # Number of tag accesses system.cpu.icache.tags.data_accesses 5335 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits @@ -303,6 +310,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61003.067485 system.cpu.icache.demand_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61003.067485 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 106.649585 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. @@ -320,6 +328,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 94 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.006653 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2205 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2205 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 163 # number of ReadCleanReq misses @@ -440,6 +449,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution @@ -469,6 +479,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 244500 # La system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 218 # Transaction distribution system.membus.trans_dist::ReadExReq 27 # Transaction distribution system.membus.trans_dist::ReadExResp 27 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 605a65a27..acde8b0d6 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000030 # Nu sim_ticks 29977500 # Number of ticks simulated final_tick 29977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 146522 # Simulator instruction rate (inst/s) -host_op_rate 171470 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 953185288 # Simulator tick rate (ticks/s) -host_mem_usage 264656 # Number of bytes of host memory used +host_inst_rate 147440 # Simulator instruction rate (inst/s) +host_op_rate 172555 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 959274014 # Simulator tick rate (ticks/s) +host_mem_usage 309288 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory system.physmem.bytes_read::total 26944 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 780000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 22324250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 1949 # Number of BP lookups system.cpu.branchPred.condPredicted 1165 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect @@ -264,6 +266,7 @@ system.cpu.branchPred.indirectHits 8 # Nu system.cpu.branchPred.indirectMisses 125 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -293,6 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -322,6 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -351,6 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -381,6 +387,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 29977500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 59955 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -427,6 +434,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 5391 # Class of committed instruction system.cpu.tickCycles 10654 # Number of cycles that the object actually ticked system.cpu.idleCycles 49301 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 86.495507 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1916 # Total number of references to valid blocks. @@ -442,6 +450,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4342 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4342 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits @@ -544,6 +553,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65510.273973 system.cpu.dcache.demand_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 4 # number of replacements system.cpu.icache.tags.tagsinuse 162.122030 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1926 # Total number of references to valid blocks. @@ -559,6 +569,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 213 system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4821 # Number of tag accesses system.cpu.icache.tags.data_accesses 4821 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1926 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1926 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1926 # number of demand (read+write) hits @@ -627,6 +638,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71848.297214 system.cpu.icache.demand_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 195.781809 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 43 # Total number of references to valid blocks. @@ -644,6 +656,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4197 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4197 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits @@ -784,6 +797,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 426 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -814,6 +828,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 484500 # La system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 378 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 9149a2fa0..e232e499c 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000017 # Nu sim_ticks 17232500 # Number of ticks simulated final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74741 # Simulator instruction rate (inst/s) -host_op_rate 87520 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 280399381 # Simulator tick rate (ticks/s) -host_mem_usage 309668 # Number of bytes of host memory used +host_inst_rate 78702 # Simulator instruction rate (inst/s) +host_op_rate 92158 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 295258113 # Simulator tick rate (ticks/s) +host_mem_usage 310332 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory system.physmem.bytes_read::total 25408 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 520000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 2837 # Number of BP lookups system.cpu.branchPred.condPredicted 1744 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect @@ -264,6 +266,7 @@ system.cpu.branchPred.indirectHits 14 # Nu system.cpu.branchPred.indirectMisses 251 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -293,6 +296,7 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -322,6 +326,7 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 0 # DTB hits system.cpu.checker.dtb.misses 0 # DTB misses system.cpu.checker.dtb.accesses 0 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -351,6 +356,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.checker.itb.walker.walks 0 # Table walker walks requested system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -381,9 +387,11 @@ system.cpu.checker.itb.hits 0 # DT system.cpu.checker.itb.misses 0 # DTB misses system.cpu.checker.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls +system.cpu.checker.pwrStateResidencyTicks::ON 17232500 # Cumulative time (in ticks) in various power states system.cpu.checker.numCycles 5391 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -413,6 +421,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -442,6 +451,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -471,6 +481,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -500,6 +511,7 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses +system.cpu.pwrStateResidencyTicks::ON 17232500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 34466 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -793,6 +805,7 @@ system.cpu.cc_regfile_reads 27801 # nu system.cpu.cc_regfile_writes 3276 # number of cc regfile writes system.cpu.misc_regfile_reads 2978 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 88.359063 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2095 # Total number of references to valid blocks. @@ -808,6 +821,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 5339 # Number of tag accesses system.cpu.dcache.tags.data_accesses 5339 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits @@ -920,6 +934,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70870.748299 system.cpu.dcache.demand_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2 # number of replacements system.cpu.icache.tags.tagsinuse 150.405898 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. @@ -935,6 +950,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 123 system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4216 # Number of tag accesses system.cpu.icache.tags.data_accesses 4216 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits @@ -1009,6 +1025,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73923.469388 system.cpu.icache.demand_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 187.999052 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. @@ -1026,6 +1043,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3933 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3933 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits @@ -1166,6 +1184,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution @@ -1196,6 +1215,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 441000 # La system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 355 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution system.membus.trans_dist::ReadExResp 42 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index d093f5feb..e81d385ba 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000019 # Nu sim_ticks 18821000 # Number of ticks simulated final_tick 18821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77535 # Simulator instruction rate (inst/s) -host_op_rate 90790 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 317684946 # Simulator tick rate (ticks/s) -host_mem_usage 305172 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 84019 # Simulator instruction rate (inst/s) +host_op_rate 98384 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 344256847 # Simulator tick rate (ticks/s) +host_mem_usage 306884 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8064 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory @@ -254,6 +255,7 @@ system.physmem_1.memoryStateTime::REF 520000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 15229250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 2438 # Number of BP lookups system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 524 # Number of conditional branches incorrect @@ -268,6 +270,7 @@ system.cpu.branchPred.indirectHits 13 # Nu system.cpu.branchPred.indirectMisses 150 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -297,6 +300,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,6 +330,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -355,6 +360,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -385,6 +391,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 18821000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 37643 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -674,6 +681,7 @@ system.cpu.cc_regfile_reads 24229 # nu system.cpu.cc_regfile_writes 2921 # number of cc regfile writes system.cpu.misc_regfile_reads 2562 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1 # number of replacements system.cpu.dcache.tags.tagsinuse 84.368926 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1930 # Total number of references to valid blocks. @@ -689,6 +697,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4723 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4723 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1188 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1188 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits @@ -803,6 +812,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65048.611111 system.cpu.dcache.demand_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 44 # number of replacements system.cpu.icache.tags.tagsinuse 137.890102 # Cycle average of tags in use system.cpu.icache.tags.total_refs 3540 # Total number of references to valid blocks. @@ -818,6 +828,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 98 system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 8101 # Number of tag accesses system.cpu.icache.tags.data_accesses 8101 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 3540 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 3540 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 3540 # number of demand (read+write) hits @@ -892,12 +903,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66140.441472 system.cpu.icache.demand_avg_mshr_miss_latency::total 66140.441472 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66140.441472 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 66140.441472 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 19.806308 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 11 # Total number of references to valid blocks. @@ -919,6 +932,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.001953 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 7675 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 7675 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits @@ -1077,6 +1091,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 system.cpu.toL2Bus.snoop_filter.tot_snoops 411 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 370 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 41 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 45 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 385 # Transaction distribution @@ -1109,6 +1124,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 448999 # La system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 216995 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 412 # Transaction distribution system.membus.trans_dist::ReadExReq 30 # Transaction distribution system.membus.trans_dist::ReadExResp 30 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 12cffc971..c4cb1f552 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000003 # Nu sim_ticks 2695000 # Number of ticks simulated final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 555825 # Simulator instruction rate (inst/s) -host_op_rate 650110 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 325439975 # Simulator tick rate (ticks/s) -host_mem_usage 298640 # Number of bytes of host memory used +host_inst_rate 569364 # Simulator instruction rate (inst/s) +host_op_rate 666035 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 333433301 # Simulator tick rate (ticks/s) +host_mem_usage 299296 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 18420 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory system.physmem.bytes_read::total 22911 # Number of bytes read from this memory @@ -35,7 +36,9 @@ system.physmem.bw_write::total 1353617811 # Wr system.physmem.bw_total::cpu.inst 6834879406 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3020037106 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9854916512 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -65,6 +68,7 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -94,6 +98,7 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 0 # DTB hits system.cpu.checker.dtb.misses 0 # DTB misses system.cpu.checker.dtb.accesses 0 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -123,6 +128,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.cpu.checker.itb.walker.walks 0 # Table walker walks requested system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,9 +159,11 @@ system.cpu.checker.itb.hits 0 # DT system.cpu.checker.itb.misses 0 # DTB misses system.cpu.checker.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls +system.cpu.checker.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states system.cpu.checker.numCycles 0 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -185,6 +193,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -214,6 +223,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -243,6 +253,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -272,6 +283,7 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses +system.cpu.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 5391 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -332,6 +344,7 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 5597 # Transaction distribution system.membus.trans_dist::ReadResp 5608 # Transaction distribution system.membus.trans_dist::WriteReq 913 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index 80bb8332d..a84dba320 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000003 # Nu sim_ticks 2695000 # Number of ticks simulated final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 589705 # Simulator instruction rate (inst/s) -host_op_rate 689852 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 345334530 # Simulator tick rate (ticks/s) -host_mem_usage 297616 # Number of bytes of host memory used +host_inst_rate 625339 # Simulator instruction rate (inst/s) +host_op_rate 731490 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 366164896 # Simulator tick rate (ticks/s) +host_mem_usage 298280 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 18420 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory system.physmem.bytes_read::total 22911 # Number of bytes read from this memory @@ -35,7 +36,9 @@ system.physmem.bw_write::total 1353617811 # Wr system.physmem.bw_total::cpu.inst 6834879406 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3020037106 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9854916512 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -65,6 +68,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -94,6 +98,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -123,6 +128,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,6 +159,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 5391 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -213,6 +220,7 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 5597 # Transaction distribution system.membus.trans_dist::ReadResp 5608 # Transaction distribution system.membus.trans_dist::WriteReq 913 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 78aca14dc..92414aab2 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000028 # Nu sim_ticks 28298500 # Number of ticks simulated final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 311400 # Simulator instruction rate (inst/s) -host_op_rate 363255 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1927478424 # Simulator tick rate (ticks/s) -host_mem_usage 306584 # Number of bytes of host memory used +host_inst_rate 377704 # Simulator instruction rate (inst/s) +host_op_rate 440559 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2337429945 # Simulator tick rate (ticks/s) +host_mem_usage 308268 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4566 # Number of instructions simulated sim_ops 5330 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory system.physmem.bytes_read::total 22400 # Number of bytes read from this memory @@ -29,7 +30,9 @@ system.physmem.bw_inst_read::total 508860894 # In system.physmem.bw_total::cpu.inst 508860894 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 282700496 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 791561390 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -59,6 +62,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -88,6 +92,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -117,6 +122,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -147,6 +153,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 28298500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 56597 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -207,6 +214,7 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 82.647245 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. @@ -222,6 +230,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits @@ -316,6 +325,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489 system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. @@ -331,6 +341,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 144 system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses system.cpu.icache.tags.data_accesses 9453 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits @@ -399,6 +410,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585 system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. @@ -416,6 +428,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 191 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits @@ -546,6 +559,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -576,6 +590,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 361500 # La system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 307 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 0194e3c6f..1d63b6535 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000023 # Nu sim_ticks 22532000 # Number of ticks simulated final_tick 22532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 96442 # Simulator instruction rate (inst/s) -host_op_rate 96403 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 434426491 # Simulator tick rate (ticks/s) -host_mem_usage 247240 # Number of bytes of host memory used +host_inst_rate 107418 # Simulator instruction rate (inst/s) +host_op_rate 107396 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 483974405 # Simulator tick rate (ticks/s) +host_mem_usage 292720 # Number of bytes of host memory used host_seconds 0.05 # Real time elapsed on the host sim_insts 4999 # Number of instructions simulated sim_ops 4999 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 21056 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory system.physmem.bytes_read::total 30016 # Number of bytes read from this memory @@ -249,6 +250,7 @@ system.physmem_1.memoryStateTime::REF 520000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 15222750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 2183 # Number of BP lookups system.cpu.branchPred.condPredicted 1455 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 425 # Number of conditional branches incorrect @@ -282,6 +284,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 22532000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 45065 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -571,6 +574,7 @@ system.cpu.int_regfile_writes 5151 # nu system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 160 # number of misc regfile reads +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 90.625823 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2393 # Total number of references to valid blocks. @@ -586,6 +590,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 105 system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 5950 # Number of tag accesses system.cpu.dcache.tags.data_accesses 5950 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1837 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1837 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits @@ -680,6 +685,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83092.850000 system.cpu.dcache.demand_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 17 # number of replacements system.cpu.icache.tags.tagsinuse 158.780297 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1610 # Total number of references to valid blocks. @@ -695,6 +701,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 172 system.cpu.icache.tags.occ_task_id_percent::1024 0.153809 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4426 # Number of tag accesses system.cpu.icache.tags.data_accesses 4426 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1610 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1610 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1610 # number of demand (read+write) hits @@ -769,6 +776,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78480.421687 system.cpu.icache.demand_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 218.003826 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. @@ -786,6 +794,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 238 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012787 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 17 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 17 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits @@ -916,6 +925,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -946,6 +956,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 498000 # La system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 419 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt index df8a010ee..873eb6862 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000003 # Nu sim_ticks 2820500 # Number of ticks simulated final_tick 2820500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 876414 # Simulator instruction rate (inst/s) -host_op_rate 873362 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 435104956 # Simulator tick rate (ticks/s) -host_mem_usage 235716 # Number of bytes of host memory used +host_inst_rate 743339 # Simulator instruction rate (inst/s) +host_op_rate 742439 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 370817863 # Simulator tick rate (ticks/s) +host_mem_usage 279644 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2820500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 22568 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 4301 # Number of bytes read from this memory system.physmem.bytes_read::total 26869 # Number of bytes read from this memory @@ -35,6 +36,7 @@ system.physmem.bw_write::total 1276723985 # Wr system.physmem.bw_total::cpu.inst 8001418188 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2801630917 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10803049105 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 2820500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -55,6 +57,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 2820500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 5642 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -113,6 +116,7 @@ system.cpu.op_class::MemWrite 902 15.99% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 2820500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6777 # Transaction distribution system.membus.trans_dist::ReadResp 6777 # Transaction distribution system.membus.trans_dist::WriteReq 901 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 194e91ae7..5b0097850 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000100 # Nu sim_ticks 100232 # Number of ticks simulated final_tick 100232 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 97717 # Simulator instruction rate (inst/s) -host_op_rate 97699 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1735645 # Simulator tick rate (ticks/s) -host_mem_usage 410048 # Number of bytes of host memory used +host_inst_rate 93908 # Simulator instruction rate (inst/s) +host_op_rate 93894 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1668107 # Simulator tick rate (ticks/s) +host_mem_usage 455812 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 94208 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 94208 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 93952 # Number of bytes written to this memory @@ -267,6 +268,7 @@ system.mem_ctrls_1.memoryStateTime::REF 3120 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 90404 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -287,6 +289,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 100232 # Cumulative time (in ticks) in various power states system.cpu.numCycles 100232 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -346,6 +349,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 2940 # delay histogram for all message @@ -382,10 +386,14 @@ system.ruby.miss_latency_hist_seqr::stdev 35.865583 system.ruby.miss_latency_hist_seqr | 1166 79.21% 79.21% | 253 17.19% 96.40% | 37 2.51% 98.91% | 4 0.27% 99.18% | 6 0.41% 99.59% | 5 0.34% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1472 system.ruby.Directory.incomplete_times_seqr 1471 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 6206 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1472 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7678 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 7.332987 system.ruby.network.routers0.msg_count.Control::2 1472 system.ruby.network.routers0.msg_count.Data::2 1468 @@ -395,6 +403,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 11776 system.ruby.network.routers0.msg_bytes.Data::2 105696 system.ruby.network.routers0.msg_bytes.Response_Data::4 105984 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11744 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 7.332987 system.ruby.network.routers1.msg_count.Control::2 1472 system.ruby.network.routers1.msg_count.Data::2 1468 @@ -404,6 +413,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 11776 system.ruby.network.routers1.msg_bytes.Data::2 105696 system.ruby.network.routers1.msg_bytes.Response_Data::4 105984 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11744 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 7.332987 system.ruby.network.routers2.msg_count.Control::2 1472 system.ruby.network.routers2.msg_count.Data::2 1468 @@ -413,6 +423,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 11776 system.ruby.network.routers2.msg_bytes.Data::2 105696 system.ruby.network.routers2.msg_bytes.Response_Data::4 105984 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11744 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 4416 system.ruby.network.msg_count.Data 4404 system.ruby.network.msg_count.Response_Data 4416 @@ -421,6 +432,7 @@ system.ruby.network.msg_byte.Control 35328 system.ruby.network.msg_byte.Data 317088 system.ruby.network.msg_byte.Response_Data 317952 system.ruby.network.msg_byte.Writeback_Control 35232 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.throttle0.link_utilization 7.340969 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1472 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1468 diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 0e87b1f2c..5a06a8f5e 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000034 # Nu sim_ticks 33932500 # Number of ticks simulated final_tick 33932500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 431758 # Simulator instruction rate (inst/s) -host_op_rate 430982 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2588300068 # Simulator tick rate (ticks/s) -host_mem_usage 244424 # Number of bytes of host memory used +host_inst_rate 497160 # Simulator instruction rate (inst/s) +host_op_rate 496749 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2985875640 # Simulator tick rate (ticks/s) +host_mem_usage 289632 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory system.physmem.bytes_read::total 27520 # Number of bytes read from this memory @@ -29,6 +30,7 @@ system.physmem.bw_inst_read::total 552626538 # In system.physmem.bw_total::cpu.inst 552626538 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 258395344 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 811021882 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -49,6 +51,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 33932500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 67865 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -107,6 +110,7 @@ system.cpu.op_class::MemWrite 902 15.99% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 86.030444 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks. @@ -122,6 +126,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 115 system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits @@ -208,6 +213,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 13 # number of replacements system.cpu.icache.tags.tagsinuse 128.953338 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5348 # Total number of references to valid blocks. @@ -223,6 +229,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 177 system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 11581 # Number of tag accesses system.cpu.icache.tags.data_accesses 11581 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 5348 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5348 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5348 # number of demand (read+write) hits @@ -291,6 +298,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525 system.cpu.icache.demand_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 183.490494 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. @@ -308,6 +316,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 255 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011597 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3990 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3990 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 13 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 13 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits @@ -438,6 +447,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 13 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -468,6 +478,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 442500 # La system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 380 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 9c7cb3cdb..c26ae805a 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000020 # Nu sim_ticks 19908000 # Number of ticks simulated final_tick 19908000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120043 # Simulator instruction rate (inst/s) -host_op_rate 120013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 412413617 # Simulator tick rate (ticks/s) -host_mem_usage 245176 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 67828 # Simulator instruction rate (inst/s) +host_op_rate 67820 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 233087583 # Simulator tick rate (ticks/s) +host_mem_usage 290888 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 6400 # Number of bytes read from this memory system.physmem.bytes_read::total 28352 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 520000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 10721750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 2407 # Number of BP lookups system.cpu.branchPred.condPredicted 1979 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 409 # Number of conditional branches incorrect @@ -283,6 +285,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 19908000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 39817 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -572,6 +575,7 @@ system.cpu.int_regfile_reads 13370 # nu system.cpu.int_regfile_writes 7150 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 64.466372 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2199 # Total number of references to valid blocks. @@ -587,6 +591,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 72 system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 5374 # Number of tag accesses system.cpu.dcache.tags.data_accesses 5374 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits @@ -681,6 +686,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81139.403846 system.cpu.dcache.demand_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 169.073673 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1420 # Total number of references to valid blocks. @@ -696,6 +702,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 163 system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4061 # Number of tag accesses system.cpu.icache.tags.data_accesses 4061 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1420 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1420 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1420 # number of demand (read+write) hits @@ -768,6 +775,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75925.714286 system.cpu.icache.demand_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 199.665471 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks. @@ -785,6 +793,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012085 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4075 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4075 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 6 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 6 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits @@ -915,6 +924,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution @@ -944,6 +954,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 523500 # La system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 396 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution system.membus.trans_dist::ReadExResp 47 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt index 5dd437e9a..7771c9798 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000003 # Nu sim_ticks 2896000 # Number of ticks simulated final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 887311 # Simulator instruction rate (inst/s) -host_op_rate 885785 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 442112700 # Simulator tick rate (ticks/s) -host_mem_usage 234416 # Number of bytes of host memory used +host_inst_rate 806520 # Simulator instruction rate (inst/s) +host_op_rate 805428 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 402167874 # Simulator tick rate (ticks/s) +host_mem_usage 277804 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5793 # Number of instructions simulated sim_ops 5793 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2896000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 23172 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 3720 # Number of bytes read from this memory system.physmem.bytes_read::total 26892 # Number of bytes read from this memory @@ -35,6 +36,7 @@ system.physmem.bw_write::total 1453383978 # Wr system.physmem.bw_total::cpu.inst 8001381215 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2737914365 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10739295580 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 2896000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -55,6 +57,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 2896000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 5793 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -113,6 +116,7 @@ system.cpu.op_class::MemWrite 1046 18.06% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5793 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 2896000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6754 # Transaction distribution system.membus.trans_dist::ReadResp 6754 # Transaction distribution system.membus.trans_dist::WriteReq 1046 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index 0889a55c9..5963e613d 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 633206 # Simulator instruction rate (inst/s) -host_op_rate 631372 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 318532177 # Simulator tick rate (ticks/s) -host_mem_usage 236156 # Number of bytes of host memory used +host_inst_rate 770174 # Simulator instruction rate (inst/s) +host_op_rate 769174 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 388618840 # Simulator tick rate (ticks/s) +host_mem_usage 281084 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2694500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 21480 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 4602 # Number of bytes read from this memory system.physmem.bytes_read::total 26082 # Number of bytes read from this memory @@ -35,8 +36,10 @@ system.physmem.bw_write::total 1879755057 # Wr system.physmem.bw_total::cpu.inst 7971794396 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3587678605 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11559473001 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 2694500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 2694500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 5390 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -95,6 +98,7 @@ system.cpu.op_class::MemWrite 678 12.63% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5370 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 2694500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6085 # Transaction distribution system.membus.trans_dist::ReadResp 6085 # Transaction distribution system.membus.trans_dist::WriteReq 673 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 3a583092f..3b20a8d52 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000082 # Nu sim_ticks 81703 # Number of ticks simulated final_tick 81703 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 79389 # Simulator instruction rate (inst/s) -host_op_rate 79372 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1217125 # Simulator tick rate (ticks/s) -host_mem_usage 409468 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 107011 # Simulator instruction rate (inst/s) +host_op_rate 106993 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1640735 # Simulator tick rate (ticks/s) +host_mem_usage 456212 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 82496 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 82496 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 82240 # Number of bytes written to this memory @@ -268,8 +269,10 @@ system.mem_ctrls_1.memoryStateTime::REF 2600 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 64875 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 81703 # Cumulative time (in ticks) in various power states system.cpu.numCycles 81703 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -329,6 +332,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5370 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 2574 # delay histogram for all message @@ -365,10 +369,14 @@ system.ruby.miss_latency_hist_seqr::stdev 32.275754 system.ruby.miss_latency_hist_seqr | 1082 83.94% 83.94% | 169 13.11% 97.05% | 28 2.17% 99.22% | 2 0.16% 99.38% | 5 0.39% 99.77% | 2 0.16% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1289 system.ruby.Directory.incomplete_times_seqr 1288 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 7.876088 system.ruby.network.routers0.msg_count.Control::2 1289 system.ruby.network.routers0.msg_count.Data::2 1285 @@ -378,6 +386,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 10312 system.ruby.network.routers0.msg_bytes.Data::2 92520 system.ruby.network.routers0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10280 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 7.876088 system.ruby.network.routers1.msg_count.Control::2 1289 system.ruby.network.routers1.msg_count.Data::2 1285 @@ -387,6 +396,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 10312 system.ruby.network.routers1.msg_bytes.Data::2 92520 system.ruby.network.routers1.msg_bytes.Response_Data::4 92808 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10280 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 7.876088 system.ruby.network.routers2.msg_count.Control::2 1289 system.ruby.network.routers2.msg_count.Data::2 1285 @@ -396,6 +406,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 10312 system.ruby.network.routers2.msg_bytes.Data::2 92520 system.ruby.network.routers2.msg_bytes.Response_Data::4 92808 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 10280 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 3867 system.ruby.network.msg_count.Data 3855 system.ruby.network.msg_count.Response_Data 3867 @@ -404,6 +415,7 @@ system.ruby.network.msg_byte.Control 30936 system.ruby.network.msg_byte.Data 277560 system.ruby.network.msg_byte.Response_Data 278424 system.ruby.network.msg_byte.Writeback_Control 30840 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.throttle0.link_utilization 7.885879 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1289 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1285 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index ad6f58618..77136ce08 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000031 # Nu sim_ticks 30526500 # Number of ticks simulated final_tick 30526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 398653 # Simulator instruction rate (inst/s) -host_op_rate 397863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2276293986 # Simulator tick rate (ticks/s) -host_mem_usage 245124 # Number of bytes of host memory used +host_inst_rate 412582 # Simulator instruction rate (inst/s) +host_op_rate 412293 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2361216779 # Simulator tick rate (ticks/s) +host_mem_usage 290052 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory system.physmem.bytes_read::total 24896 # Number of bytes read from this memory @@ -29,8 +30,10 @@ system.physmem.bw_inst_read::total 534617464 # In system.physmem.bw_total::cpu.inst 534617464 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 280936236 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 815553699 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 30526500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 61053 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -89,6 +92,7 @@ system.cpu.op_class::MemWrite 678 12.63% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5370 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 81.961543 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. @@ -104,6 +108,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits @@ -190,6 +195,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60644.444444 system.cpu.dcache.demand_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 116.865384 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. @@ -205,6 +211,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 158 system.cpu.icache.tags.occ_task_id_percent::1024 0.125488 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 10999 # Number of tag accesses system.cpu.icache.tags.data_accesses 10999 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits @@ -271,6 +278,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60628.404669 system.cpu.icache.demand_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 141.950442 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. @@ -288,6 +296,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 190 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3525 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits @@ -418,6 +427,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution @@ -447,6 +457,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 385500 # La system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 308 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution system.membus.trans_dist::ReadExResp 81 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 4713d8f7c..5bbab77d0 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000021 # Nu sim_ticks 21273500 # Number of ticks simulated final_tick 21273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54566 # Simulator instruction rate (inst/s) -host_op_rate 98846 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 215714601 # Simulator tick rate (ticks/s) -host_mem_usage 266040 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 60676 # Simulator instruction rate (inst/s) +host_op_rate 109916 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 239878032 # Simulator tick rate (ticks/s) +host_mem_usage 312536 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8896 # Number of bytes read from this memory system.physmem.bytes_read::total 26624 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 520000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 15224250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 3510 # Number of BP lookups system.cpu.branchPred.condPredicted 3510 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 564 # Number of conditional branches incorrect @@ -264,8 +266,12 @@ system.cpu.branchPred.indirectHits 493 # Nu system.cpu.branchPred.indirectMisses 2441 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 404 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 21273500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 42548 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -556,6 +562,7 @@ system.cpu.cc_regfile_reads 8296 # nu system.cpu.cc_regfile_writes 5092 # number of cc regfile writes system.cpu.misc_regfile_reads 7660 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 81.534494 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2583 # Total number of references to valid blocks. @@ -571,6 +578,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 system.cpu.dcache.tags.occ_task_id_percent::1024 0.033936 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 5685 # Number of tag accesses system.cpu.dcache.tags.data_accesses 5685 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1723 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1723 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 860 # number of WriteReq hits @@ -663,6 +671,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83525.179856 system.cpu.dcache.demand_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83525.179856 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 130.801873 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1651 # Total number of references to valid blocks. @@ -678,6 +687,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 131 system.cpu.icache.tags.occ_task_id_percent::1024 0.135742 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4350 # Number of tag accesses system.cpu.icache.tags.data_accesses 4350 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1651 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1651 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1651 # number of demand (read+write) hits @@ -750,6 +760,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78663.669065 system.cpu.icache.demand_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78663.669065 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 163.058861 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. @@ -767,6 +778,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010406 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3752 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3752 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -893,6 +905,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 342 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 75 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 75 # Transaction distribution @@ -922,6 +935,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 417000 # La system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 208500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 341 # Transaction distribution system.membus.trans_dist::ReadExReq 75 # Transaction distribution system.membus.trans_dist::ReadExResp 75 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index dcd77e088..da4043b17 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000006 # Nu sim_ticks 5615000 # Number of ticks simulated final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 380560 # Simulator instruction rate (inst/s) -host_op_rate 688269 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 395838528 # Simulator tick rate (ticks/s) -host_mem_usage 254256 # Number of bytes of host memory used +host_inst_rate 383826 # Simulator instruction rate (inst/s) +host_op_rate 694898 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 400042776 # Simulator tick rate (ticks/s) +host_mem_usage 299464 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7066 # Number of bytes read from this memory system.physmem.bytes_read::total 61978 # Number of bytes read from this memory @@ -35,9 +36,14 @@ system.physmem.bw_write::total 1266607302 # Wr system.physmem.bw_total::cpu.inst 9779519145 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2525022262 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 12304541407 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 5615000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 11231 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -98,6 +104,7 @@ system.cpu.op_class::MemWrite 935 9.59% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7917 # Transaction distribution system.membus.trans_dist::ReadResp 7917 # Transaction distribution system.membus.trans_dist::WriteReq 935 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index bf06f8c45..5369fe205 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000088 # Nu sim_ticks 87948 # Number of ticks simulated final_tick 87948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 77426 # Simulator instruction rate (inst/s) -host_op_rate 140230 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1264887 # Simulator tick rate (ticks/s) -host_mem_usage 428592 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 83700 # Simulator instruction rate (inst/s) +host_op_rate 151608 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1367648 # Simulator tick rate (ticks/s) +host_mem_usage 473696 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 88128 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 88128 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 87872 # Number of bytes written to this memory @@ -267,9 +268,14 @@ system.mem_ctrls_1.memoryStateTime::REF 2860 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 77782 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 16 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 87948 # Cumulative time (in ticks) in various power states system.cpu.numCycles 87948 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -331,6 +337,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 2750 # delay histogram for all message @@ -367,10 +374,14 @@ system.ruby.miss_latency_hist_seqr::stdev 33.292581 system.ruby.miss_latency_hist_seqr | 1149 83.44% 83.44% | 191 13.87% 97.31% | 24 1.74% 99.06% | 5 0.36% 99.42% | 2 0.15% 99.56% | 6 0.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1377 system.ruby.Directory.incomplete_times_seqr 1376 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 7.817119 system.ruby.network.routers0.msg_count.Control::2 1377 system.ruby.network.routers0.msg_count.Data::2 1373 @@ -380,6 +391,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 11016 system.ruby.network.routers0.msg_bytes.Data::2 98856 system.ruby.network.routers0.msg_bytes.Response_Data::4 99144 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10984 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 7.817119 system.ruby.network.routers1.msg_count.Control::2 1377 system.ruby.network.routers1.msg_count.Data::2 1373 @@ -389,6 +401,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 11016 system.ruby.network.routers1.msg_bytes.Data::2 98856 system.ruby.network.routers1.msg_bytes.Response_Data::4 99144 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10984 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 7.817119 system.ruby.network.routers2.msg_count.Control::2 1377 system.ruby.network.routers2.msg_count.Data::2 1373 @@ -398,6 +411,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 11016 system.ruby.network.routers2.msg_bytes.Data::2 98856 system.ruby.network.routers2.msg_bytes.Response_Data::4 99144 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 10984 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 4131 system.ruby.network.msg_count.Data 4119 system.ruby.network.msg_count.Response_Data 4131 @@ -406,6 +420,7 @@ system.ruby.network.msg_byte.Control 33048 system.ruby.network.msg_byte.Data 296568 system.ruby.network.msg_byte.Response_Data 297432 system.ruby.network.msg_byte.Writeback_Control 32952 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.throttle0.link_utilization 7.826215 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 0e6d74be3..be586bcab 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000031 # Nu sim_ticks 30886500 # Number of ticks simulated final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 324268 # Simulator instruction rate (inst/s) -host_op_rate 586988 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1858658321 # Simulator tick rate (ticks/s) -host_mem_usage 262968 # Number of bytes of host memory used +host_inst_rate 223066 # Simulator instruction rate (inst/s) +host_op_rate 403939 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1279464733 # Simulator tick rate (ticks/s) +host_mem_usage 309460 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory system.physmem.bytes_read::total 23104 # Number of bytes read from this memory @@ -29,9 +30,14 @@ system.physmem.bw_inst_read::total 470367313 # In system.physmem.bw_total::cpu.inst 470367313 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 277661762 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 748029074 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 30886500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 61773 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -92,6 +98,7 @@ system.cpu.op_class::MemWrite 935 9.59% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 80.558239 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. @@ -107,6 +114,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits @@ -193,6 +201,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 105.267613 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. @@ -208,6 +217,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 142 system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses system.cpu.icache.tags.data_accesses 13956 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 6636 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6636 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6636 # number of demand (read+write) hits @@ -274,6 +284,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60791.666667 system.cpu.icache.demand_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 133.672095 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. @@ -291,6 +302,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008606 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -417,6 +429,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution @@ -446,6 +459,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 342000 # La system.cpu.toL2Bus.respLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 282 # Transaction distribution system.membus.trans_dist::ReadExReq 79 # Transaction distribution system.membus.trans_dist::ReadExResp 79 # Transaction distribution diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt index 458736244..6380191ed 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000026 # Nu sim_ticks 25580500 # Number of ticks simulated final_tick 25580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119260 # Simulator instruction rate (inst/s) -host_op_rate 119247 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 238851205 # Simulator tick rate (ticks/s) -host_mem_usage 249876 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 131467 # Simulator instruction rate (inst/s) +host_op_rate 131454 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 263302304 # Simulator tick rate (ticks/s) +host_mem_usage 296128 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 12770 # Number of instructions simulated sim_ops 12770 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 39680 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 21824 # Number of bytes read from this memory system.physmem.bytes_read::total 61504 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 780000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 22525750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 4883 # Number of BP lookups system.cpu.branchPred.condPredicted 2924 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 790 # Number of conditional branches incorrect @@ -298,6 +300,7 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 25580500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 51162 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -728,6 +731,7 @@ system.cpu.fp_regfile_reads 16 # nu system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements::0 0 # number of replacements system.cpu.dcache.tags.replacements::1 0 # number of replacements system.cpu.dcache.tags.replacements::total 0 # number of replacements @@ -745,6 +749,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 269 system.cpu.dcache.tags.occ_task_id_percent::1024 0.083252 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 10889 # Number of tag accesses system.cpu.dcache.tags.data_accesses 10889 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 3245 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 3245 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1018 # number of WriteReq hits @@ -839,6 +844,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87893.233918 system.cpu.dcache.demand_avg_mshr_miss_latency::total 87893.233918 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87893.233918 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 87893.233918 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements::0 7 # number of replacements system.cpu.icache.tags.replacements::1 0 # number of replacements system.cpu.icache.tags.replacements::total 7 # number of replacements @@ -856,6 +862,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 379 system.cpu.icache.tags.occ_task_id_percent::1024 0.300781 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 8261 # Number of tag accesses system.cpu.icache.tags.data_accesses 8261 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 2916 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2916 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2916 # number of demand (read+write) hits @@ -930,6 +937,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80906.894061 system.cpu.icache.demand_avg_mshr_miss_latency::total 80906.894061 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80906.894061 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 80906.894061 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements::0 0 # number of replacements system.cpu.l2cache.tags.replacements::1 0 # number of replacements system.cpu.l2cache.tags.replacements::total 0 # number of replacements @@ -949,6 +957,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 529 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.024872 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 8737 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 8737 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits @@ -1079,6 +1088,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 818 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution @@ -1109,6 +1119,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 934500 # La system.cpu.toL2Bus.respLayer0.utilization 3.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 511500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 815 # Transaction distribution system.membus.trans_dist::ReadExReq 146 # Transaction distribution system.membus.trans_dist::ReadExResp 146 # Transaction distribution diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 917779471..4d702e129 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000029 # Nu sim_ticks 28845500 # Number of ticks simulated final_tick 28845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50478 # Simulator instruction rate (inst/s) -host_op_rate 50473 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 100846842 # Simulator tick rate (ticks/s) -host_mem_usage 247864 # Number of bytes of host memory used -host_seconds 0.29 # Real time elapsed on the host +host_inst_rate 97927 # Simulator instruction rate (inst/s) +host_op_rate 97921 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 195651101 # Simulator tick rate (ticks/s) +host_mem_usage 293060 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory system.physmem.bytes_read::total 32640 # Number of bytes read from this memory @@ -249,6 +250,7 @@ system.physmem_1.memoryStateTime::REF 780000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 21995000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 12618 # Number of BP lookups system.cpu.branchPred.condPredicted 7653 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1475 # Number of conditional branches incorrect @@ -264,6 +266,7 @@ system.cpu.branchPred.indirectMisses 7614 # Nu system.cpu.branchPredindirectMispredicted 897 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 28845500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 57692 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -548,6 +551,7 @@ system.cpu.int_regfile_reads 36850 # nu system.cpu.int_regfile_writes 20548 # number of integer regfile writes system.cpu.misc_regfile_reads 8142 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 99.867537 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 4648 # Total number of references to valid blocks. @@ -563,6 +567,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 10540 # Number of tag accesses system.cpu.dcache.tags.data_accesses 10540 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 3609 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 3609 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits @@ -661,6 +666,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78962.837838 system.cpu.dcache.demand_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 206.414108 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6949 # Total number of references to valid blocks. @@ -676,6 +682,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 274 system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 15425 # Number of tag accesses system.cpu.icache.tags.data_accesses 15425 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 6949 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6949 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6949 # number of demand (read+write) hits @@ -748,6 +755,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76017.808219 system.cpu.icache.demand_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 240.923513 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. @@ -765,6 +773,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 318 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4613 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4613 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -891,6 +900,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution @@ -920,6 +930,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 547500 # La system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 426 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution system.membus.trans_dist::ReadExResp 83 # Transaction distribution diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index 036ee4f34..f85a288f2 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000008 # Nu sim_ticks 7612000 # Number of ticks simulated final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 353219 # Simulator instruction rate (inst/s) -host_op_rate 353015 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 177141347 # Simulator tick rate (ticks/s) -host_mem_usage 236080 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 696198 # Simulator instruction rate (inst/s) +host_op_rate 695914 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 349255842 # Simulator tick rate (ticks/s) +host_mem_usage 279976 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 7612000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 60828 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 11342 # Number of bytes read from this memory system.physmem.bytes_read::total 72170 # Number of bytes read from this memory @@ -37,8 +38,10 @@ system.physmem.bw_write::total 1187861272 # Wr system.physmem.bw_total::cpu.inst 7991066737 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2677877036 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10668943773 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 7612000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 7612000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 15225 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -97,6 +100,7 @@ system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 15207 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 7612000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 17432 # Transaction distribution system.membus.trans_dist::ReadResp 17432 # Transaction distribution system.membus.trans_dist::WriteReq 1442 # Transaction distribution diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 35f2e5918..718aa1232 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000044 # Nu sim_ticks 44282500 # Number of ticks simulated final_tick 44282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 282453 # Simulator instruction rate (inst/s) -host_op_rate 282325 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 824249311 # Simulator tick rate (ticks/s) -host_mem_usage 245052 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 533053 # Simulator instruction rate (inst/s) +host_op_rate 532883 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1555927955 # Simulator tick rate (ticks/s) +host_mem_usage 289976 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory system.physmem.bytes_read::total 26624 # Number of bytes read from this memory @@ -29,8 +30,10 @@ system.physmem.bw_inst_read::total 401784000 # In system.physmem.bw_total::cpu.inst 401784000 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 199446734 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 601230734 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 44282500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 88565 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -89,6 +92,7 @@ system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 15207 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 97.148649 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. @@ -104,6 +108,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits @@ -194,6 +199,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 151.748662 # Cycle average of tags in use system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. @@ -209,6 +215,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 235 system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses system.cpu.icache.tags.data_accesses 30696 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits @@ -275,6 +282,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60658.928571 system.cpu.icache.demand_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 182.297739 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. @@ -292,6 +300,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 276 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -418,6 +427,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution @@ -447,6 +457,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 420000 # La system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 331 # Transaction distribution system.membus.trans_dist::ReadExReq 85 # Transaction distribution system.membus.trans_dist::ReadExResp 85 # Transaction distribution diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt index 3711ab70b..540013051 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000405 # Nu sim_ticks 405365000 # Number of ticks simulated final_tick 405365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 217578 # Simulator instruction rate (inst/s) -host_op_rate 217432 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13650898473 # Simulator tick rate (ticks/s) -host_mem_usage 630716 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 281711 # Simulator instruction rate (inst/s) +host_op_rate 281601 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17683002929 # Simulator tick rate (ticks/s) +host_mem_usage 675684 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 6453 # Number of instructions simulated sim_ops 6453 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 405365000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 25852 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8844 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 34696 # Number of bytes read from this memory @@ -271,6 +272,7 @@ system.mem_ctrl_1.memoryStateTime::REF 13520000 # Ti system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT 324052250 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 405365000 # Cumulative time (in ticks) in various power states system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -304,6 +306,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 405365000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 405365 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -362,6 +365,7 @@ system.cpu.op_class::MemWrite 868 13.43% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6463 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 405365000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7654 # Transaction distribution system.membus.trans_dist::ReadResp 7653 # Transaction distribution system.membus.trans_dist::WriteReq 865 # Transaction distribution diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt index 57afd555e..965f59d57 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000061 # Nu sim_ticks 61470000 # Number of ticks simulated final_tick 61470000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 556042 # Simulator instruction rate (inst/s) -host_op_rate 555477 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5286056763 # Simulator tick rate (ticks/s) -host_mem_usage 634812 # Number of bytes of host memory used +host_inst_rate 534192 # Simulator instruction rate (inst/s) +host_op_rate 533574 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5078648410 # Simulator tick rate (ticks/s) +host_mem_usage 679784 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 6453 # Number of instructions simulated sim_ops 6453 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory @@ -249,6 +250,7 @@ system.mem_ctrl_1.memoryStateTime::REF 1820000 # Ti system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT 51068500 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -282,6 +284,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 61470000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 61470 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -340,6 +343,7 @@ system.cpu.op_class::MemWrite 868 13.43% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6463 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 104.645861 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks. @@ -355,6 +359,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4278 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits @@ -441,6 +446,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101452.380952 system.cpu.dcache.demand_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 62 # number of replacements system.cpu.icache.tags.tagsinuse 113.715440 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks. @@ -456,6 +462,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 167 system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses system.cpu.icache.tags.data_accesses 13209 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits @@ -528,6 +535,7 @@ system.l2bus.snoop_filter.hit_multi_requests 0 system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2bus.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 376 # Transaction distribution system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -557,6 +565,7 @@ system.l2bus.respLayer0.occupancy 843000 # La system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements system.l2cache.tags.tagsinuse 185.619069 # Cycle average of tags in use system.l2cache.tags.total_refs 65 # Total number of references to valid blocks. @@ -574,6 +583,7 @@ system.l2cache.tags.age_task_id_blocks_1024::1 311 system.l2cache.tags.occ_task_id_percent::1024 0.091064 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 4534 # Number of tag accesses system.l2cache.tags.data_accesses 4534 # Number of data accesses +system.l2cache.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 3 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits system.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -685,6 +695,7 @@ system.l2cache.demand_avg_mshr_miss_latency::total 76461.883408 system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 373 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt index 0fe3c4c97..1d743770e 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000326 # Nu sim_ticks 325849000 # Number of ticks simulated final_tick 325849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 204518 # Simulator instruction rate (inst/s) -host_op_rate 236491 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13350749795 # Simulator tick rate (ticks/s) -host_mem_usage 689808 # Number of bytes of host memory used +host_inst_rate 301831 # Simulator instruction rate (inst/s) +host_op_rate 348968 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19697741357 # Simulator tick rate (ticks/s) +host_mem_usage 691496 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 20108 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 4672 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 24780 # Number of bytes read from this memory @@ -269,6 +270,8 @@ system.mem_ctrl_1.memoryStateTime::REF 10660000 # Ti system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT 256888500 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -298,6 +301,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -327,6 +331,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,6 +361,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -386,6 +392,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 325849000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 325849 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -446,6 +453,7 @@ system.cpu.op_class::MemWrite 950 16.29% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5831 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6078 # Transaction distribution system.membus.trans_dist::ReadResp 6088 # Transaction distribution system.membus.trans_dist::WriteReq 925 # Transaction distribution diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt index 825faee95..bff9edae7 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000050 # Nu sim_ticks 49855000 # Number of ticks simulated final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 372227 # Simulator instruction rate (inst/s) -host_op_rate 430264 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3715181399 # Simulator tick rate (ticks/s) -host_mem_usage 693900 # Number of bytes of host memory used +host_inst_rate 407452 # Simulator instruction rate (inst/s) +host_op_rate 470980 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4066768251 # Simulator tick rate (ticks/s) +host_mem_usage 695596 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory @@ -249,6 +250,8 @@ system.mem_ctrl_1.memoryStateTime::REF 1560000 # Ti system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT 42873250 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -278,6 +281,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -307,6 +311,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -336,6 +341,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -366,6 +372,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 49855000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 49855 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -426,6 +433,7 @@ system.cpu.op_class::MemWrite 950 16.29% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5831 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 84.288257 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks. @@ -441,6 +449,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 system.cpu.dcache.tags.occ_task_id_percent::1024 0.138672 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4136 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4136 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 951 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 951 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 882 # number of WriteReq hits @@ -535,6 +544,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437 system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 70 # number of replacements system.cpu.icache.tags.tagsinuse 96.468360 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. @@ -550,6 +560,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 125 system.cpu.icache.tags.occ_task_id_percent::1024 0.699219 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 10305 # Number of tag accesses system.cpu.icache.tags.data_accesses 10305 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 4779 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4779 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4779 # number of demand (read+write) hits @@ -622,6 +633,7 @@ system.l2bus.snoop_filter.hit_multi_requests 10 system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2bus.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 348 # Transaction distribution system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -651,6 +663,7 @@ system.l2bus.respLayer0.occupancy 747000 # La system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements system.l2cache.tags.tagsinuse 156.197536 # Cycle average of tags in use system.l2cache.tags.total_refs 100 # Total number of references to valid blocks. @@ -668,6 +681,7 @@ system.l2cache.tags.age_task_id_blocks_1024::1 246 system.l2cache.tags.occ_task_id_percent::1024 0.075195 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 3959 # Number of tag accesses system.l2cache.tags.data_accesses 3959 # Number of data accesses +system.l2cache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 24 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 40 # number of ReadSharedReq hits @@ -782,6 +796,7 @@ system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114 system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 308 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt index 9cc36ad4e..e9f25f2b3 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000369 # Nu sim_ticks 368887000 # Number of ticks simulated final_tick 368887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 294016 # Simulator instruction rate (inst/s) -host_op_rate 293668 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19182713753 # Simulator tick rate (ticks/s) -host_mem_usage 628676 # Number of bytes of host memory used +host_inst_rate 323597 # Simulator instruction rate (inst/s) +host_op_rate 323434 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21140902807 # Simulator tick rate (ticks/s) +host_mem_usage 672844 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 368887000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 22568 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 4301 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 26869 # Number of bytes read from this memory @@ -270,6 +271,7 @@ system.mem_ctrl_1.memoryStateTime::REF 12220000 # Ti system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT 350555250 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 368887000 # Cumulative time (in ticks) in various power states system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -289,6 +291,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 368887000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 368887 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -347,6 +350,7 @@ system.cpu.op_class::MemWrite 902 15.99% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 368887000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6778 # Transaction distribution system.membus.trans_dist::ReadResp 6777 # Transaction distribution system.membus.trans_dist::WriteReq 901 # Transaction distribution diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt index f4dfddbc8..41fba603d 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000059 # Nu sim_ticks 58892000 # Number of ticks simulated final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 509573 # Simulator instruction rate (inst/s) -host_op_rate 509069 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5309891860 # Simulator tick rate (ticks/s) -host_mem_usage 632772 # Number of bytes of host memory used +host_inst_rate 486513 # Simulator instruction rate (inst/s) +host_op_rate 486102 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5071440381 # Simulator tick rate (ticks/s) +host_mem_usage 676956 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 18752 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 27520 # Number of bytes read from this memory @@ -249,6 +250,7 @@ system.mem_ctrl_1.memoryStateTime::REF 1820000 # Ti system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT 52812500 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -268,6 +270,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 58892000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 58892 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -326,6 +329,7 @@ system.cpu.op_class::MemWrite 902 15.99% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 86.268662 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks. @@ -341,6 +345,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 system.cpu.dcache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits @@ -427,6 +432,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101459.854015 system.cpu.dcache.demand_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 94 # number of replacements system.cpu.icache.tags.tagsinuse 110.145403 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5346 # Total number of references to valid blocks. @@ -442,6 +448,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 139 system.cpu.icache.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 11583 # Number of tag accesses system.cpu.icache.tags.data_accesses 11583 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 5346 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5346 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5346 # number of demand (read+write) hits @@ -514,6 +521,7 @@ system.l2bus.snoop_filter.hit_multi_requests 0 system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2bus.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 384 # Transaction distribution system.l2bus.trans_dist::CleanEvict 94 # Transaction distribution system.l2bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -543,6 +551,7 @@ system.l2bus.respLayer0.occupancy 891000 # La system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) system.l2bus.respLayer1.occupancy 411000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements system.l2cache.tags.tagsinuse 183.861903 # Cycle average of tags in use system.l2cache.tags.total_refs 98 # Total number of references to valid blocks. @@ -560,6 +569,7 @@ system.l2cache.tags.age_task_id_blocks_1024::1 303 system.l2cache.tags.occ_task_id_percent::1024 0.092773 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 4654 # Number of tag accesses system.l2cache.tags.data_accesses 4654 # Number of data accesses +system.l2cache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 4 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 4 # number of ReadSharedReq hits system.l2cache.demand_hits::cpu.inst 4 # number of demand (read+write) hits @@ -671,6 +681,7 @@ system.l2cache.demand_avg_mshr_miss_latency::total 78023.255814 system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 380 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt index aae0960f1..1263f399d 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000333 # Nu sim_ticks 333033000 # Number of ticks simulated final_tick 333033000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 348800 # Simulator instruction rate (inst/s) -host_op_rate 348537 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20908249754 # Simulator tick rate (ticks/s) -host_mem_usage 629116 # Number of bytes of host memory used +host_inst_rate 352196 # Simulator instruction rate (inst/s) +host_op_rate 351993 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21118670028 # Simulator tick rate (ticks/s) +host_mem_usage 673252 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 333033000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 22364 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 4640 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 27004 # Number of bytes read from this memory @@ -271,7 +272,9 @@ system.mem_ctrl_1.memoryStateTime::REF 10920000 # Ti system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT 229634250 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 333033000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 333033000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 333033 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -330,6 +333,7 @@ system.cpu.op_class::MemWrite 678 12.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5591 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 333033000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6310 # Transaction distribution system.membus.trans_dist::ReadResp 6309 # Transaction distribution system.membus.trans_dist::WriteReq 673 # Transaction distribution diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt index f9225f3bc..8682445d5 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000053 # Nu sim_ticks 53334000 # Number of ticks simulated final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 429905 # Simulator instruction rate (inst/s) -host_op_rate 429380 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4122052129 # Simulator tick rate (ticks/s) -host_mem_usage 633208 # Number of bytes of host memory used +host_inst_rate 483647 # Simulator instruction rate (inst/s) +host_op_rate 483274 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4642649843 # Simulator tick rate (ticks/s) +host_mem_usage 677372 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 16448 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 25216 # Number of bytes read from this memory @@ -254,7 +255,9 @@ system.mem_ctrl_1.memoryStateTime::REF 1560000 # Ti system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT 41660500 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 53334000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 53334 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -313,6 +316,7 @@ system.cpu.op_class::MemWrite 678 12.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5591 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 83.743129 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. @@ -328,6 +332,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 system.cpu.dcache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 2920 # Number of tag accesses system.cpu.dcache.tags.data_accesses 2920 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 591 # number of WriteReq hits @@ -414,6 +419,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 99195.652174 system.cpu.dcache.demand_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 71 # number of replacements system.cpu.icache.tags.tagsinuse 98.062907 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks. @@ -429,6 +435,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 128 system.cpu.icache.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 11443 # Number of tag accesses system.cpu.icache.tags.data_accesses 11443 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 5333 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5333 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5333 # number of demand (read+write) hits @@ -501,6 +508,7 @@ system.l2bus.snoop_filter.hit_multi_requests 1 system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2bus.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 315 # Transaction distribution system.l2bus.trans_dist::CleanEvict 71 # Transaction distribution system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution @@ -530,6 +538,7 @@ system.l2bus.respLayer0.occupancy 777000 # La system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) system.l2bus.respLayer1.occupancy 414000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements system.l2cache.tags.tagsinuse 144.000978 # Cycle average of tags in use system.l2cache.tags.total_refs 73 # Total number of references to valid blocks. @@ -547,6 +556,7 @@ system.l2cache.tags.age_task_id_blocks_1024::1 244 system.l2cache.tags.occ_task_id_percent::1024 0.076172 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 4130 # Number of tag accesses system.l2cache.tags.data_accesses 4130 # Number of data accesses +system.l2cache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 2 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits @@ -661,6 +671,7 @@ system.l2cache.demand_avg_mshr_miss_latency::total 76725.888325 system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 312 # Transaction distribution system.membus.trans_dist::ReadExReq 82 # Transaction distribution system.membus.trans_dist::ReadExResp 82 # Transaction distribution diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt index f88f09a70..9c22d46ab 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000445 # Nu sim_ticks 445082000 # Number of ticks simulated final_tick 445082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 211115 # Simulator instruction rate (inst/s) -host_op_rate 380995 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16432986499 # Simulator tick rate (ticks/s) -host_mem_usage 647212 # Number of bytes of host memory used +host_inst_rate 219197 # Simulator instruction rate (inst/s) +host_op_rate 395662 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17068456983 # Simulator tick rate (ticks/s) +host_mem_usage 691636 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 58264 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 7167 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 65431 # Number of bytes read from this memory @@ -273,8 +274,13 @@ system.mem_ctrl_1.memoryStateTime::REF 14820000 # Ti system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT 377923250 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 445082000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 445082 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -335,6 +341,7 @@ system.cpu.op_class::MemWrite 941 9.12% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 10314 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 8367 # Transaction distribution system.membus.trans_dist::ReadResp 8367 # Transaction distribution system.membus.trans_dist::WriteReq 941 # Transaction distribution diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt index 78bfc0a03..41d5837a9 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000056 # Nu sim_ticks 55844000 # Number of ticks simulated final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 299396 # Simulator instruction rate (inst/s) -host_op_rate 540174 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2922543083 # Simulator tick rate (ticks/s) -host_mem_usage 651308 # Number of bytes of host memory used +host_inst_rate 304150 # Simulator instruction rate (inst/s) +host_op_rate 548931 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2970813002 # Simulator tick rate (ticks/s) +host_mem_usage 696756 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 14656 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8640 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 23296 # Number of bytes read from this memory @@ -250,8 +251,13 @@ system.mem_ctrl_1.memoryStateTime::REF 1820000 # Ti system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT 51070000 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 55844000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 55844 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -312,6 +318,7 @@ system.cpu.op_class::MemWrite 941 9.12% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 10314 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 81.671640 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks. @@ -327,6 +334,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4185 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4185 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1028 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1028 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits @@ -413,6 +421,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103674.074074 system.cpu.dcache.demand_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 58 # number of replacements system.cpu.icache.tags.tagsinuse 91.239705 # Cycle average of tags in use system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. @@ -428,6 +437,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 133 system.cpu.icache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 14801 # Number of tag accesses system.cpu.icache.tags.data_accesses 14801 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 7048 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 7048 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 7048 # number of demand (read+write) hits @@ -500,6 +510,7 @@ system.l2bus.snoop_filter.hit_multi_requests 0 system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2bus.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 291 # Transaction distribution system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution @@ -529,6 +540,7 @@ system.l2bus.respLayer0.occupancy 705000 # La system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%) system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements system.l2cache.tags.tagsinuse 135.848259 # Cycle average of tags in use system.l2cache.tags.total_refs 64 # Total number of references to valid blocks. @@ -546,6 +558,7 @@ system.l2cache.tags.age_task_id_blocks_1024::1 231 system.l2cache.tags.occ_task_id_percent::1024 0.069580 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 3788 # Number of tag accesses system.l2cache.tags.data_accesses 3788 # Number of data accesses +system.l2cache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 6 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 6 # number of ReadSharedReq hits system.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits @@ -657,6 +670,7 @@ system.l2cache.demand_avg_mshr_miss_latency::total 78873.626374 system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 285 # Transaction distribution system.membus.trans_dist::ReadExReq 79 # Transaction distribution system.membus.trans_dist::ReadExResp 79 # Transaction distribution diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt index 1711c0a9f..bde6c8cac 100644 --- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000663 # Nu sim_ticks 663454500 # Number of ticks simulated final_tick 663454500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 153021 # Simulator instruction rate (inst/s) -host_op_rate 314663 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1515963159 # Simulator tick rate (ticks/s) -host_mem_usage 1308268 # Number of bytes of host memory used -host_seconds 0.44 # Real time elapsed on the host +host_inst_rate 237471 # Simulator instruction rate (inst/s) +host_op_rate 488329 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2352682974 # Simulator tick rate (ticks/s) +host_mem_usage 1358064 # Number of bytes of host memory used +host_seconds 0.28 # Real time elapsed on the host sim_insts 66963 # Number of instructions simulated sim_ops 137705 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::dir_cntrl0 99264 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 99264 # Number of bytes read from this memory system.mem_ctrls.num_reads::dir_cntrl0 1551 # Number of read requests responded to by this memory @@ -243,6 +244,7 @@ system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # system.mem_ctrls_1.memoryStateTime::ACT 524145250 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.ruby.clk_domain.clock 500 # Clock period in ticks +system.ruby.phys_mem.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory system.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 3280 # Number of bytes read from this memory @@ -283,6 +285,8 @@ system.ruby.phys_mem.bw_total::cpu0.data 290297225 # To system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 5329680 # Total bandwidth to/from this memory (bytes/s) system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 5329680 # Total bandwidth to/from this memory (bytes/s) system.ruby.phys_mem.bw_total::total 1351156711 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 system.ruby.outstanding_req_hist_seqr::samples 114203 @@ -365,9 +369,24 @@ system.cp_cntrl0.L2cache.num_data_array_reads 120 system.cp_cntrl0.L2cache.num_data_array_writes 11982 # number of data array writes system.cp_cntrl0.L2cache.num_tag_array_reads 12059 # number of tag array reads system.cp_cntrl0.L2cache.num_tag_array_writes 1649 # number of tag array writes +system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.cpu0.clk_domain.clock 500 # Clock period in ticks +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu0.interrupts.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.cpu0.workload.num_syscalls 21 # Number of system calls +system.cpu0.numPwrStateTransitions 2 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 2615501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 1 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 2615501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 2615501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 660838999 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2615501 # Cumulative time (in ticks) in various power states system.cpu0.numCycles 1326909 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -430,6 +449,7 @@ system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu0.op_class::total 137705 # Class of executed instruction system.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.cpu1.clk_domain.clock 1000 # Clock period in ticks +system.cpu1.CUs0.localDataStore.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 307 # number of times the wf's instructions are blocked due to RAW dependencies @@ -1198,6 +1218,7 @@ system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0 system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it @@ -1466,6 +1487,7 @@ system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 system.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations system.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed system.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts +system.cpu1.CUs1.localDataStore.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 401 # number of times the wf's instructions are blocked due to RAW dependencies @@ -2234,6 +2256,7 @@ system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0 system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it @@ -2502,6 +2525,9 @@ system.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0 system.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations system.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed system.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts +system.cpu1.CUs0.ldsBus.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.cpu1.CUs1.ldsBus.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.cpu2.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.cpu2.num_kernel_launched 1 # number of kernel launched system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses @@ -2509,8 +2535,10 @@ system.dir_cntrl0.L3CacheMemory.demand_accesses 0 system.dir_cntrl0.L3CacheMemory.num_data_array_writes 1551 # number of data array writes system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1551 # number of tag array reads system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1551 # number of tag array writes +system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks +system.dispatcher_coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses system.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses system.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue @@ -2518,6 +2546,7 @@ system.dispatcher_coalescer.local_queuing_cycles 0 system.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts system.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks +system.dispatcher_tlb.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses system.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits system.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses @@ -2534,6 +2563,7 @@ system.dispatcher_tlb.local_latency nan # Av system.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) system.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks +system.l1_coalescer0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses system.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses system.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue @@ -2541,6 +2571,7 @@ system.l1_coalescer0.local_queuing_cycles 0 # N system.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts system.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks +system.l1_coalescer1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses system.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses system.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue @@ -2548,6 +2579,7 @@ system.l1_coalescer1.local_queuing_cycles 0 # N system.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts system.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks +system.l1_tlb0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses system.l1_tlb0.local_TLB_hits 774 # Number of TLB hits system.l1_tlb0.local_TLB_misses 4 # Number of TLB misses @@ -2564,6 +2596,7 @@ system.l1_tlb0.local_latency 0 # Av system.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) system.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks +system.l1_tlb1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses system.l1_tlb1.local_TLB_hits 766 # Number of TLB hits system.l1_tlb1.local_TLB_misses 3 # Number of TLB misses @@ -2580,6 +2613,7 @@ system.l1_tlb1.local_latency 0 # Av system.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) system.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks +system.l2_coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses system.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses system.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue @@ -2587,6 +2621,7 @@ system.l2_coalescer.local_queuing_cycles 1000 # Nu system.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts system.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l2_tlb.clk_domain.clock 1000 # Clock period in ticks +system.l2_tlb.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses system.l2_tlb.local_TLB_hits 3 # Number of TLB hits system.l2_tlb.local_TLB_misses 5 # Number of TLB misses @@ -2603,6 +2638,7 @@ system.l2_tlb.local_latency 8625.125000 # Av system.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) system.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks +system.l3_coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses system.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses system.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue @@ -2610,6 +2646,7 @@ system.l3_coalescer.local_queuing_cycles 1000 # Nu system.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts system.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l3_tlb.clk_domain.clock 1000 # Clock period in ticks +system.l3_tlb.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses system.l3_tlb.local_TLB_hits 0 # Number of TLB hits system.l3_tlb.local_TLB_misses 5 # Number of TLB misses @@ -2624,6 +2661,7 @@ system.l3_tlb.unique_pages 5 # Nu system.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs system.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs system.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.piobus.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.piobus.trans_dist::WriteReq 94 # Transaction distribution system.piobus.trans_dist::WriteResp 94 # Transaction distribution system.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes) @@ -2634,6 +2672,7 @@ system.piobus.reqLayer0.occupancy 188000 # La system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks) system.piobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.ruby.network.ext_links0.int_node.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.ruby.network.ext_links0.int_node.percent_links_utilized 0.007952 system.ruby.network.ext_links0.int_node.msg_count.Control::0 1551 system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1551 @@ -2645,6 +2684,7 @@ system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 1240 system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 112536 system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 12312 system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12408 +system.ruby.network.ext_links1.int_node.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.ruby.network.ext_links1.int_node.percent_links_utilized 0.009970 system.ruby.network.ext_links1.int_node.msg_count.Control::0 16 system.ruby.network.ext_links1.int_node.msg_count.Request_Control::0 1535 @@ -2664,6 +2704,7 @@ system.tcp_cntrl0.L1cache.num_data_array_writes 11 system.tcp_cntrl0.L1cache.num_tag_array_reads 26 # number of tag array reads system.tcp_cntrl0.L1cache.num_tag_array_writes 18 # number of tag array writes system.tcp_cntrl0.L1cache.num_data_array_stalls 2 # number of stalls caused by data array +system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC @@ -2680,6 +2721,9 @@ system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links2.int_node.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.ruby.network.ext_links2.int_node.percent_links_utilized 0.000721 system.ruby.network.ext_links2.int_node.msg_count.Control::0 1535 system.ruby.network.ext_links2.int_node.msg_count.Control::1 14 @@ -2708,6 +2752,7 @@ system.tcp_cntrl1.L1cache.num_tag_array_reads 25 system.tcp_cntrl1.L1cache.num_tag_array_writes 18 # number of tag array writes system.tcp_cntrl1.L1cache.num_tag_array_stalls 2 # number of stalls caused by tag array system.tcp_cntrl1.L1cache.num_data_array_stalls 2 # number of stalls caused by data array +system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 3 # loads that hit in the TCP system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 2 # TCP to TCP load transfers system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC @@ -2724,6 +2769,8 @@ system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses @@ -2732,15 +2779,20 @@ system.sqc_cntrl0.L1cache.num_data_array_writes 5 system.sqc_cntrl0.L1cache.num_tag_array_reads 86 # number of tag array reads system.sqc_cntrl0.L1cache.num_tag_array_writes 5 # number of tag array writes system.sqc_cntrl0.L1cache.num_data_array_stalls 47 # number of stalls caused by data array +system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.sqc_cntrl0.sequencer.load_waiting_on_load 120 # Number of times a load aliased with a pending load +system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses +system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses system.tccdir_cntrl0.directory.num_tag_array_reads 1554 # number of tag array reads system.tccdir_cntrl0.directory.num_tag_array_writes 27 # number of tag array writes +system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 3116 system.ruby.network.msg_count.Request_Control 3121 system.ruby.network.msg_count.Response_Data 3159 @@ -2753,6 +2805,7 @@ system.ruby.network.msg_byte.Response_Control 24624 system.ruby.network.msg_byte.Unblock_Control 24968 system.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks +system.sqc_coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses system.sqc_coalescer.coalesced_accesses 60 # Number of coalesced TLB accesses system.sqc_coalescer.queuing_cycles 108000 # Number of cycles spent in queue @@ -2760,6 +2813,7 @@ system.sqc_coalescer.local_queuing_cycles 108000 # N system.sqc_coalescer.local_latency 1255.813953 # Avg. latency over all incoming pkts system.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks +system.sqc_tlb.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.sqc_tlb.local_TLB_accesses 60 # Number of TLB accesses system.sqc_tlb.local_TLB_hits 59 # Number of TLB hits system.sqc_tlb.local_TLB_misses 1 # Number of TLB misses @@ -2774,6 +2828,7 @@ system.sqc_tlb.unique_pages 1 # Nu system.sqc_tlb.local_cycles 60001 # Number of cycles spent in queue for all incoming reqs system.sqc_tlb.local_latency 1000.016667 # Avg. latency over incoming coalesced reqs system.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.005592 system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1551 system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 12 diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 05fda5798..2b946b0e1 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.054141 # Nu sim_ticks 54141000500 # Number of ticks simulated final_tick 54141000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2133242 # Simulator instruction rate (inst/s) -host_op_rate 2143866 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1274754382 # Simulator tick rate (ticks/s) -host_mem_usage 434732 # Number of bytes of host memory used -host_seconds 42.47 # Real time elapsed on the host +host_inst_rate 2060319 # Simulator instruction rate (inst/s) +host_op_rate 2070580 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1231177946 # Simulator tick rate (ticks/s) +host_mem_usage 436424 # Number of bytes of host memory used +host_seconds 43.98 # Real time elapsed on the host sim_insts 90602408 # Number of instructions simulated sim_ops 91053639 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 431323084 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory system.physmem.bytes_read::total 521339682 # Number of bytes read from this memory @@ -35,7 +36,9 @@ system.physmem.bw_write::total 349238799 # Wr system.physmem.bw_total::cpu.inst 7966662604 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2011871502 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9978534106 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -65,6 +68,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -94,6 +98,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -123,6 +128,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,6 +159,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 54141000500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 108282002 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -213,6 +220,7 @@ system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91054081 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 130287906 # Transaction distribution system.membus.trans_dist::ReadResp 130291793 # Transaction distribution system.membus.trans_dist::WriteReq 4734981 # Transaction distribution diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 1f4d8614e..1c05d7789 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.147149 # Nu sim_ticks 147148719500 # Number of ticks simulated final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1356153 # Simulator instruction rate (inst/s) -host_op_rate 1362892 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2203169070 # Simulator tick rate (ticks/s) -host_mem_usage 444740 # Number of bytes of host memory used -host_seconds 66.79 # Real time elapsed on the host +host_inst_rate 1337875 # Simulator instruction rate (inst/s) +host_op_rate 1344524 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2173475460 # Simulator tick rate (ticks/s) +host_mem_usage 445404 # Number of bytes of host memory used +host_seconds 67.70 # Real time elapsed on the host sim_insts 90576862 # Number of instructions simulated sim_ops 91026991 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory system.physmem.bytes_read::total 981760 # Number of bytes read from this memory @@ -29,7 +30,9 @@ system.physmem.bw_inst_read::total 250957 # In system.physmem.bw_total::cpu.inst 250957 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 6420933 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 6671890 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -59,6 +62,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -88,6 +92,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -117,6 +122,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -147,6 +153,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 147148719500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 294297439 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -207,6 +214,7 @@ system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91054081 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 942702 # number of replacements system.cpu.dcache.tags.tagsinuse 3565.478025 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. @@ -224,6 +232,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits @@ -342,6 +351,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704 system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2 # number of replacements system.cpu.icache.tags.tagsinuse 510.111710 # Cycle average of tags in use system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks. @@ -359,6 +369,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 552 system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 215662143 # Number of tag accesses system.cpu.icache.tags.data_accesses 215662143 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 107830173 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 107830173 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 107830173 # number of demand (read+write) hits @@ -427,6 +438,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710 system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 9564.658425 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks. @@ -449,6 +461,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15181828 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 15181828 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 942334 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 942334 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits @@ -589,6 +602,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution @@ -621,6 +635,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 898500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 792 # Transaction distribution system.membus.trans_dist::ReadExReq 14548 # Transaction distribution system.membus.trans_dist::ReadExResp 14548 # Transaction distribution diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index 95dd6c0ff..329845e75 100644 --- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.122216 # Nu sim_ticks 122215823500 # Number of ticks simulated final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1393980 # Simulator instruction rate (inst/s) -host_op_rate 1394037 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 698723411 # Simulator tick rate (ticks/s) -host_mem_usage 370524 # Number of bytes of host memory used -host_seconds 174.91 # Real time elapsed on the host +host_inst_rate 2850562 # Simulator instruction rate (inst/s) +host_op_rate 2850680 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1428826010 # Simulator tick rate (ticks/s) +host_mem_usage 416224 # Number of bytes of host memory used +host_seconds 85.54 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 122215823500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 977685992 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 328674008 # Number of bytes read from this memory system.physmem.bytes_read::total 1306360000 # Number of bytes read from this memory @@ -37,8 +38,10 @@ system.physmem.bw_write::total 749543606 # Wr system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3438835373 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11438503207 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 122215823500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 443 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 122215823500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 244431648 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -97,6 +100,7 @@ system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 244431613 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 122215823500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 326641931 # Transaction distribution system.membus.trans_dist::ReadResp 326641931 # Transaction distribution system.membus.trans_dist::WriteReq 22901951 # Transaction distribution diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index aba308f8c..cac921e45 100644 --- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.168950 # Nu sim_ticks 168950040000 # Number of ticks simulated final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 769614 # Simulator instruction rate (inst/s) -host_op_rate 1355167 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 823011137 # Simulator tick rate (ticks/s) -host_mem_usage 396564 # Number of bytes of host memory used -host_seconds 205.28 # Real time elapsed on the host +host_inst_rate 1541579 # Simulator instruction rate (inst/s) +host_op_rate 2714473 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1648535817 # Simulator tick rate (ticks/s) +host_mem_usage 443832 # Number of bytes of host memory used +host_seconds 102.49 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 717246013 # Number of bytes read from this memory system.physmem.bytes_read::total 2458815325 # Number of bytes read from this memory @@ -35,9 +36,14 @@ system.physmem.bw_write::total 1439319677 # Wr system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 444 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 168950040000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 337900081 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -98,6 +104,7 @@ system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 278192465 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 308475611 # Transaction distribution system.membus.trans_dist::ReadResp 308475611 # Transaction distribution system.membus.trans_dist::WriteReq 31439752 # Transaction distribution diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt index 28924494c..f279a3d46 100644 --- a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.199332 # Nu sim_ticks 199332411500 # Number of ticks simulated final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1428598 # Simulator instruction rate (inst/s) -host_op_rate 1428597 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 714299076 # Simulator tick rate (ticks/s) -host_mem_usage 244476 # Number of bytes of host memory used -host_seconds 279.06 # Real time elapsed on the host +host_inst_rate 3079687 # Simulator instruction rate (inst/s) +host_op_rate 3079687 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1539844146 # Simulator tick rate (ticks/s) +host_mem_usage 290224 # Number of bytes of host memory used +host_seconds 129.45 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 199332411500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 1594658604 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 662449271 # Number of bytes read from this memory system.physmem.bytes_read::total 2257107875 # Number of bytes read from this memory @@ -35,6 +36,7 @@ system.physmem.bw_write::total 2470028804 # Wr system.physmem.bw_total::cpu.inst 7999996548 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5793368275 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13793364824 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 199332411500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -69,6 +71,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 199332411500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 398664824 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -127,6 +130,7 @@ system.cpu.op_class::MemWrite 73520764 18.44% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 398664651 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 199332411500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 493419140 # Transaction distribution system.membus.trans_dist::ReadResp 493419140 # Transaction distribution system.membus.trans_dist::WriteReq 73520729 # Transaction distribution diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 3f4ff4c5a..b9708b9b9 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000125 # Nu sim_ticks 124523000 # Number of ticks simulated final_tick 124523000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139641 # Simulator instruction rate (inst/s) -host_op_rate 139640 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15068671 # Simulator tick rate (ticks/s) -host_mem_usage 262532 # Number of bytes of host memory used -host_seconds 8.26 # Real time elapsed on the host +host_inst_rate 259079 # Simulator instruction rate (inst/s) +host_op_rate 259078 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27957290 # Simulator tick rate (ticks/s) +host_mem_usage 308636 # Number of bytes of host memory used +host_seconds 4.45 # Real time elapsed on the host sim_insts 1153943 # Number of instructions simulated sim_ops 1153943 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.inst 24000 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10880 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 5888 # Number of bytes read from this memory @@ -280,6 +281,7 @@ system.physmem_1.memoryStateTime::REF 3900000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 70805750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states system.cpu0.branchPred.lookups 98739 # Number of BP lookups system.cpu0.branchPred.condPredicted 94242 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 1562 # Number of conditional branches incorrect @@ -295,6 +297,7 @@ system.cpu0.branchPred.indirectMisses 7353 # Nu system.cpu0.branchPredindirectMispredicted 1035 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls +system.cpu0.pwrStateResidencyTicks::ON 124523000 # Cumulative time (in ticks) in various power states system.cpu0.numCycles 249047 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -583,6 +586,7 @@ system.cpu0.int_regfile_writes 371919 # nu system.cpu0.fp_regfile_reads 192 # number of floating regfile reads system.cpu0.misc_regfile_reads 269052 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 2 # number of replacements system.cpu0.dcache.tags.tagsinuse 142.724931 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 178078 # Total number of references to valid blocks. @@ -599,6 +603,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 143 system.cpu0.dcache.tags.occ_task_id_percent::1024 0.332031 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 717658 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 717658 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 90413 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 90413 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 87748 # number of WriteReq hits @@ -715,6 +720,7 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 43486.111111 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 43486.111111 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 43486.111111 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 43486.111111 # average overall mshr miss latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 394 # number of replacements system.cpu0.icache.tags.tagsinuse 248.905102 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 7041 # Total number of references to valid blocks. @@ -731,6 +737,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::2 192 system.cpu0.icache.tags.occ_task_id_percent::1024 0.587891 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 8647 # Number of tag accesses system.cpu0.icache.tags.data_accesses 8647 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states system.cpu0.icache.ReadReq_hits::cpu0.inst 7041 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 7041 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 7041 # number of demand (read+write) hits @@ -818,6 +825,7 @@ system.cpu1.branchPred.indirectLookups 62113 # Nu system.cpu1.branchPred.indirectHits 52196 # Number of indirect target hits. system.cpu1.branchPred.indirectMisses 9917 # Number of indirect misses. system.cpu1.branchPredindirectMispredicted 1232 # Number of mispredicted indirect branches. +system.cpu1.pwrStateResidencyTicks::ON 124523000 # Cumulative time (in ticks) in various power states system.cpu1.numCycles 193493 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -1107,6 +1115,7 @@ system.cpu1.int_regfile_writes 230976 # nu system.cpu1.fp_regfile_writes 64 # number of floating regfile writes system.cpu1.misc_regfile_reads 146210 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.tags.replacements 0 # number of replacements system.cpu1.dcache.tags.tagsinuse 26.604916 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 52484 # Total number of references to valid blocks. @@ -1123,6 +1132,7 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::2 4 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.060547 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 405985 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 405985 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.ReadReq_hits::cpu1.data 55568 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 55568 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 45140 # number of WriteReq hits @@ -1239,6 +1249,7 @@ system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13806.985294 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13806.985294 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13806.985294 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13806.985294 # average overall mshr miss latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states system.cpu1.icache.tags.replacements 579 # number of replacements system.cpu1.icache.tags.tagsinuse 98.515696 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 22662 # Total number of references to valid blocks. @@ -1255,6 +1266,7 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::2 8 system.cpu1.icache.tags.occ_task_id_percent::1024 0.261719 # Percentage of cache occupancy per task id system.cpu1.icache.tags.tag_accesses 24245 # Number of tag accesses system.cpu1.icache.tags.data_accesses 24245 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states system.cpu1.icache.ReadReq_hits::cpu1.inst 22662 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 22662 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 22662 # number of demand (read+write) hits @@ -1342,6 +1354,7 @@ system.cpu2.branchPred.indirectLookups 55606 # Nu system.cpu2.branchPred.indirectHits 44645 # Number of indirect target hits. system.cpu2.branchPred.indirectMisses 10961 # Number of indirect misses. system.cpu2.branchPredindirectMispredicted 1342 # Number of mispredicted indirect branches. +system.cpu2.pwrStateResidencyTicks::ON 124523000 # Cumulative time (in ticks) in various power states system.cpu2.numCycles 193104 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -1631,6 +1644,7 @@ system.cpu2.int_regfile_writes 194388 # nu system.cpu2.fp_regfile_writes 64 # number of floating regfile writes system.cpu2.misc_regfile_reads 119022 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes +system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states system.cpu2.dcache.tags.replacements 0 # number of replacements system.cpu2.dcache.tags.tagsinuse 25.641689 # Cycle average of tags in use system.cpu2.dcache.tags.total_refs 42500 # Total number of references to valid blocks. @@ -1647,6 +1661,7 @@ system.cpu2.dcache.tags.age_task_id_blocks_1024::2 4 system.cpu2.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id system.cpu2.dcache.tags.tag_accesses 336580 # Number of tag accesses system.cpu2.dcache.tags.data_accesses 336580 # Number of data accesses +system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states system.cpu2.dcache.ReadReq_hits::cpu2.data 48215 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 48215 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 35154 # number of WriteReq hits @@ -1763,6 +1778,7 @@ system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12723.880597 system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12723.880597 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12723.880597 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12723.880597 # average overall mshr miss latency +system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states system.cpu2.icache.tags.replacements 598 # number of replacements system.cpu2.icache.tags.tagsinuse 95.853337 # Cycle average of tags in use system.cpu2.icache.tags.total_refs 28564 # Total number of references to valid blocks. @@ -1779,6 +1795,7 @@ system.cpu2.icache.tags.age_task_id_blocks_1024::2 11 system.cpu2.icache.tags.occ_task_id_percent::1024 0.263672 # Percentage of cache occupancy per task id system.cpu2.icache.tags.tag_accesses 30149 # Number of tag accesses system.cpu2.icache.tags.data_accesses 30149 # Number of data accesses +system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states system.cpu2.icache.ReadReq_hits::cpu2.inst 28564 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 28564 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 28564 # number of demand (read+write) hits @@ -1866,6 +1883,7 @@ system.cpu3.branchPred.indirectLookups 53501 # Nu system.cpu3.branchPred.indirectHits 43109 # Number of indirect target hits. system.cpu3.branchPred.indirectMisses 10392 # Number of indirect misses. system.cpu3.branchPredindirectMispredicted 1225 # Number of mispredicted indirect branches. +system.cpu3.pwrStateResidencyTicks::ON 124523000 # Cumulative time (in ticks) in various power states system.cpu3.numCycles 192748 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -2153,6 +2171,7 @@ system.cpu3.int_regfile_writes 185063 # nu system.cpu3.fp_regfile_writes 64 # number of floating regfile writes system.cpu3.misc_regfile_reads 112177 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes +system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states system.cpu3.dcache.tags.replacements 0 # number of replacements system.cpu3.dcache.tags.tagsinuse 24.465247 # Cycle average of tags in use system.cpu3.dcache.tags.total_refs 40069 # Total number of references to valid blocks. @@ -2168,6 +2187,7 @@ system.cpu3.dcache.tags.age_task_id_blocks_1024::2 3 system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id system.cpu3.dcache.tags.tag_accesses 319388 # Number of tag accesses system.cpu3.dcache.tags.data_accesses 319388 # Number of data accesses +system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states system.cpu3.dcache.ReadReq_hits::cpu3.data 46353 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 46353 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 32769 # number of WriteReq hits @@ -2284,6 +2304,7 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12147.727273 system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12147.727273 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12147.727273 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12147.727273 # average overall mshr miss latency +system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states system.cpu3.icache.tags.replacements 563 # number of replacements system.cpu3.icache.tags.tagsinuse 93.764815 # Cycle average of tags in use system.cpu3.icache.tags.total_refs 29516 # Total number of references to valid blocks. @@ -2300,6 +2321,7 @@ system.cpu3.icache.tags.age_task_id_blocks_1024::2 10 system.cpu3.icache.tags.occ_task_id_percent::1024 0.269531 # Percentage of cache occupancy per task id system.cpu3.icache.tags.tag_accesses 31038 # Number of tag accesses system.cpu3.icache.tags.data_accesses 31038 # Number of data accesses +system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states system.cpu3.icache.ReadReq_hits::cpu3.inst 29516 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 29516 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 29516 # number of demand (read+write) hits @@ -2374,6 +2396,7 @@ system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 14331.669044 system.cpu3.icache.demand_avg_mshr_miss_latency::total 14331.669044 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 14331.669044 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::total 14331.669044 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 0 # number of replacements system.l2c.tags.tagsinuse 455.287968 # Cycle average of tags in use system.l2c.tags.total_refs 3075 # Total number of references to valid blocks. @@ -2406,6 +2429,7 @@ system.l2c.tags.age_task_id_blocks_1024::2 408 # system.l2c.tags.occ_task_id_percent::1024 0.008850 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 31874 # Number of tag accesses system.l2c.tags.data_accesses 31874 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits system.l2c.WritebackClean_hits::writebacks 709 # number of WritebackClean hits @@ -2803,6 +2827,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 582 # Transaction distribution system.membus.trans_dist::UpgradeReq 274 # Transaction distribution system.membus.trans_dist::ReadExReq 186 # Transaction distribution @@ -2833,6 +2858,7 @@ system.toL2Bus.snoop_filter.hit_multi_requests 3317 system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadResp 3517 # Transaction distribution system.toL2Bus.trans_dist::ReadRespWithInvalidate 9 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 8aafd14ee..42d05c9b0 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 856943 # Simulator instruction rate (inst/s) -host_op_rate 856930 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 110961270 # Simulator tick rate (ticks/s) -host_mem_usage 258436 # Number of bytes of host memory used -host_seconds 0.79 # Real time elapsed on the host +host_inst_rate 1934217 # Simulator instruction rate (inst/s) +host_op_rate 1934165 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 250446535 # Simulator tick rate (ticks/s) +host_mem_usage 303372 # Number of bytes of host memory used +host_seconds 0.35 # Real time elapsed on the host sim_insts 677333 # Number of instructions simulated sim_ops 677333 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory @@ -59,8 +60,10 @@ system.physmem.bw_total::cpu2.data 9486130 # To system.physmem.bw_total::cpu3.inst 729702 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls +system.cpu0.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states system.cpu0.numCycles 175415 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -119,6 +122,7 @@ system.cpu0.op_class::MemWrite 27806 15.85% 100.00% # Cl system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 175388 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 2 # number of replacements system.cpu0.dcache.tags.tagsinuse 150.745705 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 81882 # Total number of references to valid blocks. @@ -134,6 +138,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::1 149 system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 329804 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 329804 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits @@ -182,6 +187,7 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 215 # number of replacements system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. @@ -197,6 +203,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 199 system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits @@ -229,6 +236,7 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.writebacks::writebacks 215 # number of writebacks system.cpu0.icache.writebacks::total 215 # number of writebacks +system.cpu1.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states system.cpu1.numCycles 173297 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -287,6 +295,7 @@ system.cpu1.op_class::MemWrite 10149 6.06% 100.00% # Cl system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 167432 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.tags.replacements 0 # number of replacements system.cpu1.dcache.tags.tagsinuse 30.295170 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 21529 # Total number of references to valid blocks. @@ -301,6 +310,7 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::1 26 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 198211 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 198211 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.ReadReq_hits::cpu1.data 39152 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 39152 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 9968 # number of WriteReq hits @@ -347,6 +357,7 @@ system.cpu1.dcache.blocked::no_mshrs 0 # nu system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.cpu1.icache.tags.replacements 278 # number of replacements system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks. @@ -362,6 +373,7 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id system.cpu1.icache.tags.tag_accesses 167790 # Number of tag accesses system.cpu1.icache.tags.data_accesses 167790 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.cpu1.icache.ReadReq_hits::cpu1.inst 167074 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 167074 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 167074 # number of demand (read+write) hits @@ -394,6 +406,7 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.writebacks::writebacks 278 # number of writebacks system.cpu1.icache.writebacks::total 278 # number of writebacks +system.cpu2.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states system.cpu2.numCycles 173296 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -452,6 +465,7 @@ system.cpu2.op_class::MemWrite 17037 10.18% 100.00% # Cl system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::total 167367 # Class of executed instruction +system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.cpu2.dcache.tags.replacements 0 # number of replacements system.cpu2.dcache.tags.tagsinuse 29.575165 # Cycle average of tags in use system.cpu2.dcache.tags.total_refs 35457 # Total number of references to valid blocks. @@ -467,6 +481,7 @@ system.cpu2.dcache.tags.age_task_id_blocks_1024::1 26 system.cpu2.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id system.cpu2.dcache.tags.tag_accesses 239521 # Number of tag accesses system.cpu2.dcache.tags.data_accesses 239521 # Number of data accesses +system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.cpu2.dcache.ReadReq_hits::cpu2.data 42635 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 42635 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 16864 # number of WriteReq hits @@ -513,6 +528,7 @@ system.cpu2.dcache.blocked::no_mshrs 0 # nu system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.cpu2.icache.tags.replacements 278 # number of replacements system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks. @@ -528,6 +544,7 @@ system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id system.cpu2.icache.tags.tag_accesses 167725 # Number of tag accesses system.cpu2.icache.tags.data_accesses 167725 # Number of data accesses +system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.cpu2.icache.ReadReq_hits::cpu2.inst 167009 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 167009 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 167009 # number of demand (read+write) hits @@ -560,6 +577,7 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.writebacks::writebacks 278 # number of writebacks system.cpu2.icache.writebacks::total 278 # number of writebacks +system.cpu3.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states system.cpu3.numCycles 173297 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -618,6 +636,7 @@ system.cpu3.op_class::MemWrite 16166 9.66% 100.00% # Cl system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::total 167304 # Class of executed instruction +system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.cpu3.dcache.tags.replacements 0 # number of replacements system.cpu3.dcache.tags.tagsinuse 28.848199 # Cycle average of tags in use system.cpu3.dcache.tags.total_refs 33595 # Total number of references to valid blocks. @@ -632,6 +651,7 @@ system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 system.cpu3.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id system.cpu3.dcache.tags.tag_accesses 234241 # Number of tag accesses system.cpu3.dcache.tags.data_accesses 234241 # Number of data accesses +system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.cpu3.dcache.ReadReq_hits::cpu3.data 42185 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 42185 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 15991 # number of WriteReq hits @@ -678,6 +698,7 @@ system.cpu3.dcache.blocked::no_mshrs 0 # nu system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.cpu3.icache.tags.replacements 279 # number of replacements system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks. @@ -693,6 +714,7 @@ system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id system.cpu3.icache.tags.tag_accesses 167663 # Number of tag accesses system.cpu3.icache.tags.data_accesses 167663 # Number of data accesses +system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.cpu3.icache.ReadReq_hits::cpu3.inst 166945 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 166945 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 166945 # number of demand (read+write) hits @@ -725,6 +747,7 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.writebacks::writebacks 279 # number of writebacks system.cpu3.icache.writebacks::total 279 # number of writebacks +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 0 # number of replacements system.l2c.tags.tagsinuse 367.545675 # Cycle average of tags in use system.l2c.tags.total_refs 1716 # Total number of references to valid blocks. @@ -756,6 +779,7 @@ system.l2c.tags.age_task_id_blocks_1024::1 374 # system.l2c.tags.occ_task_id_percent::1024 0.006439 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 19424 # Number of tag accesses system.l2c.tags.data_accesses 19424 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits @@ -920,6 +944,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 423 # Transaction distribution system.membus.trans_dist::UpgradeReq 273 # Transaction distribution system.membus.trans_dist::UpgradeResp 80 # Transaction distribution @@ -947,6 +972,7 @@ system.toL2Bus.snoop_filter.hit_multi_requests 1709 system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution system.toL2Bus.trans_dist::WritebackClean 1050 # Transaction distribution diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index e6dfdce46..be0efa0c8 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000264 # Nu sim_ticks 264174500 # Number of ticks simulated final_tick 264174500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 587931 # Simulator instruction rate (inst/s) -host_op_rate 587915 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 234112560 # Simulator tick rate (ticks/s) -host_mem_usage 258432 # Number of bytes of host memory used -host_seconds 1.13 # Real time elapsed on the host +host_inst_rate 1178179 # Simulator instruction rate (inst/s) +host_op_rate 1178160 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 469155398 # Simulator tick rate (ticks/s) +host_mem_usage 303372 # Number of bytes of host memory used +host_seconds 0.56 # Real time elapsed on the host sim_insts 663394 # Number of instructions simulated sim_ops 663394 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory @@ -59,8 +60,10 @@ system.physmem.bw_total::cpu2.data 5572075 # To system.physmem.bw_total::cpu3.inst 969056 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3.data 3633962 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 138575071 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls +system.cpu0.pwrStateResidencyTicks::ON 264174500 # Cumulative time (in ticks) in various power states system.cpu0.numCycles 528349 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -119,6 +122,7 @@ system.cpu0.op_class::MemWrite 24963 15.77% 100.00% # Cl system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 158330 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 2 # number of replacements system.cpu0.dcache.tags.tagsinuse 144.970648 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 73336 # Total number of references to valid blocks. @@ -134,6 +138,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 295705 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 295705 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 48725 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 48725 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 24729 # number of WriteReq hits @@ -242,6 +247,7 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33036.827195 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33036.827195 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33036.827195 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33036.827195 # average overall mshr miss latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 215 # number of replacements system.cpu0.icache.tags.tagsinuse 211.220090 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 157864 # Total number of references to valid blocks. @@ -257,6 +263,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 158798 # Number of tag accesses system.cpu0.icache.tags.data_accesses 158798 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states system.cpu0.icache.ReadReq_hits::cpu0.inst 157864 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 157864 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 157864 # number of demand (read+write) hits @@ -325,6 +332,7 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42739.828694 system.cpu0.icache.demand_avg_mshr_miss_latency::total 42739.828694 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42739.828694 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 42739.828694 # average overall mshr miss latency +system.cpu1.pwrStateResidencyTicks::ON 264174500 # Cumulative time (in ticks) in various power states system.cpu1.numCycles 528348 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -383,6 +391,7 @@ system.cpu1.op_class::MemWrite 12537 7.37% 100.00% # Cl system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 170032 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states system.cpu1.dcache.tags.replacements 0 # number of replacements system.cpu1.dcache.tags.tagsinuse 26.444551 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 27473 # Total number of references to valid blocks. @@ -398,6 +407,7 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 215113 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 215113 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states system.cpu1.dcache.ReadReq_hits::cpu1.data 41008 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 41008 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 12359 # number of WriteReq hits @@ -504,6 +514,7 @@ system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12262.773723 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12262.773723 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12262.773723 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12262.773723 # average overall mshr miss latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states system.cpu1.icache.tags.replacements 280 # number of replacements system.cpu1.icache.tags.tagsinuse 66.843295 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 169667 # Total number of references to valid blocks. @@ -520,6 +531,7 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id system.cpu1.icache.tags.tag_accesses 170399 # Number of tag accesses system.cpu1.icache.tags.data_accesses 170399 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states system.cpu1.icache.ReadReq_hits::cpu1.inst 169667 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 169667 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 169667 # number of demand (read+write) hits @@ -588,6 +600,7 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14560.109290 system.cpu1.icache.demand_avg_mshr_miss_latency::total 14560.109290 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14560.109290 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 14560.109290 # average overall mshr miss latency +system.cpu2.pwrStateResidencyTicks::ON 264174500 # Cumulative time (in ticks) in various power states system.cpu2.numCycles 528349 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -646,6 +659,7 @@ system.cpu2.op_class::MemWrite 14183 8.56% 100.00% # Cl system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::total 165719 # Class of executed instruction +system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states system.cpu2.dcache.tags.replacements 0 # number of replacements system.cpu2.dcache.tags.tagsinuse 27.447331 # Cycle average of tags in use system.cpu2.dcache.tags.total_refs 30642 # Total number of references to valid blocks. @@ -661,6 +675,7 @@ system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id system.cpu2.dcache.tags.tag_accesses 220669 # Number of tag accesses system.cpu2.dcache.tags.data_accesses 220669 # Number of data accesses +system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states system.cpu2.dcache.ReadReq_hits::cpu2.data 40751 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 40751 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 14004 # number of WriteReq hits @@ -767,6 +782,7 @@ system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13405.109489 system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13405.109489 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13405.109489 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13405.109489 # average overall mshr miss latency +system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states system.cpu2.icache.tags.replacements 280 # number of replacements system.cpu2.icache.tags.tagsinuse 69.258301 # Cycle average of tags in use system.cpu2.icache.tags.total_refs 165354 # Total number of references to valid blocks. @@ -783,6 +799,7 @@ system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id system.cpu2.icache.tags.tag_accesses 166086 # Number of tag accesses system.cpu2.icache.tags.data_accesses 166086 # Number of data accesses +system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states system.cpu2.icache.ReadReq_hits::cpu2.inst 165354 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 165354 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 165354 # number of demand (read+write) hits @@ -851,6 +868,7 @@ system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21310.109290 system.cpu2.icache.demand_avg_mshr_miss_latency::total 21310.109290 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21310.109290 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::total 21310.109290 # average overall mshr miss latency +system.cpu3.pwrStateResidencyTicks::ON 264174500 # Cumulative time (in ticks) in various power states system.cpu3.numCycles 528348 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -909,6 +927,7 @@ system.cpu3.op_class::MemWrite 13113 7.74% 100.00% # Cl system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::total 169471 # Class of executed instruction +system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states system.cpu3.dcache.tags.replacements 0 # number of replacements system.cpu3.dcache.tags.tagsinuse 25.601960 # Cycle average of tags in use system.cpu3.dcache.tags.total_refs 28504 # Total number of references to valid blocks. @@ -924,6 +943,7 @@ system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id system.cpu3.dcache.tags.tag_accesses 218004 # Number of tag accesses system.cpu3.dcache.tags.data_accesses 218004 # Number of data accesses +system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states system.cpu3.dcache.ReadReq_hits::cpu3.data 41179 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 41179 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 12939 # number of WriteReq hits @@ -1030,6 +1050,7 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12324.218750 system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12324.218750 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12324.218750 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12324.218750 # average overall mshr miss latency +system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states system.cpu3.icache.tags.replacements 281 # number of replacements system.cpu3.icache.tags.tagsinuse 64.834449 # Cycle average of tags in use system.cpu3.icache.tags.total_refs 169105 # Total number of references to valid blocks. @@ -1046,6 +1067,7 @@ system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id system.cpu3.icache.tags.tag_accesses 169839 # Number of tag accesses system.cpu3.icache.tags.data_accesses 169839 # Number of data accesses +system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states system.cpu3.icache.ReadReq_hits::cpu3.inst 169105 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 169105 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 169105 # number of demand (read+write) hits @@ -1114,6 +1136,7 @@ system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13935.967302 system.cpu3.icache.demand_avg_mshr_miss_latency::total 13935.967302 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13935.967302 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::total 13935.967302 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 0 # number of replacements system.l2c.tags.tagsinuse 346.893205 # Cycle average of tags in use system.l2c.tags.total_refs 1714 # Total number of references to valid blocks. @@ -1145,6 +1168,7 @@ system.l2c.tags.age_task_id_blocks_1024::2 374 # system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 19677 # Number of tag accesses system.l2c.tags.data_accesses 19677 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits @@ -1546,6 +1570,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 430 # Transaction distribution system.membus.trans_dist::UpgradeReq 272 # Transaction distribution system.membus.trans_dist::ReadExReq 208 # Transaction distribution @@ -1576,6 +1601,7 @@ system.toL2Bus.snoop_filter.hit_multi_requests 1865 system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution system.toL2Bus.trans_dist::WritebackClean 1056 # Transaction distribution diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt index b7f3d9217..ceff215ec 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,12 @@ sim_seconds 0.010022 # Nu sim_ticks 10021833 # Number of ticks simulated final_tick 10021833 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 162199 # Simulator tick rate (ticks/s) -host_mem_usage 417868 # Number of bytes of host memory used -host_seconds 61.79 # Real time elapsed on the host +host_tick_rate 187111 # Simulator tick rate (ticks/s) +host_mem_usage 467772 # Number of bytes of host memory used +host_seconds 53.56 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39622272 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 39622272 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14218944 # Number of bytes written to this memory @@ -285,24 +286,34 @@ system.mem_ctrls_1.memoryStateTime::REF 334620 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 1 # Clock period in ticks +system.cpu0.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.cpu0.num_reads 99423 # number of read accesses completed system.cpu0.num_writes 55170 # number of write accesses completed +system.cpu1.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.cpu1.num_reads 98761 # number of read accesses completed system.cpu1.num_writes 54523 # number of write accesses completed +system.cpu2.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.cpu2.num_reads 100000 # number of read accesses completed system.cpu2.num_writes 55115 # number of write accesses completed +system.cpu3.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.cpu3.num_reads 99531 # number of read accesses completed system.cpu3.num_writes 55151 # number of write accesses completed +system.cpu4.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.cpu4.num_reads 99248 # number of read accesses completed system.cpu4.num_writes 55036 # number of write accesses completed +system.cpu5.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.cpu5.num_reads 99097 # number of read accesses completed system.cpu5.num_writes 55621 # number of write accesses completed +system.cpu6.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.cpu6.num_reads 99456 # number of read accesses completed system.cpu6.num_writes 55200 # number of write accesses completed +system.cpu7.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.cpu7.num_reads 99560 # number of read accesses completed system.cpu7.num_writes 55285 # number of write accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 32 # delay histogram for all message system.ruby.delayHist::max_bucket 319 # delay histogram for all message system.ruby.delayHist::samples 4985028 # delay histogram for all message @@ -341,6 +352,7 @@ system.ruby.miss_latency_hist_seqr::gmean 1585.472070 system.ruby.miss_latency_hist_seqr::stdev 1206.840773 system.ruby.miss_latency_hist_seqr | 164661 26.36% 26.36% | 154480 24.73% 51.08% | 150906 24.16% 75.24% | 129850 20.78% 96.02% | 24588 3.94% 99.96% | 246 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 624731 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 78237 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78237 # Number of cache demand accesses @@ -356,6 +368,8 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl1.L1Dcache.demand_hits 3 # Number of cache demand hits system.ruby.l1_cntrl1.L1Dcache.demand_misses 77673 # Number of cache demand misses system.ruby.l1_cntrl1.L1Dcache.demand_accesses 77676 # Number of cache demand accesses @@ -371,6 +385,8 @@ system.ruby.l1_cntrl1.prefetcher.hits 0 # nu system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l1_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl1.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl2.L1Dcache.demand_hits 1 # Number of cache demand hits system.ruby.l1_cntrl2.L1Dcache.demand_misses 78377 # Number of cache demand misses system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78378 # Number of cache demand accesses @@ -386,6 +402,8 @@ system.ruby.l1_cntrl2.prefetcher.hits 0 # nu system.ruby.l1_cntrl2.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl2.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl2.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l1_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl2.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl3.L1Dcache.demand_hits 1 # Number of cache demand hits system.ruby.l1_cntrl3.L1Dcache.demand_misses 78097 # Number of cache demand misses system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78098 # Number of cache demand accesses @@ -401,6 +419,8 @@ system.ruby.l1_cntrl3.prefetcher.hits 0 # nu system.ruby.l1_cntrl3.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl3.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl3.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l1_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl3.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl4.L1Dcache.demand_hits 1 # Number of cache demand hits system.ruby.l1_cntrl4.L1Dcache.demand_misses 78248 # Number of cache demand misses system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78249 # Number of cache demand accesses @@ -416,6 +436,8 @@ system.ruby.l1_cntrl4.prefetcher.hits 0 # nu system.ruby.l1_cntrl4.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl4.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl4.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l1_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl4.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl5.L1Dcache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl5.L1Dcache.demand_misses 77823 # Number of cache demand misses system.ruby.l1_cntrl5.L1Dcache.demand_accesses 77823 # Number of cache demand accesses @@ -431,6 +453,8 @@ system.ruby.l1_cntrl5.prefetcher.hits 0 # nu system.ruby.l1_cntrl5.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl5.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl5.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l1_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl5.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl6.L1Dcache.demand_hits 2 # Number of cache demand hits system.ruby.l1_cntrl6.L1Dcache.demand_misses 78233 # Number of cache demand misses system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78235 # Number of cache demand accesses @@ -446,6 +470,8 @@ system.ruby.l1_cntrl6.prefetcher.hits 0 # nu system.ruby.l1_cntrl6.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl6.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl6.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l1_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl6.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl7.L1Dcache.demand_hits 2 # Number of cache demand hits system.ruby.l1_cntrl7.L1Dcache.demand_misses 78071 # Number of cache demand misses system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78073 # Number of cache demand accesses @@ -461,11 +487,15 @@ system.ruby.l1_cntrl7.prefetcher.hits 0 # nu system.ruby.l1_cntrl7.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl7.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl7.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l1_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl7.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.l2_cntrl0.L2cache.demand_hits 35 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 624702 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 624737 # Number of cache demand accesses +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.l2_cntrl0.fully_busy_cycles 3 # cycles for which number of transistions == max transitions system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers00.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.network.routers00.percent_links_utilized 4.083916 system.ruby.network.routers00.msg_count.Control::0 78237 system.ruby.network.routers00.msg_count.Request_Control::2 76723 @@ -483,6 +513,7 @@ system.ruby.network.routers00.msg_bytes.Response_Control::2 620736 system.ruby.network.routers00.msg_bytes.Writeback_Data::0 1062792 system.ruby.network.routers00.msg_bytes.Writeback_Data::1 3769848 system.ruby.network.routers00.msg_bytes.Writeback_Control::0 210944 +system.ruby.network.routers01.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.network.routers01.percent_links_utilized 4.041267 system.ruby.network.routers01.msg_count.Control::0 77673 system.ruby.network.routers01.msg_count.Request_Control::2 76172 @@ -500,6 +531,7 @@ system.ruby.network.routers01.msg_bytes.Response_Control::2 616256 system.ruby.network.routers01.msg_bytes.Writeback_Data::0 1049904 system.ruby.network.routers01.msg_bytes.Writeback_Data::1 3712104 system.ruby.network.routers01.msg_bytes.Writeback_Control::0 206776 +system.ruby.network.routers02.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.network.routers02.percent_links_utilized 4.088773 system.ruby.network.routers02.msg_count.Control::0 78377 system.ruby.network.routers02.msg_count.Request_Control::2 76766 @@ -517,6 +549,7 @@ system.ruby.network.routers02.msg_bytes.Response_Control::2 622120 system.ruby.network.routers02.msg_bytes.Writeback_Data::0 1071288 system.ruby.network.routers02.msg_bytes.Writeback_Data::1 3762576 system.ruby.network.routers02.msg_bytes.Writeback_Control::0 210960 +system.ruby.network.routers03.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.network.routers03.percent_links_utilized 4.065454 system.ruby.network.routers03.msg_count.Control::0 78097 system.ruby.network.routers03.msg_count.Request_Control::2 76565 @@ -534,6 +567,7 @@ system.ruby.network.routers03.msg_bytes.Response_Control::2 619600 system.ruby.network.routers03.msg_bytes.Writeback_Data::0 1051848 system.ruby.network.routers03.msg_bytes.Writeback_Data::1 3735792 system.ruby.network.routers03.msg_bytes.Writeback_Control::0 209704 +system.ruby.network.routers04.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.network.routers04.percent_links_utilized 4.076620 system.ruby.network.routers04.msg_count.Control::0 78248 system.ruby.network.routers04.msg_count.Request_Control::2 76737 @@ -551,6 +585,7 @@ system.ruby.network.routers04.msg_bytes.Response_Control::2 620976 system.ruby.network.routers04.msg_bytes.Writeback_Data::0 1053288 system.ruby.network.routers04.msg_bytes.Writeback_Data::1 3754656 system.ruby.network.routers04.msg_bytes.Writeback_Control::0 211016 +system.ruby.network.routers05.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.network.routers05.percent_links_utilized 4.060382 system.ruby.network.routers05.msg_count.Control::0 77823 system.ruby.network.routers05.msg_count.Request_Control::2 76343 @@ -568,6 +603,7 @@ system.ruby.network.routers05.msg_bytes.Response_Control::2 617624 system.ruby.network.routers05.msg_bytes.Writeback_Data::0 1064016 system.ruby.network.routers05.msg_bytes.Writeback_Data::1 3742560 system.ruby.network.routers05.msg_bytes.Writeback_Control::0 206368 +system.ruby.network.routers06.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.network.routers06.percent_links_utilized 4.079877 system.ruby.network.routers06.msg_count.Control::0 78233 system.ruby.network.routers06.msg_count.Request_Control::2 76715 @@ -585,6 +621,7 @@ system.ruby.network.routers06.msg_bytes.Response_Control::2 620720 system.ruby.network.routers06.msg_bytes.Writeback_Data::0 1060488 system.ruby.network.routers06.msg_bytes.Writeback_Data::1 3756816 system.ruby.network.routers06.msg_bytes.Writeback_Control::0 211304 +system.ruby.network.routers07.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.network.routers07.percent_links_utilized 4.070416 system.ruby.network.routers07.msg_count.Control::0 78071 system.ruby.network.routers07.msg_count.Request_Control::2 76560 @@ -602,6 +639,7 @@ system.ruby.network.routers07.msg_bytes.Response_Control::2 619304 system.ruby.network.routers07.msg_bytes.Writeback_Data::0 1061712 system.ruby.network.routers07.msg_bytes.Writeback_Data::1 3745296 system.ruby.network.routers07.msg_bytes.Writeback_Control::0 208768 +system.ruby.network.routers08.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.network.routers08.percent_links_utilized 55.328626 system.ruby.network.routers08.msg_count.Control::0 1243860 system.ruby.network.routers08.msg_count.Request_Control::2 608794 @@ -619,6 +657,7 @@ system.ruby.network.routers08.msg_bytes.Response_Control::2 4957328 system.ruby.network.routers08.msg_bytes.Writeback_Data::0 8475336 system.ruby.network.routers08.msg_bytes.Writeback_Data::1 29979648 system.ruby.network.routers08.msg_bytes.Writeback_Control::0 1675840 +system.ruby.network.routers09.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.network.routers09.percent_links_utilized 22.966170 system.ruby.network.routers09.msg_count.Control::0 619101 system.ruby.network.routers09.msg_count.Response_Data::1 841268 @@ -626,6 +665,7 @@ system.ruby.network.routers09.msg_count.Response_Control::1 1016015 system.ruby.network.routers09.msg_bytes.Control::0 4952808 system.ruby.network.routers09.msg_bytes.Response_Data::1 60571296 system.ruby.network.routers09.msg_bytes.Response_Control::1 8128120 +system.ruby.network.routers10.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.network.routers10.percent_links_utilized 11.092782 system.ruby.network.routers10.msg_count.Control::0 1243860 system.ruby.network.routers10.msg_count.Request_Control::2 612581 @@ -643,6 +683,7 @@ system.ruby.network.routers10.msg_bytes.Response_Control::2 4957336 system.ruby.network.routers10.msg_bytes.Writeback_Data::0 8475336 system.ruby.network.routers10.msg_bytes.Writeback_Data::1 29979648 system.ruby.network.routers10.msg_bytes.Writeback_Control::0 1675840 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 3731580 system.ruby.network.msg_count.Request_Control 1833956 system.ruby.network.msg_count.Response_Data 4399208 @@ -655,6 +696,7 @@ system.ruby.network.msg_byte.Response_Data 316742976 system.ruby.network.msg_byte.Response_Control 51743816 system.ruby.network.msg_byte.Writeback_Data 115364952 system.ruby.network.msg_byte.Writeback_Control 5027520 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states system.ruby.network.routers00.throttle0.link_utilization 4.100802 system.ruby.network.routers00.throttle0.msg_count.Request_Control::2 76723 system.ruby.network.routers00.throttle0.msg_count.Response_Data::1 78233 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt index b8eac504c..d708f1911 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,12 @@ sim_seconds 0.007437 # Nu sim_ticks 7436579 # Number of ticks simulated final_tick 7436579 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 74529 # Simulator tick rate (ticks/s) -host_mem_usage 420508 # Number of bytes of host memory used -host_seconds 99.78 # Real time elapsed on the host +host_tick_rate 82813 # Simulator tick rate (ticks/s) +host_mem_usage 469820 # Number of bytes of host memory used +host_seconds 89.80 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39411840 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 39411840 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14207680 # Number of bytes written to this memory @@ -285,24 +286,34 @@ system.mem_ctrls_1.memoryStateTime::REF 248300 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 1 # Clock period in ticks +system.cpu0.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.cpu0.num_reads 99533 # number of read accesses completed system.cpu0.num_writes 55594 # number of write accesses completed +system.cpu1.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.cpu1.num_reads 99397 # number of read accesses completed system.cpu1.num_writes 55662 # number of write accesses completed +system.cpu2.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.cpu2.num_reads 99976 # number of read accesses completed system.cpu2.num_writes 55789 # number of write accesses completed +system.cpu3.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.cpu3.num_reads 99413 # number of read accesses completed system.cpu3.num_writes 55629 # number of write accesses completed +system.cpu4.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.cpu4.num_reads 99342 # number of read accesses completed system.cpu4.num_writes 55223 # number of write accesses completed +system.cpu5.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.cpu5.num_reads 100000 # number of read accesses completed system.cpu5.num_writes 55687 # number of write accesses completed +system.cpu6.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.cpu6.num_reads 99314 # number of read accesses completed system.cpu6.num_writes 55046 # number of write accesses completed +system.cpu7.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.cpu7.num_reads 99437 # number of read accesses completed system.cpu7.num_writes 55128 # number of write accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 2 system.ruby.outstanding_req_hist_seqr::max_bucket 19 system.ruby.outstanding_req_hist_seqr::samples 627422 @@ -334,58 +345,77 @@ system.ruby.miss_latency_hist_seqr::gmean 960.502379 system.ruby.miss_latency_hist_seqr::stdev 1631.335046 system.ruby.miss_latency_hist_seqr | 473768 75.54% 75.54% | 104367 16.64% 92.18% | 33291 5.31% 97.49% | 11023 1.76% 99.25% | 3421 0.55% 99.80% | 948 0.15% 99.95% | 243 0.04% 99.99% | 74 0.01% 100.00% | 12 0.00% 100.00% | 6 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 627153 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 22 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 78254 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78276 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl1.L1Dcache.demand_hits 9 # Number of cache demand hits system.ruby.l1_cntrl1.L1Dcache.demand_misses 78372 # Number of cache demand misses system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78381 # Number of cache demand accesses system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl1.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl2.L1Dcache.demand_hits 19 # Number of cache demand hits system.ruby.l1_cntrl2.L1Dcache.demand_misses 78709 # Number of cache demand misses system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78728 # Number of cache demand accesses system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl2.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl3.L1Dcache.demand_hits 17 # Number of cache demand hits system.ruby.l1_cntrl3.L1Dcache.demand_misses 78281 # Number of cache demand misses system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78298 # Number of cache demand accesses system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl3.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl4.L1Dcache.demand_hits 23 # Number of cache demand hits system.ruby.l1_cntrl4.L1Dcache.demand_misses 78290 # Number of cache demand misses system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78313 # Number of cache demand accesses system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl4.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl5.L1Dcache.demand_hits 11 # Number of cache demand hits system.ruby.l1_cntrl5.L1Dcache.demand_misses 78570 # Number of cache demand misses system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78581 # Number of cache demand accesses system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl5.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl6.L1Dcache.demand_hits 23 # Number of cache demand hits system.ruby.l1_cntrl6.L1Dcache.demand_misses 78475 # Number of cache demand misses system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78498 # Number of cache demand accesses system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl6.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl7.L1Dcache.demand_hits 17 # Number of cache demand hits system.ruby.l1_cntrl7.L1Dcache.demand_misses 78224 # Number of cache demand misses system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78241 # Number of cache demand accesses system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl7.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.l2_cntrl0.L2cache.demand_hits 4647 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 622511 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 627158 # Number of cache demand accesses +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers00.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.network.routers00.percent_links_utilized 5.789295 system.ruby.network.routers00.msg_count.Request_Control::0 78254 system.ruby.network.routers00.msg_count.Response_Data::2 76885 @@ -407,6 +437,7 @@ system.ruby.network.routers00.msg_bytes.Writeback_Control::0 1251264 system.ruby.network.routers00.msg_bytes.Forwarded_Control::0 6984 system.ruby.network.routers00.msg_bytes.Invalidate_Control::0 1912 system.ruby.network.routers00.msg_bytes.Unblock_Control::2 632264 +system.ruby.network.routers01.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.network.routers01.percent_links_utilized 5.798120 system.ruby.network.routers01.msg_count.Request_Control::0 78372 system.ruby.network.routers01.msg_count.Response_Data::2 76915 @@ -428,6 +459,7 @@ system.ruby.network.routers01.msg_bytes.Writeback_Control::0 1253096 system.ruby.network.routers01.msg_bytes.Forwarded_Control::0 7176 system.ruby.network.routers01.msg_bytes.Invalidate_Control::0 1824 system.ruby.network.routers01.msg_bytes.Unblock_Control::2 633568 +system.ruby.network.routers02.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.network.routers02.percent_links_utilized 5.822099 system.ruby.network.routers02.msg_count.Request_Control::0 78709 system.ruby.network.routers02.msg_count.Response_Data::2 77304 @@ -449,6 +481,7 @@ system.ruby.network.routers02.msg_bytes.Writeback_Control::0 1258632 system.ruby.network.routers02.msg_bytes.Forwarded_Control::0 6656 system.ruby.network.routers02.msg_bytes.Invalidate_Control::0 1920 system.ruby.network.routers02.msg_bytes.Unblock_Control::2 635792 +system.ruby.network.routers03.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.network.routers03.percent_links_utilized 5.790606 system.ruby.network.routers03.msg_count.Request_Control::0 78281 system.ruby.network.routers03.msg_count.Response_Data::2 76851 @@ -470,6 +503,7 @@ system.ruby.network.routers03.msg_bytes.Writeback_Control::0 1251680 system.ruby.network.routers03.msg_bytes.Forwarded_Control::0 6880 system.ruby.network.routers03.msg_bytes.Invalidate_Control::0 1792 system.ruby.network.routers03.msg_bytes.Unblock_Control::2 632632 +system.ruby.network.routers04.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.network.routers04.percent_links_utilized 5.791907 system.ruby.network.routers04.msg_count.Request_Control::0 78290 system.ruby.network.routers04.msg_count.Response_Data::2 76878 @@ -491,6 +525,7 @@ system.ruby.network.routers04.msg_bytes.Writeback_Control::0 1251960 system.ruby.network.routers04.msg_bytes.Forwarded_Control::0 6824 system.ruby.network.routers04.msg_bytes.Invalidate_Control::0 1720 system.ruby.network.routers04.msg_bytes.Unblock_Control::2 632680 +system.ruby.network.routers05.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.network.routers05.percent_links_utilized 5.809960 system.ruby.network.routers05.msg_count.Request_Control::0 78570 system.ruby.network.routers05.msg_count.Response_Data::2 77119 @@ -512,6 +547,7 @@ system.ruby.network.routers05.msg_bytes.Writeback_Control::0 1256320 system.ruby.network.routers05.msg_bytes.Forwarded_Control::0 6280 system.ruby.network.routers05.msg_bytes.Invalidate_Control::0 2112 system.ruby.network.routers05.msg_bytes.Unblock_Control::2 634616 +system.ruby.network.routers06.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.network.routers06.percent_links_utilized 5.804383 system.ruby.network.routers06.msg_count.Request_Control::0 78475 system.ruby.network.routers06.msg_count.Response_Data::2 77081 @@ -533,6 +569,7 @@ system.ruby.network.routers06.msg_bytes.Writeback_Control::0 1254880 system.ruby.network.routers06.msg_bytes.Forwarded_Control::0 6584 system.ruby.network.routers06.msg_bytes.Invalidate_Control::0 1776 system.ruby.network.routers06.msg_bytes.Unblock_Control::2 634088 +system.ruby.network.routers07.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.network.routers07.percent_links_utilized 5.784636 system.ruby.network.routers07.msg_count.Request_Control::0 78224 system.ruby.network.routers07.msg_count.Response_Data::2 76772 @@ -554,6 +591,7 @@ system.ruby.network.routers07.msg_bytes.Writeback_Control::0 1251024 system.ruby.network.routers07.msg_bytes.Forwarded_Control::0 6224 system.ruby.network.routers07.msg_bytes.Invalidate_Control::0 1808 system.ruby.network.routers07.msg_bytes.Unblock_Control::2 632056 +system.ruby.network.routers08.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.network.routers08.percent_links_utilized 76.954202 system.ruby.network.routers08.msg_count.Request_Control::0 627158 system.ruby.network.routers08.msg_count.Request_Control::1 615810 @@ -577,6 +615,7 @@ system.ruby.network.routers08.msg_bytes.Writeback_Control::1 3551992 system.ruby.network.routers08.msg_bytes.Forwarded_Control::0 53608 system.ruby.network.routers08.msg_bytes.Invalidate_Control::0 14816 system.ruby.network.routers08.msg_bytes.Unblock_Control::2 9993920 +system.ruby.network.routers09.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.network.routers09.percent_links_utilized 30.981463 system.ruby.network.routers09.msg_count.Request_Control::1 615810 system.ruby.network.routers09.msg_count.Response_Data::2 615809 @@ -588,6 +627,7 @@ system.ruby.network.routers09.msg_bytes.Response_Data::2 44338248 system.ruby.network.routers09.msg_bytes.Writeback_Data::2 15983640 system.ruby.network.routers09.msg_bytes.Writeback_Control::1 3552064 system.ruby.network.routers09.msg_bytes.Unblock_Control::2 4926320 +system.ruby.network.routers10.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.network.routers10.percent_links_utilized 15.432642 system.ruby.network.routers10.msg_count.Request_Control::0 627158 system.ruby.network.routers10.msg_count.Request_Control::1 615810 @@ -613,6 +653,7 @@ system.ruby.network.routers10.msg_bytes.Writeback_Control::1 3551992 system.ruby.network.routers10.msg_bytes.Forwarded_Control::0 53608 system.ruby.network.routers10.msg_bytes.Invalidate_Control::0 14864 system.ruby.network.routers10.msg_bytes.Unblock_Control::2 9993920 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Request_Control 3728921 system.ruby.network.msg_count.Response_Data 3694837 system.ruby.network.msg_count.ResponseL2hit_Data 13941 @@ -633,6 +674,7 @@ system.ruby.network.msg_byte.Writeback_Control 40742344 system.ruby.network.msg_byte.Forwarded_Control 160824 system.ruby.network.msg_byte.Invalidate_Control 44544 system.ruby.network.msg_byte.Unblock_Control 29981856 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states system.ruby.network.routers00.throttle0.link_utilization 5.270831 system.ruby.network.routers00.throttle0.msg_count.Response_Data::2 76885 system.ruby.network.routers00.throttle0.msg_count.ResponseL2hit_Data::2 587 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index d149e53a7..3b8234590 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,12 @@ sim_seconds 0.006099 # Nu sim_ticks 6099346 # Number of ticks simulated final_tick 6099346 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 81040 # Simulator tick rate (ticks/s) -host_mem_usage 421980 # Number of bytes of host memory used -host_seconds 75.26 # Real time elapsed on the host +host_tick_rate 91228 # Simulator tick rate (ticks/s) +host_mem_usage 473028 # Number of bytes of host memory used +host_seconds 66.86 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39765376 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 39765376 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 19455168 # Number of bytes written to this memory @@ -289,24 +290,34 @@ system.mem_ctrls_1.memoryStateTime::REF 203580 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 1 # Clock period in ticks +system.cpu0.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.cpu0.num_reads 99731 # number of read accesses completed system.cpu0.num_writes 55103 # number of write accesses completed +system.cpu1.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.cpu1.num_reads 99468 # number of read accesses completed system.cpu1.num_writes 55228 # number of write accesses completed +system.cpu2.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.cpu2.num_reads 100000 # number of read accesses completed system.cpu2.num_writes 55518 # number of write accesses completed +system.cpu3.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.cpu3.num_reads 99696 # number of read accesses completed system.cpu3.num_writes 55953 # number of write accesses completed +system.cpu4.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.cpu4.num_reads 98851 # number of read accesses completed system.cpu4.num_writes 55227 # number of write accesses completed +system.cpu5.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.cpu5.num_reads 98859 # number of read accesses completed system.cpu5.num_writes 55313 # number of write accesses completed +system.cpu6.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.cpu6.num_reads 99329 # number of read accesses completed system.cpu6.num_writes 55461 # number of write accesses completed +system.cpu7.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.cpu7.num_reads 99244 # number of read accesses completed system.cpu7.num_writes 55110 # number of write accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 2 system.ruby.outstanding_req_hist_seqr::max_bucket 19 system.ruby.outstanding_req_hist_seqr::samples 626716 @@ -341,12 +352,15 @@ system.ruby.miss_latency_hist_seqr | 107181 17.19% 17.19% | system.ruby.miss_latency_hist_seqr::total 623627 system.ruby.L1Cache.incomplete_times_seqr 2150 system.ruby.Directory.incomplete_times_seqr 621474 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 20 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 78435 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78455 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.fully_busy_cycles 12 # cycles for which number of transistions == max transitions system.ruby.l1_cntrl1.L1Dcache.demand_hits 26 # Number of cache demand hits system.ruby.l1_cntrl1.L1Dcache.demand_misses 78293 # Number of cache demand misses @@ -354,6 +368,8 @@ system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78319 system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl1.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl1.fully_busy_cycles 8 # cycles for which number of transistions == max transitions system.ruby.l1_cntrl2.L1Dcache.demand_hits 21 # Number of cache demand hits system.ruby.l1_cntrl2.L1Dcache.demand_misses 78389 # Number of cache demand misses @@ -361,6 +377,8 @@ system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78410 system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl2.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl2.fully_busy_cycles 6 # cycles for which number of transistions == max transitions system.ruby.l1_cntrl3.L1Dcache.demand_hits 20 # Number of cache demand hits system.ruby.l1_cntrl3.L1Dcache.demand_misses 78553 # Number of cache demand misses @@ -368,6 +386,8 @@ system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78573 system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl3.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl3.fully_busy_cycles 6 # cycles for which number of transistions == max transitions system.ruby.l1_cntrl4.L1Dcache.demand_hits 24 # Number of cache demand hits system.ruby.l1_cntrl4.L1Dcache.demand_misses 78168 # Number of cache demand misses @@ -375,6 +395,8 @@ system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78192 system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl4.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl4.fully_busy_cycles 12 # cycles for which number of transistions == max transitions system.ruby.l1_cntrl5.L1Dcache.demand_hits 31 # Number of cache demand hits system.ruby.l1_cntrl5.L1Dcache.demand_misses 78418 # Number of cache demand misses @@ -382,6 +404,8 @@ system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78449 system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl5.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl5.fully_busy_cycles 8 # cycles for which number of transistions == max transitions system.ruby.l1_cntrl6.L1Dcache.demand_hits 32 # Number of cache demand hits system.ruby.l1_cntrl6.L1Dcache.demand_misses 78003 # Number of cache demand misses @@ -389,6 +413,8 @@ system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78035 system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl6.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl6.fully_busy_cycles 7 # cycles for which number of transistions == max transitions system.ruby.l1_cntrl7.L1Dcache.demand_hits 24 # Number of cache demand hits system.ruby.l1_cntrl7.L1Dcache.demand_misses 78156 # Number of cache demand misses @@ -396,11 +422,15 @@ system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78180 system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl7.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl7.fully_busy_cycles 7 # cycles for which number of transistions == max transitions system.ruby.l2_cntrl0.L2cache.demand_hits 1651 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 624764 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 626415 # Number of cache demand accesses +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers00.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.network.routers00.percent_links_utilized 11.233413 system.ruby.network.routers00.msg_count.Request_Control::1 78435 system.ruby.network.routers00.msg_count.Response_Data::4 81785 @@ -418,6 +448,7 @@ system.ruby.network.routers00.msg_bytes.Response_Control::4 976 system.ruby.network.routers00.msg_bytes.Writeback_Data::4 7742088 system.ruby.network.routers00.msg_bytes.Broadcast_Control::1 5011320 system.ruby.network.routers00.msg_bytes.Persistent_Control::3 2626808 +system.ruby.network.routers01.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.network.routers01.percent_links_utilized 11.216772 system.ruby.network.routers01.msg_count.Request_Control::1 78293 system.ruby.network.routers01.msg_count.Response_Data::4 81463 @@ -435,6 +466,7 @@ system.ruby.network.routers01.msg_bytes.Response_Control::4 808 system.ruby.network.routers01.msg_bytes.Writeback_Data::4 7733808 system.ruby.network.routers01.msg_bytes.Broadcast_Control::1 5011320 system.ruby.network.routers01.msg_bytes.Persistent_Control::3 2627240 +system.ruby.network.routers02.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.network.routers02.percent_links_utilized 11.235213 system.ruby.network.routers02.msg_count.Request_Control::1 78389 system.ruby.network.routers02.msg_count.Response_Data::4 81630 @@ -452,6 +484,7 @@ system.ruby.network.routers02.msg_bytes.Response_Control::4 1072 system.ruby.network.routers02.msg_bytes.Writeback_Data::4 7755264 system.ruby.network.routers02.msg_bytes.Broadcast_Control::1 5011320 system.ruby.network.routers02.msg_bytes.Persistent_Control::3 2629448 +system.ruby.network.routers03.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.network.routers03.percent_links_utilized 11.269241 system.ruby.network.routers03.msg_count.Request_Control::1 78553 system.ruby.network.routers03.msg_count.Response_Data::4 82027 @@ -469,6 +502,7 @@ system.ruby.network.routers03.msg_bytes.Response_Control::4 1016 system.ruby.network.routers03.msg_bytes.Writeback_Data::4 7790256 system.ruby.network.routers03.msg_bytes.Broadcast_Control::1 5011320 system.ruby.network.routers03.msg_bytes.Persistent_Control::3 2630952 +system.ruby.network.routers04.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.network.routers04.percent_links_utilized 11.220096 system.ruby.network.routers04.msg_count.Request_Control::1 78168 system.ruby.network.routers04.msg_count.Response_Data::4 81565 @@ -486,6 +520,7 @@ system.ruby.network.routers04.msg_bytes.Response_Control::4 1192 system.ruby.network.routers04.msg_bytes.Writeback_Data::4 7733736 system.ruby.network.routers04.msg_bytes.Broadcast_Control::1 5011320 system.ruby.network.routers04.msg_bytes.Persistent_Control::3 2627576 +system.ruby.network.routers05.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.network.routers05.percent_links_utilized 11.228085 system.ruby.network.routers05.msg_count.Request_Control::1 78418 system.ruby.network.routers05.msg_count.Response_Data::4 81763 @@ -505,6 +540,7 @@ system.ruby.network.routers05.msg_bytes.Writeback_Data::4 7733016 system.ruby.network.routers05.msg_bytes.Writeback_Control::4 16 system.ruby.network.routers05.msg_bytes.Broadcast_Control::1 5011320 system.ruby.network.routers05.msg_bytes.Persistent_Control::3 2627096 +system.ruby.network.routers06.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.network.routers06.percent_links_utilized 11.201853 system.ruby.network.routers06.msg_count.Request_Control::1 78003 system.ruby.network.routers06.msg_count.Response_Data::4 81441 @@ -522,6 +558,7 @@ system.ruby.network.routers06.msg_bytes.Response_Control::4 1064 system.ruby.network.routers06.msg_bytes.Writeback_Data::4 7705872 system.ruby.network.routers06.msg_bytes.Broadcast_Control::1 5011320 system.ruby.network.routers06.msg_bytes.Persistent_Control::3 2626824 +system.ruby.network.routers07.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.network.routers07.percent_links_utilized 11.201172 system.ruby.network.routers07.msg_count.Request_Control::1 78156 system.ruby.network.routers07.msg_count.Response_Data::4 81436 @@ -539,6 +576,7 @@ system.ruby.network.routers07.msg_bytes.Response_Control::4 1168 system.ruby.network.routers07.msg_bytes.Writeback_Data::4 7704936 system.ruby.network.routers07.msg_bytes.Broadcast_Control::1 5011320 system.ruby.network.routers07.msg_bytes.Persistent_Control::3 2625032 +system.ruby.network.routers08.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.network.routers08.percent_links_utilized 42.049426 system.ruby.network.routers08.msg_count.Request_Control::1 626415 system.ruby.network.routers08.msg_count.Request_Control::2 624764 @@ -556,6 +594,7 @@ system.ruby.network.routers08.msg_bytes.Response_Control::4 8336 system.ruby.network.routers08.msg_bytes.Writeback_Data::4 65968992 system.ruby.network.routers08.msg_bytes.Writeback_Control::4 2544984 system.ruby.network.routers08.msg_bytes.Persistent_Control::3 2335664 +system.ruby.network.routers09.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.network.routers09.percent_links_utilized 39.472142 system.ruby.network.routers09.msg_count.Request_Control::2 624764 system.ruby.network.routers09.msg_count.Response_Data::4 635954 @@ -571,6 +610,7 @@ system.ruby.network.routers09.msg_bytes.Response_Control::4 72 system.ruby.network.routers09.msg_bytes.Writeback_Data::4 21367296 system.ruby.network.routers09.msg_bytes.Writeback_Control::4 2545000 system.ruby.network.routers09.msg_bytes.Persistent_Control::3 2335664 +system.ruby.network.routers10.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.network.routers10.percent_links_utilized 19.510945 system.ruby.network.routers10.msg_count.Request_Control::1 626415 system.ruby.network.routers10.msg_count.Request_Control::2 624764 @@ -592,6 +632,7 @@ system.ruby.network.routers10.msg_bytes.Writeback_Data::4 74617632 system.ruby.network.routers10.msg_bytes.Writeback_Control::4 2545000 system.ruby.network.routers10.msg_bytes.Broadcast_Control::1 35079240 system.ruby.network.routers10.msg_bytes.Persistent_Control::3 21020976 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Request_Control 3753537 system.ruby.network.msg_count.Response_Data 1956209 system.ruby.network.msg_count.ResponseL2hit_Data 5226 @@ -610,6 +651,7 @@ system.ruby.network.msg_byte.Writeback_Data 223852896 system.ruby.network.msg_byte.Writeback_Control 7635000 system.ruby.network.msg_byte.Broadcast_Control 75169800 system.ruby.network.msg_byte.Persistent_Control 46713280 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states system.ruby.network.routers00.throttle0.link_utilization 13.880578 system.ruby.network.routers00.throttle0.msg_count.Response_Data::4 79888 system.ruby.network.routers00.throttle0.msg_count.ResponseL2hit_Data::4 199 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index 2391b011d..9f9e8dc83 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,12 @@ sim_seconds 0.004723 # Nu sim_ticks 4722948 # Number of ticks simulated final_tick 4722948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 53510 # Simulator tick rate (ticks/s) -host_mem_usage 421672 # Number of bytes of host memory used -host_seconds 88.26 # Real time elapsed on the host +host_tick_rate 61998 # Simulator tick rate (ticks/s) +host_mem_usage 471708 # Number of bytes of host memory used +host_seconds 76.18 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 38973248 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 38973248 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14131456 # Number of bytes written to this memory @@ -274,24 +275,34 @@ system.mem_ctrls_1.memoryStateTime::REF 157560 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 1 # Clock period in ticks +system.cpu0.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.cpu0.num_reads 99221 # number of read accesses completed system.cpu0.num_writes 55233 # number of write accesses completed +system.cpu1.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.cpu1.num_reads 99634 # number of read accesses completed system.cpu1.num_writes 55697 # number of write accesses completed +system.cpu2.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.cpu2.num_reads 99089 # number of read accesses completed system.cpu2.num_writes 55519 # number of write accesses completed +system.cpu3.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.cpu3.num_reads 100000 # number of read accesses completed system.cpu3.num_writes 55486 # number of write accesses completed +system.cpu4.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.cpu4.num_reads 99397 # number of read accesses completed system.cpu4.num_writes 55450 # number of write accesses completed +system.cpu5.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.cpu5.num_reads 99838 # number of read accesses completed system.cpu5.num_writes 55386 # number of write accesses completed +system.cpu6.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.cpu6.num_reads 99890 # number of read accesses completed system.cpu6.num_writes 55532 # number of write accesses completed +system.cpu7.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.cpu7.num_reads 99124 # number of read accesses completed system.cpu7.num_writes 55205 # number of write accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 2 system.ruby.outstanding_req_hist_seqr::max_bucket 19 system.ruby.outstanding_req_hist_seqr::samples 630039 @@ -329,6 +340,7 @@ system.ruby.Directory.incomplete_times_seqr 176578 system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 10 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 78639 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78649 # Number of cache demand accesses @@ -338,6 +350,8 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 system.ruby.l1_cntrl0.L2cache.demand_hits 70 # Number of cache demand hits system.ruby.l1_cntrl0.L2cache.demand_misses 78569 # Number of cache demand misses system.ruby.l1_cntrl0.L2cache.demand_accesses 78639 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.fully_busy_cycles 19 # cycles for which number of transistions == max transitions system.ruby.l1_cntrl1.L1Dcache.demand_hits 13 # Number of cache demand hits system.ruby.l1_cntrl1.L1Dcache.demand_misses 78770 # Number of cache demand misses @@ -348,6 +362,8 @@ system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 system.ruby.l1_cntrl1.L2cache.demand_hits 66 # Number of cache demand hits system.ruby.l1_cntrl1.L2cache.demand_misses 78704 # Number of cache demand misses system.ruby.l1_cntrl1.L2cache.demand_accesses 78770 # Number of cache demand accesses +system.ruby.l1_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl1.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl1.fully_busy_cycles 15 # cycles for which number of transistions == max transitions system.ruby.l1_cntrl2.L1Dcache.demand_hits 19 # Number of cache demand hits system.ruby.l1_cntrl2.L1Dcache.demand_misses 78920 # Number of cache demand misses @@ -358,6 +374,8 @@ system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 system.ruby.l1_cntrl2.L2cache.demand_hits 68 # Number of cache demand hits system.ruby.l1_cntrl2.L2cache.demand_misses 78852 # Number of cache demand misses system.ruby.l1_cntrl2.L2cache.demand_accesses 78920 # Number of cache demand accesses +system.ruby.l1_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl2.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl2.fully_busy_cycles 16 # cycles for which number of transistions == max transitions system.ruby.l1_cntrl3.L1Dcache.demand_hits 12 # Number of cache demand hits system.ruby.l1_cntrl3.L1Dcache.demand_misses 78627 # Number of cache demand misses @@ -368,6 +386,8 @@ system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 system.ruby.l1_cntrl3.L2cache.demand_hits 62 # Number of cache demand hits system.ruby.l1_cntrl3.L2cache.demand_misses 78565 # Number of cache demand misses system.ruby.l1_cntrl3.L2cache.demand_accesses 78627 # Number of cache demand accesses +system.ruby.l1_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl3.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl3.fully_busy_cycles 14 # cycles for which number of transistions == max transitions system.ruby.l1_cntrl4.L1Dcache.demand_hits 19 # Number of cache demand hits system.ruby.l1_cntrl4.L1Dcache.demand_misses 78575 # Number of cache demand misses @@ -378,6 +398,8 @@ system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 system.ruby.l1_cntrl4.L2cache.demand_hits 52 # Number of cache demand hits system.ruby.l1_cntrl4.L2cache.demand_misses 78523 # Number of cache demand misses system.ruby.l1_cntrl4.L2cache.demand_accesses 78575 # Number of cache demand accesses +system.ruby.l1_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl4.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl4.fully_busy_cycles 17 # cycles for which number of transistions == max transitions system.ruby.l1_cntrl5.L1Dcache.demand_hits 19 # Number of cache demand hits system.ruby.l1_cntrl5.L1Dcache.demand_misses 78844 # Number of cache demand misses @@ -388,6 +410,8 @@ system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 system.ruby.l1_cntrl5.L2cache.demand_hits 64 # Number of cache demand hits system.ruby.l1_cntrl5.L2cache.demand_misses 78780 # Number of cache demand misses system.ruby.l1_cntrl5.L2cache.demand_accesses 78844 # Number of cache demand accesses +system.ruby.l1_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl5.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl5.fully_busy_cycles 18 # cycles for which number of transistions == max transitions system.ruby.l1_cntrl6.L1Dcache.demand_hits 20 # Number of cache demand hits system.ruby.l1_cntrl6.L1Dcache.demand_misses 78880 # Number of cache demand misses @@ -398,6 +422,8 @@ system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 system.ruby.l1_cntrl6.L2cache.demand_hits 70 # Number of cache demand hits system.ruby.l1_cntrl6.L2cache.demand_misses 78810 # Number of cache demand misses system.ruby.l1_cntrl6.L2cache.demand_accesses 78880 # Number of cache demand accesses +system.ruby.l1_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl6.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl6.fully_busy_cycles 21 # cycles for which number of transistions == max transitions system.ruby.l1_cntrl7.L1Dcache.demand_hits 14 # Number of cache demand hits system.ruby.l1_cntrl7.L1Dcache.demand_misses 78558 # Number of cache demand misses @@ -408,8 +434,11 @@ system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 system.ruby.l1_cntrl7.L2cache.demand_hits 84 # Number of cache demand hits system.ruby.l1_cntrl7.L2cache.demand_misses 78474 # Number of cache demand misses system.ruby.l1_cntrl7.L2cache.demand_accesses 78558 # Number of cache demand accesses +system.ruby.l1_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl7.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl7.fully_busy_cycles 9 # cycles for which number of transistions == max transitions system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 15.732330 system.ruby.network.routers0.msg_count.Request_Control::2 78569 system.ruby.network.routers0.msg_count.Request_Control::3 120 @@ -431,6 +460,7 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::3 591832 system.ruby.network.routers0.msg_bytes.Writeback_Control::5 371040 system.ruby.network.routers0.msg_bytes.Broadcast_Control::3 4398864 system.ruby.network.routers0.msg_bytes.Unblock_Control::5 630016 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 15.771198 system.ruby.network.routers1.msg_count.Request_Control::2 78704 system.ruby.network.routers1.msg_count.Request_Control::3 125 @@ -452,6 +482,7 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::3 594424 system.ruby.network.routers1.msg_bytes.Writeback_Control::5 370416 system.ruby.network.routers1.msg_bytes.Broadcast_Control::3 4397704 system.ruby.network.routers1.msg_bytes.Unblock_Control::5 631088 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 15.778059 system.ruby.network.routers2.msg_count.Request_Control::2 78852 system.ruby.network.routers2.msg_count.Request_Control::3 126 @@ -473,6 +504,7 @@ system.ruby.network.routers2.msg_bytes.Writeback_Control::3 595120 system.ruby.network.routers2.msg_bytes.Writeback_Control::5 372080 system.ruby.network.routers2.msg_bytes.Broadcast_Control::3 4396552 system.ruby.network.routers2.msg_bytes.Unblock_Control::5 632224 +system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.ruby.network.routers3.percent_links_utilized 15.737131 system.ruby.network.routers3.msg_count.Request_Control::2 78565 system.ruby.network.routers3.msg_count.Request_Control::3 100 @@ -494,6 +526,7 @@ system.ruby.network.routers3.msg_bytes.Writeback_Control::3 592080 system.ruby.network.routers3.msg_bytes.Writeback_Control::5 370360 system.ruby.network.routers3.msg_bytes.Broadcast_Control::3 4398936 system.ruby.network.routers3.msg_bytes.Unblock_Control::5 629800 +system.ruby.network.routers4.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.ruby.network.routers4.percent_links_utilized 15.736924 system.ruby.network.routers4.msg_count.Request_Control::2 78523 system.ruby.network.routers4.msg_count.Request_Control::3 120 @@ -515,6 +548,7 @@ system.ruby.network.routers4.msg_bytes.Writeback_Control::3 592808 system.ruby.network.routers4.msg_bytes.Writeback_Control::5 371136 system.ruby.network.routers4.msg_bytes.Broadcast_Control::3 4399192 system.ruby.network.routers4.msg_bytes.Unblock_Control::5 629616 +system.ruby.network.routers5.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.ruby.network.routers5.percent_links_utilized 15.767186 system.ruby.network.routers5.msg_count.Request_Control::2 78780 system.ruby.network.routers5.msg_count.Request_Control::3 112 @@ -536,6 +570,7 @@ system.ruby.network.routers5.msg_bytes.Writeback_Control::3 594832 system.ruby.network.routers5.msg_bytes.Writeback_Control::5 371664 system.ruby.network.routers5.msg_bytes.Broadcast_Control::3 4397184 system.ruby.network.routers5.msg_bytes.Unblock_Control::5 631696 +system.ruby.network.routers6.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.ruby.network.routers6.percent_links_utilized 15.767377 system.ruby.network.routers6.msg_count.Request_Control::2 78810 system.ruby.network.routers6.msg_count.Request_Control::3 118 @@ -557,6 +592,7 @@ system.ruby.network.routers6.msg_bytes.Writeback_Control::3 594976 system.ruby.network.routers6.msg_bytes.Writeback_Control::5 373176 system.ruby.network.routers6.msg_bytes.Broadcast_Control::3 4397000 system.ruby.network.routers6.msg_bytes.Unblock_Control::5 631896 +system.ruby.network.routers7.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.ruby.network.routers7.percent_links_utilized 15.733208 system.ruby.network.routers7.msg_count.Request_Control::2 78474 system.ruby.network.routers7.msg_count.Request_Control::3 141 @@ -578,6 +614,7 @@ system.ruby.network.routers7.msg_bytes.Writeback_Control::3 592208 system.ruby.network.routers7.msg_bytes.Writeback_Control::5 370352 system.ruby.network.routers7.msg_bytes.Broadcast_Control::3 4399536 system.ruby.network.routers7.msg_bytes.Unblock_Control::5 629248 +system.ruby.network.routers8.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.ruby.network.routers8.percent_links_utilized 57.778553 system.ruby.network.routers8.msg_count.Request_Control::2 629277 system.ruby.network.routers8.msg_count.Request_Control::3 962 @@ -597,6 +634,7 @@ system.ruby.network.routers8.msg_bytes.Writeback_Control::3 4748288 system.ruby.network.routers8.msg_bytes.Writeback_Control::5 2970224 system.ruby.network.routers8.msg_bytes.Broadcast_Control::3 5026424 system.ruby.network.routers8.msg_bytes.Unblock_Control::5 5045576 +system.ruby.network.routers9.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.ruby.network.routers9.percent_links_utilized 22.639639 system.ruby.network.routers9.msg_count.Request_Control::2 629277 system.ruby.network.routers9.msg_count.Request_Control::3 962 @@ -618,6 +656,7 @@ system.ruby.network.routers9.msg_bytes.Writeback_Control::3 4748280 system.ruby.network.routers9.msg_bytes.Writeback_Control::5 2970224 system.ruby.network.routers9.msg_bytes.Broadcast_Control::3 35184968 system.ruby.network.routers9.msg_bytes.Unblock_Control::5 5045576 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Request_Control 1890717 system.ruby.network.msg_count.Response_Data 1887741 system.ruby.network.msg_count.Response_Control 13136322 @@ -632,6 +671,7 @@ system.ruby.network.msg_byte.Writeback_Data 47693808 system.ruby.network.msg_byte.Writeback_Control 37400648 system.ruby.network.msg_byte.Broadcast_Control 75396360 system.ruby.network.msg_byte.Unblock_Control 15136736 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.throttle0.link_utilization 19.878030 system.ruby.network.routers0.throttle0.msg_count.Request_Control::3 120 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 78565 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index 87ea51c89..ab74f2592 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -4,11 +4,12 @@ sim_seconds 0.007679 # Nu sim_ticks 7678882 # Number of ticks simulated final_tick 7678882 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 120821 # Simulator tick rate (ticks/s) -host_mem_usage 418672 # Number of bytes of host memory used -host_seconds 63.56 # Real time elapsed on the host +host_tick_rate 172641 # Simulator tick rate (ticks/s) +host_mem_usage 467856 # Number of bytes of host memory used +host_seconds 44.48 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39687936 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 39687936 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 39686592 # Number of bytes written to this memory @@ -265,24 +266,34 @@ system.mem_ctrls_1.memoryStateTime::REF 256360 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 1 # Clock period in ticks +system.cpu0.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.cpu0.num_reads 99754 # number of read accesses completed system.cpu0.num_writes 55550 # number of write accesses completed +system.cpu1.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.cpu1.num_reads 99722 # number of read accesses completed system.cpu1.num_writes 55422 # number of write accesses completed +system.cpu2.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.cpu2.num_reads 99859 # number of read accesses completed system.cpu2.num_writes 56114 # number of write accesses completed +system.cpu3.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.cpu3.num_reads 99399 # number of read accesses completed system.cpu3.num_writes 55238 # number of write accesses completed +system.cpu4.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.cpu4.num_reads 99564 # number of read accesses completed system.cpu4.num_writes 55685 # number of write accesses completed +system.cpu5.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.cpu5.num_reads 100000 # number of read accesses completed system.cpu5.num_writes 55705 # number of write accesses completed +system.cpu6.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.cpu6.num_reads 99381 # number of read accesses completed system.cpu6.num_writes 55293 # number of write accesses completed +system.cpu7.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.cpu7.num_reads 99930 # number of read accesses completed system.cpu7.num_writes 55169 # number of write accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 32 # delay histogram for all message system.ruby.delayHist::max_bucket 319 # delay histogram for all message system.ruby.delayHist::samples 1260795 # delay histogram for all message @@ -316,31 +327,49 @@ system.ruby.miss_latency_hist_seqr | 77 0.01% 0.01% | system.ruby.miss_latency_hist_seqr::total 628456 system.ruby.L1Cache.incomplete_times_seqr 8337 system.ruby.Directory.incomplete_times_seqr 620116 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 78526 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 78526 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl1.cacheMemory.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl1.cacheMemory.demand_misses 78474 # Number of cache demand misses system.ruby.l1_cntrl1.cacheMemory.demand_accesses 78474 # Number of cache demand accesses +system.ruby.l1_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl1.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl2.cacheMemory.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl2.cacheMemory.demand_misses 78844 # Number of cache demand misses system.ruby.l1_cntrl2.cacheMemory.demand_accesses 78844 # Number of cache demand accesses +system.ruby.l1_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl2.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl3.cacheMemory.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl3.cacheMemory.demand_misses 78573 # Number of cache demand misses system.ruby.l1_cntrl3.cacheMemory.demand_accesses 78573 # Number of cache demand accesses +system.ruby.l1_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl3.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl4.cacheMemory.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl4.cacheMemory.demand_misses 78575 # Number of cache demand misses system.ruby.l1_cntrl4.cacheMemory.demand_accesses 78575 # Number of cache demand accesses +system.ruby.l1_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl4.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl5.cacheMemory.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl5.cacheMemory.demand_misses 78529 # Number of cache demand misses system.ruby.l1_cntrl5.cacheMemory.demand_accesses 78529 # Number of cache demand accesses +system.ruby.l1_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl5.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl6.cacheMemory.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl6.cacheMemory.demand_misses 78440 # Number of cache demand misses system.ruby.l1_cntrl6.cacheMemory.demand_accesses 78440 # Number of cache demand accesses +system.ruby.l1_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl6.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl7.cacheMemory.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl7.cacheMemory.demand_misses 78515 # Number of cache demand misses system.ruby.l1_cntrl7.cacheMemory.demand_accesses 78515 # Number of cache demand accesses +system.ruby.l1_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl7.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 5.128100 system.ruby.network.routers0.msg_count.Control::2 78526 system.ruby.network.routers0.msg_count.Data::2 77981 @@ -350,6 +379,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 628208 system.ruby.network.routers0.msg_bytes.Data::2 5614632 system.ruby.network.routers0.msg_bytes.Response_Data::4 5726232 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 631912 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 5.125007 system.ruby.network.routers1.msg_count.Control::2 78474 system.ruby.network.routers1.msg_count.Data::2 77933 @@ -359,6 +389,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 627792 system.ruby.network.routers1.msg_bytes.Data::2 5611176 system.ruby.network.routers1.msg_bytes.Response_Data::4 5722848 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 631568 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 5.149581 system.ruby.network.routers2.msg_count.Control::2 78844 system.ruby.network.routers2.msg_count.Data::2 78287 @@ -368,6 +399,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 630752 system.ruby.network.routers2.msg_bytes.Data::2 5636664 system.ruby.network.routers2.msg_bytes.Response_Data::4 5751720 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 634632 +system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.ruby.network.routers3.percent_links_utilized 5.132918 system.ruby.network.routers3.msg_count.Control::2 78573 system.ruby.network.routers3.msg_count.Data::2 78015 @@ -377,6 +409,7 @@ system.ruby.network.routers3.msg_bytes.Control::2 628584 system.ruby.network.routers3.msg_bytes.Data::2 5617080 system.ruby.network.routers3.msg_bytes.Response_Data::4 5734440 system.ruby.network.routers3.msg_bytes.Writeback_Control::3 632720 +system.ruby.network.routers4.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.ruby.network.routers4.percent_links_utilized 5.131284 system.ruby.network.routers4.msg_count.Control::2 78575 system.ruby.network.routers4.msg_count.Data::2 78023 @@ -386,6 +419,7 @@ system.ruby.network.routers4.msg_bytes.Control::2 628600 system.ruby.network.routers4.msg_bytes.Data::2 5617656 system.ruby.network.routers4.msg_bytes.Response_Data::4 5730264 system.ruby.network.routers4.msg_bytes.Writeback_Control::3 632288 +system.ruby.network.routers5.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.ruby.network.routers5.percent_links_utilized 5.129285 system.ruby.network.routers5.msg_count.Control::2 78525 system.ruby.network.routers5.msg_count.Data::2 77953 @@ -395,6 +429,7 @@ system.ruby.network.routers5.msg_bytes.Control::2 628200 system.ruby.network.routers5.msg_bytes.Data::2 5612616 system.ruby.network.routers5.msg_bytes.Response_Data::4 5730912 system.ruby.network.routers5.msg_bytes.Writeback_Control::3 632192 +system.ruby.network.routers6.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.ruby.network.routers6.percent_links_utilized 5.123636 system.ruby.network.routers6.msg_count.Control::2 78440 system.ruby.network.routers6.msg_count.Data::2 77859 @@ -404,6 +439,7 @@ system.ruby.network.routers6.msg_bytes.Control::2 627520 system.ruby.network.routers6.msg_bytes.Data::2 5605848 system.ruby.network.routers6.msg_bytes.Response_Data::4 5725152 system.ruby.network.routers6.msg_bytes.Writeback_Control::3 631496 +system.ruby.network.routers7.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.ruby.network.routers7.percent_links_utilized 5.127709 system.ruby.network.routers7.msg_count.Control::2 78515 system.ruby.network.routers7.msg_count.Data::2 77951 @@ -413,6 +449,7 @@ system.ruby.network.routers7.msg_bytes.Control::2 628120 system.ruby.network.routers7.msg_bytes.Data::2 5612472 system.ruby.network.routers7.msg_bytes.Response_Data::4 5727528 system.ruby.network.routers7.msg_bytes.Writeback_Control::3 631904 +system.ruby.network.routers8.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.ruby.network.routers8.percent_links_utilized 40.558977 system.ruby.network.routers8.msg_count.Control::2 628472 system.ruby.network.routers8.msg_count.Data::2 624002 @@ -422,6 +459,7 @@ system.ruby.network.routers8.msg_bytes.Control::2 5027776 system.ruby.network.routers8.msg_bytes.Data::2 44928144 system.ruby.network.routers8.msg_bytes.Response_Data::4 44648640 system.ruby.network.routers8.msg_bytes.Writeback_Control::3 5058712 +system.ruby.network.routers9.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.ruby.network.routers9.percent_links_utilized 9.067388 system.ruby.network.routers9.msg_count.Control::2 628472 system.ruby.network.routers9.msg_count.Data::2 624002 @@ -431,6 +469,7 @@ system.ruby.network.routers9.msg_bytes.Control::2 5027776 system.ruby.network.routers9.msg_bytes.Data::2 44928144 system.ruby.network.routers9.msg_bytes.Response_Data::4 45248832 system.ruby.network.routers9.msg_bytes.Writeback_Control::3 5058712 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 1885416 system.ruby.network.msg_count.Data 1872006 system.ruby.network.msg_count.Response_Data 1885369 @@ -439,6 +478,7 @@ system.ruby.network.msg_byte.Control 15083328 system.ruby.network.msg_byte.Data 134784432 system.ruby.network.msg_byte.Response_Data 135746568 system.ruby.network.msg_byte.Writeback_Control 15176136 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.throttle0.link_utilization 5.115953 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 78523 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 78989 diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt index f24c7c909..863fa9c63 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -4,11 +4,12 @@ sim_seconds 0.000502 # Nu sim_ticks 501584000 # Number of ticks simulated final_tick 501584000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 82658959 # Simulator tick rate (ticks/s) -host_mem_usage 231728 # Number of bytes of host memory used -host_seconds 6.07 # Real time elapsed on the host +host_tick_rate 130273139 # Simulator tick rate (ticks/s) +host_mem_usage 277304 # Number of bytes of host memory used +host_seconds 3.85 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0 77173 # Number of bytes read from this memory system.physmem.bytes_read::cpu1 79943 # Number of bytes read from this memory system.physmem.bytes_read::cpu2 80467 # Number of bytes read from this memory @@ -76,9 +77,12 @@ system.physmem.bw_total::cpu5 173414622 # To system.physmem.bw_total::cpu6 169419280 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu7 163206960 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2146087196 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu0.num_reads 99682 # number of read accesses completed system.cpu0.num_writes 55240 # number of write accesses completed +system.cpu0.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu0.l1c.tags.replacements 22392 # number of replacements system.cpu0.l1c.tags.tagsinuse 393.390751 # Cycle average of tags in use system.cpu0.l1c.tags.total_refs 13565 # Total number of references to valid blocks. @@ -94,6 +98,7 @@ system.cpu0.l1c.tags.age_task_id_blocks_1024::1 10 system.cpu0.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id system.cpu0.l1c.tags.tag_accesses 339133 # Number of tag accesses system.cpu0.l1c.tags.data_accesses 339133 # Number of data accesses +system.cpu0.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu0.l1c.ReadReq_hits::cpu0 8847 # number of ReadReq hits system.cpu0.l1c.ReadReq_hits::total 8847 # number of ReadReq hits system.cpu0.l1c.WriteReq_hits::cpu0 1120 # number of WriteReq hits @@ -196,8 +201,10 @@ system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 76081.849950 system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76081.849950 # average ReadReq mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 49324.292359 # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 49324.292359 # average overall mshr uncacheable latency +system.cpu1.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu1.num_reads 99541 # number of read accesses completed system.cpu1.num_writes 55028 # number of write accesses completed +system.cpu1.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu1.l1c.tags.replacements 22314 # number of replacements system.cpu1.l1c.tags.tagsinuse 393.210618 # Cycle average of tags in use system.cpu1.l1c.tags.total_refs 13573 # Total number of references to valid blocks. @@ -213,6 +220,7 @@ system.cpu1.l1c.tags.age_task_id_blocks_1024::1 9 system.cpu1.l1c.tags.occ_task_id_percent::1024 0.796875 # Percentage of cache occupancy per task id system.cpu1.l1c.tags.tag_accesses 338638 # Number of tag accesses system.cpu1.l1c.tags.data_accesses 338638 # Number of data accesses +system.cpu1.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu1.l1c.ReadReq_hits::cpu1 8704 # number of ReadReq hits system.cpu1.l1c.ReadReq_hits::total 8704 # number of ReadReq hits system.cpu1.l1c.WriteReq_hits::cpu1 1149 # number of WriteReq hits @@ -315,8 +323,10 @@ system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 76088.624594 system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76088.624594 # average ReadReq mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 48764.745176 # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 48764.745176 # average overall mshr uncacheable latency +system.cpu2.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu2.num_reads 99993 # number of read accesses completed system.cpu2.num_writes 55211 # number of write accesses completed +system.cpu2.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu2.l1c.tags.replacements 22333 # number of replacements system.cpu2.l1c.tags.tagsinuse 392.533782 # Cycle average of tags in use system.cpu2.l1c.tags.total_refs 13552 # Total number of references to valid blocks. @@ -332,6 +342,7 @@ system.cpu2.l1c.tags.age_task_id_blocks_1024::1 5 system.cpu2.l1c.tags.occ_task_id_percent::1024 0.828125 # Percentage of cache occupancy per task id system.cpu2.l1c.tags.tag_accesses 338842 # Number of tag accesses system.cpu2.l1c.tags.data_accesses 338842 # Number of data accesses +system.cpu2.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu2.l1c.ReadReq_hits::cpu2 8700 # number of ReadReq hits system.cpu2.l1c.ReadReq_hits::total 8700 # number of ReadReq hits system.cpu2.l1c.WriteReq_hits::cpu2 1131 # number of WriteReq hits @@ -434,8 +445,10 @@ system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 75960.835082 system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75960.835082 # average ReadReq mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 49072.651579 # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 49072.651579 # average overall mshr uncacheable latency +system.cpu3.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu3.num_reads 99085 # number of read accesses completed system.cpu3.num_writes 55606 # number of write accesses completed +system.cpu3.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu3.l1c.tags.replacements 22528 # number of replacements system.cpu3.l1c.tags.tagsinuse 391.624901 # Cycle average of tags in use system.cpu3.l1c.tags.total_refs 13493 # Total number of references to valid blocks. @@ -451,6 +464,7 @@ system.cpu3.l1c.tags.age_task_id_blocks_1024::1 7 system.cpu3.l1c.tags.occ_task_id_percent::1024 0.744141 # Percentage of cache occupancy per task id system.cpu3.l1c.tags.tag_accesses 339302 # Number of tag accesses system.cpu3.l1c.tags.data_accesses 339302 # Number of data accesses +system.cpu3.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu3.l1c.ReadReq_hits::cpu3 8770 # number of ReadReq hits system.cpu3.l1c.ReadReq_hits::total 8770 # number of ReadReq hits system.cpu3.l1c.WriteReq_hits::cpu3 1134 # number of WriteReq hits @@ -553,8 +567,10 @@ system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 76104.905863 system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76104.905863 # average ReadReq mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 48577.705245 # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 48577.705245 # average overall mshr uncacheable latency +system.cpu4.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu4.num_reads 99978 # number of read accesses completed system.cpu4.num_writes 55474 # number of write accesses completed +system.cpu4.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu4.l1c.tags.replacements 22223 # number of replacements system.cpu4.l1c.tags.tagsinuse 391.899958 # Cycle average of tags in use system.cpu4.l1c.tags.total_refs 13858 # Total number of references to valid blocks. @@ -570,6 +586,7 @@ system.cpu4.l1c.tags.age_task_id_blocks_1024::1 9 system.cpu4.l1c.tags.occ_task_id_percent::1024 0.791016 # Percentage of cache occupancy per task id system.cpu4.l1c.tags.tag_accesses 340964 # Number of tag accesses system.cpu4.l1c.tags.data_accesses 340964 # Number of data accesses +system.cpu4.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu4.l1c.ReadReq_hits::cpu4 8890 # number of ReadReq hits system.cpu4.l1c.ReadReq_hits::total 8890 # number of ReadReq hits system.cpu4.l1c.WriteReq_hits::cpu4 1171 # number of WriteReq hits @@ -672,8 +689,10 @@ system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 76323.866340 system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76323.866340 # average ReadReq mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 48895.366625 # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 48895.366625 # average overall mshr uncacheable latency +system.cpu5.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu5.num_reads 100000 # number of read accesses completed system.cpu5.num_writes 55110 # number of write accesses completed +system.cpu5.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu5.l1c.tags.replacements 22358 # number of replacements system.cpu5.l1c.tags.tagsinuse 391.816568 # Cycle average of tags in use system.cpu5.l1c.tags.total_refs 13630 # Total number of references to valid blocks. @@ -689,6 +708,7 @@ system.cpu5.l1c.tags.age_task_id_blocks_1024::1 5 system.cpu5.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id system.cpu5.l1c.tags.tag_accesses 340100 # Number of tag accesses system.cpu5.l1c.tags.data_accesses 340100 # Number of data accesses +system.cpu5.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu5.l1c.ReadReq_hits::cpu5 8821 # number of ReadReq hits system.cpu5.l1c.ReadReq_hits::total 8821 # number of ReadReq hits system.cpu5.l1c.WriteReq_hits::cpu5 1107 # number of WriteReq hits @@ -791,8 +811,10 @@ system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 76212.561495 system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76212.561495 # average ReadReq mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 49035.755617 # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 49035.755617 # average overall mshr uncacheable latency +system.cpu6.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu6.num_reads 99774 # number of read accesses completed system.cpu6.num_writes 55185 # number of write accesses completed +system.cpu6.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu6.l1c.tags.replacements 22542 # number of replacements system.cpu6.l1c.tags.tagsinuse 391.726459 # Cycle average of tags in use system.cpu6.l1c.tags.total_refs 13419 # Total number of references to valid blocks. @@ -808,6 +830,7 @@ system.cpu6.l1c.tags.age_task_id_blocks_1024::1 12 system.cpu6.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id system.cpu6.l1c.tags.tag_accesses 339673 # Number of tag accesses system.cpu6.l1c.tags.data_accesses 339673 # Number of data accesses +system.cpu6.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu6.l1c.ReadReq_hits::cpu6 8710 # number of ReadReq hits system.cpu6.l1c.ReadReq_hits::total 8710 # number of ReadReq hits system.cpu6.l1c.WriteReq_hits::cpu6 1147 # number of WriteReq hits @@ -910,8 +933,10 @@ system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 76198.851155 system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76198.851155 # average ReadReq mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 48973.532326 # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 48973.532326 # average overall mshr uncacheable latency +system.cpu7.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu7.num_reads 99703 # number of read accesses completed system.cpu7.num_writes 55656 # number of write accesses completed +system.cpu7.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu7.l1c.tags.replacements 22447 # number of replacements system.cpu7.l1c.tags.tagsinuse 392.675740 # Cycle average of tags in use system.cpu7.l1c.tags.total_refs 13542 # Total number of references to valid blocks. @@ -927,6 +952,7 @@ system.cpu7.l1c.tags.age_task_id_blocks_1024::1 7 system.cpu7.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id system.cpu7.l1c.tags.tag_accesses 338950 # Number of tag accesses system.cpu7.l1c.tags.data_accesses 338950 # Number of data accesses +system.cpu7.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.cpu7.l1c.ReadReq_hits::cpu7 8682 # number of ReadReq hits system.cpu7.l1c.ReadReq_hits::total 8682 # number of ReadReq hits system.cpu7.l1c.WriteReq_hits::cpu7 1173 # number of WriteReq hits @@ -1029,6 +1055,7 @@ system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 76167.022510 system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76167.022510 # average ReadReq mshr uncacheable latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 49319.237441 # average overall mshr uncacheable latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 49319.237441 # average overall mshr uncacheable latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 13600 # number of replacements system.l2c.tags.tagsinuse 785.994901 # Cycle average of tags in use system.l2c.tags.total_refs 164496 # Total number of references to valid blocks. @@ -1060,6 +1087,7 @@ system.l2c.tags.age_task_id_blocks_1024::1 140 # system.l2c.tags.occ_task_id_percent::1024 0.772461 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 2102241 # Number of tag accesses system.l2c.tags.data_accesses 2102241 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.l2c.WritebackDirty_hits::writebacks 77703 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 77703 # number of WritebackDirty hits system.l2c.UpgradeReq_hits::cpu0 290 # number of UpgradeReq hits @@ -1635,6 +1663,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 78845 # Transaction distribution system.membus.trans_dist::ReadResp 84388 # Transaction distribution system.membus.trans_dist::WriteReq 43678 # Transaction distribution @@ -1670,6 +1699,7 @@ system.toL2Bus.snoop_filter.hit_multi_requests 334405 system.toL2Bus.snoop_filter.tot_snoops 12239 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 5805 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 6434 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 78849 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 372013 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 43679 # Transaction distribution diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index b05d177c6..e55bb9c63 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -4,11 +4,12 @@ sim_seconds 0.000500 # Nu sim_ticks 500337000 # Number of ticks simulated final_tick 500337000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 90464630 # Simulator tick rate (ticks/s) -host_mem_usage 231728 # Number of bytes of host memory used -host_seconds 5.53 # Real time elapsed on the host +host_tick_rate 117513072 # Simulator tick rate (ticks/s) +host_mem_usage 278328 # Number of bytes of host memory used +host_seconds 4.26 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0 75919 # Number of bytes read from this memory system.physmem.bytes_read::cpu1 81043 # Number of bytes read from this memory system.physmem.bytes_read::cpu2 80577 # Number of bytes read from this memory @@ -76,9 +77,12 @@ system.physmem.bw_total::cpu5 163601732 # To system.physmem.bw_total::cpu6 177978043 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu7 166783588 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2162126727 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu0.num_reads 99905 # number of read accesses completed system.cpu0.num_writes 55400 # number of write accesses completed +system.cpu0.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu0.l1c.tags.replacements 22463 # number of replacements system.cpu0.l1c.tags.tagsinuse 391.153981 # Cycle average of tags in use system.cpu0.l1c.tags.total_refs 13877 # Total number of references to valid blocks. @@ -94,6 +98,7 @@ system.cpu0.l1c.tags.age_task_id_blocks_1024::1 10 system.cpu0.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id system.cpu0.l1c.tags.tag_accesses 340651 # Number of tag accesses system.cpu0.l1c.tags.data_accesses 340651 # Number of data accesses +system.cpu0.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu0.l1c.ReadReq_hits::cpu0 8894 # number of ReadReq hits system.cpu0.l1c.ReadReq_hits::total 8894 # number of ReadReq hits system.cpu0.l1c.WriteReq_hits::cpu0 1261 # number of WriteReq hits @@ -196,8 +201,10 @@ system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 75003.675562 system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75003.675562 # average ReadReq mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 48257.334148 # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 48257.334148 # average overall mshr uncacheable latency +system.cpu1.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu1.num_reads 99552 # number of read accesses completed system.cpu1.num_writes 55243 # number of write accesses completed +system.cpu1.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu1.l1c.tags.replacements 22440 # number of replacements system.cpu1.l1c.tags.tagsinuse 392.475962 # Cycle average of tags in use system.cpu1.l1c.tags.total_refs 13641 # Total number of references to valid blocks. @@ -213,6 +220,7 @@ system.cpu1.l1c.tags.age_task_id_blocks_1024::1 12 system.cpu1.l1c.tags.occ_task_id_percent::1024 0.802734 # Percentage of cache occupancy per task id system.cpu1.l1c.tags.tag_accesses 339640 # Number of tag accesses system.cpu1.l1c.tags.data_accesses 339640 # Number of data accesses +system.cpu1.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu1.l1c.ReadReq_hits::cpu1 8906 # number of ReadReq hits system.cpu1.l1c.ReadReq_hits::total 8906 # number of ReadReq hits system.cpu1.l1c.WriteReq_hits::cpu1 1136 # number of WriteReq hits @@ -315,8 +323,10 @@ system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 74878.985934 system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74878.985934 # average ReadReq mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 48081.532234 # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 48081.532234 # average overall mshr uncacheable latency +system.cpu2.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu2.num_reads 100001 # number of read accesses completed system.cpu2.num_writes 55556 # number of write accesses completed +system.cpu2.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu2.l1c.tags.replacements 22129 # number of replacements system.cpu2.l1c.tags.tagsinuse 390.469202 # Cycle average of tags in use system.cpu2.l1c.tags.total_refs 13617 # Total number of references to valid blocks. @@ -332,6 +342,7 @@ system.cpu2.l1c.tags.age_task_id_blocks_1024::1 8 system.cpu2.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id system.cpu2.l1c.tags.tag_accesses 339163 # Number of tag accesses system.cpu2.l1c.tags.data_accesses 339163 # Number of data accesses +system.cpu2.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu2.l1c.ReadReq_hits::cpu2 8741 # number of ReadReq hits system.cpu2.l1c.ReadReq_hits::total 8741 # number of ReadReq hits system.cpu2.l1c.WriteReq_hits::cpu2 1177 # number of WriteReq hits @@ -434,8 +445,10 @@ system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 74755.242364 system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74755.242364 # average ReadReq mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 48431.812549 # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 48431.812549 # average overall mshr uncacheable latency +system.cpu3.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu3.num_reads 99831 # number of read accesses completed system.cpu3.num_writes 55461 # number of write accesses completed +system.cpu3.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu3.l1c.tags.replacements 22291 # number of replacements system.cpu3.l1c.tags.tagsinuse 391.006782 # Cycle average of tags in use system.cpu3.l1c.tags.total_refs 13350 # Total number of references to valid blocks. @@ -451,6 +464,7 @@ system.cpu3.l1c.tags.age_task_id_blocks_1024::1 11 system.cpu3.l1c.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id system.cpu3.l1c.tags.tag_accesses 338050 # Number of tag accesses system.cpu3.l1c.tags.data_accesses 338050 # Number of data accesses +system.cpu3.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu3.l1c.ReadReq_hits::cpu3 8529 # number of ReadReq hits system.cpu3.l1c.ReadReq_hits::total 8529 # number of ReadReq hits system.cpu3.l1c.WriteReq_hits::cpu3 1176 # number of WriteReq hits @@ -553,8 +567,10 @@ system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 75018.386537 system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75018.386537 # average ReadReq mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 47881.283715 # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 47881.283715 # average overall mshr uncacheable latency +system.cpu4.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu4.num_reads 99911 # number of read accesses completed system.cpu4.num_writes 55300 # number of write accesses completed +system.cpu4.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu4.l1c.tags.replacements 22364 # number of replacements system.cpu4.l1c.tags.tagsinuse 391.705900 # Cycle average of tags in use system.cpu4.l1c.tags.total_refs 13535 # Total number of references to valid blocks. @@ -570,6 +586,7 @@ system.cpu4.l1c.tags.age_task_id_blocks_1024::1 8 system.cpu4.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id system.cpu4.l1c.tags.tag_accesses 339861 # Number of tag accesses system.cpu4.l1c.tags.data_accesses 339861 # Number of data accesses +system.cpu4.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu4.l1c.ReadReq_hits::cpu4 8886 # number of ReadReq hits system.cpu4.l1c.ReadReq_hits::total 8886 # number of ReadReq hits system.cpu4.l1c.WriteReq_hits::cpu4 1168 # number of WriteReq hits @@ -672,8 +689,10 @@ system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 74866.678445 system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74866.678445 # average ReadReq mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 48019.883304 # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 48019.883304 # average overall mshr uncacheable latency +system.cpu5.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu5.num_reads 99665 # number of read accesses completed system.cpu5.num_writes 55439 # number of write accesses completed +system.cpu5.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu5.l1c.tags.replacements 22286 # number of replacements system.cpu5.l1c.tags.tagsinuse 391.859990 # Cycle average of tags in use system.cpu5.l1c.tags.total_refs 13458 # Total number of references to valid blocks. @@ -689,6 +708,7 @@ system.cpu5.l1c.tags.age_task_id_blocks_1024::1 10 system.cpu5.l1c.tags.occ_task_id_percent::1024 0.814453 # Percentage of cache occupancy per task id system.cpu5.l1c.tags.tag_accesses 338594 # Number of tag accesses system.cpu5.l1c.tags.data_accesses 338594 # Number of data accesses +system.cpu5.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu5.l1c.ReadReq_hits::cpu5 8649 # number of ReadReq hits system.cpu5.l1c.ReadReq_hits::total 8649 # number of ReadReq hits system.cpu5.l1c.WriteReq_hits::cpu5 1196 # number of WriteReq hits @@ -791,8 +811,10 @@ system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 74875.790313 system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74875.790313 # average ReadReq mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 48305.389102 # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 48305.389102 # average overall mshr uncacheable latency +system.cpu6.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu6.num_reads 99712 # number of read accesses completed system.cpu6.num_writes 55282 # number of write accesses completed +system.cpu6.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu6.l1c.tags.replacements 22239 # number of replacements system.cpu6.l1c.tags.tagsinuse 392.046110 # Cycle average of tags in use system.cpu6.l1c.tags.total_refs 13503 # Total number of references to valid blocks. @@ -808,6 +830,7 @@ system.cpu6.l1c.tags.age_task_id_blocks_1024::1 16 system.cpu6.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id system.cpu6.l1c.tags.tag_accesses 338073 # Number of tag accesses system.cpu6.l1c.tags.data_accesses 338073 # Number of data accesses +system.cpu6.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu6.l1c.ReadReq_hits::cpu6 8758 # number of ReadReq hits system.cpu6.l1c.ReadReq_hits::total 8758 # number of ReadReq hits system.cpu6.l1c.WriteReq_hits::cpu6 1067 # number of WriteReq hits @@ -910,8 +933,10 @@ system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 74822.857824 system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74822.857824 # average ReadReq mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 47746.599431 # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 47746.599431 # average overall mshr uncacheable latency +system.cpu7.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu7.num_reads 99031 # number of read accesses completed system.cpu7.num_writes 54931 # number of write accesses completed +system.cpu7.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu7.l1c.tags.replacements 22638 # number of replacements system.cpu7.l1c.tags.tagsinuse 391.993848 # Cycle average of tags in use system.cpu7.l1c.tags.total_refs 13556 # Total number of references to valid blocks. @@ -927,6 +952,7 @@ system.cpu7.l1c.tags.age_task_id_blocks_1024::1 14 system.cpu7.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id system.cpu7.l1c.tags.tag_accesses 339734 # Number of tag accesses system.cpu7.l1c.tags.data_accesses 339734 # Number of data accesses +system.cpu7.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.cpu7.l1c.ReadReq_hits::cpu7 8818 # number of ReadReq hits system.cpu7.l1c.ReadReq_hits::total 8818 # number of ReadReq hits system.cpu7.l1c.WriteReq_hits::cpu7 1148 # number of WriteReq hits @@ -1029,6 +1055,7 @@ system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 75003.057084 system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75003.057084 # average ReadReq mshr uncacheable latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 48382.659514 # average overall mshr uncacheable latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 48382.659514 # average overall mshr uncacheable latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 13688 # number of replacements system.l2c.tags.tagsinuse 782.559938 # Cycle average of tags in use system.l2c.tags.total_refs 164623 # Total number of references to valid blocks. @@ -1060,6 +1087,7 @@ system.l2c.tags.age_task_id_blocks_1024::1 126 # system.l2c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 2107372 # Number of tag accesses system.l2c.tags.data_accesses 2107372 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.l2c.WritebackDirty_hits::writebacks 77671 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 77671 # number of WritebackDirty hits system.l2c.UpgradeReq_hits::cpu0 272 # number of UpgradeReq hits @@ -1628,6 +1656,7 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 33504.118091 system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 33149.271115 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 33500.900238 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total 33381.197903 # average overall mshr uncacheable latency +system.membus.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 78773 # Transaction distribution system.membus.trans_dist::ReadResp 84410 # Transaction distribution system.membus.trans_dist::WriteReq 43787 # Transaction distribution @@ -1663,6 +1692,7 @@ system.toL2Bus.snoop_filter.hit_multi_requests 332740 system.toL2Bus.snoop_filter.tot_snoops 12293 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 5765 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 6528 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 78775 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 371396 # Transaction distribution system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index d7757f328..f25ed6812 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.044221 # Nu sim_ticks 44221003000 # Number of ticks simulated final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1535738 # Simulator instruction rate (inst/s) -host_op_rate 1535737 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 768748978 # Simulator tick rate (ticks/s) -host_mem_usage 246592 # Number of bytes of host memory used -host_seconds 57.52 # Real time elapsed on the host +host_inst_rate 3085186 # Simulator instruction rate (inst/s) +host_op_rate 3085185 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1544361453 # Simulator tick rate (ticks/s) +host_mem_usage 293364 # Number of bytes of host memory used +host_seconds 28.63 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 44221003000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 126702647 # Number of bytes read from this memory system.physmem.bytes_read::total 480454939 # Number of bytes read from this memory @@ -35,6 +36,7 @@ system.physmem.bw_write::total 2072610067 # Wr system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 44221003000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -69,6 +71,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 44221003000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 88442007 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -127,6 +130,7 @@ system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 88438073 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 44221003000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 108714711 # Transaction distribution system.membus.trans_dist::ReadResp 108714711 # Transaction distribution system.membus.trans_dist::WriteReq 14613377 # Transaction distribution diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 4daa87195..b00dd906e 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.134742 # Nu sim_ticks 134741611500 # Number of ticks simulated final_tick 134741611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 882134 # Simulator instruction rate (inst/s) -host_op_rate 882134 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1345475029 # Simulator tick rate (ticks/s) -host_mem_usage 255564 # Number of bytes of host memory used -host_seconds 100.14 # Real time elapsed on the host +host_inst_rate 1731648 # Simulator instruction rate (inst/s) +host_op_rate 1731647 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2641194476 # Simulator tick rate (ticks/s) +host_mem_usage 302344 # Number of bytes of host memory used +host_seconds 51.02 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 367360 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10138112 # Number of bytes read from this memory system.physmem.bytes_read::total 10505472 # Number of bytes read from this memory @@ -36,6 +37,7 @@ system.physmem.bw_total::writebacks 54329527 # To system.physmem.bw_total::cpu.inst 2726403 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 75241137 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 132297067 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -70,6 +72,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 134741611500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 269483223 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -128,6 +131,7 @@ system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 88438073 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 200248 # number of replacements system.cpu.dcache.tags.tagsinuse 4078.397630 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. @@ -144,6 +148,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 3595 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits @@ -232,6 +237,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49986.498258 system.cpu.dcache.demand_avg_mshr_miss_latency::total 49986.498258 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49986.498258 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 49986.498258 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 74391 # number of replacements system.cpu.icache.tags.tagsinuse 1870.507754 # Cycle average of tags in use system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks. @@ -249,6 +255,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1708 system.cpu.icache.tags.occ_task_id_percent::1024 0.998535 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 176952584 # Number of tag accesses system.cpu.icache.tags.data_accesses 176952584 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits @@ -317,6 +324,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15687.405149 system.cpu.icache.demand_avg_mshr_miss_latency::total 15687.405149 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15687.405149 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 15687.405149 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 131998 # number of replacements system.cpu.l2cache.tags.tagsinuse 30708.485304 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 247404 # Total number of references to valid blocks. @@ -339,6 +347,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 122 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978882 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4751004 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4751004 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 168278 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 168278 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 74391 # number of WritebackClean hits @@ -485,6 +494,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 3875 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3875 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 282660 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 74391 # Transaction distribution @@ -517,6 +527,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 114654000 # La system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 33266 # Transaction distribution system.membus.trans_dist::WritebackDirty 114382 # Transaction distribution system.membus.trans_dist::CleanEvict 13845 # Transaction distribution diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 545d841c6..00bb71a79 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.048960 # Nu sim_ticks 48960022500 # Number of ticks simulated final_tick 48960022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1798045 # Simulator instruction rate (inst/s) -host_op_rate 2299450 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1241408996 # Simulator tick rate (ticks/s) -host_mem_usage 309432 # Number of bytes of host memory used -host_seconds 39.44 # Real time elapsed on the host +host_inst_rate 1718625 # Simulator instruction rate (inst/s) +host_op_rate 2197882 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1186575552 # Simulator tick rate (ticks/s) +host_mem_usage 310104 # Number of bytes of host memory used +host_seconds 41.26 # Real time elapsed on the host sim_insts 70913204 # Number of instructions simulated sim_ops 90688159 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 312580364 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 106573345 # Number of bytes read from this memory system.physmem.bytes_read::total 419153709 # Number of bytes read from this memory @@ -35,7 +36,9 @@ system.physmem.bw_write::total 1606621218 # Wr system.physmem.bw_total::cpu.inst 6384399925 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3783363376 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10167763301 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -65,6 +68,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -94,6 +98,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -123,6 +128,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,6 +159,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 48960022500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 97920046 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -213,6 +220,7 @@ system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 90690106 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 100925158 # Transaction distribution system.membus.trans_dist::ReadResp 100941077 # Transaction distribution system.membus.trans_dist::WriteReq 19849901 # Transaction distribution diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index f303216c1..b2023c05c 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.128077 # Nu sim_ticks 128076834500 # Number of ticks simulated final_tick 128076834500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1113892 # Simulator instruction rate (inst/s) -host_op_rate 1422128 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2027232976 # Simulator tick rate (ticks/s) -host_mem_usage 319564 # Number of bytes of host memory used -host_seconds 63.18 # Real time elapsed on the host +host_inst_rate 1093594 # Simulator instruction rate (inst/s) +host_op_rate 1396212 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1990290276 # Simulator tick rate (ticks/s) +host_mem_usage 320240 # Number of bytes of host memory used +host_seconds 64.35 # Real time elapsed on the host sim_insts 70373651 # Number of instructions simulated sim_ops 89847385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 233152 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7925248 # Number of bytes read from this memory system.physmem.bytes_read::total 8158400 # Number of bytes read from this memory @@ -36,7 +37,9 @@ system.physmem.bw_total::writebacks 43049159 # To system.physmem.bw_total::cpu.inst 1820407 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 61878856 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 106748422 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -66,6 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -95,6 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -124,6 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -154,6 +160,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 128076834500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 256153669 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -214,6 +221,7 @@ system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 90690106 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 155902 # number of replacements system.cpu.dcache.tags.tagsinuse 4075.927155 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 42601677 # Total number of references to valid blocks. @@ -230,6 +238,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 3263 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 22743361 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 22743361 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits @@ -348,6 +357,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49898.108565 system.cpu.dcache.demand_avg_mshr_miss_latency::total 49898.108565 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 16890 # number of replacements system.cpu.icache.tags.tagsinuse 1732.356634 # Cycle average of tags in use system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks. @@ -365,6 +375,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits @@ -433,6 +444,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.749947 system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 95333 # number of replacements system.cpu.l2cache.tags.tagsinuse 30336.891531 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 114380 # Total number of references to valid blocks. @@ -455,6 +467,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 624 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949768 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3017503 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3017503 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 128175 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 128175 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 15790 # number of WritebackClean hits @@ -601,6 +614,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 system.cpu.toL2Bus.snoop_filter.tot_snoops 3119 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3089 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 214325 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution @@ -633,6 +647,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 28362000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 25194 # Transaction distribution system.membus.trans_dist::WritebackDirty 86150 # Transaction distribution system.membus.trans_dist::CleanEvict 6168 # Transaction distribution diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index 75464de1f..ff66806fe 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.068149 # Nu sim_ticks 68148677000 # Number of ticks simulated final_tick 68148677000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1339454 # Simulator instruction rate (inst/s) -host_op_rate 1356797 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 679186650 # Simulator tick rate (ticks/s) -host_mem_usage 246572 # Number of bytes of host memory used -host_seconds 100.34 # Real time elapsed on the host +host_inst_rate 2845356 # Simulator instruction rate (inst/s) +host_op_rate 2882198 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1442772972 # Simulator tick rate (ticks/s) +host_mem_usage 292276 # Number of bytes of host memory used +host_seconds 47.23 # Real time elapsed on the host sim_insts 134398959 # Number of instructions simulated sim_ops 136139187 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 68148677000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 538214320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 147559360 # Number of bytes read from this memory system.physmem.bytes_read::total 685773680 # Number of bytes read from this memory @@ -37,8 +38,10 @@ system.physmem.bw_write::total 1318924357 # Wr system.physmem.bw_total::cpu.inst 7897648842 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3484180771 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11381829614 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 68148677000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 68148677000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 136297355 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -97,6 +100,7 @@ system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 136293808 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 68148677000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 171784880 # Transaction distribution system.membus.trans_dist::ReadResp 171784880 # Transaction distribution system.membus.trans_dist::WriteReq 20864304 # Transaction distribution diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 18f2ca2b3..be1596583 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.203116 # Nu sim_ticks 203115946500 # Number of ticks simulated final_tick 203115946500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 790551 # Simulator instruction rate (inst/s) -host_op_rate 800787 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1194752753 # Simulator tick rate (ticks/s) -host_mem_usage 255284 # Number of bytes of host memory used -host_seconds 170.01 # Real time elapsed on the host +host_inst_rate 1546845 # Simulator instruction rate (inst/s) +host_op_rate 1566874 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2337732587 # Simulator tick rate (ticks/s) +host_mem_usage 302284 # Number of bytes of host memory used +host_seconds 86.89 # Real time elapsed on the host sim_insts 134398959 # Number of instructions simulated sim_ops 136139187 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 525056 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7828352 # Number of bytes read from this memory system.physmem.bytes_read::total 8353408 # Number of bytes read from this memory @@ -36,8 +37,10 @@ system.physmem.bw_total::writebacks 26867807 # To system.physmem.bw_total::cpu.inst 2585006 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 38541297 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 67994110 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 203115946500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 406231893 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -96,6 +99,7 @@ system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 136293808 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 146583 # number of replacements system.cpu.dcache.tags.tagsinuse 4087.268923 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 57960841 # Total number of references to valid blocks. @@ -112,6 +116,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 3586 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 116373719 # Number of tag accesses system.cpu.dcache.tags.data_accesses 116373719 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 37185800 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 37185800 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits @@ -220,6 +225,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.466336 system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 184976 # number of replacements system.cpu.icache.tags.tagsinuse 2004.181265 # Cycle average of tags in use system.cpu.icache.tags.total_refs 134366557 # Total number of references to valid blocks. @@ -238,6 +244,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 269294186 # Number of tag accesses system.cpu.icache.tags.data_accesses 269294186 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 134366557 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 134366557 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 134366557 # number of demand (read+write) hits @@ -306,6 +313,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14159.760245 system.cpu.icache.demand_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 99022 # number of replacements system.cpu.l2cache.tags.tagsinuse 30843.699683 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 433832 # Total number of references to valid blocks. @@ -328,6 +336,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 557 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.947357 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 5588812 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 5588812 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 123865 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 123865 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 184923 # number of WritebackClean hits @@ -474,6 +483,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 system.cpu.toL2Bus.snoop_filter.tot_snoops 3547 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3547 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 232524 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 209135 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution @@ -506,6 +516,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 280536000 # La system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 226018500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 29258 # Transaction distribution system.membus.trans_dist::WritebackDirty 85270 # Transaction distribution system.membus.trans_dist::CleanEvict 10301 # Transaction distribution diff --git a/tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt b/tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt index 6e51bc804..fdc10b410 100644 --- a/tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt +++ b/tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt @@ -4,11 +4,12 @@ sim_seconds 0.010000 # Nu sim_ticks 10000000000 # Number of ticks simulated final_tick 10000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 621801419 # Simulator tick rate (ticks/s) -host_mem_usage 1442452 # Number of bytes of host memory used -host_seconds 16.08 # Real time elapsed on the host +host_tick_rate 757790256 # Simulator tick rate (ticks/s) +host_mem_usage 1498684 # Number of bytes of host memory used +host_seconds 13.20 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::l0subsys0.tester0 2151552 # Number of bytes read from this memory system.physmem.bytes_read::l0subsys0.tester1 2168960 # Number of bytes read from this memory system.physmem.bytes_read::l0subsys1.tester0 2107520 # Number of bytes read from this memory @@ -307,9 +308,14 @@ system.physmem_1.memoryStateTime::REF 333840000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 9620586338 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states +system.l0subsys0.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states +system.l0subsys0.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states +system.l0subsys0.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys0.tester0.numPackets 67424 # Number of packets generated system.l0subsys0.tester0.numRetries 2732 # Number of retries system.l0subsys0.tester0.retryTicks 71787172 # Time spent waiting due to back-pressure (ticks) +system.l0subsys0.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys0.tester1.numPackets 67451 # Number of packets generated system.l0subsys0.tester1.numRetries 2817 # Number of retries system.l0subsys0.tester1.retryTicks 69161680 # Time spent waiting due to back-pressure (ticks) @@ -319,6 +325,7 @@ system.l0subsys0.xbar.snoop_filter.hit_multi_requests 0 system.l0subsys0.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l0subsys0.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l0subsys0.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l0subsys0.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys0.xbar.trans_dist::ReadReq 86409 # Transaction distribution system.l0subsys0.xbar.trans_dist::ReadResp 82049 # Transaction distribution system.l0subsys0.xbar.trans_dist::ReadRespWithInvalidate 4359 # Transaction distribution @@ -351,9 +358,13 @@ system.l0subsys0.xbar.respLayer0.occupancy 116989147 # system.l0subsys0.xbar.respLayer0.utilization 1.2 # Layer utilization (%) system.l0subsys0.xbar.respLayer1.occupancy 116411811 # Layer occupancy (ticks) system.l0subsys0.xbar.respLayer1.utilization 1.2 # Layer utilization (%) +system.l0subsys1.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states +system.l0subsys1.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states +system.l0subsys1.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys1.tester0.numPackets 65180 # Number of packets generated system.l0subsys1.tester0.numRetries 2851 # Number of retries system.l0subsys1.tester0.retryTicks 74729692 # Time spent waiting due to back-pressure (ticks) +system.l0subsys1.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys1.tester1.numPackets 68174 # Number of packets generated system.l0subsys1.tester1.numRetries 2790 # Number of retries system.l0subsys1.tester1.retryTicks 74335880 # Time spent waiting due to back-pressure (ticks) @@ -363,6 +374,7 @@ system.l0subsys1.xbar.snoop_filter.hit_multi_requests 0 system.l0subsys1.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l0subsys1.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l0subsys1.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l0subsys1.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys1.xbar.trans_dist::ReadReq 85972 # Transaction distribution system.l0subsys1.xbar.trans_dist::ReadResp 82000 # Transaction distribution system.l0subsys1.xbar.trans_dist::ReadRespWithInvalidate 3972 # Transaction distribution @@ -395,9 +407,13 @@ system.l0subsys1.xbar.respLayer0.occupancy 113396564 # system.l0subsys1.xbar.respLayer0.utilization 1.1 # Layer utilization (%) system.l0subsys1.xbar.respLayer1.occupancy 118377078 # Layer occupancy (ticks) system.l0subsys1.xbar.respLayer1.utilization 1.2 # Layer utilization (%) +system.l0subsys2.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states +system.l0subsys2.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states +system.l0subsys2.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys2.tester0.numPackets 65223 # Number of packets generated system.l0subsys2.tester0.numRetries 2584 # Number of retries system.l0subsys2.tester0.retryTicks 64900705 # Time spent waiting due to back-pressure (ticks) +system.l0subsys2.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys2.tester1.numPackets 65256 # Number of packets generated system.l0subsys2.tester1.numRetries 2558 # Number of retries system.l0subsys2.tester1.retryTicks 64249844 # Time spent waiting due to back-pressure (ticks) @@ -407,6 +423,7 @@ system.l0subsys2.xbar.snoop_filter.hit_multi_requests 0 system.l0subsys2.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l0subsys2.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l0subsys2.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l0subsys2.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys2.xbar.trans_dist::ReadReq 84127 # Transaction distribution system.l0subsys2.xbar.trans_dist::ReadResp 80122 # Transaction distribution system.l0subsys2.xbar.trans_dist::ReadRespWithInvalidate 4004 # Transaction distribution @@ -439,9 +456,13 @@ system.l0subsys2.xbar.respLayer0.occupancy 113755357 # system.l0subsys2.xbar.respLayer0.utilization 1.1 # Layer utilization (%) system.l0subsys2.xbar.respLayer1.occupancy 113314488 # Layer occupancy (ticks) system.l0subsys2.xbar.respLayer1.utilization 1.1 # Layer utilization (%) +system.l0subsys3.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states +system.l0subsys3.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states +system.l0subsys3.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys3.tester0.numPackets 66015 # Number of packets generated system.l0subsys3.tester0.numRetries 2474 # Number of retries system.l0subsys3.tester0.retryTicks 61325178 # Time spent waiting due to back-pressure (ticks) +system.l0subsys3.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys3.tester1.numPackets 63774 # Number of packets generated system.l0subsys3.tester1.numRetries 2406 # Number of retries system.l0subsys3.tester1.retryTicks 60532485 # Time spent waiting due to back-pressure (ticks) @@ -451,6 +472,7 @@ system.l0subsys3.xbar.snoop_filter.hit_multi_requests 0 system.l0subsys3.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l0subsys3.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l0subsys3.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l0subsys3.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys3.xbar.trans_dist::ReadReq 83355 # Transaction distribution system.l0subsys3.xbar.trans_dist::ReadResp 78973 # Transaction distribution system.l0subsys3.xbar.trans_dist::ReadRespWithInvalidate 4382 # Transaction distribution @@ -483,9 +505,13 @@ system.l0subsys3.xbar.respLayer0.occupancy 114100947 # system.l0subsys3.xbar.respLayer0.utilization 1.1 # Layer utilization (%) system.l0subsys3.xbar.respLayer1.occupancy 110374985 # Layer occupancy (ticks) system.l0subsys3.xbar.respLayer1.utilization 1.1 # Layer utilization (%) +system.l0subsys4.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states +system.l0subsys4.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states +system.l0subsys4.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys4.tester0.numPackets 67184 # Number of packets generated system.l0subsys4.tester0.numRetries 2523 # Number of retries system.l0subsys4.tester0.retryTicks 66430147 # Time spent waiting due to back-pressure (ticks) +system.l0subsys4.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys4.tester1.numPackets 65756 # Number of packets generated system.l0subsys4.tester1.numRetries 2580 # Number of retries system.l0subsys4.tester1.retryTicks 67683660 # Time spent waiting due to back-pressure (ticks) @@ -495,6 +521,7 @@ system.l0subsys4.xbar.snoop_filter.hit_multi_requests 0 system.l0subsys4.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l0subsys4.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l0subsys4.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l0subsys4.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys4.xbar.trans_dist::ReadReq 85507 # Transaction distribution system.l0subsys4.xbar.trans_dist::ReadResp 81442 # Transaction distribution system.l0subsys4.xbar.trans_dist::ReadRespWithInvalidate 4064 # Transaction distribution @@ -527,9 +554,13 @@ system.l0subsys4.xbar.respLayer0.occupancy 116964811 # system.l0subsys4.xbar.respLayer0.utilization 1.2 # Layer utilization (%) system.l0subsys4.xbar.respLayer1.occupancy 114597175 # Layer occupancy (ticks) system.l0subsys4.xbar.respLayer1.utilization 1.1 # Layer utilization (%) +system.l0subsys5.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states +system.l0subsys5.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states +system.l0subsys5.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys5.tester0.numPackets 67119 # Number of packets generated system.l0subsys5.tester0.numRetries 2560 # Number of retries system.l0subsys5.tester0.retryTicks 65403498 # Time spent waiting due to back-pressure (ticks) +system.l0subsys5.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys5.tester1.numPackets 65308 # Number of packets generated system.l0subsys5.tester1.numRetries 2642 # Number of retries system.l0subsys5.tester1.retryTicks 65659220 # Time spent waiting due to back-pressure (ticks) @@ -539,6 +570,7 @@ system.l0subsys5.xbar.snoop_filter.hit_multi_requests 0 system.l0subsys5.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l0subsys5.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l0subsys5.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l0subsys5.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys5.xbar.trans_dist::ReadReq 85511 # Transaction distribution system.l0subsys5.xbar.trans_dist::ReadResp 81276 # Transaction distribution system.l0subsys5.xbar.trans_dist::ReadRespWithInvalidate 4233 # Transaction distribution @@ -571,6 +603,7 @@ system.l0subsys5.xbar.respLayer0.occupancy 116426882 # system.l0subsys5.xbar.respLayer0.utilization 1.2 # Layer utilization (%) system.l0subsys5.xbar.respLayer1.occupancy 112976792 # Layer occupancy (ticks) system.l0subsys5.xbar.respLayer1.utilization 1.1 # Layer utilization (%) +system.l1subsys0.cache0.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l1subsys0.cache0.tags.replacements 67551 # number of replacements system.l1subsys0.cache0.tags.tagsinuse 502.758409 # Cycle average of tags in use system.l1subsys0.cache0.tags.total_refs 31003 # Total number of references to valid blocks. @@ -589,6 +622,7 @@ system.l1subsys0.cache0.tags.age_task_id_blocks_1024::2 63 system.l1subsys0.cache0.tags.occ_task_id_percent::1024 0.990234 # Percentage of cache occupancy per task id system.l1subsys0.cache0.tags.tag_accesses 641417 # Number of tag accesses system.l1subsys0.cache0.tags.data_accesses 641417 # Number of data accesses +system.l1subsys0.cache0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l1subsys0.cache0.ReadReq_hits::l0subsys0.tester0 9938 # number of ReadReq hits system.l1subsys0.cache0.ReadReq_hits::l0subsys0.tester1 9361 # number of ReadReq hits system.l1subsys0.cache0.ReadReq_hits::total 19299 # number of ReadReq hits @@ -729,6 +763,7 @@ system.l1subsys0.cache0.demand_avg_mshr_miss_latency::total 90055.037917 system.l1subsys0.cache0.overall_avg_mshr_miss_latency::l0subsys0.tester0 90387.265234 # average overall mshr miss latency system.l1subsys0.cache0.overall_avg_mshr_miss_latency::l0subsys0.tester1 89727.019386 # average overall mshr miss latency system.l1subsys0.cache0.overall_avg_mshr_miss_latency::total 90055.037917 # average overall mshr miss latency +system.l1subsys0.cache1.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l1subsys0.cache1.tags.replacements 68848 # number of replacements system.l1subsys0.cache1.tags.tagsinuse 504.594743 # Cycle average of tags in use system.l1subsys0.cache1.tags.total_refs 31105 # Total number of references to valid blocks. @@ -747,6 +782,7 @@ system.l1subsys0.cache1.tags.age_task_id_blocks_1024::2 90 system.l1subsys0.cache1.tags.occ_task_id_percent::1024 0.976562 # Percentage of cache occupancy per task id system.l1subsys0.cache1.tags.tag_accesses 633805 # Number of tag accesses system.l1subsys0.cache1.tags.data_accesses 633805 # Number of data accesses +system.l1subsys0.cache1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l1subsys0.cache1.ReadReq_hits::l0subsys1.tester0 9817 # number of ReadReq hits system.l1subsys0.cache1.ReadReq_hits::l0subsys1.tester1 9861 # number of ReadReq hits system.l1subsys0.cache1.ReadReq_hits::total 19678 # number of ReadReq hits @@ -893,6 +929,7 @@ system.l1subsys0.xbar.snoop_filter.hit_multi_requests 8556 system.l1subsys0.xbar.snoop_filter.tot_snoops 114062 # Total number of snoops made to the snoop filter. system.l1subsys0.xbar.snoop_filter.hit_single_snoops 98725 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l1subsys0.xbar.snoop_filter.hit_multi_snoops 15337 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l1subsys0.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l1subsys0.xbar.trans_dist::ReadResp 154200 # Transaction distribution system.l1subsys0.xbar.trans_dist::ReadRespWithInvalidate 3741 # Transaction distribution system.l1subsys0.xbar.trans_dist::WritebackDirty 97097 # Transaction distribution @@ -928,6 +965,7 @@ system.l1subsys0.xbar.respLayer0.occupancy 318997409 # system.l1subsys0.xbar.respLayer0.utilization 3.2 # Layer utilization (%) system.l1subsys0.xbar.respLayer1.occupancy 314273952 # Layer occupancy (ticks) system.l1subsys0.xbar.respLayer1.utilization 3.1 # Layer utilization (%) +system.l1subsys1.cache0.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l1subsys1.cache0.tags.replacements 64055 # number of replacements system.l1subsys1.cache0.tags.tagsinuse 501.915078 # Cycle average of tags in use system.l1subsys1.cache0.tags.total_refs 31614 # Total number of references to valid blocks. @@ -946,6 +984,7 @@ system.l1subsys1.cache0.tags.age_task_id_blocks_1024::2 23 system.l1subsys1.cache0.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id system.l1subsys1.cache0.tags.tag_accesses 619158 # Number of tag accesses system.l1subsys1.cache0.tags.data_accesses 619158 # Number of data accesses +system.l1subsys1.cache0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l1subsys1.cache0.ReadReq_hits::l0subsys2.tester0 10039 # number of ReadReq hits system.l1subsys1.cache0.ReadReq_hits::l0subsys2.tester1 9798 # number of ReadReq hits system.l1subsys1.cache0.ReadReq_hits::total 19837 # number of ReadReq hits @@ -1086,6 +1125,7 @@ system.l1subsys1.cache0.demand_avg_mshr_miss_latency::total 89695.571963 system.l1subsys1.cache0.overall_avg_mshr_miss_latency::l0subsys2.tester0 90126.933848 # average overall mshr miss latency system.l1subsys1.cache0.overall_avg_mshr_miss_latency::l0subsys2.tester1 89266.884167 # average overall mshr miss latency system.l1subsys1.cache0.overall_avg_mshr_miss_latency::total 89695.571963 # average overall mshr miss latency +system.l1subsys1.cache1.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l1subsys1.cache1.tags.replacements 63731 # number of replacements system.l1subsys1.cache1.tags.tagsinuse 503.303418 # Cycle average of tags in use system.l1subsys1.cache1.tags.total_refs 29004 # Total number of references to valid blocks. @@ -1104,6 +1144,7 @@ system.l1subsys1.cache1.tags.age_task_id_blocks_1024::2 93 system.l1subsys1.cache1.tags.occ_task_id_percent::1024 0.982422 # Percentage of cache occupancy per task id system.l1subsys1.cache1.tags.tag_accesses 617940 # Number of tag accesses system.l1subsys1.cache1.tags.data_accesses 617940 # Number of data accesses +system.l1subsys1.cache1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l1subsys1.cache1.ReadReq_hits::l0subsys3.tester0 9182 # number of ReadReq hits system.l1subsys1.cache1.ReadReq_hits::l0subsys3.tester1 9019 # number of ReadReq hits system.l1subsys1.cache1.ReadReq_hits::total 18201 # number of ReadReq hits @@ -1250,6 +1291,7 @@ system.l1subsys1.xbar.snoop_filter.hit_multi_requests 8795 system.l1subsys1.xbar.snoop_filter.tot_snoops 114270 # Total number of snoops made to the snoop filter. system.l1subsys1.xbar.snoop_filter.hit_single_snoops 97861 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l1subsys1.xbar.snoop_filter.hit_multi_snoops 16409 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l1subsys1.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l1subsys1.xbar.trans_dist::ReadResp 151000 # Transaction distribution system.l1subsys1.xbar.trans_dist::ReadRespWithInvalidate 3767 # Transaction distribution system.l1subsys1.xbar.trans_dist::WritebackDirty 90510 # Transaction distribution @@ -1285,6 +1327,7 @@ system.l1subsys1.xbar.respLayer0.occupancy 305008955 # system.l1subsys1.xbar.respLayer0.utilization 3.1 # Layer utilization (%) system.l1subsys1.xbar.respLayer1.occupancy 309946184 # Layer occupancy (ticks) system.l1subsys1.xbar.respLayer1.utilization 3.1 # Layer utilization (%) +system.l1subsys2.cache0.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l1subsys2.cache0.tags.replacements 65353 # number of replacements system.l1subsys2.cache0.tags.tagsinuse 504.458871 # Cycle average of tags in use system.l1subsys2.cache0.tags.total_refs 33188 # Total number of references to valid blocks. @@ -1303,6 +1346,7 @@ system.l1subsys2.cache0.tags.age_task_id_blocks_1024::2 28 system.l1subsys2.cache0.tags.occ_task_id_percent::1024 0.986328 # Percentage of cache occupancy per task id system.l1subsys2.cache0.tags.tag_accesses 629863 # Number of tag accesses system.l1subsys2.cache0.tags.data_accesses 629863 # Number of data accesses +system.l1subsys2.cache0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l1subsys2.cache0.ReadReq_hits::l0subsys4.tester0 10527 # number of ReadReq hits system.l1subsys2.cache0.ReadReq_hits::l0subsys4.tester1 10271 # number of ReadReq hits system.l1subsys2.cache0.ReadReq_hits::total 20798 # number of ReadReq hits @@ -1443,6 +1487,7 @@ system.l1subsys2.cache0.demand_avg_mshr_miss_latency::total 90569.637316 system.l1subsys2.cache0.overall_avg_mshr_miss_latency::l0subsys4.tester0 91822.941718 # average overall mshr miss latency system.l1subsys2.cache0.overall_avg_mshr_miss_latency::l0subsys4.tester1 89290.677324 # average overall mshr miss latency system.l1subsys2.cache0.overall_avg_mshr_miss_latency::total 90569.637316 # average overall mshr miss latency +system.l1subsys2.cache1.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l1subsys2.cache1.tags.replacements 67065 # number of replacements system.l1subsys2.cache1.tags.tagsinuse 502.741649 # Cycle average of tags in use system.l1subsys2.cache1.tags.total_refs 30001 # Total number of references to valid blocks. @@ -1461,6 +1506,7 @@ system.l1subsys2.cache1.tags.age_task_id_blocks_1024::2 70 system.l1subsys2.cache1.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id system.l1subsys2.cache1.tags.tag_accesses 630788 # Number of tag accesses system.l1subsys2.cache1.tags.data_accesses 630788 # Number of data accesses +system.l1subsys2.cache1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l1subsys2.cache1.ReadReq_hits::l0subsys5.tester0 9835 # number of ReadReq hits system.l1subsys2.cache1.ReadReq_hits::l0subsys5.tester1 9033 # number of ReadReq hits system.l1subsys2.cache1.ReadReq_hits::total 18868 # number of ReadReq hits @@ -1607,6 +1653,7 @@ system.l1subsys2.xbar.snoop_filter.hit_multi_requests 8459 system.l1subsys2.xbar.snoop_filter.tot_snoops 114014 # Total number of snoops made to the snoop filter. system.l1subsys2.xbar.snoop_filter.hit_single_snoops 99574 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l1subsys2.xbar.snoop_filter.hit_multi_snoops 14440 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l1subsys2.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l1subsys2.xbar.trans_dist::ReadResp 152712 # Transaction distribution system.l1subsys2.xbar.trans_dist::ReadRespWithInvalidate 3827 # Transaction distribution system.l1subsys2.xbar.trans_dist::WritebackDirty 93911 # Transaction distribution @@ -1642,6 +1689,7 @@ system.l1subsys2.xbar.respLayer0.occupancy 307826729 # system.l1subsys2.xbar.respLayer0.utilization 3.1 # Layer utilization (%) system.l1subsys2.xbar.respLayer1.occupancy 316356652 # Layer occupancy (ticks) system.l1subsys2.xbar.respLayer1.utilization 3.2 # Layer utilization (%) +system.l2subsys0.cache0.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l2subsys0.cache0.tags.replacements 33571 # number of replacements system.l2subsys0.cache0.tags.tagsinuse 498.351113 # Cycle average of tags in use system.l2subsys0.cache0.tags.total_refs 14579 # Total number of references to valid blocks. @@ -1658,6 +1706,7 @@ system.l2subsys0.cache0.tags.age_task_id_blocks_1024::2 218 system.l2subsys0.cache0.tags.occ_task_id_percent::1024 0.990234 # Percentage of cache occupancy per task id system.l2subsys0.cache0.tags.tag_accesses 327999 # Number of tag accesses system.l2subsys0.cache0.tags.data_accesses 327999 # Number of data accesses +system.l2subsys0.cache0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l2subsys0.cache0.ReadReq_hits::l2subsys0.tester 9421 # number of ReadReq hits system.l2subsys0.cache0.ReadReq_hits::total 9421 # number of ReadReq hits system.l2subsys0.cache0.WriteReq_hits::l2subsys0.tester 1165 # number of WriteReq hits @@ -1754,6 +1803,7 @@ system.l2subsys0.cache0.demand_avg_mshr_miss_latency::l2subsys0.tester 65232.365 system.l2subsys0.cache0.demand_avg_mshr_miss_latency::total 65232.365364 # average overall mshr miss latency system.l2subsys0.cache0.overall_avg_mshr_miss_latency::l2subsys0.tester 65232.365364 # average overall mshr miss latency system.l2subsys0.cache0.overall_avg_mshr_miss_latency::total 65232.365364 # average overall mshr miss latency +system.l2subsys0.cache1.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l2subsys0.cache1.tags.replacements 134581 # number of replacements system.l2subsys0.cache1.tags.tagsinuse 1490.708088 # Cycle average of tags in use system.l2subsys0.cache1.tags.total_refs 68619 # Total number of references to valid blocks. @@ -1778,6 +1828,7 @@ system.l2subsys0.cache1.tags.age_task_id_blocks_1024::2 462 system.l2subsys0.cache1.tags.occ_task_id_percent::1024 0.977214 # Percentage of cache occupancy per task id system.l2subsys0.cache1.tags.tag_accesses 4309680 # Number of tag accesses system.l2subsys0.cache1.tags.data_accesses 4309680 # Number of data accesses +system.l2subsys0.cache1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l2subsys0.cache1.WritebackDirty_hits::writebacks 48994 # number of WritebackDirty hits system.l2subsys0.cache1.WritebackDirty_hits::total 48994 # number of WritebackDirty hits system.l2subsys0.cache1.ReadExReq_hits::l0subsys0.tester0 45 # number of ReadExReq hits @@ -2059,6 +2110,7 @@ system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys0.tester1 86901.8 system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester0 88785.081065 # average overall mshr miss latency system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester1 90884.489838 # average overall mshr miss latency system.l2subsys0.cache1.overall_avg_mshr_miss_latency::total 88472.037304 # average overall mshr miss latency +system.l2subsys0.cache2.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l2subsys0.cache2.tags.replacements 126032 # number of replacements system.l2subsys0.cache2.tags.tagsinuse 1489.728979 # Cycle average of tags in use system.l2subsys0.cache2.tags.total_refs 65365 # Total number of references to valid blocks. @@ -2083,6 +2135,7 @@ system.l2subsys0.cache2.tags.age_task_id_blocks_1024::2 358 system.l2subsys0.cache2.tags.occ_task_id_percent::1024 0.974609 # Percentage of cache occupancy per task id system.l2subsys0.cache2.tags.tag_accesses 4109673 # Number of tag accesses system.l2subsys0.cache2.tags.data_accesses 4109673 # Number of data accesses +system.l2subsys0.cache2.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l2subsys0.cache2.WritebackDirty_hits::writebacks 45683 # number of WritebackDirty hits system.l2subsys0.cache2.WritebackDirty_hits::total 45683 # number of WritebackDirty hits system.l2subsys0.cache2.ReadExReq_hits::l0subsys2.tester0 37 # number of ReadExReq hits @@ -2364,6 +2417,7 @@ system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys2.tester1 87967.7 system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys3.tester0 86634.785961 # average overall mshr miss latency system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys3.tester1 86857.574211 # average overall mshr miss latency system.l2subsys0.cache2.overall_avg_mshr_miss_latency::total 87244.093661 # average overall mshr miss latency +system.l2subsys0.cache3.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l2subsys0.cache3.tags.replacements 130662 # number of replacements system.l2subsys0.cache3.tags.tagsinuse 1489.946036 # Cycle average of tags in use system.l2subsys0.cache3.tags.total_refs 67604 # Total number of references to valid blocks. @@ -2388,6 +2442,7 @@ system.l2subsys0.cache3.tags.age_task_id_blocks_1024::2 316 system.l2subsys0.cache3.tags.occ_task_id_percent::1024 0.975911 # Percentage of cache occupancy per task id system.l2subsys0.cache3.tags.tag_accesses 4225473 # Number of tag accesses system.l2subsys0.cache3.tags.data_accesses 4225473 # Number of data accesses +system.l2subsys0.cache3.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l2subsys0.cache3.WritebackDirty_hits::writebacks 47372 # number of WritebackDirty hits system.l2subsys0.cache3.WritebackDirty_hits::total 47372 # number of WritebackDirty hits system.l2subsys0.cache3.ReadExReq_hits::l0subsys4.tester0 45 # number of ReadExReq hits @@ -2669,6 +2724,8 @@ system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys4.tester1 87375.7 system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys5.tester0 86334.880792 # average overall mshr miss latency system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys5.tester1 87645.156672 # average overall mshr miss latency system.l2subsys0.cache3.overall_avg_mshr_miss_latency::total 87740.882016 # average overall mshr miss latency +system.l2subsys0.checkers.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states +system.l2subsys0.tester.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l2subsys0.tester.numPackets 68517 # Number of packets generated system.l2subsys0.tester.numRetries 121 # Number of retries system.l2subsys0.tester.retryTicks 5829034 # Time spent waiting due to back-pressure (ticks) @@ -2678,6 +2735,7 @@ system.l2subsys0.xbar.snoop_filter.hit_multi_requests 120892 system.l2subsys0.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2subsys0.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2subsys0.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2subsys0.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l2subsys0.xbar.trans_dist::ReadResp 374921 # Transaction distribution system.l2subsys0.xbar.trans_dist::ReadRespWithInvalidate 1348 # Transaction distribution system.l2subsys0.xbar.trans_dist::WritebackDirty 151339 # Transaction distribution diff --git a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt index bdf77ebe4..40be86e31 100644 --- a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt +++ b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt @@ -4,11 +4,12 @@ sim_seconds 0.000014 # Nu sim_ticks 14181 # Number of ticks simulated final_tick 14181 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 154609 # Simulator tick rate (ticks/s) -host_mem_usage 480252 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 238683 # Simulator tick rate (ticks/s) +host_mem_usage 530468 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::dir_cntrl0 16576 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 16576 # Number of bytes read from this memory system.mem_ctrls.bytes_written::dir_cntrl0 576 # Number of bytes written to this memory @@ -238,7 +239,9 @@ system.mem_ctrls_1.memoryStateTime::REF 260 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 2 system.ruby.outstanding_req_hist_seqr::max_bucket 19 system.ruby.outstanding_req_hist_seqr::samples 63 @@ -319,11 +322,15 @@ system.cp_cntrl0.L2cache.num_data_array_reads 81 system.cp_cntrl0.L2cache.num_data_array_writes 84 # number of data array writes system.cp_cntrl0.L2cache.num_tag_array_reads 380 # number of tag array reads system.cp_cntrl0.L2cache.num_tag_array_writes 371 # number of tag array writes +system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.cp_cntrl0.sequencer.store_waiting_on_load 2 # Number of times a store aliased with a pending load system.cp_cntrl0.sequencer.store_waiting_on_store 3 # Number of times a store aliased with a pending store +system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.cp_cntrl0.sequencer1.store_waiting_on_load 1 # Number of times a store aliased with a pending load system.cp_cntrl0.sequencer1.store_waiting_on_store 4 # Number of times a store aliased with a pending store +system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.cp_cntrl0.fully_busy_cycles 2 # cycles for which number of transistions == max transitions +system.cpu.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses system.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses @@ -332,6 +339,8 @@ system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 378 system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 378 # number of tag array writes system.dir_cntrl0.L3CacheMemory.num_tag_array_stalls 10169 # number of stalls caused by tag array system.dir_cntrl0.L3CacheMemory.num_data_array_stalls 5502 # number of stalls caused by data array +system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links00.int_node.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.ruby.network.ext_links00.int_node.percent_links_utilized 0.199210 system.ruby.network.ext_links00.int_node.msg_count.Control::0 308 system.ruby.network.ext_links00.int_node.msg_count.Request_Control::0 385 @@ -347,6 +356,7 @@ system.ruby.network.ext_links00.int_node.msg_bytes.Response_Control::2 1 system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Data::2 4752 system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Control::2 560 system.ruby.network.ext_links00.int_node.msg_bytes.Unblock_Control::4 2424 +system.ruby.network.ext_links01.int_node.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.ruby.network.ext_links01.int_node.percent_links_utilized 0.120981 system.ruby.network.ext_links01.int_node.msg_count.Control::0 227 system.ruby.network.ext_links01.int_node.msg_count.Request_Control::0 153 @@ -370,6 +380,7 @@ system.tcp_cntrl0.L1cache.num_data_array_writes 116 system.tcp_cntrl0.L1cache.num_tag_array_reads 314 # number of tag array reads system.tcp_cntrl0.L1cache.num_tag_array_writes 305 # number of tag array writes system.tcp_cntrl0.L1cache.num_tag_array_stalls 38 # number of stalls caused by tag array +system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 5 # TCP to TCP load transfers system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC @@ -386,6 +397,9 @@ system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links02.int_node.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.ruby.network.ext_links02.int_node.percent_links_utilized 0.173894 system.ruby.network.ext_links02.int_node.msg_count.Control::0 81 system.ruby.network.ext_links02.int_node.msg_count.Control::1 814 @@ -415,6 +429,7 @@ system.tcp_cntrl1.L1cache.num_data_array_writes 108 system.tcp_cntrl1.L1cache.num_tag_array_reads 300 # number of tag array reads system.tcp_cntrl1.L1cache.num_tag_array_writes 289 # number of tag array writes system.tcp_cntrl1.L1cache.num_tag_array_stalls 44 # number of stalls caused by tag array +system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 4 # TCP to TCP load transfers system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC @@ -431,6 +446,8 @@ system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.tcp_cntrl2.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl2.L1cache.demand_misses 0 # Number of cache demand misses system.tcp_cntrl2.L1cache.demand_accesses 0 # Number of cache demand accesses @@ -440,6 +457,7 @@ system.tcp_cntrl2.L1cache.num_tag_array_reads 302 system.tcp_cntrl2.L1cache.num_tag_array_writes 292 # number of tag array writes system.tcp_cntrl2.L1cache.num_tag_array_stalls 36 # number of stalls caused by tag array system.tcp_cntrl2.L1cache.num_data_array_stalls 3 # number of stalls caused by data array +system.tcp_cntrl2.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.tcp_cntrl2.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP system.tcp_cntrl2.coalescer.gpu_tcp_ld_transfers 9 # TCP to TCP load transfers system.tcp_cntrl2.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC @@ -456,6 +474,8 @@ system.tcp_cntrl2.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl2.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl2.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl2.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.tcp_cntrl2.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.tcp_cntrl3.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl3.L1cache.demand_misses 0 # Number of cache demand misses system.tcp_cntrl3.L1cache.demand_accesses 0 # Number of cache demand accesses @@ -465,6 +485,7 @@ system.tcp_cntrl3.L1cache.num_tag_array_reads 272 system.tcp_cntrl3.L1cache.num_tag_array_writes 262 # number of tag array writes system.tcp_cntrl3.L1cache.num_tag_array_stalls 16 # number of stalls caused by tag array system.tcp_cntrl3.L1cache.num_data_array_stalls 3 # number of stalls caused by data array +system.tcp_cntrl3.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.tcp_cntrl3.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP system.tcp_cntrl3.coalescer.gpu_tcp_ld_transfers 13 # TCP to TCP load transfers system.tcp_cntrl3.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC @@ -481,6 +502,8 @@ system.tcp_cntrl3.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl3.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl3.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl3.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.tcp_cntrl3.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.tcp_cntrl4.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl4.L1cache.demand_misses 0 # Number of cache demand misses system.tcp_cntrl4.L1cache.demand_accesses 0 # Number of cache demand accesses @@ -489,6 +512,7 @@ system.tcp_cntrl4.L1cache.num_data_array_writes 115 system.tcp_cntrl4.L1cache.num_tag_array_reads 317 # number of tag array reads system.tcp_cntrl4.L1cache.num_tag_array_writes 309 # number of tag array writes system.tcp_cntrl4.L1cache.num_tag_array_stalls 29 # number of stalls caused by tag array +system.tcp_cntrl4.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.tcp_cntrl4.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP system.tcp_cntrl4.coalescer.gpu_tcp_ld_transfers 4 # TCP to TCP load transfers system.tcp_cntrl4.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC @@ -505,6 +529,8 @@ system.tcp_cntrl4.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl4.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl4.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl4.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.tcp_cntrl4.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.tcp_cntrl5.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl5.L1cache.demand_misses 0 # Number of cache demand misses system.tcp_cntrl5.L1cache.demand_accesses 0 # Number of cache demand accesses @@ -513,6 +539,7 @@ system.tcp_cntrl5.L1cache.num_data_array_writes 107 system.tcp_cntrl5.L1cache.num_tag_array_reads 295 # number of tag array reads system.tcp_cntrl5.L1cache.num_tag_array_writes 287 # number of tag array writes system.tcp_cntrl5.L1cache.num_tag_array_stalls 31 # number of stalls caused by tag array +system.tcp_cntrl5.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.tcp_cntrl5.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP system.tcp_cntrl5.coalescer.gpu_tcp_ld_transfers 6 # TCP to TCP load transfers system.tcp_cntrl5.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC @@ -529,6 +556,8 @@ system.tcp_cntrl5.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl5.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl5.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl5.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.tcp_cntrl5.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.tcp_cntrl6.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl6.L1cache.demand_misses 0 # Number of cache demand misses system.tcp_cntrl6.L1cache.demand_accesses 0 # Number of cache demand accesses @@ -537,6 +566,7 @@ system.tcp_cntrl6.L1cache.num_data_array_writes 123 system.tcp_cntrl6.L1cache.num_tag_array_reads 342 # number of tag array reads system.tcp_cntrl6.L1cache.num_tag_array_writes 335 # number of tag array writes system.tcp_cntrl6.L1cache.num_tag_array_stalls 49 # number of stalls caused by tag array +system.tcp_cntrl6.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.tcp_cntrl6.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP system.tcp_cntrl6.coalescer.gpu_tcp_ld_transfers 11 # TCP to TCP load transfers system.tcp_cntrl6.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC @@ -553,6 +583,8 @@ system.tcp_cntrl6.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl6.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl6.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl6.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.tcp_cntrl6.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.tcp_cntrl7.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl7.L1cache.demand_misses 0 # Number of cache demand misses system.tcp_cntrl7.L1cache.demand_accesses 0 # Number of cache demand accesses @@ -561,6 +593,7 @@ system.tcp_cntrl7.L1cache.num_data_array_writes 97 system.tcp_cntrl7.L1cache.num_tag_array_reads 263 # number of tag array reads system.tcp_cntrl7.L1cache.num_tag_array_writes 256 # number of tag array writes system.tcp_cntrl7.L1cache.num_tag_array_stalls 11 # number of stalls caused by tag array +system.tcp_cntrl7.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.tcp_cntrl7.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP system.tcp_cntrl7.coalescer.gpu_tcp_ld_transfers 10 # TCP to TCP load transfers system.tcp_cntrl7.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC @@ -577,6 +610,8 @@ system.tcp_cntrl7.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl7.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl7.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl7.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.tcp_cntrl7.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses @@ -584,6 +619,8 @@ system.sqc_cntrl0.L1cache.num_data_array_reads 12 system.sqc_cntrl0.L1cache.num_data_array_writes 12 # number of data array writes system.sqc_cntrl0.L1cache.num_tag_array_reads 22 # number of tag array reads system.sqc_cntrl0.L1cache.num_tag_array_writes 22 # number of tag array writes +system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.sqc_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits system.sqc_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses system.sqc_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses @@ -591,14 +628,19 @@ system.sqc_cntrl1.L1cache.num_data_array_reads 15 system.sqc_cntrl1.L1cache.num_data_array_writes 15 # number of data array writes system.sqc_cntrl1.L1cache.num_tag_array_reads 29 # number of tag array reads system.sqc_cntrl1.L1cache.num_tag_array_writes 29 # number of tag array writes +system.sqc_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.sqc_cntrl1.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses +system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses system.tccdir_cntrl0.directory.num_tag_array_reads 917 # number of tag array reads system.tccdir_cntrl0.directory.num_tag_array_writes 902 # number of tag array writes +system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 1430 system.ruby.network.msg_count.Request_Control 1616 system.ruby.network.msg_count.Response_Data 2430 @@ -613,6 +655,7 @@ system.ruby.network.msg_byte.Response_Control 3648 system.ruby.network.msg_byte.Writeback_Data 9504 system.ruby.network.msg_byte.Writeback_Control 1120 system.ruby.network.msg_byte.Unblock_Control 11496 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states system.ruby.network.ext_links00.int_node.throttle0.link_utilization 0.250555 system.ruby.network.ext_links00.int_node.throttle0.msg_count.Request_Control::0 385 system.ruby.network.ext_links00.int_node.throttle0.msg_count.Response_Data::2 85 diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt index 16afa43a3..da6a7f59a 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,12 @@ sim_seconds 0.000043 # Nu sim_ticks 43191 # Number of ticks simulated final_tick 43191 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 667875 # Simulator tick rate (ticks/s) -host_mem_usage 406088 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 648785 # Simulator tick rate (ticks/s) +host_mem_usage 451080 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 57728 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 57728 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 51904 # Number of bytes written to this memory @@ -265,7 +266,10 @@ system.mem_ctrls_1.memoryStateTime::REF 1300 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 4 # delay histogram for all message system.ruby.delayHist::max_bucket 39 # delay histogram for all message system.ruby.delayHist::samples 6720 # delay histogram for all message @@ -304,6 +308,7 @@ system.ruby.miss_latency_hist_seqr::gmean 632.888578 system.ruby.miss_latency_hist_seqr::stdev 227.503250 system.ruby.miss_latency_hist_seqr | 65 6.94% 6.94% | 24 2.56% 9.51% | 5 0.53% 10.04% | 4 0.43% 10.47% | 32 3.42% 13.89% | 302 32.26% 46.15% | 418 44.66% 90.81% | 49 5.24% 96.05% | 28 2.99% 99.04% | 9 0.96% 100.00% system.ruby.miss_latency_hist_seqr::total 936 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 89 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 875 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 964 # Number of cache demand accesses @@ -319,13 +324,17 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 4 # Number of times a store aliased with a pending load system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 80 # Number of times a store aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 6 # Number of times a load aliased with a pending store +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states system.ruby.l2_cntrl0.L2cache.demand_hits 34 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 904 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 938 # Number of cache demand accesses +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 11.804543 system.ruby.network.routers0.msg_count.Control::0 939 system.ruby.network.routers0.msg_count.Request_Control::2 278 @@ -343,6 +352,7 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 6984 system.ruby.network.routers0.msg_bytes.Writeback_Data::0 56520 system.ruby.network.routers0.msg_bytes.Writeback_Data::1 15336 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 200 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 21.822255 system.ruby.network.routers1.msg_count.Control::0 1842 system.ruby.network.routers1.msg_count.Request_Control::2 279 @@ -360,6 +370,7 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2 6984 system.ruby.network.routers1.msg_bytes.Writeback_Data::0 56520 system.ruby.network.routers1.msg_bytes.Writeback_Data::1 15336 system.ruby.network.routers1.msg_bytes.Writeback_Control::0 200 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 10.015976 system.ruby.network.routers2.msg_count.Control::0 902 system.ruby.network.routers2.msg_count.Response_Data::1 1713 @@ -367,6 +378,7 @@ system.ruby.network.routers2.msg_count.Response_Control::1 985 system.ruby.network.routers2.msg_bytes.Control::0 7216 system.ruby.network.routers2.msg_bytes.Response_Data::1 123336 system.ruby.network.routers2.msg_bytes.Response_Control::1 7880 +system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states system.ruby.network.routers3.percent_links_utilized 14.547012 system.ruby.network.routers3.msg_count.Control::0 1841 system.ruby.network.routers3.msg_count.Request_Control::2 278 @@ -384,6 +396,7 @@ system.ruby.network.routers3.msg_bytes.Response_Control::2 6984 system.ruby.network.routers3.msg_bytes.Writeback_Data::0 56520 system.ruby.network.routers3.msg_bytes.Writeback_Data::1 15336 system.ruby.network.routers3.msg_bytes.Writeback_Control::0 200 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 5524 system.ruby.network.msg_count.Request_Control 835 system.ruby.network.msg_count.Response_Data 7947 @@ -396,6 +409,7 @@ system.ruby.network.msg_byte.Response_Data 572184 system.ruby.network.msg_byte.Response_Control 65552 system.ruby.network.msg_byte.Writeback_Data 215568 system.ruby.network.msg_byte.Writeback_Control 600 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.throttle0.link_utilization 11.009238 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 278 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 936 diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt index 75f44776f..ade451317 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,12 @@ sim_seconds 0.000054 # Nu sim_ticks 54211 # Number of ticks simulated final_tick 54211 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 538772 # Simulator tick rate (ticks/s) -host_mem_usage 406688 # Number of bytes of host memory used +host_tick_rate 528623 # Simulator tick rate (ticks/s) +host_mem_usage 452196 # Number of bytes of host memory used host_seconds 0.10 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54016 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 54016 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 48256 # Number of bytes written to this memory @@ -265,7 +266,10 @@ system.mem_ctrls_1.memoryStateTime::REF 1560 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 2 system.ruby.outstanding_req_hist_seqr::max_bucket 19 system.ruby.outstanding_req_hist_seqr::samples 985 @@ -297,19 +301,24 @@ system.ruby.miss_latency_hist_seqr::gmean 862.901849 system.ruby.miss_latency_hist_seqr::stdev 251.425992 system.ruby.miss_latency_hist_seqr | 54 6.15% 6.15% | 6 0.68% 6.83% | 4 0.46% 7.29% | 388 44.19% 51.48% | 418 47.61% 99.09% | 8 0.91% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 878 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 90 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 836 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 926 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 2 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 44 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 46 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 7 # Number of times a store aliased with a pending load system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 75 # Number of times a store aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 2 # Number of times a load aliased with a pending store +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states system.ruby.l2_cntrl0.L2cache.demand_hits 36 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 844 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 880 # Number of cache demand accesses +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 8.888879 system.ruby.network.routers0.msg_count.Request_Control::0 880 system.ruby.network.routers0.msg_count.Response_Data::2 843 @@ -323,6 +332,7 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 2520 system.ruby.network.routers0.msg_bytes.Writeback_Data::2 62928 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 13992 system.ruby.network.routers0.msg_bytes.Unblock_Control::2 7024 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 16.994245 system.ruby.network.routers1.msg_count.Request_Control::0 880 system.ruby.network.routers1.msg_count.Request_Control::1 844 @@ -340,6 +350,7 @@ system.ruby.network.routers1.msg_bytes.Writeback_Data::2 117216 system.ruby.network.routers1.msg_bytes.Writeback_Control::0 13992 system.ruby.network.routers1.msg_bytes.Writeback_Control::1 12072 system.ruby.network.routers1.msg_bytes.Unblock_Control::2 13760 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 8.101677 system.ruby.network.routers2.msg_count.Request_Control::1 844 system.ruby.network.routers2.msg_count.Response_Data::2 843 @@ -351,6 +362,7 @@ system.ruby.network.routers2.msg_bytes.Response_Data::2 60696 system.ruby.network.routers2.msg_bytes.Writeback_Data::2 54288 system.ruby.network.routers2.msg_bytes.Writeback_Control::1 12072 system.ruby.network.routers2.msg_bytes.Unblock_Control::2 6736 +system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states system.ruby.network.routers3.percent_links_utilized 11.328267 system.ruby.network.routers3.msg_count.Request_Control::0 880 system.ruby.network.routers3.msg_count.Request_Control::1 844 @@ -368,6 +380,7 @@ system.ruby.network.routers3.msg_bytes.Writeback_Data::2 117216 system.ruby.network.routers3.msg_bytes.Writeback_Control::0 13992 system.ruby.network.routers3.msg_bytes.Writeback_Control::1 12072 system.ruby.network.routers3.msg_bytes.Unblock_Control::2 13760 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Request_Control 5172 system.ruby.network.msg_count.Response_Data 5058 system.ruby.network.msg_count.ResponseL2hit_Data 107 @@ -380,6 +393,7 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 7704 system.ruby.network.msg_byte.Writeback_Data 351648 system.ruby.network.msg_byte.Writeback_Control 78192 system.ruby.network.msg_byte.Unblock_Control 41280 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.throttle0.link_utilization 8.094298 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 843 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 35 diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt index f8400a6e4..22bd0b2f6 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,12 @@ sim_seconds 0.000050 # Nu sim_ticks 50141 # Number of ticks simulated final_tick 50141 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 969830 # Simulator tick rate (ticks/s) -host_mem_usage 406616 # Number of bytes of host memory used +host_tick_rate 922495 # Simulator tick rate (ticks/s) +host_mem_usage 453168 # Number of bytes of host memory used host_seconds 0.05 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 50624 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 50624 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 46016 # Number of bytes written to this memory @@ -262,7 +263,10 @@ system.mem_ctrls_1.memoryStateTime::REF 1560 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 2 system.ruby.outstanding_req_hist_seqr::max_bucket 19 system.ruby.outstanding_req_hist_seqr::samples 961 @@ -296,19 +300,24 @@ system.ruby.miss_latency_hist_seqr::stdev 316.811320 system.ruby.miss_latency_hist_seqr | 76 9.62% 9.62% | 7 0.89% 10.51% | 5 0.63% 11.14% | 245 31.01% 42.15% | 403 51.01% 93.16% | 54 6.84% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 790 system.ruby.Directory.incomplete_times_seqr 790 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 105 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 788 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 893 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 1 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 54 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 55 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 6 # Number of times a store aliased with a pending load system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 74 # Number of times a store aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 6 # Number of times a load aliased with a pending store +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states system.ruby.l2_cntrl0.L2cache.demand_hits 48 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 793 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 841 # Number of cache demand accesses +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 8.090684 system.ruby.network.routers0.msg_count.Request_Control::1 841 system.ruby.network.routers0.msg_count.Response_Data::4 790 @@ -322,6 +331,7 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 3600 system.ruby.network.routers0.msg_bytes.Response_Control::4 8 system.ruby.network.routers0.msg_bytes.Writeback_Data::4 62064 system.ruby.network.routers0.msg_bytes.Persistent_Control::3 544 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 8.057777 system.ruby.network.routers1.msg_count.Request_Control::1 841 system.ruby.network.routers1.msg_count.Request_Control::2 793 @@ -337,6 +347,7 @@ system.ruby.network.routers1.msg_bytes.Response_Control::4 8 system.ruby.network.routers1.msg_bytes.Writeback_Data::4 111816 system.ruby.network.routers1.msg_bytes.Writeback_Control::4 520 system.ruby.network.routers1.msg_bytes.Persistent_Control::3 272 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 7.216150 system.ruby.network.routers2.msg_count.Request_Control::2 793 system.ruby.network.routers2.msg_count.Response_Data::4 790 @@ -348,6 +359,7 @@ system.ruby.network.routers2.msg_bytes.Response_Data::4 56880 system.ruby.network.routers2.msg_bytes.Writeback_Data::4 51768 system.ruby.network.routers2.msg_bytes.Writeback_Control::4 520 system.ruby.network.routers2.msg_bytes.Persistent_Control::3 272 +system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states system.ruby.network.routers3.percent_links_utilized 7.788370 system.ruby.network.routers3.msg_count.Request_Control::1 841 system.ruby.network.routers3.msg_count.Request_Control::2 793 @@ -365,6 +377,7 @@ system.ruby.network.routers3.msg_bytes.Response_Control::4 8 system.ruby.network.routers3.msg_bytes.Writeback_Data::4 112824 system.ruby.network.routers3.msg_bytes.Writeback_Control::4 520 system.ruby.network.routers3.msg_bytes.Persistent_Control::3 544 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Request_Control 4902 system.ruby.network.msg_count.Response_Data 2370 system.ruby.network.msg_count.ResponseL2hit_Data 150 @@ -379,6 +392,7 @@ system.ruby.network.msg_byte.Response_Control 24 system.ruby.network.msg_byte.Writeback_Data 338472 system.ruby.network.msg_byte.Writeback_Control 1560 system.ruby.network.msg_byte.Persistent_Control 1632 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.throttle0.link_utilization 7.698291 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 790 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 50 diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt index c2eacbfda..7a535a15b 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,12 @@ sim_seconds 0.000030 # Nu sim_ticks 29561 # Number of ticks simulated final_tick 29561 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 593739 # Simulator tick rate (ticks/s) -host_mem_usage 406316 # Number of bytes of host memory used +host_tick_rate 585115 # Simulator tick rate (ticks/s) +host_mem_usage 452068 # Number of bytes of host memory used host_seconds 0.05 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 56000 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 56000 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 50560 # Number of bytes written to this memory @@ -261,7 +262,10 @@ system.mem_ctrls_1.memoryStateTime::REF 780 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 2 system.ruby.outstanding_req_hist_seqr::max_bucket 19 system.ruby.outstanding_req_hist_seqr::samples 1027 @@ -298,6 +302,7 @@ system.ruby.Directory.incomplete_times_seqr 872 system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 96 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 859 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 955 # Number of cache demand accesses @@ -307,11 +312,14 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 57 system.ruby.l1_cntrl0.L2cache.demand_hits 39 # Number of cache demand hits system.ruby.l1_cntrl0.L2cache.demand_misses 874 # Number of cache demand misses system.ruby.l1_cntrl0.L2cache.demand_accesses 913 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 8 # Number of times a store aliased with a pending load system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 72 # Number of times a store aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 4 # Number of times a load aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 3 # Number of times a load aliased with a pending load +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 15.685362 system.ruby.network.routers0.msg_count.Request_Control::2 876 system.ruby.network.routers0.msg_count.Response_Data::4 874 @@ -327,6 +335,7 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2 6952 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 6952 system.ruby.network.routers0.msg_bytes.Writeback_Control::5 616 system.ruby.network.routers0.msg_bytes.Unblock_Control::5 6968 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 15.679443 system.ruby.network.routers1.msg_count.Request_Control::2 876 system.ruby.network.routers1.msg_count.Response_Data::4 874 @@ -342,6 +351,7 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::2 6952 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 6952 system.ruby.network.routers1.msg_bytes.Writeback_Control::5 616 system.ruby.network.routers1.msg_bytes.Unblock_Control::5 6968 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 15.682825 system.ruby.network.routers2.msg_count.Request_Control::2 876 system.ruby.network.routers2.msg_count.Response_Data::4 874 @@ -357,6 +367,7 @@ system.ruby.network.routers2.msg_bytes.Writeback_Control::2 6952 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 6952 system.ruby.network.routers2.msg_bytes.Writeback_Control::5 616 system.ruby.network.routers2.msg_bytes.Unblock_Control::5 6968 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Request_Control 2628 system.ruby.network.msg_count.Response_Data 2622 system.ruby.network.msg_count.Writeback_Data 2373 @@ -367,6 +378,7 @@ system.ruby.network.msg_byte.Response_Data 188784 system.ruby.network.msg_byte.Writeback_Data 170856 system.ruby.network.msg_byte.Writeback_Control 43560 system.ruby.network.msg_byte.Unblock_Control 20904 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.throttle0.link_utilization 14.774534 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 874 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 869 diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt index 3208bfd4e..4e47c8bcd 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt @@ -4,11 +4,12 @@ sim_seconds 0.000038 # Nu sim_ticks 37741 # Number of ticks simulated final_tick 37741 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 877206 # Simulator tick rate (ticks/s) -host_mem_usage 404076 # Number of bytes of host memory used +host_tick_rate 891959 # Simulator tick rate (ticks/s) +host_mem_usage 449872 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 60992 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 60992 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 60800 # Number of bytes written to this memory @@ -259,7 +260,10 @@ system.mem_ctrls_1.memoryStateTime::REF 1040 # Ti system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 1903 # delay histogram for all message @@ -300,14 +304,18 @@ system.ruby.miss_latency_hist_seqr::stdev 94.945507 system.ruby.miss_latency_hist_seqr | 2 0.21% 0.21% | 9 0.94% 1.15% | 5 0.52% 1.68% | 89 9.34% 11.02% | 639 67.05% 78.07% | 153 16.05% 94.12% | 49 5.14% 99.27% | 7 0.73% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 953 system.ruby.Directory.incomplete_times_seqr 953 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 39 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 955 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 994 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 7 # Number of times a store aliased with a pending load system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 129 # Number of times a store aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 6 # Number of times a load aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 12.606979 system.ruby.network.routers0.msg_count.Control::2 953 system.ruby.network.routers0.msg_count.Data::2 951 @@ -317,6 +325,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 7624 system.ruby.network.routers0.msg_bytes.Data::2 68472 system.ruby.network.routers0.msg_bytes.Response_Data::4 68616 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 7600 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 12.605654 system.ruby.network.routers1.msg_count.Control::2 953 system.ruby.network.routers1.msg_count.Data::2 950 @@ -326,6 +335,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 7624 system.ruby.network.routers1.msg_bytes.Data::2 68400 system.ruby.network.routers1.msg_bytes.Response_Data::4 68616 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 7600 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 12.605654 system.ruby.network.routers2.msg_count.Control::2 953 system.ruby.network.routers2.msg_count.Data::2 950 @@ -335,6 +345,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 7624 system.ruby.network.routers2.msg_bytes.Data::2 68400 system.ruby.network.routers2.msg_bytes.Response_Data::4 68616 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 7600 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 2859 system.ruby.network.msg_count.Data 2851 system.ruby.network.msg_count.Response_Data 2859 @@ -343,6 +354,7 @@ system.ruby.network.msg_byte.Control 22872 system.ruby.network.msg_byte.Data 205272 system.ruby.network.msg_byte.Response_Data 205848 system.ruby.network.msg_byte.Writeback_Control 22800 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.throttle0.link_utilization 12.621552 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 953 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 950 diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt index 238ebf7d9..c0bb5bc83 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt @@ -4,11 +4,12 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 9064709748 # Simulator tick rate (ticks/s) -host_mem_usage 219696 # Number of bytes of host memory used -host_seconds 11.03 # Real time elapsed on the host +host_tick_rate 10668065661 # Simulator tick rate (ticks/s) +host_mem_usage 263968 # Number of bytes of host memory used +host_seconds 9.37 # Real time elapsed on the host system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu 106649408 # Number of bytes read from this memory system.physmem.bytes_read::total 106649408 # Number of bytes read from this memory system.physmem.bytes_written::cpu 106680256 # Number of bytes written to this memory @@ -272,9 +273,12 @@ system.physmem_1.memoryStateTime::REF 3339180000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 96120321460 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states system.cpu.numPackets 3333276 # Number of packets generated system.cpu.numRetries 0 # Number of retries system.cpu.retryTicks 0 # Time spent waiting due to back-pressure (ticks) +system.membus.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 1666397 # Transaction distribution system.membus.trans_dist::ReadResp 1666397 # Transaction distribution system.membus.trans_dist::WriteReq 1666879 # Transaction distribution @@ -287,6 +291,7 @@ system.membus.reqLayer0.occupancy 11679751447 # La system.membus.reqLayer0.utilization 11.7 # Layer utilization (%) system.membus.respLayer0.occupancy 11025969759 # Layer occupancy (ticks) system.membus.respLayer0.utilization 11.0 # Layer utilization (%) +system.monitor.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states system.monitor.readBurstLengthHist::samples 1666397 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt index cbbc1075a..bb8dbf182 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt @@ -4,11 +4,12 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 16220790107 # Simulator tick rate (ticks/s) -host_mem_usage 221740 # Number of bytes of host memory used -host_seconds 6.17 # Real time elapsed on the host +host_tick_rate 18414287723 # Simulator tick rate (ticks/s) +host_mem_usage 264992 # Number of bytes of host memory used +host_seconds 5.43 # Real time elapsed on the host system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory system.physmem.bytes_read::total 64 # Number of bytes read from this memory system.physmem.bytes_written::cpu 853312 # Number of bytes written to this memory @@ -23,9 +24,12 @@ system.physmem.bw_write::cpu 8533120 # Wr system.physmem.bw_write::total 8533120 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu 8533760 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 8533760 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states system.cpu.numPackets 13334 # Number of packets generated system.cpu.numRetries 1 # Number of retries system.cpu.retryTicks 1672 # Time spent waiting due to back-pressure (ticks) +system.membus.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 1 # Transaction distribution system.membus.trans_dist::ReadResp 1 # Transaction distribution system.membus.trans_dist::WriteReq 13333 # Transaction distribution @@ -38,6 +42,7 @@ system.membus.reqLayer0.occupancy 66667328 # La system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.respLayer0.occupancy 13338000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) +system.monitor.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states system.monitor.readBurstLengthHist::samples 1 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index 185d54bdc..ba862710c 100644 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.045952 # Nu sim_ticks 45951567500 # Number of ticks simulated final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1593313 # Simulator instruction rate (inst/s) -host_op_rate 1593310 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 796655733 # Simulator tick rate (ticks/s) -host_mem_usage 242160 # Number of bytes of host memory used -host_seconds 57.68 # Real time elapsed on the host +host_inst_rate 3168591 # Simulator instruction rate (inst/s) +host_op_rate 3168590 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1584296087 # Simulator tick rate (ticks/s) +host_mem_usage 288936 # Number of bytes of host memory used +host_seconds 29.00 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 45951567500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 367612356 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 108337521 # Number of bytes read from this memory system.physmem.bytes_read::total 475949877 # Number of bytes read from this memory @@ -35,6 +36,7 @@ system.physmem.bw_write::total 672903574 # Wr system.physmem.bw_total::cpu.inst 7999995996 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3030549393 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11030545389 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 45951567500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -69,6 +71,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 45951567500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 91903136 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -127,6 +130,7 @@ system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91903089 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 45951567500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 111899287 # Transaction distribution system.membus.trans_dist::ReadResp 111899287 # Transaction distribution system.membus.trans_dist::WriteReq 6501103 # Transaction distribution diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 356207999..12386b790 100644 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.118763 # Nu sim_ticks 118762761500 # Number of ticks simulated final_tick 118762761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 940295 # Simulator instruction rate (inst/s) -host_op_rate 940295 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1215106876 # Simulator tick rate (ticks/s) -host_mem_usage 251128 # Number of bytes of host memory used -host_seconds 97.74 # Real time elapsed on the host +host_inst_rate 1861883 # Simulator instruction rate (inst/s) +host_op_rate 1861883 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2406038400 # Simulator tick rate (ticks/s) +host_mem_usage 298932 # Number of bytes of host memory used +host_seconds 49.36 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory system.physmem.bytes_read::total 304960 # Number of bytes read from this memory @@ -29,6 +30,7 @@ system.physmem.bw_inst_read::total 1412429 # In system.physmem.bw_total::cpu.inst 1412429 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1155379 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2567808 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -63,6 +65,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 118762761500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 237525523 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -121,6 +124,7 @@ system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91903089 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 157 # number of replacements system.cpu.dcache.tags.tagsinuse 1441.946319 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. @@ -139,6 +143,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits @@ -227,6 +232,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59260.683761 system.cpu.dcache.demand_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59260.683761 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 6681 # number of replacements system.cpu.icache.tags.tagsinuse 1417.953327 # Cycle average of tags in use system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. @@ -245,6 +251,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 953 system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 183814690 # Number of tag accesses system.cpu.icache.tags.data_accesses 183814690 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits @@ -313,6 +320,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27101.645123 system.cpu.icache.demand_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27101.645123 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 2073.923151 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 12687 # Total number of references to valid blocks. @@ -335,6 +343,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2096 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.094879 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 145425 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 145425 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 6681 # number of WritebackClean hits @@ -475,6 +484,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 6681 # Transaction distribution @@ -507,6 +517,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 12765000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3043 # Transaction distribution system.membus.trans_dist::ReadExReq 1722 # Transaction distribution system.membus.trans_dist::ReadExResp 1722 # Transaction distribution diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index 5f1cdd65c..a504e35f9 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.099596 # Nu sim_ticks 99596491500 # Number of ticks simulated final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2176341 # Simulator instruction rate (inst/s) -host_op_rate 2294214 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1257887009 # Simulator tick rate (ticks/s) -host_mem_usage 304976 # Number of bytes of host memory used -host_seconds 79.18 # Real time elapsed on the host +host_inst_rate 2111044 # Simulator instruction rate (inst/s) +host_op_rate 2225381 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1220146763 # Simulator tick rate (ticks/s) +host_mem_usage 306656 # Number of bytes of host memory used +host_seconds 81.63 # Real time elapsed on the host sim_insts 172317410 # Number of instructions simulated sim_ops 181650342 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 759440208 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 110533661 # Number of bytes read from this memory system.physmem.bytes_read::total 869973869 # Number of bytes read from this memory @@ -35,7 +36,9 @@ system.physmem.bw_write::total 454362792 # Wr system.physmem.bw_total::cpu.inst 7625170290 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1564177600 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9189347890 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -65,6 +68,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -94,6 +98,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -123,6 +128,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,6 +159,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 99596491500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 199192984 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -213,6 +220,7 @@ system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650743 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 217614903 # Transaction distribution system.membus.trans_dist::ReadResp 217637310 # Transaction distribution system.membus.trans_dist::WriteReq 12364287 # Transaction distribution diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 84721fe7c..f6691b610 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.230198 # Nu sim_ticks 230197694500 # Number of ticks simulated final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1495549 # Simulator instruction rate (inst/s) -host_op_rate 1576687 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2003415873 # Simulator tick rate (ticks/s) -host_mem_usage 314964 # Number of bytes of host memory used -host_seconds 114.90 # Real time elapsed on the host +host_inst_rate 1499491 # Simulator instruction rate (inst/s) +host_op_rate 1580842 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2008696236 # Simulator tick rate (ticks/s) +host_mem_usage 315632 # Number of bytes of host memory used +host_seconds 114.60 # Real time elapsed on the host sim_insts 171842484 # Number of instructions simulated sim_ops 181165371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory system.physmem.bytes_read::total 220992 # Number of bytes read from this memory @@ -29,7 +30,9 @@ system.physmem.bw_inst_read::total 480700 # In system.physmem.bw_total::cpu.inst 480700 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 479310 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 960010 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -59,6 +62,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -88,6 +92,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -117,6 +122,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -147,6 +153,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 230197694500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 460395389 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -207,6 +214,7 @@ system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650743 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 40 # number of replacements system.cpu.dcache.tags.tagsinuse 1363.571253 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. @@ -225,6 +233,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits @@ -337,6 +346,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59278.803132 system.cpu.dcache.demand_avg_mshr_miss_latency::total 59278.803132 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59279.765232 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 59279.765232 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1506 # number of replacements system.cpu.icache.tags.tagsinuse 1147.958164 # Cycle average of tags in use system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks. @@ -355,6 +365,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 942 system.cpu.icache.tags.occ_task_id_percent::1024 0.754395 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 379723157 # Number of tag accesses system.cpu.icache.tags.data_accesses 379723157 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 189857002 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 189857002 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 189857002 # number of demand (read+write) hits @@ -423,6 +434,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39836.447067 system.cpu.icache.demand_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 1675.610098 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks. @@ -445,6 +457,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1679 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.072296 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 54045 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 54045 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1448 # number of WritebackClean hits @@ -585,6 +598,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1506 # Transaction distribution @@ -617,6 +631,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 4576500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 2361 # Transaction distribution system.membus.trans_dist::ReadExReq 1092 # Transaction distribution system.membus.trans_dist::ReadExResp 1092 # Transaction distribution diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index 4c392ae66..00d6259ce 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.096723 # Nu sim_ticks 96722945000 # Number of ticks simulated final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1393535 # Simulator instruction rate (inst/s) -host_op_rate 1393537 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 696772335 # Simulator tick rate (ticks/s) -host_mem_usage 242012 # Number of bytes of host memory used -host_seconds 138.82 # Real time elapsed on the host +host_inst_rate 2890225 # Simulator instruction rate (inst/s) +host_op_rate 2890229 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1445122551 # Simulator tick rate (ticks/s) +host_mem_usage 288744 # Number of bytes of host memory used +host_seconds 66.93 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 96722945000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 773782140 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 223463413 # Number of bytes read from this memory system.physmem.bytes_read::total 997245553 # Number of bytes read from this memory @@ -37,8 +38,10 @@ system.physmem.bw_write::total 745070490 # Wr system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3055415910 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11055401229 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 96722945000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 401 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 96722945000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 193445891 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -97,6 +100,7 @@ system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 193445773 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 96722945000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 251180603 # Transaction distribution system.membus.trans_dist::ReadResp 251180603 # Transaction distribution system.membus.trans_dist::WriteReq 18976439 # Transaction distribution diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 812685f18..a32bf8738 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.270600 # Nu sim_ticks 270599529500 # Number of ticks simulated final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 833752 # Simulator instruction rate (inst/s) -host_op_rate 833752 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1166291607 # Simulator tick rate (ticks/s) -host_mem_usage 251752 # Number of bytes of host memory used -host_seconds 232.02 # Real time elapsed on the host +host_inst_rate 1741327 # Simulator instruction rate (inst/s) +host_op_rate 1741329 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2435851420 # Simulator tick rate (ticks/s) +host_mem_usage 298736 # Number of bytes of host memory used +host_seconds 111.09 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory system.physmem.bytes_read::total 331072 # Number of bytes read from this memory @@ -29,8 +30,10 @@ system.physmem.bw_inst_read::total 850733 # In system.physmem.bw_total::cpu.inst 850733 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 372743 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1223476 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 401 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 270599529500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 541199059 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -89,6 +92,7 @@ system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 193445773 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2 # number of replacements system.cpu.dcache.tags.tagsinuse 1237.159344 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. @@ -107,6 +111,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits @@ -215,6 +220,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302 system.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 10362 # number of replacements system.cpu.icache.tags.tagsinuse 1591.528232 # Cycle average of tags in use system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. @@ -233,6 +239,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 687 system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits @@ -301,6 +308,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828 system.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 2678.246108 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks. @@ -323,6 +331,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 198999 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 198999 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 10362 # number of WritebackClean hits @@ -457,6 +466,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution @@ -488,6 +498,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 18432000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4095 # Transaction distribution system.membus.trans_dist::ReadExReq 1078 # Transaction distribution system.membus.trans_dist::ReadExResp 1078 # Transaction distribution diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index a92d8585c..044a8cac9 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.131393 # Nu sim_ticks 131393279000 # Number of ticks simulated final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 719836 # Simulator instruction rate (inst/s) -host_op_rate 1206511 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 716141111 # Simulator tick rate (ticks/s) -host_mem_usage 284280 # Number of bytes of host memory used -host_seconds 183.47 # Real time elapsed on the host +host_inst_rate 1595970 # Simulator instruction rate (inst/s) +host_op_rate 2674991 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1587777431 # Simulator tick rate (ticks/s) +host_mem_usage 331680 # Number of bytes of host memory used +host_seconds 82.75 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 310423752 # Number of bytes read from this memory system.physmem.bytes_read::total 1698378688 # Number of bytes read from this memory @@ -35,9 +36,14 @@ system.physmem.bw_write::total 759720678 # Wr system.physmem.bw_total::cpu.inst 10563363260 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3122274945 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13685638205 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 131393279000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 262786559 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -98,6 +104,7 @@ system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 221363385 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 230176372 # Transaction distribution system.membus.trans_dist::ReadResp 230176372 # Transaction distribution system.membus.trans_dist::WriteReq 20515731 # Transaction distribution diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index cbc3cc2d9..42017c57f 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.250987 # Nu sim_ticks 250987138500 # Number of ticks simulated final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 489633 # Simulator instruction rate (inst/s) -host_op_rate 820669 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 930494730 # Simulator tick rate (ticks/s) -host_mem_usage 293244 # Number of bytes of host memory used -host_seconds 269.74 # Real time elapsed on the host +host_inst_rate 1028477 # Simulator instruction rate (inst/s) +host_op_rate 1723822 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1954510825 # Simulator tick rate (ticks/s) +host_mem_usage 341680 # Number of bytes of host memory used +host_seconds 128.41 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory system.physmem.bytes_read::total 303040 # Number of bytes read from this memory @@ -29,9 +30,14 @@ system.physmem.bw_inst_read::total 724181 # In system.physmem.bw_total::cpu.inst 724181 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 483212 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1207393 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 250987138500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 501974277 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -92,6 +98,7 @@ system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 221363385 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 41 # number of replacements system.cpu.dcache.tags.tagsinuse 1363.414730 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. @@ -110,6 +117,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits @@ -198,6 +206,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60745.144357 system.cpu.dcache.demand_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2836 # number of replacements system.cpu.icache.tags.tagsinuse 1455.245085 # Cycle average of tags in use system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. @@ -216,6 +225,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 869 system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits @@ -284,6 +294,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41657.115467 system.cpu.icache.demand_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 2058.105553 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks. @@ -306,6 +317,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 80550 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 80550 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 7 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 7 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 2836 # number of WritebackClean hits @@ -446,6 +458,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2836 # Transaction distribution @@ -478,6 +491,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 7041000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3160 # Transaction distribution system.membus.trans_dist::ReadExReq 1575 # Transaction distribution system.membus.trans_dist::ReadExResp 1575 # Transaction distribution |