diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
| commit | c4e91289ae8806eb051fb1f41ece8be308f0ff85 (patch) | |
| tree | 6f35a7725cfd4072c8516ee0bb2ae799d48ce896 /tests/quick/se | |
| parent | cc6523e2d686447f90acccac20c0fb2940dc3e3b (diff) | |
| download | gem5-c4e91289ae8806eb051fb1f41ece8be308f0ff85.tar.xz | |
stats: Bump stats for filter, crossbar and config changes
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
Diffstat (limited to 'tests/quick/se')
43 files changed, 7809 insertions, 7089 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index b10a33b72..353f5c8e3 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000035 # Number of seconds simulated -sim_ticks 35015500 # Number of ticks simulated -final_tick 35015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 35024500 # Number of ticks simulated +final_tick 35024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57020 # Simulator instruction rate (inst/s) -host_op_rate 57008 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 311836228 # Simulator tick rate (ticks/s) -host_mem_usage 240292 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 173753 # Simulator instruction rate (inst/s) +host_op_rate 173686 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 950177695 # Simulator tick rate (ticks/s) +host_mem_usage 289108 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -19,12 +19,12 @@ system.physmem.bytes_inst_read::cpu.inst 23296 # Nu system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 533 # Number of read requests responded to by this memory system.physmem.num_reads::total 533 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 974197141 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 974197141 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 665305365 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 665305365 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 974197141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 974197141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 973946809 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 973946809 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 665134406 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 665134406 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 973946809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 973946809 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 533 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue @@ -71,7 +71,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 34917000 # Total gap between requests +system.physmem.totGap 34926000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -196,15 +196,15 @@ system.physmem.bytesPerActivate::768-895 1 1.11% 84.44% # By system.physmem.bytesPerActivate::896-1023 4 4.44% 88.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 11.11% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 90 # Bytes accessed per row activation -system.physmem.totQLat 3823500 # Total ticks spent queuing -system.physmem.totMemAccLat 13817250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3928000 # Total ticks spent queuing +system.physmem.totMemAccLat 13921750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7173.55 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7369.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25923.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 974.20 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26119.61 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 973.95 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 974.20 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 973.95 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 7.61 # Data bus utilization in percentage @@ -216,24 +216,32 @@ system.physmem.readRowHits 435 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 65510.32 # Average gap between requests +system.physmem.avgGap 65527.20 # Average gap between requests system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 15500 # Time in different power states system.physmem.memoryStateTime::REF 1040000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 30385500 # Time in different power states +system.physmem.memoryStateTime::ACT 30394500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 974197141 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 460 # Transaction distribution system.membus.trans_dist::ReadResp 460 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34112 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 533 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 533 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 533 # Request fanout histogram system.membus.reqLayer0.occupancy 618000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) system.membus.respLayer1.occupancy 4976250 # Layer occupancy (ticks) @@ -281,26 +289,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 70031 # number of cpu cycles simulated +system.cpu.numCycles 70049 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6400 # Number of instructions committed system.cpu.committedOps 6400 # Number of ops (including micro ops) committed system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 10.942344 # CPI: cycles per instruction -system.cpu.ipc 0.091388 # IPC: instructions per cycle -system.cpu.tickCycles 12510 # Number of cycles that the object actually ticked -system.cpu.idleCycles 57521 # Total number of cycles that the object has spent stopped +system.cpu.cpi 10.945156 # CPI: cycles per instruction +system.cpu.ipc 0.091365 # IPC: instructions per cycle +system.cpu.tickCycles 12515 # Number of cycles that the object actually ticked +system.cpu.idleCycles 57534 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 176.143820 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 176.176418 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2265 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 6.205479 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 176.143820 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.086008 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.086008 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 176.176418 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.086024 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.086024 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id @@ -319,12 +327,12 @@ system.cpu.icache.demand_misses::cpu.inst 365 # n system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25932750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25932750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25932750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25932750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25932750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25932750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25941750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25941750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25941750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25941750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25941750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25941750 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2630 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2630 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2630 # number of demand (read+write) accesses @@ -337,12 +345,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.138783 system.cpu.icache.demand_miss_rate::total 0.138783 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.138783 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.138783 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71048.630137 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71048.630137 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71048.630137 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71048.630137 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71048.630137 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71048.630137 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71073.287671 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 71073.287671 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 71073.287671 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 71073.287671 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 71073.287671 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 71073.287671 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -357,26 +365,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365 system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25045250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25045250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25045250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25045250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25045250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25045250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25054250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25054250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25054250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25054250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25054250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25054250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138783 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.138783 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.138783 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68617.123288 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68617.123288 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68617.123288 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68617.123288 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68617.123288 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68617.123288 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68641.780822 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68641.780822 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68641.780822 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68641.780822 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68641.780822 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68641.780822 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 976024903 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -384,11 +391,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 73 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 34176 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 534 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 534 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 626250 # Layer occupancy (ticks) @@ -396,14 +413,14 @@ system.cpu.toL2Bus.respLayer0.utilization 1.8 # L system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 233.878182 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 233.917543 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.878182 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007137 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007137 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.917543 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007139 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007139 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id @@ -426,12 +443,12 @@ system.cpu.l2cache.overall_misses::cpu.inst 533 # system.cpu.l2cache.overall_misses::total 533 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31726750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 31726750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5056000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5056000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 36782750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36782750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 36782750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36782750 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5065000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5065000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 36791750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 36791750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 36791750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 36791750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 461 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.inst 73 # number of ReadExReq accesses(hits+misses) @@ -450,12 +467,12 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998127 system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68971.195652 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 68971.195652 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69260.273973 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69260.273973 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69010.787992 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69010.787992 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69010.787992 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69010.787992 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69383.561644 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69383.561644 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69027.673546 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69027.673546 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69027.673546 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69027.673546 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,14 +489,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 533 system.cpu.l2cache.demand_mshr_misses::total 533 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 533 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25965250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25965250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4138000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4138000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30103250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30103250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30103250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30103250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25964750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25964750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4147500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4147500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30112250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30112250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30112250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30112250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997831 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses @@ -488,24 +505,24 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998127 system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56446.195652 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56446.195652 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56684.931507 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56684.931507 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56478.893058 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56478.893058 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56478.893058 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56478.893058 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56445.108696 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56445.108696 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56815.068493 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56815.068493 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 104.053835 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 104.075920 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1968 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.644970 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 104.053835 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.025404 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025404 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 104.075920 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.025409 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025409 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id @@ -528,10 +545,10 @@ system.cpu.dcache.demand_misses::cpu.inst 227 # n system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses system.cpu.dcache.overall_misses::total 227 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7727250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7727250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8696750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8696750 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7718250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7718250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8705750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8705750 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.inst 16424000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 16424000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.inst 16424000 # number of overall miss cycles @@ -552,10 +569,10 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.103417 system.cpu.dcache.demand_miss_rate::total 0.103417 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.103417 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.103417 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75757.352941 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75757.352941 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69574 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69574 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75669.117647 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75669.117647 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69646 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69646 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 72352.422907 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency @@ -584,10 +601,10 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 169 system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7154500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7154500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5130500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5130500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7145500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7145500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5139500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5139500 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12285000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 12285000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12285000 # number of overall MSHR miss cycles @@ -600,10 +617,10 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.076993 system.cpu.dcache.demand_mshr_miss_rate::total 0.076993 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.076993 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74526.041667 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74526.041667 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70280.821918 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70280.821918 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74432.291667 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74432.291667 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70404.109589 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70404.109589 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index f7bb9a203..b6d7e6ec3 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 20537500 # Number of ticks simulated final_tick 20537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 46749 # Simulator instruction rate (inst/s) -host_op_rate 46745 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 150649735 # Simulator tick rate (ticks/s) -host_mem_usage 236424 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 100086 # Simulator instruction rate (inst/s) +host_op_rate 100066 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 322455292 # Simulator tick rate (ticks/s) +host_mem_usage 290128 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 1 1.22% 82.93% # By system.physmem.bytesPerActivate::896-1023 3 3.66% 86.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 11 13.41% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 82 # Bytes accessed per row activation -system.physmem.totQLat 4551750 # Total ticks spent queuing -system.physmem.totMemAccLat 13683000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 4742750 # Total ticks spent queuing +system.physmem.totMemAccLat 13874000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2435000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9346.51 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9738.71 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28096.51 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28488.71 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1517.61 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1517.61 # Average system read bandwidth in MiByte/s @@ -227,17 +227,25 @@ system.physmem.memoryStateTime::REF 520000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15339250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1517614121 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 415 # Transaction distribution system.membus.trans_dist::ReadResp 415 # Transaction distribution system.membus.trans_dist::ReadExReq 72 # Transaction distribution system.membus.trans_dist::ReadExResp 72 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 974 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 974 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 31168 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 487 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 487 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 487 # Request fanout histogram system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) system.membus.respLayer1.occupancy 4554500 # Layer occupancy (ticks) @@ -579,7 +587,6 @@ system.cpu.fp_regfile_reads 8 # nu system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1520730371 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution @@ -587,11 +594,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 72 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 976 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 31232 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 488 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 488 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 488 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 244000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 528500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt index 60119bd53..a2eda1208 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 3208000 # Number of ticks simulated final_tick 3208000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172950 # Simulator instruction rate (inst/s) -host_op_rate 172880 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 86758979 # Simulator tick rate (ticks/s) -host_mem_usage 253924 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 1057772 # Simulator instruction rate (inst/s) +host_op_rate 1055326 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 528762156 # Simulator tick rate (ticks/s) +host_mem_usage 277832 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,27 @@ system.physmem.bw_write::total 2087281796 # Wr system.physmem.bw_total::cpu.inst 7980049875 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4826683292 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 12806733167 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 12806733167 # Throughput (bytes/s) -system.membus.data_through_bus 41084 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 7583 # Transaction distribution +system.membus.trans_dist::ReadResp 7583 # Transaction distribution +system.membus.trans_dist::WriteReq 865 # Transaction distribution +system.membus.trans_dist::WriteResp 865 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 12800 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4096 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 16896 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 25600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 15484 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 41084 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 8448 # Request fanout histogram +system.membus.snoop_fanout::mean 0.757576 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.428575 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2048 24.24% 24.24% # Request fanout histogram +system.membus.snoop_fanout::1 6400 75.76% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 8448 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index e6ec389d1..dcfebc3a2 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000033 # Nu sim_ticks 32544000 # Number of ticks simulated final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 550056 # Simulator instruction rate (inst/s) -host_op_rate 549394 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2794675827 # Simulator tick rate (ticks/s) -host_mem_usage 262632 # Number of bytes of host memory used +host_inst_rate 485157 # Simulator instruction rate (inst/s) +host_op_rate 484642 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2465828156 # Simulator tick rate (ticks/s) +host_mem_usage 286540 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 546705998 # In system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 877089479 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 373 # Transaction distribution system.membus.trans_dist::ReadResp 373 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 28544 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 446 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 446 # Request fanout histogram system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) system.membus.respLayer1.occupancy 4014000 # Layer occupancy (ticks) @@ -455,7 +463,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 879056047 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -463,11 +470,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 73 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 28608 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 447 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 447 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 7e0b73788..6f17c0be9 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18662000 # Number of ticks simulated final_tick 18662000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 32674 # Simulator instruction rate (inst/s) -host_op_rate 32664 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 235769003 # Simulator tick rate (ticks/s) -host_mem_usage 238980 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 154264 # Simulator instruction rate (inst/s) +host_op_rate 154144 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1111892278 # Simulator tick rate (ticks/s) +host_mem_usage 287792 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 3 6.82% 88.64% # By system.physmem.bytesPerActivate::896-1023 1 2.27% 90.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 4 9.09% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 44 # Bytes accessed per row activation -system.physmem.totQLat 1654250 # Total ticks spent queuing -system.physmem.totMemAccLat 7429250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1719250 # Total ticks spent queuing +system.physmem.totMemAccLat 7494250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5370.94 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5581.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24120.94 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24331.98 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1056.26 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1056.26 # Average system read bandwidth in MiByte/s @@ -223,17 +223,25 @@ system.physmem.memoryStateTime::REF 520000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15310750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1056264066 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 281 # Transaction distribution system.membus.trans_dist::ReadResp 281 # Transaction distribution system.membus.trans_dist::ReadExReq 27 # Transaction distribution system.membus.trans_dist::ReadExResp 27 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 616 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 616 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19712 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 19712 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19712 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 308 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 308 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 308 # Request fanout histogram system.membus.reqLayer0.occupancy 362000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) system.membus.respLayer1.occupancy 2870500 # Layer occupancy (ticks) @@ -376,7 +384,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 66880.044843 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66880.044843 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 66880.044843 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1056264066 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution @@ -384,11 +391,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 27 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 446 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 616 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 19712 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 308 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 308 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 381750 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index a87953c0f..286f63d05 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu sim_ticks 11765500 # Number of ticks simulated final_tick 11765500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 45706 # Simulator instruction rate (inst/s) -host_op_rate 45696 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 225189511 # Simulator tick rate (ticks/s) -host_mem_usage 236100 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 81487 # Simulator instruction rate (inst/s) +host_op_rate 81445 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 401265305 # Simulator tick rate (ticks/s) +host_mem_usage 288836 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 1 2.56% 82.05% # By system.physmem.bytesPerActivate::896-1023 1 2.56% 84.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 6 15.38% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 39 # Bytes accessed per row activation -system.physmem.totQLat 1710500 # Total ticks spent queuing -system.physmem.totMemAccLat 6810500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1802000 # Total ticks spent queuing +system.physmem.totMemAccLat 6902000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6288.60 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6625.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25038.60 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25375.00 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1479.58 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1479.58 # Average system read bandwidth in MiByte/s @@ -227,17 +227,25 @@ system.physmem.memoryStateTime::REF 260000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 7778000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1479580128 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 248 # Transaction distribution system.membus.trans_dist::ReadResp 248 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution system.membus.trans_dist::ReadExResp 24 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 544 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 544 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17408 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 272 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 272 # Request fanout histogram system.membus.reqLayer0.occupancy 339500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) system.membus.respLayer1.occupancy 2545000 # Layer occupancy (ticks) @@ -577,7 +585,6 @@ system.cpu.int_regfile_writes 2774 # nu system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1479580128 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution @@ -585,11 +592,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 24 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 544 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 17408 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 272 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 272 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 314250 # Layer occupancy (ticks) @@ -717,14 +734,14 @@ system.cpu.l2cache.overall_misses::total 272 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12706250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4451500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 17157750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1692250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1692250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1694250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1694250 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 12706250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6143750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18850000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6145750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 18852000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 12706250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6143750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18850000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6145750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18852000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 187 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 248 # number of ReadReq accesses(hits+misses) @@ -750,14 +767,14 @@ system.cpu.l2cache.overall_miss_rate::total 1 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67947.860963 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72975.409836 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 69184.475806 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70510.416667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70510.416667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70593.750000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70593.750000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67947.860963 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72279.411765 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69301.470588 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72302.941176 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69308.823529 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67947.860963 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72279.411765 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69301.470588 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72302.941176 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69308.823529 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -780,14 +797,14 @@ system.cpu.l2cache.overall_mshr_misses::total 272 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10348750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3702000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14050750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1398750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1398750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1400750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1400750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10348750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5100750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15449500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5102750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15451500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10348750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5100750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15449500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5102750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15451500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -802,22 +819,22 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 1 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55340.909091 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60688.524590 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56656.250000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58281.250000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58281.250000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58364.583333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58364.583333 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55340.909091 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60008.823529 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56799.632353 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60032.352941 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56806.985294 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55340.909091 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60008.823529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56799.632353 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60032.352941 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56806.985294 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 46.118379 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 46.118209 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 729 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.576471 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 46.118379 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 46.118209 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.011259 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.011259 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id @@ -842,14 +859,14 @@ system.cpu.dcache.demand_misses::cpu.data 198 # n system.cpu.dcache.demand_misses::total 198 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 198 # number of overall misses system.cpu.dcache.overall_misses::total 198 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7443000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7443000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5304000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5304000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12747000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12747000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12747000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12747000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7447000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7447000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5312000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5312000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12759000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12759000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12759000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12759000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 633 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 633 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -866,14 +883,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.213592 system.cpu.dcache.demand_miss_rate::total 0.213592 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.213592 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.213592 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63615.384615 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63615.384615 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65481.481481 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65481.481481 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64378.787879 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64378.787879 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64378.787879 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64378.787879 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63649.572650 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63649.572650 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65580.246914 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65580.246914 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64439.393939 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64439.393939 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 131 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -900,12 +917,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 85 system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4512500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 4512500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1717750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1717750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6230250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6230250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6230250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6230250 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1719750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1719750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6232250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6232250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6232250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6232250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096367 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096367 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses @@ -916,12 +933,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091694 system.cpu.dcache.overall_mshr_miss_rate::total 0.091694 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73975.409836 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73975.409836 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71572.916667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71572.916667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73297.058824 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73297.058824 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73297.058824 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73297.058824 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71656.250000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71656.250000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index 6080ce665..8c96cc883 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000001 # Nu sim_ticks 1297500 # Number of ticks simulated final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 741583 # Simulator instruction rate (inst/s) -host_op_rate 738395 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 370291096 # Simulator tick rate (ticks/s) -host_mem_usage 253628 # Number of bytes of host memory used +host_inst_rate 828617 # Simulator instruction rate (inst/s) +host_op_rate 824640 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 413479924 # Simulator tick rate (ticks/s) +host_mem_usage 276508 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated @@ -35,9 +35,27 @@ system.physmem.bw_write::total 1586127168 # Wr system.physmem.bw_total::cpu.inst 7969171484 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3910597303 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11879768786 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 11879768786 # Throughput (bytes/s) -system.membus.data_through_bus 15414 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 3000 # Transaction distribution +system.membus.trans_dist::ReadResp 3000 # Transaction distribution +system.membus.trans_dist::WriteReq 294 # Transaction distribution +system.membus.trans_dist::WriteResp 294 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 5170 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1418 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6588 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 10340 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 5074 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15414 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3294 # Request fanout histogram +system.membus.snoop_fanout::mean 0.784760 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.411051 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 709 21.52% 21.52% # Request fanout histogram +system.membus.snoop_fanout::1 2585 78.48% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 3294 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 3ccccfd43..6695f502c 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000017 # Nu sim_ticks 16524000 # Number of ticks simulated final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 366311 # Simulator instruction rate (inst/s) -host_op_rate 365532 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2339184598 # Simulator tick rate (ticks/s) -host_mem_usage 262348 # Number of bytes of host memory used +host_inst_rate 428144 # Simulator instruction rate (inst/s) +host_op_rate 427151 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2733498759 # Simulator tick rate (ticks/s) +host_mem_usage 286260 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated @@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 631324135 # In system.physmem.bw_total::cpu.inst 631324135 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 317598644 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 948922779 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 948922779 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 218 # Transaction distribution system.membus.trans_dist::ReadResp 218 # Transaction distribution system.membus.trans_dist::ReadExReq 27 # Transaction distribution system.membus.trans_dist::ReadExResp 27 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15680 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 245 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 245 # Request fanout histogram system.membus.reqLayer0.occupancy 245000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) system.membus.respLayer1.occupancy 2205000 # Layer occupancy (ticks) @@ -449,7 +457,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 948922779 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution @@ -457,11 +464,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 27 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 326 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 164 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 490 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 15680 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 245 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 245 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 245 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 244500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 65ff8dd3e..59eccf84d 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 27911000 # Number of ticks simulated final_tick 27911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66829 # Simulator instruction rate (inst/s) -host_op_rate 78212 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 404876453 # Simulator tick rate (ticks/s) -host_mem_usage 278412 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 116522 # Simulator instruction rate (inst/s) +host_op_rate 136369 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 705946329 # Simulator tick rate (ticks/s) +host_mem_usage 304192 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 4604 # Number of instructions simulated sim_ops 5390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -195,12 +195,12 @@ system.physmem.bytesPerActivate::640-767 2 3.12% 79.69% # By system.physmem.bytesPerActivate::768-895 3 4.69% 84.38% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 15.62% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 64 # Bytes accessed per row activation -system.physmem.totQLat 2525000 # Total ticks spent queuing -system.physmem.totMemAccLat 10400000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2575500 # Total ticks spent queuing +system.physmem.totMemAccLat 10450500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6011.90 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6132.14 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24761.90 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24882.14 # Average memory access latency per DRAM burst system.physmem.avgRdBW 963.06 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 963.06 # Average system read bandwidth in MiByte/s @@ -222,30 +222,38 @@ system.physmem.memoryStateTime::REF 780000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 22840500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 963061159 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 377 # Transaction distribution system.membus.trans_dist::ReadResp 377 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 26880 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 420 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 420 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 420 # Request fanout histogram system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) system.membus.respLayer1.occupancy 3924000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 14.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 1905 # Number of BP lookups -system.cpu.branchPred.condPredicted 1139 # Number of conditional branches predicted +system.cpu.branchPred.lookups 1903 # Number of BP lookups +system.cpu.branchPred.condPredicted 1138 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1574 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1573 # Number of BTB lookups system.cpu.branchPred.BTBHits 325 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 20.648030 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 223 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 20.661157 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -341,59 +349,59 @@ system.cpu.discardedOps 1208 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 12.124674 # CPI: cycles per instruction system.cpu.ipc 0.082476 # IPC: instructions per cycle -system.cpu.tickCycles 10535 # Number of cycles that the object actually ticked -system.cpu.idleCycles 45287 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 10521 # Number of cycles that the object actually ticked +system.cpu.idleCycles 45301 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 162.198888 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1923 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 162.201432 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.990654 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.978193 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 162.198888 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.079199 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.079199 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 162.201432 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.079200 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.079200 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4809 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4809 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1923 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1923 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1923 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1923 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1923 # number of overall hits -system.cpu.icache.overall_hits::total 1923 # number of overall hits +system.cpu.icache.tags.tag_accesses 4801 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4801 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits +system.cpu.icache.overall_hits::total 1919 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses system.cpu.icache.overall_misses::total 321 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21494250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21494250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21494250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21494250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21494250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21494250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2244 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2244 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2244 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2244 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2244 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2244 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143048 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.143048 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.143048 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.143048 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.143048 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.143048 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66960.280374 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66960.280374 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66960.280374 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66960.280374 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66960.280374 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66960.280374 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21503250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21503250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21503250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21503250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21503250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21503250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2240 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2240 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2240 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2240 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2240 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2240 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143304 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.143304 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.143304 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.143304 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.143304 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.143304 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66988.317757 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 66988.317757 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66988.317757 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66988.317757 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -408,26 +416,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 321 system.cpu.icache.demand_mshr_misses::total 321 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20721750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20721750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20721750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20721750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20721750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20721750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143048 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143048 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143048 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.143048 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143048 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.143048 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64553.738318 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64553.738318 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64553.738318 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 64553.738318 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64553.738318 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 64553.738318 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20730750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20730750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20730750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20730750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20730750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20730750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143304 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.143304 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.143304 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64581.775701 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64581.775701 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1070832288 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -435,11 +442,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 43 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 934 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20544 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29888 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 29888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 467 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 467 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 467 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 233500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 546750 # Layer occupancy (ticks) @@ -447,12 +468,12 @@ system.cpu.toL2Bus.respLayer0.utilization 2.0 # L system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 195.954343 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 195.957604 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 377 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.103448 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.954343 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.957604 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005980 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005980 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 377 # Occupied blocks per task id @@ -475,14 +496,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 428 # system.cpu.l2cache.demand_misses::total 428 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 428 # number of overall misses system.cpu.l2cache.overall_misses::total 428 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26168000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 26168000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26169000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 26169000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2824000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2824000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 28992000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28992000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 28992000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28992000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 28993000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28993000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 28993000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28993000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 424 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 424 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.inst 43 # number of ReadExReq accesses(hits+misses) @@ -499,14 +520,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.916488 system.cpu.l2cache.demand_miss_rate::total 0.916488 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.916488 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916488 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67968.831169 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67968.831169 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67971.428571 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67971.428571 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65674.418605 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65674.418605 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67738.317757 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67738.317757 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67738.317757 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67738.317757 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67740.654206 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67740.654206 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -529,14 +550,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 420 system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 420 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20973000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20973000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20974000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20974000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 2284000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2284000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23257000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23257000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23257000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23257000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23258000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23258000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23258000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23258000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.889151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses @@ -545,24 +566,24 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899358 system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899358 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55631.299735 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55631.299735 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55633.952255 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55633.952255 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53116.279070 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53116.279070 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55373.809524 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55373.809524 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55373.809524 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55373.809524 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.663656 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.665340 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1919 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.143836 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 86.663656 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.021158 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021158 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 86.665340 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.021159 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021159 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id @@ -589,14 +610,14 @@ system.cpu.dcache.demand_misses::cpu.inst 182 # n system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 182 # number of overall misses system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6958741 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6958741 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6950741 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6950741 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.inst 4586500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 4586500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 11545241 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 11545241 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 11545241 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 11545241 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 11537241 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 11537241 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 11537241 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 11537241 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 1166 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1166 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 913 # number of WriteReq accesses(hits+misses) @@ -617,14 +638,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.087542 system.cpu.dcache.demand_miss_rate::total 0.087542 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.087542 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.087542 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60510.791304 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60510.791304 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60441.226087 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60441.226087 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68455.223881 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 68455.223881 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63435.390110 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63435.390110 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63435.390110 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63435.390110 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63391.434066 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63391.434066 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,14 +670,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6265258 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6265258 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6257258 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6257258 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2867000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2867000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9132258 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9132258 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9132258 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9132258 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9124258 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9124258 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9124258 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9124258 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.088336 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088336 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.047097 # mshr miss rate for WriteReq accesses @@ -665,14 +686,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.070226 system.cpu.dcache.demand_mshr_miss_rate::total 0.070226 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.070226 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60827.747573 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.747573 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60750.077670 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60750.077670 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66674.418605 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66674.418605 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62549.712329 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62549.712329 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62549.712329 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62549.712329 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index a4baa9644..bbf908c21 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000016 # Nu sim_ticks 16223000 # Number of ticks simulated final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 32617 # Simulator instruction rate (inst/s) -host_op_rate 38195 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 115221437 # Simulator tick rate (ticks/s) -host_mem_usage 253076 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 55920 # Simulator instruction rate (inst/s) +host_op_rate 65484 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 197542740 # Simulator tick rate (ticks/s) +host_mem_usage 304472 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see @@ -199,12 +199,12 @@ system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # By system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 2970000 # Total ticks spent queuing -system.physmem.totMemAccLat 10413750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3126000 # Total ticks spent queuing +system.physmem.totMemAccLat 10569750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7481.11 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7874.06 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26231.11 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26624.06 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1566.17 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1566.17 # Average system read bandwidth in MiByte/s @@ -226,17 +226,25 @@ system.physmem.memoryStateTime::REF 520000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15315250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1566171485 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 355 # Transaction distribution system.membus.trans_dist::ReadResp 355 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution system.membus.trans_dist::ReadExResp 42 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25408 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 397 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 397 # Request fanout histogram system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) @@ -718,7 +726,6 @@ system.cpu.cc_regfile_reads 28734 # nu system.cpu.cc_regfile_writes 3302 # number of cc regfile writes system.cpu.misc_regfile_reads 3189 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1735807187 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution @@ -726,11 +733,29 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 42 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 28160 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::9 441 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) @@ -738,14 +763,14 @@ system.cpu.toL2Bus.respLayer0.utilization 3.0 # L system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 150.758993 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 150.722255 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5.666667 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 150.758993 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073613 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073613 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 150.722255 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073595 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073595 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 293 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id @@ -764,12 +789,12 @@ system.cpu.icache.demand_misses::cpu.inst 402 # n system.cpu.icache.demand_misses::total 402 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 402 # number of overall misses system.cpu.icache.overall_misses::total 402 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25574000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25574000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25574000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25574000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25574000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25574000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25584000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25584000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25584000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25584000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25584000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25584000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses @@ -782,12 +807,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.194391 system.cpu.icache.demand_miss_rate::total 0.194391 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.194391 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.194391 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63616.915423 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63616.915423 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63616.915423 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63616.915423 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63641.791045 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63641.791045 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63641.791045 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63641.791045 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63641.791045 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63641.791045 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -808,36 +833,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 294 system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19742750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19742750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19742750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19742750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19742750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19742750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19740750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19740750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19740750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19740750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19740750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19740750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142166 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.142166 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.142166 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67152.210884 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67152.210884 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67152.210884 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67152.210884 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67152.210884 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67152.210884 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67145.408163 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67145.408163 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67145.408163 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67145.408163 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67145.408163 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67145.408163 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 188.170247 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 188.125989 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.371533 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.798714 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004314 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.336521 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.789468 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001428 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005743 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id @@ -864,16 +889,16 @@ system.cpu.l2cache.demand_misses::total 402 # nu system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 402 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19251250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6010750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19249250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6012750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 25262000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3101750 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3101750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19251250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9112500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 19249250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9114500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 28363750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19251250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9112500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 19249250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9114500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 28363750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 294 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses) @@ -897,16 +922,16 @@ system.cpu.l2cache.demand_miss_rate::total 0.911565 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.935374 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.911565 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70004.545455 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70714.705882 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69997.272727 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70738.235294 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 70172.222222 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73851.190476 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73851.190476 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70004.545455 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71751.968504 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69997.272727 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71767.716535 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 70556.592040 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70004.545455 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71751.968504 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69997.272727 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71767.716535 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 70556.592040 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -933,16 +958,16 @@ system.cpu.l2cache.demand_mshr_misses::total 397 system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15797750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4736000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15795750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4738000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20533750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2589250 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2589250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15797750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7325250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15795750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7327250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 23123000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15797750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7325250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15795750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7327250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 23123000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.761905 # mshr miss rate for ReadReq accesses @@ -955,27 +980,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57446.363636 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59200 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57439.090909 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59225 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57841.549296 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61648.809524 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61648.809524 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57446.363636 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60043.032787 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57446.363636 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60043.032787 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.133302 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 87.114563 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.133302 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021273 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021273 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 87.114563 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021268 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021268 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id @@ -1004,16 +1029,16 @@ system.cpu.dcache.demand_misses::cpu.data 521 # n system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses system.cpu.dcache.overall_misses::total 521 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11351493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11351493 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353493 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11353493 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32096993 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32096993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32096993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32096993 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32098993 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32098993 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32098993 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32098993 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -1036,16 +1061,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55918.684729 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55918.684729 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61606.512476 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61606.512476 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61610.351248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61610.351248 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -1072,14 +1097,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6245255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6245255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6247255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6247255 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9390005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9390005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9390005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9390005 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9392005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9392005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9392005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9392005 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses @@ -1088,14 +1113,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59478.619048 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59478.619048 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index adfd7b504..f52a81778 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,62 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16223000 # Number of ticks simulated -final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 11859500 # Number of ticks simulated +final_tick 11859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 35590 # Simulator instruction rate (inst/s) -host_op_rate 41676 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 125719954 # Simulator tick rate (ticks/s) -host_mem_usage 252016 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 50616 # Simulator instruction rate (inst/s) +host_op_rate 59274 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 130716325 # Simulator tick rate (ticks/s) +host_mem_usage 300356 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory -system.physmem.bytes_read::total 25408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 397 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1084879492 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 481291993 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1566171485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1084879492 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1084879492 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1084879492 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 481291993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1566171485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 397 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 3776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 37184 # Number of bytes read from this memory +system.physmem.bytes_read::total 46848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 3776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 3776 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 59 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 92 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 581 # Number of read requests responded to by this memory +system.physmem.num_reads::total 732 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 318394536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 496479615 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 3135376702 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3950250854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 318394536 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 318394536 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 318394536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 496479615 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 3135376702 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3950250854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 733 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 733 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 46912 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side +system.physmem.bytesReadSys 46912 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 90 # Per bank write bursts -system.physmem.perBankRdBursts::1 46 # Per bank write bursts -system.physmem.perBankRdBursts::2 20 # Per bank write bursts -system.physmem.perBankRdBursts::3 43 # Per bank write bursts -system.physmem.perBankRdBursts::4 18 # Per bank write bursts -system.physmem.perBankRdBursts::5 32 # Per bank write bursts -system.physmem.perBankRdBursts::6 35 # Per bank write bursts -system.physmem.perBankRdBursts::7 10 # Per bank write bursts -system.physmem.perBankRdBursts::8 4 # Per bank write bursts -system.physmem.perBankRdBursts::9 8 # Per bank write bursts -system.physmem.perBankRdBursts::10 28 # Per bank write bursts -system.physmem.perBankRdBursts::11 42 # Per bank write bursts -system.physmem.perBankRdBursts::12 9 # Per bank write bursts -system.physmem.perBankRdBursts::13 6 # Per bank write bursts +system.physmem.perBankRdBursts::0 143 # Per bank write bursts +system.physmem.perBankRdBursts::1 90 # Per bank write bursts +system.physmem.perBankRdBursts::2 40 # Per bank write bursts +system.physmem.perBankRdBursts::3 73 # Per bank write bursts +system.physmem.perBankRdBursts::4 58 # Per bank write bursts +system.physmem.perBankRdBursts::5 88 # Per bank write bursts +system.physmem.perBankRdBursts::6 52 # Per bank write bursts +system.physmem.perBankRdBursts::7 18 # Per bank write bursts +system.physmem.perBankRdBursts::8 12 # Per bank write bursts +system.physmem.perBankRdBursts::9 28 # Per bank write bursts +system.physmem.perBankRdBursts::10 34 # Per bank write bursts +system.physmem.perBankRdBursts::11 47 # Per bank write bursts +system.physmem.perBankRdBursts::12 17 # Per bank write bursts +system.physmem.perBankRdBursts::13 19 # Per bank write bursts system.physmem.perBankRdBursts::14 0 # Per bank write bursts -system.physmem.perBankRdBursts::15 6 # Per bank write bursts +system.physmem.perBankRdBursts::15 14 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 16156000 # Total gap between requests +system.physmem.totGap 11846500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 397 # Read request sizes (log2) +system.physmem.readPktSize::6 733 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,22 +94,22 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 96 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -186,71 +190,80 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 396.190476 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 265.364013 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.900990 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12 19.05% 19.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 25.40% 44.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 9 14.29% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 2970000 # Total ticks spent queuing -system.physmem.totMemAccLat 10413750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7481.11 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 712.533333 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 570.872295 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 336.283550 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 4 6.67% 6.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 5 8.33% 15.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4 6.67% 21.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1 1.67% 23.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 6.67% 30.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10 16.67% 46.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 6.67% 53.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5 8.33% 61.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23 38.33% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation +system.physmem.totQLat 17284989 # Total ticks spent queuing +system.physmem.totMemAccLat 31028739 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3665000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23581.16 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26231.11 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1566.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 42331.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3955.65 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1566.17 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 3955.65 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 12.24 # Data bus utilization in percentage -system.physmem.busUtilRead 12.24 # Data bus utilization in percentage for reads +system.physmem.busUtil 30.90 # Data bus utilization in percentage +system.physmem.busUtilRead 30.90 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing +system.physmem.avgRdQLen 5.25 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 331 # Number of row buffer hits during reads +system.physmem.readRowHits 662 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.31 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 40695.21 # Average gap between requests -system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11000 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states +system.physmem.avgGap 16161.66 # Average gap between requests +system.physmem.pageHitRate 90.31 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 6500 # Time in different power states +system.physmem.memoryStateTime::REF 260000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15315250 # Time in different power states +system.physmem.memoryStateTime::ACT 7800750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1566171485 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 355 # Transaction distribution -system.membus.trans_dist::ReadResp 355 # Transaction distribution -system.membus.trans_dist::ReadExReq 42 # Transaction distribution -system.membus.trans_dist::ReadExResp 42 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25408 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.8 # Layer utilization (%) +system.membus.trans_dist::ReadReq 704 # Transaction distribution +system.membus.trans_dist::ReadResp 702 # Transaction distribution +system.membus.trans_dist::ReadExReq 29 # Transaction distribution +system.membus.trans_dist::ReadExResp 29 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1464 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1464 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 46784 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 733 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 733 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 733 # Request fanout histogram +system.membus.reqLayer0.occupancy 803724 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 6.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 6629985 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 55.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 2638 # Number of BP lookups -system.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2101 # Number of BTB lookups -system.cpu.branchPred.BTBHits 783 # Number of BTB hits +system.cpu.branchPred.lookups 2560 # Number of BP lookups +system.cpu.branchPred.condPredicted 1531 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 510 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 939 # Number of BTB lookups +system.cpu.branchPred.BTBHits 497 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.267968 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 354 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 52.928647 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 297 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -336,237 +349,234 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 32447 # number of cpu cycles simulated +system.cpu.numCycles 23720 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7786 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12484 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2638 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1137 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4850 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1010 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 2068 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 320 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13433 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.098935 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.478489 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 4394 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12370 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2560 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 794 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 11397 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1062 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 322 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 84 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 4117 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 139 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 16747 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.858243 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.204203 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10743 79.97% 79.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 265 1.97% 81.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 241 1.79% 83.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 235 1.75% 85.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 238 1.77% 87.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 291 2.17% 89.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 141 1.05% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 175 1.30% 91.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1104 8.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9977 59.57% 59.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2687 16.04% 75.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 563 3.36% 78.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3520 21.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13433 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.081302 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.384751 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6529 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4272 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2145 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 138 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 349 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 390 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12118 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 349 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6736 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 846 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2304 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2064 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1134 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11483 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 163 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 117 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 963 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11820 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 52846 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12757 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 16747 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.107926 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.521501 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 4535 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 6577 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5106 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 160 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 369 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 338 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 165 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 10143 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1684 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 369 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5681 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3207 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2422 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4105 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 963 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 9048 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 426 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 101 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 748 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9432 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 41033 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9977 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 18 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6326 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 43 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 443 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2313 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10354 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8358 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4760 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12835 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13433 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.622199 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.376807 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 3938 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 31 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 472 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1824 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1295 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 8517 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 7242 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 203 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2981 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8241 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 16747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.432436 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.833231 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10179 75.78% 75.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1183 8.81% 84.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 748 5.57% 90.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 453 3.37% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 362 2.69% 96.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 286 2.13% 98.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 135 1.00% 99.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 64 0.48% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 23 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12501 74.65% 74.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1960 11.70% 86.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1628 9.72% 96.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 606 3.62% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 52 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13433 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 16747 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 5.33% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 80 47.34% 52.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 80 47.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 437 29.61% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 482 32.66% 62.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 557 37.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5041 60.31% 60.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2009 24.04% 84.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1299 15.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4533 62.59% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.08% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1613 22.27% 84.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1087 15.01% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8358 # Type of FU issued -system.cpu.iq.rate 0.257589 # Inst issue rate -system.cpu.iq.fu_busy_cnt 169 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020220 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30275 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15052 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7570 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 31 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8484 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 25 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 7242 # Type of FU issued +system.cpu.iq.rate 0.305312 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1476 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.203811 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 32865 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11527 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6638 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 45 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 18 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 8689 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 29 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 15 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1286 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 701 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 797 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 357 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 39 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 349 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 800 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10411 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2313 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 252 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 364 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8063 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1908 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 295 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 369 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 705 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 159 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 8571 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1824 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1295 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 151 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 362 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 6828 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1428 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 11 # number of nop insts executed -system.cpu.iew.exec_refs 3148 # number of memory reference insts executed -system.cpu.iew.exec_branches 1457 # Number of branches executed -system.cpu.iew.exec_stores 1240 # Number of stores executed -system.cpu.iew.exec_rate 0.248498 # Inst execution rate -system.cpu.iew.wb_sent 7735 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7601 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3572 # num instructions producing a value -system.cpu.iew.wb_consumers 6998 # num instructions consuming a value +system.cpu.iew.exec_nop 14 # number of nop insts executed +system.cpu.iew.exec_refs 2449 # number of memory reference insts executed +system.cpu.iew.exec_branches 1283 # Number of branches executed +system.cpu.iew.exec_stores 1021 # Number of stores executed +system.cpu.iew.exec_rate 0.287858 # Inst execution rate +system.cpu.iew.wb_sent 6699 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6654 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3045 # num instructions producing a value +system.cpu.iew.wb_consumers 5519 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.234259 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.510432 # average fanout of values written-back +system.cpu.iew.wb_rate 0.280523 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.551730 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5037 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2714 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 324 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12552 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.428378 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.273949 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 348 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 16184 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.332242 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.986798 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10495 83.61% 83.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 893 7.11% 90.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 426 3.39% 94.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 211 1.68% 95.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 111 0.88% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 212 1.69% 98.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 50 0.40% 98.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 37 0.29% 99.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 117 0.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 13581 83.92% 83.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1345 8.31% 92.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 599 3.70% 95.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 281 1.74% 97.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 168 1.04% 98.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 78 0.48% 99.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 47 0.29% 99.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 33 0.20% 99.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 52 0.32% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12552 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 16184 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -612,403 +622,449 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5377 # Class of committed instruction -system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 52 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22692 # The number of ROB reads -system.cpu.rob.rob_writes 21719 # The number of ROB writes -system.cpu.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19014 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 24066 # The number of ROB reads +system.cpu.rob.rob_writes 16749 # The number of ROB writes +system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6973 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.067523 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.067523 # CPI: Total CPI of All Threads -system.cpu.ipc 0.141492 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.141492 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7944 # number of integer regfile reads -system.cpu.int_regfile_writes 4420 # number of integer regfile writes -system.cpu.fp_regfile_reads 31 # number of floating regfile reads -system.cpu.cc_regfile_reads 28734 # number of cc regfile reads -system.cpu.cc_regfile_writes 3302 # number of cc regfile writes -system.cpu.misc_regfile_reads 3189 # number of misc regfile reads +system.cpu.cpi 5.166630 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.166630 # CPI: Total CPI of All Threads +system.cpu.ipc 0.193550 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.193550 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6786 # number of integer regfile reads +system.cpu.int_regfile_writes 3839 # number of integer regfile writes +system.cpu.fp_regfile_reads 16 # number of floating regfile reads +system.cpu.cc_regfile_reads 24301 # number of cc regfile reads +system.cpu.cc_regfile_writes 2919 # number of cc regfile writes +system.cpu.misc_regfile_reads 2642 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1735807187 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 28160 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 150.758993 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.666667 # Average number of references to valid blocks. +system.cpu.toL2Bus.trans_dist::ReadReq 408 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 407 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1026 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 40 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 40 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 608 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 895 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1026 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1474 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.696065 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.460111 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 448 30.39% 30.39% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 1026 69.61% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1474 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 224000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 461250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 223747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) +system.cpu.icache.tags.replacements 47 # number of replacements +system.cpu.icache.tags.tagsinuse 138.950029 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3784 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 304 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12.447368 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 150.758993 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073613 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073613 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 293 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.143066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4430 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4430 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1666 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1666 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1666 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1666 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1666 # number of overall hits -system.cpu.icache.overall_hits::total 1666 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 402 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 402 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 402 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 402 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 402 # number of overall misses -system.cpu.icache.overall_misses::total 402 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25574000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25574000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25574000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25574000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25574000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25574000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2068 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2068 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2068 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194391 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.194391 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.194391 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.194391 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.194391 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.194391 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63616.915423 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63616.915423 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63616.915423 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63616.915423 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 138.950029 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.271387 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.271387 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.501953 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 8536 # Number of tag accesses +system.cpu.icache.tags.data_accesses 8536 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 3784 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3784 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3784 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3784 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3784 # number of overall hits +system.cpu.icache.overall_hits::total 3784 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 332 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 332 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 332 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 332 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 332 # number of overall misses +system.cpu.icache.overall_misses::total 332 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 7426247 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 7426247 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 7426247 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 7426247 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 7426247 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 7426247 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 4116 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4116 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 4116 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4116 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 4116 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4116 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.080661 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.080661 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.080661 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.080661 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.080661 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.080661 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22368.213855 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22368.213855 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22368.213855 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22368.213855 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22368.213855 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22368.213855 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1112 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 66 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 16.848485 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19742750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19742750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19742750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19742750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19742750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19742750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142166 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.142166 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.142166 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67152.210884 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67152.210884 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67152.210884 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67152.210884 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67152.210884 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67152.210884 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 28 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 28 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 28 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 28 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6489997 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 6489997 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6489997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 6489997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6489997 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 6489997 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.073858 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.073858 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.073858 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.073858 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.073858 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.073858 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21348.674342 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21348.674342 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21348.674342 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21348.674342 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21348.674342 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21348.674342 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 2346 # number of hwpf identified +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 489 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 1139 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 86 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 29 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 603 # number of hwpf issued +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 198 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 188.170247 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 370.948422 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 270 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 691 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.390738 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.371533 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.798714 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004314 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001428 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005743 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3925 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3925 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 19 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits -system.cpu.l2cache.overall_hits::total 39 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 275 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 360 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 402 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses -system.cpu.l2cache.overall_misses::total 402 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19251250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6010750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 25262000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3101750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3101750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19251250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9112500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28363750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19251250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9112500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28363750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 294 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 399 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 294 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 294 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.935374 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.809524 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.902256 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.935374 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.911565 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.935374 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.911565 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70004.545455 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70714.705882 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70172.222222 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73851.190476 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73851.190476 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70004.545455 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71751.968504 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70556.592040 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70004.545455 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71751.968504 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70556.592040 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.tags.occ_blocks::cpu.inst 30.449811 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 36.598805 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 303.899806 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001859 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002234 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.018549 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.022641 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 570 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 121 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 471 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 99 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.034790 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007385 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 7899 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7899 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 234 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 35 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 269 # number of ReadReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 234 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 46 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 280 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 234 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 46 # number of overall hits +system.cpu.l2cache.overall_hits::total 280 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 70 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 69 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 139 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 29 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 29 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 70 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 98 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 168 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 70 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 98 # number of overall misses +system.cpu.l2cache.overall_misses::total 168 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 4724750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5170750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 9895500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2577500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2577500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 4724750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7748250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12473000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 4724750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7748250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12473000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 408 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 40 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 40 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 448 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 448 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.230263 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.663462 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.340686 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.725000 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.725000 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.230263 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.680556 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.375000 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.230263 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.680556 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.375000 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67496.428571 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74938.405797 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71190.647482 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88879.310345 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88879.310345 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67496.428571 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79063.775510 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74244.047619 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67496.428571 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79063.775510 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74244.047619 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 388 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 22.823529 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 80 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 355 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15797750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4736000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20533750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2589250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2589250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15797750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7325250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23123000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15797750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7325250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23123000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.761905 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889724 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57446.363636 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59200 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57841.549296 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61648.809524 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61648.809524 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57446.363636 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60043.032787 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57446.363636 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60043.032787 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 59 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 122 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 603 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 603 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 29 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 59 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 92 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 151 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 59 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 92 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 603 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 754 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 3978500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4478500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8457000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 49457864 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 49457864 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2337500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2337500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 3978500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6816000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10794500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 3978500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6816000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 49457864 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 60252364 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.605769 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.299020 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.725000 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.725000 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.638889 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.337054 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.638889 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 1.683036 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67432.203390 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71087.301587 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69319.672131 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82019.674959 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80603.448276 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80603.448276 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67432.203390 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74086.956522 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71486.754967 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67432.203390 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74086.956522 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79910.297082 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.133302 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1 # number of replacements +system.cpu.dcache.tags.tagsinuse 82.309019 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1894 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.244755 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.133302 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021273 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021273 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 595 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 595 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 82.309019 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.160760 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.160760 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4719 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4719 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1158 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1158 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2146 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2146 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2146 # number of overall hits -system.cpu.dcache.overall_hits::total 2146 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 203 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 203 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 1873 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1873 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1873 # number of overall hits +system.cpu.dcache.overall_hits::total 1873 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 194 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 194 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 198 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 198 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses -system.cpu.dcache.overall_misses::total 521 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11351493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11351493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32096993 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32096993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32096993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32096993 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 392 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 392 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 392 # number of overall misses +system.cpu.dcache.overall_misses::total 392 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10805495 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10805495 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8861750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8861750 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 152500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 152500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19667245 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19667245 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19667245 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19667245 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1352 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1352 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55918.684729 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55918.684729 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61606.512476 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61606.512476 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2265 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2265 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2265 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2265 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.143491 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.143491 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.216867 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.216867 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.173068 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173068 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173068 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173068 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55698.427835 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55698.427835 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44756.313131 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44756.313131 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 76250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 76250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 50171.543367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 50171.543367 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 617 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 34.277778 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 90 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6245255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6245255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9390005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9390005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9390005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9390005 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59478.619048 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59478.619048 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 248 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 248 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 248 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 40 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5492753 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5492753 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2689000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2689000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8181753 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8181753 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8181753 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8181753 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076923 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076923 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.043812 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.043812 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063576 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063576 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52814.932692 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52814.932692 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67225 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67225 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index f5795e533..9b7b2bcb6 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109620 # Simulator instruction rate (inst/s) -host_op_rate 128318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64270947 # Simulator tick rate (ticks/s) -host_mem_usage 268656 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 582910 # Simulator instruction rate (inst/s) +host_op_rate 681582 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 341032781 # Simulator tick rate (ticks/s) +host_mem_usage 293692 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,34 @@ system.physmem.bw_write::total 1353868992 # Wr system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9855260716 # Throughput (bytes/s) -system.membus.data_through_bus 26555 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 5596 # Transaction distribution +system.membus.trans_dist::ReadResp 5607 # Transaction distribution +system.membus.trans_dist::WriteReq 913 # Transaction distribution +system.membus.trans_dist::WriteResp 913 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondResp 11 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6531 # Request fanout histogram +system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram +system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 6531 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index efe28c206..73cde8525 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133655 # Simulator instruction rate (inst/s) -host_op_rate 156442 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 78348823 # Simulator tick rate (ticks/s) -host_mem_usage 267596 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 685428 # Simulator instruction rate (inst/s) +host_op_rate 801222 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 400788339 # Simulator tick rate (ticks/s) +host_mem_usage 292412 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,34 @@ system.physmem.bw_write::total 1353868992 # Wr system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9855260716 # Throughput (bytes/s) -system.membus.data_through_bus 26555 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 5596 # Transaction distribution +system.membus.trans_dist::ReadResp 5607 # Transaction distribution +system.membus.trans_dist::WriteReq 913 # Transaction distribution +system.membus.trans_dist::WriteResp 913 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondResp 11 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6531 # Request fanout histogram +system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram +system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 6531 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index f26a07dcf..8f2c9257f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu sim_ticks 25815000 # Number of ticks simulated final_tick 25815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 85918 # Simulator instruction rate (inst/s) -host_op_rate 100276 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 485659481 # Simulator tick rate (ticks/s) -host_mem_usage 277384 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 367819 # Simulator instruction rate (inst/s) +host_op_rate 428893 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2075494452 # Simulator tick rate (ticks/s) +host_mem_usage 302164 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5329 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 557815224 # In system.physmem.bw_total::cpu.inst 557815224 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 309897347 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 867712570 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 867712570 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 307 # Transaction distribution system.membus.trans_dist::ReadResp 307 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 22400 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 350 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 350 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 350 # Request fanout histogram system.membus.reqLayer0.occupancy 355000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) system.membus.respLayer1.occupancy 3155000 # Layer occupancy (ticks) @@ -520,7 +528,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 947046291 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -528,11 +535,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 43 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 482 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 764 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 24448 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 382 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 12868f8fc..2de82825c 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu sim_ticks 24907000 # Number of ticks simulated final_tick 24907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84163 # Simulator instruction rate (inst/s) -host_op_rate 84145 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 360406899 # Simulator tick rate (ticks/s) -host_mem_usage 264444 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 110455 # Simulator instruction rate (inst/s) +host_op_rate 110427 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 472950648 # Simulator tick rate (ticks/s) +host_mem_usage 286112 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -199,12 +199,12 @@ system.physmem.bytesPerActivate::640-767 2 1.89% 92.45% # By system.physmem.bytesPerActivate::768-895 3 2.83% 95.28% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 4.72% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 106 # Bytes accessed per row activation -system.physmem.totQLat 4873000 # Total ticks spent queuing -system.physmem.totMemAccLat 13404250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 4936500 # Total ticks spent queuing +system.physmem.totMemAccLat 13467750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2275000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10709.89 # Average queueing delay per DRAM burst +system.physmem.avgQLat 10849.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29459.89 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29599.45 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1169.15 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1169.15 # Average system read bandwidth in MiByte/s @@ -226,17 +226,25 @@ system.physmem.memoryStateTime::REF 780000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 22841500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1169149235 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 404 # Transaction distribution system.membus.trans_dist::ReadResp 404 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution system.membus.trans_dist::ReadExResp 51 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 910 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 910 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 29120 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 29120 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 29120 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 455 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 455 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 455 # Request fanout histogram system.membus.reqLayer0.occupancy 552000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) system.membus.respLayer1.occupancy 4259500 # Layer occupancy (ticks) @@ -292,12 +300,12 @@ system.cpu.execution_unit.executions 3133 # Nu system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9484 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 462 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 44432 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 5383 # Number of cycles cpu stages are processed. -system.cpu.activity 10.805982 # Percentage of cycles cpu is active +system.cpu.idleCycles 44434 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 5381 # Number of cycles cpu stages are processed. +system.cpu.activity 10.801967 # Percentage of cycles cpu is active system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed @@ -315,30 +323,30 @@ system.cpu.cpi_total 8.568111 # CP system.cpu.ipc 0.116712 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.ipc_total 0.116712 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 46167 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3648 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 7.323095 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 47002 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 2813 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 5.646894 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 46168 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 3647 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 7.321088 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 47003 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 2812 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 5.644886 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.idleCycles 47048 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 2767 # Number of cycles 1+ instructions are processed. system.cpu.stage2.utilization 5.554552 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage3.idleCycles 48577 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1238 # Number of cycles 1+ instructions are processed. system.cpu.stage3.utilization 2.485195 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 46927 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 2888 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 5.797451 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46929 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 2886 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 5.793436 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 150.585033 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 150.581339 # Cycle average of tags in use system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 150.585033 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073528 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073528 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 150.581339 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073526 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073526 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 306 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id @@ -357,12 +365,12 @@ system.cpu.icache.demand_misses::cpu.inst 350 # n system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses system.cpu.icache.overall_misses::total 350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25291750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25291750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25291750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25291750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25291750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25291750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25285250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25285250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25285250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25285250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25285250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25285250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses @@ -375,12 +383,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.449871 system.cpu.icache.demand_miss_rate::total 0.449871 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.449871 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.449871 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72262.142857 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72262.142857 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72262.142857 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72262.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72262.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72262.142857 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72243.571429 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72243.571429 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72243.571429 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72243.571429 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72243.571429 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72243.571429 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -401,26 +409,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319 system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22956750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22956750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22956750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22956750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22956750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22956750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22950250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22950250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22950250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22950250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22950250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22950250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.410026 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.410026 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71964.733542 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71964.733542 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71964.733542 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71964.733542 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71964.733542 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71964.733542 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71944.357367 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71944.357367 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71944.357367 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71944.357367 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71944.357367 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71944.357367 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1174288353 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution @@ -428,11 +435,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 51 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 638 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 914 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29248 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 29248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 457 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 457 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 457 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 538750 # Layer occupancy (ticks) @@ -440,13 +457,13 @@ system.cpu.toL2Bus.respLayer0.utilization 2.2 # L system.cpu.toL2Bus.respLayer1.occupancy 226250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 208.347330 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 208.342392 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.267110 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.080220 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.263135 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.079256 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004647 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001711 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006358 # Average percentage of cache occupancy @@ -473,17 +490,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22611250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6877000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29488250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3810250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3810250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22611250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10687250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33298500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22611250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10687250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33298500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22604750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6885000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29489750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3812750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3812750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22604750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10697750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33302500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22604750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10697750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33302500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -506,17 +523,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71328.864353 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79045.977011 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72990.717822 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74710.784314 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74710.784314 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71328.864353 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77443.840580 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73183.516484 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71328.864353 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77443.840580 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73183.516484 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71308.359621 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79137.931034 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72994.430693 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74759.803922 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74759.803922 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71308.359621 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77519.927536 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73192.307692 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71308.359621 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77519.927536 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73192.307692 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -536,17 +553,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18629250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5798500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24427750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3166750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3166750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18629250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8965250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27594500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18629250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8965250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27594500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18622750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5806500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24429250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3169250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3169250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18622750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8975750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27598500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18622750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8975750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27598500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -558,25 +575,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58767.350158 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66649.425287 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60464.727723 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62093.137255 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62093.137255 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58767.350158 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64965.579710 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60647.252747 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58767.350158 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64965.579710 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60647.252747 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58746.845426 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66741.379310 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60468.440594 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62142.156863 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62142.156863 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58746.845426 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65041.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60656.043956 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58746.845426 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65041.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60656.043956 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 90.296415 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 90.295130 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1638 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.869565 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 90.296415 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 90.295130 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.022045 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.022045 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id @@ -601,14 +618,14 @@ system.cpu.dcache.demand_misses::cpu.data 450 # n system.cpu.dcache.demand_misses::total 450 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 450 # number of overall misses system.cpu.dcache.overall_misses::total 450 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7634750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7634750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21637250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21637250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29272000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29272000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29272000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29272000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7642750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7642750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21639750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21639750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29282500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29282500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29282500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29282500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -625,14 +642,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.215517 system.cpu.dcache.demand_miss_rate::total 0.215517 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.215517 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.215517 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78708.762887 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 78708.762887 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61295.325779 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61295.325779 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65048.888889 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65048.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65048.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65048.888889 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78791.237113 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 78791.237113 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61302.407932 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61302.407932 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65072.222222 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65072.222222 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65072.222222 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65072.222222 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked @@ -657,14 +674,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6970500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6970500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3864250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3864250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10834750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10834750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10834750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10834750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6978500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6978500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3866750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3866750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10845250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10845250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10845250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10845250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -673,14 +690,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80120.689655 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80120.689655 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75769.607843 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75769.607843 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78512.681159 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78512.681159 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78512.681159 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78512.681159 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80212.643678 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80212.643678 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75818.627451 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75818.627451 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78588.768116 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78588.768116 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78588.768116 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78588.768116 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 8c5d2b15c..cc5bb948f 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 21611500 # Number of ticks simulated final_tick 21611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 39362 # Simulator instruction rate (inst/s) -host_op_rate 39354 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 164927772 # Simulator tick rate (ticks/s) -host_mem_usage 235848 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 87050 # Simulator instruction rate (inst/s) +host_op_rate 87030 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 364707967 # Simulator tick rate (ticks/s) +host_mem_usage 288672 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -199,12 +199,12 @@ system.physmem.bytesPerActivate::768-895 3 2.75% 93.58% # By system.physmem.bytesPerActivate::896-1023 2 1.83% 95.41% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 4.59% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 109 # Bytes accessed per row activation -system.physmem.totQLat 5548500 # Total ticks spent queuing -system.physmem.totMemAccLat 14529750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 5601000 # Total ticks spent queuing +system.physmem.totMemAccLat 14582250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2395000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11583.51 # Average queueing delay per DRAM burst +system.physmem.avgQLat 11693.11 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30333.51 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30443.11 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1418.50 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1418.50 # Average system read bandwidth in MiByte/s @@ -226,20 +226,28 @@ system.physmem.memoryStateTime::REF 520000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15315250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1418504037 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 428 # Transaction distribution system.membus.trans_dist::ReadResp 428 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution system.membus.trans_dist::ReadExResp 51 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 958 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 958 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30656 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 30656 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 30656 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30656 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 479 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 479 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 479 # Request fanout histogram system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4492750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4492250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 20.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 2196 # Number of BP lookups @@ -562,7 +570,6 @@ system.cpu.int_regfile_writes 5412 # nu system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 164 # number of misc regfile reads -system.cpu.toL2Bus.throughput 1427388196 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 431 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 431 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution @@ -570,11 +577,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 51 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 680 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 964 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 30848 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 482 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 482 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 482 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 575000 # Layer occupancy (ticks) @@ -582,14 +599,14 @@ system.cpu.toL2Bus.respLayer0.utilization 2.7 # L system.cpu.toL2Bus.respLayer1.occupancy 228250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 161.374264 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 161.371303 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1615 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 340 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4.750000 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 161.374264 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078796 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078796 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 161.371303 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078795 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078795 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 323 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id @@ -608,12 +625,12 @@ system.cpu.icache.demand_misses::cpu.inst 453 # n system.cpu.icache.demand_misses::total 453 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 453 # number of overall misses system.cpu.icache.overall_misses::total 453 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31448500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31448500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31448500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31448500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31448500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31448500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31446500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31446500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31446500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31446500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31446500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31446500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses @@ -626,12 +643,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.219052 system.cpu.icache.demand_miss_rate::total 0.219052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.219052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.219052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69422.737307 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69422.737307 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69422.737307 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69422.737307 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69422.737307 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69422.737307 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69418.322296 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69418.322296 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69418.322296 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69418.322296 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69418.322296 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69418.322296 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -652,33 +669,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 340 system.cpu.icache.demand_mshr_misses::total 340 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 340 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 340 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24624500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24624500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24624500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24624500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24624500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24624500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24622500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24622500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24622500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24622500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24622500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24622500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.164410 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.164410 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.164410 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72425 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72425 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72425 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72425 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72425 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72425 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72419.117647 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72419.117647 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72419.117647 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72419.117647 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72419.117647 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72419.117647 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 222.300532 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 222.296900 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 428 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.007009 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.614658 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 58.685875 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.611488 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 58.685412 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004993 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001791 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006784 # Average percentage of cache occupancy @@ -705,17 +722,17 @@ system.cpu.l2cache.demand_misses::total 479 # nu system.cpu.l2cache.overall_misses::cpu.inst 337 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 479 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24254500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7288250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 31542750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4058000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4058000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 24254500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11346250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35600750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 24254500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11346250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35600750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24252500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7286250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 31538750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4056000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4056000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 24252500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11342250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 35594750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 24252500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11342250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35594750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 340 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 431 # number of ReadReq accesses(hits+misses) @@ -738,17 +755,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993776 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991176 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993776 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71971.810089 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80090.659341 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73698.014019 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79568.627451 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79568.627451 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71971.810089 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79903.169014 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74323.068894 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71971.810089 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79903.169014 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74323.068894 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71965.875371 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80068.681319 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73688.668224 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79529.411765 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79529.411765 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71965.875371 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79875 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74310.542797 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71965.875371 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79875 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74310.542797 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -768,17 +785,17 @@ system.cpu.l2cache.demand_mshr_misses::total 479 system.cpu.l2cache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 479 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19999000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6168250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26167250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3423500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3423500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19999000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9591750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29590750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19999000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9591750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 29590750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19997500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6166250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26163750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3421500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3421500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19997500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9587750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29585250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19997500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9587750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29585250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991176 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993039 # mshr miss rate for ReadReq accesses @@ -790,25 +807,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993776 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991176 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993776 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59344.213650 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67782.967033 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61138.434579 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67127.450980 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67127.450980 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59344.213650 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67547.535211 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61776.096033 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59344.213650 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67547.535211 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61776.096033 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59339.762611 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67760.989011 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61130.257009 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67088.235294 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67088.235294 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59339.762611 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67519.366197 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61764.613779 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59339.762611 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67519.366197 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61764.613779 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 92.430317 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 92.429669 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2508 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 17.661972 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 92.430317 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 92.429669 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.022566 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.022566 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id @@ -833,14 +850,14 @@ system.cpu.dcache.demand_misses::cpu.data 531 # n system.cpu.dcache.demand_misses::total 531 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 531 # number of overall misses system.cpu.dcache.overall_misses::total 531 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11709000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11709000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23266249 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23266249 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34975249 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34975249 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34975249 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34975249 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11707000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11707000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23264249 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23264249 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34971249 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34971249 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34971249 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34971249 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2114 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2114 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -857,14 +874,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.174729 system.cpu.dcache.demand_miss_rate::total 0.174729 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.174729 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.174729 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69284.023669 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 69284.023669 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64271.406077 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64271.406077 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65866.758945 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65866.758945 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65866.758945 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65866.758945 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69272.189349 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 69272.189349 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64265.881215 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64265.881215 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65859.225989 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65859.225989 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65859.225989 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65859.225989 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked @@ -889,14 +906,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7382750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7382750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4109999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4109999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11492749 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11492749 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11492749 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11492749 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7380750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7380750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4107999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4107999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11488749 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11488749 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11488749 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11488749 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.043046 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.043046 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -905,14 +922,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046726 system.cpu.dcache.demand_mshr_miss_rate::total 0.046726 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046726 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.046726 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81129.120879 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81129.120879 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80588.215686 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80588.215686 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80934.852113 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80934.852113 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80934.852113 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80934.852113 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81107.142857 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81107.142857 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80549 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80549 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80906.683099 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80906.683099 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80906.683099 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80906.683099 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt index c5418ef55..49c05c732 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2907000 # Number of ticks simulated final_tick 2907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1298058 # Simulator instruction rate (inst/s) -host_op_rate 1293725 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 644853594 # Simulator tick rate (ticks/s) -host_mem_usage 255756 # Number of bytes of host memory used -host_seconds 0.00 # Real time elapsed on the host +host_inst_rate 972729 # Simulator instruction rate (inst/s) +host_op_rate 970456 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 484177215 # Simulator tick rate (ticks/s) +host_mem_usage 275596 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,27 @@ system.physmem.bw_write::total 1258341933 # Wr system.physmem.bw_total::cpu.inst 8001375989 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2762985896 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10764361885 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 10764361885 # Throughput (bytes/s) -system.membus.data_through_bus 31292 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 6978 # Transaction distribution +system.membus.trans_dist::ReadResp 6978 # Transaction distribution +system.membus.trans_dist::WriteReq 925 # Transaction distribution +system.membus.trans_dist::WriteResp 925 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11630 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4176 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15806 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 23260 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 31292 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7903 # Request fanout histogram +system.membus.snoop_fanout::mean 0.735797 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.440936 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2088 26.42% 26.42% # Request fanout histogram +system.membus.snoop_fanout::1 5815 73.58% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 7903 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index ee2cc6627..a40ed7ca5 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000032 # Nu sim_ticks 31633000 # Number of ticks simulated final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 474922 # Simulator instruction rate (inst/s) -host_op_rate 474341 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2577866515 # Simulator tick rate (ticks/s) -host_mem_usage 263440 # Number of bytes of host memory used +host_inst_rate 442331 # Simulator instruction rate (inst/s) +host_op_rate 441894 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2401898254 # Simulator tick rate (ticks/s) +host_mem_usage 285092 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated @@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 608984289 # In system.physmem.bw_total::cpu.inst 608984289 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 279202099 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 888186388 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 888186388 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 388 # Transaction distribution system.membus.trans_dist::ReadResp 388 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution system.membus.trans_dist::ReadExResp 51 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 878 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 28096 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 28096 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28096 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 439 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 439 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 439 # Request fanout histogram system.membus.reqLayer0.occupancy 439000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) system.membus.respLayer1.occupancy 3951000 # Layer occupancy (ticks) @@ -441,7 +449,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 892232795 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 390 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 390 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution @@ -449,11 +456,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 51 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 606 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 882 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 28224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 28224 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 441 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 454500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 895c59829..2b23aa030 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18857500 # Number of ticks simulated final_tick 18857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 41326 # Simulator instruction rate (inst/s) -host_op_rate 41320 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 134509153 # Simulator tick rate (ticks/s) -host_mem_usage 232584 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 98075 # Simulator instruction rate (inst/s) +host_op_rate 98051 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 319158839 # Simulator tick rate (ticks/s) +host_mem_usage 285824 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 1 1.27% 82.28% # By system.physmem.bytesPerActivate::896-1023 3 3.80% 86.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 11 13.92% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation -system.physmem.totQLat 3609000 # Total ticks spent queuing -system.physmem.totMemAccLat 11934000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3635500 # Total ticks spent queuing +system.physmem.totMemAccLat 11960500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8128.38 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8188.06 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26878.38 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26938.06 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1506.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1506.88 # Average system read bandwidth in MiByte/s @@ -227,17 +227,25 @@ system.physmem.memoryStateTime::REF 520000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15315250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1506880552 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 397 # Transaction distribution system.membus.trans_dist::ReadResp 397 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution system.membus.trans_dist::ReadExResp 47 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 28416 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 444 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 444 # Request fanout histogram system.membus.reqLayer0.occupancy 555500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) system.membus.respLayer1.occupancy 4160750 # Layer occupancy (ticks) @@ -563,7 +571,6 @@ system.cpu.int_regfile_reads 13743 # nu system.cpu.int_regfile_writes 7176 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.toL2Bus.throughput 1530637677 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution @@ -571,11 +578,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 47 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 903 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 28864 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 584250 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt index bcfd2d5d0..080dd7c2e 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2896000 # Number of ticks simulated final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1148266 # Simulator instruction rate (inst/s) -host_op_rate 1144862 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 570752858 # Simulator tick rate (ticks/s) -host_mem_usage 250716 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 1326844 # Simulator instruction rate (inst/s) +host_op_rate 1322603 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 659230594 # Simulator tick rate (ticks/s) +host_mem_usage 274036 # Number of bytes of host memory used +host_seconds 0.00 # Real time elapsed on the host sim_insts 5793 # Number of instructions simulated sim_ops 5793 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,27 @@ system.physmem.bw_write::total 1453383978 # Wr system.physmem.bw_total::cpu.inst 8001381215 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2737914365 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10739295580 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 10739295580 # Throughput (bytes/s) -system.membus.data_through_bus 31101 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 6754 # Transaction distribution +system.membus.trans_dist::ReadResp 6754 # Transaction distribution +system.membus.trans_dist::WriteReq 1046 # Transaction distribution +system.membus.trans_dist::WriteResp 1046 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11586 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4014 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15600 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 23172 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 7929 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 31101 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7800 # Request fanout histogram +system.membus.snoop_fanout::mean 0.742692 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.437178 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2007 25.73% 25.73% # Request fanout histogram +system.membus.snoop_fanout::1 5793 74.27% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 7800 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 90109d140..8a50d5754 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20918500 # Number of ticks simulated -final_tick 20918500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20927500 # Number of ticks simulated +final_tick 20927500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69876 # Simulator instruction rate (inst/s) -host_op_rate 69862 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 274294219 # Simulator tick rate (ticks/s) -host_mem_usage 270808 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 84066 # Simulator instruction rate (inst/s) +host_op_rate 84047 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 330123200 # Simulator tick rate (ticks/s) +host_mem_usage 286520 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 884193417 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 409972034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1294165452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 884193417 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 884193417 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 884193417 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 409972034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1294165452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 883813164 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 409795723 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1293608888 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 883813164 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 883813164 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 883813164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 409795723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1293608888 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 423 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 423 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20849000 # Total gap between requests +system.physmem.totGap 20858000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -198,15 +198,15 @@ system.physmem.bytesPerActivate::512-639 8 10.81% 87.84% # By system.physmem.bytesPerActivate::640-767 4 5.41% 93.24% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 6.76% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 74 # Bytes accessed per row activation -system.physmem.totQLat 3773250 # Total ticks spent queuing -system.physmem.totMemAccLat 11704500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3885750 # Total ticks spent queuing +system.physmem.totMemAccLat 11817000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8920.21 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9186.17 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27670.21 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1294.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27936.17 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1293.61 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1294.17 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1293.61 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 10.11 # Data bus utilization in percentage @@ -218,24 +218,32 @@ system.physmem.readRowHits 339 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.14 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 49288.42 # Average gap between requests +system.physmem.avgGap 49309.69 # Average gap between requests system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 13500 # Time in different power states system.physmem.memoryStateTime::REF 520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15312750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1294165452 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 342 # Transaction distribution system.membus.trans_dist::ReadResp 342 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution system.membus.trans_dist::ReadExResp 81 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 846 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 846 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27072 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 27072 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 423 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 423 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 423 # Request fanout histogram system.membus.reqLayer0.occupancy 501500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) system.membus.respLayer1.occupancy 3931250 # Layer occupancy (ticks) @@ -251,7 +259,7 @@ system.cpu.branchPred.BTBHitPct 43.484736 # BT system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 41838 # number of cpu cycles simulated +system.cpu.numCycles 41856 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True). @@ -273,12 +281,12 @@ system.cpu.execution_unit.executions 3957 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9657 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9651 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 422 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35590 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6248 # Number of cycles cpu stages are processed. -system.cpu.activity 14.933792 # Percentage of cycles cpu is active +system.cpu.timesIdled 424 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35611 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6245 # Number of cycles cpu stages are processed. +system.cpu.activity 14.920203 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -290,36 +298,36 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 7.853952 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.857331 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.853952 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127324 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.857331 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127270 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.127324 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 37198 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.127270 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 37216 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.090396 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38644 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3194 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.634208 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38804 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 3034 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.251781 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 40862 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 976 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.332807 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38681 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 11.085627 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38661 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 7.633314 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38823 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 7.246273 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 40881 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 2.329415 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 38699 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.545772 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 7.542527 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 142.676310 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 142.708262 # Cycle average of tags in use system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 142.676310 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.069666 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.069666 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 142.708262 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.069682 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.069682 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id @@ -338,12 +346,12 @@ system.cpu.icache.demand_misses::cpu.inst 366 # n system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25425250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25425250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25425250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25425250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25425250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25425250 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25412000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25412000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25412000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25412000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25412000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25412000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses @@ -356,12 +364,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.290938 system.cpu.icache.demand_miss_rate::total 0.290938 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.290938 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.290938 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69467.896175 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69467.896175 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69467.896175 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69467.896175 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69467.896175 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69467.896175 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69431.693989 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69431.693989 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69431.693989 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69431.693989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69431.693989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69431.693989 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,26 +390,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20653250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20653250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20653250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20653250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20653250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20653250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20639500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20639500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20639500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20639500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20639500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20639500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70973.367698 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70973.367698 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70973.367698 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70973.367698 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70973.367698 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70973.367698 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70926.116838 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70926.116838 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70926.116838 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70926.116838 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70926.116838 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70926.116838 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1303343930 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution @@ -409,31 +416,41 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 81 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 27264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 27264 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 27264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 426 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 426 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 426 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 486250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 486500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 217000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 216750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 169.122448 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 169.161112 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.106217 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 27.016231 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004337 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005161 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.138007 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 27.023105 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004338 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000825 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005162 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010437 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3831 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3831 # Number of data accesses @@ -457,17 +474,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20334750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4016000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24350750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5999500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5999500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20334750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10015500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30350250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20334750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10015500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30350250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20321000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4025000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24346000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6008250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6008250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20321000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10033250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30354250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20321000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10033250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30354250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -490,17 +507,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70362.456747 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75773.584906 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71201.023392 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74067.901235 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74067.901235 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70362.456747 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74742.537313 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71750 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70362.456747 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74742.537313 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71750 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70314.878893 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75943.396226 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71187.134503 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74175.925926 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74175.925926 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70314.878893 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74875 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71759.456265 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70314.878893 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74875 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71759.456265 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -520,17 +537,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16720750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3361000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20081750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5004000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5004000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16720750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8365000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25085750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16720750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8365000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25085750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16706500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3370000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20076500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5013250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5013250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16706500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8383250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25089750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16706500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8383250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25089750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -542,27 +559,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57857.266436 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63415.094340 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58718.567251 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61777.777778 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61777.777778 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57857.266436 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62425.373134 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59304.373522 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57857.266436 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62425.373134 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59304.373522 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57807.958478 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63584.905660 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58703.216374 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61891.975309 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61891.975309 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57807.958478 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62561.567164 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59313.829787 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57807.958478 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62561.567164 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59313.829787 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 85.354091 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 85.369863 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 85.354091 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020838 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020838 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 85.369863 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020842 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020842 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id @@ -585,14 +602,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4579750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4579750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 28882250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 28882250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33462000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33462000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33462000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33462000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4588750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4588750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 28972250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 28972250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33561000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33561000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33561000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33561000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -609,14 +626,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75077.868852 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75077.868852 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69932.808717 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69932.808717 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70594.936709 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70594.936709 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 70594.936709 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 70594.936709 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75225.409836 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75225.409836 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70150.726392 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70150.726392 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70803.797468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70803.797468 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked @@ -641,14 +658,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4082500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4082500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6083000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6083000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10165500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10165500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10165500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10165500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4091500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4091500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6091750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6091750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10183250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10183250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10183250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10183250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -657,14 +674,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75601.851852 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75601.851852 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75098.765432 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75098.765432 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75300 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75300 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75300 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75300 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75768.518519 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75768.518519 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75206.790123 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75206.790123 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index 0e41891dc..e454f5068 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1015247 # Simulator instruction rate (inst/s) -host_op_rate 1012545 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 510902541 # Simulator tick rate (ticks/s) -host_mem_usage 261064 # Number of bytes of host memory used +host_inst_rate 399685 # Simulator instruction rate (inst/s) +host_op_rate 399265 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 201759641 # Simulator tick rate (ticks/s) +host_mem_usage 276260 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated @@ -35,9 +35,27 @@ system.physmem.bw_write::total 1879755057 # Wr system.physmem.bw_total::cpu.inst 7971794396 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3587678605 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11559473001 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 11559473001 # Throughput (bytes/s) -system.membus.data_through_bus 31147 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 6085 # Transaction distribution +system.membus.trans_dist::ReadResp 6085 # Transaction distribution +system.membus.trans_dist::WriteReq 673 # Transaction distribution +system.membus.trans_dist::WriteResp 673 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 10740 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 2776 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13516 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 21480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 9667 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 31147 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6758 # Request fanout histogram +system.membus.snoop_fanout::mean 0.794614 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.404013 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1388 20.54% 20.54% # Request fanout histogram +system.membus.snoop_fanout::1 5370 79.46% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 6758 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 5390 # number of cpu cycles simulated diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index f251b736b..706af6d1d 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000028 # Nu sim_ticks 27800000 # Number of ticks simulated final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 487107 # Simulator instruction rate (inst/s) -host_op_rate 486440 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2535570960 # Simulator tick rate (ticks/s) -host_mem_usage 269788 # Number of bytes of host memory used +host_inst_rate 583909 # Simulator instruction rate (inst/s) +host_op_rate 583078 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3038583452 # Simulator tick rate (ticks/s) +host_mem_usage 285748 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated @@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 587050360 # In system.physmem.bw_total::cpu.inst 587050360 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 308489209 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 895539568 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 895539568 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 308 # Transaction distribution system.membus.trans_dist::ReadResp 308 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution system.membus.trans_dist::ReadExResp 81 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 24896 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 389 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 389 # Request fanout histogram system.membus.reqLayer0.occupancy 389000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) system.membus.respLayer1.occupancy 3501000 # Layer occupancy (ticks) @@ -426,7 +434,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 902446043 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution @@ -434,11 +441,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 81 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 25088 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 392 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 392 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index f7173c445..0db4f4424 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19744000 # Number of ticks simulated -final_tick 19744000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19678000 # Number of ticks simulated +final_tick 19678000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27433 # Simulator instruction rate (inst/s) -host_op_rate 49695 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 100653274 # Simulator tick rate (ticks/s) -host_mem_usage 249652 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 48979 # Simulator instruction rate (inst/s) +host_op_rate 88725 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 179100946 # Simulator tick rate (ticks/s) +host_mem_usage 305852 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17600 # Nu system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 891410049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 457050243 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1348460292 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 891410049 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 891410049 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 891410049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 457050243 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1348460292 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 894399837 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 458583189 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1352983027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 894399837 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 894399837 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 894399837 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 458583189 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1352983027 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 417 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 19695500 # Total gap between requests +system.physmem.totGap 19629500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -188,44 +188,43 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 98 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 242.285714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 159.132678 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 257.193096 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 35 35.71% 35.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 32 32.65% 68.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12 12.24% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 158.475642 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 257.521253 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 36 36.73% 36.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 30 30.61% 67.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13 13.27% 80.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 6 6.12% 86.73% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 6 6.12% 92.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 4 4.08% 96.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 3 3.06% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 98 # Bytes accessed per row activation -system.physmem.totQLat 4076000 # Total ticks spent queuing -system.physmem.totMemAccLat 11894750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 4347000 # Total ticks spent queuing +system.physmem.totMemAccLat 12165750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9774.58 # Average queueing delay per DRAM burst +system.physmem.avgQLat 10424.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28524.58 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1351.70 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29174.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1356.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1351.70 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1356.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.56 # Data bus utilization in percentage -system.physmem.busUtilRead 10.56 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.60 # Data bus utilization in percentage +system.physmem.busUtilRead 10.60 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 309 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 74.10 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47231.41 # Average gap between requests +system.physmem.avgGap 47073.14 # Average gap between requests system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 11000 # Time in different power states system.physmem.memoryStateTime::REF 520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15315250 # Time in different power states +system.physmem.memoryStateTime::ACT 15318250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1348460292 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 339 # Transaction distribution system.membus.trans_dist::ReadResp 338 # Transaction distribution system.membus.trans_dist::ReadExReq 78 # Transaction distribution @@ -233,15 +232,24 @@ system.membus.trans_dist::ReadExResp 78 # Tr system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 26624 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 417 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 417 # Request fanout histogram system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) system.membus.respLayer1.occupancy 3897000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.7 # Layer utilization (%) +system.membus.respLayer1.utilization 19.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 3423 # Number of BP lookups system.cpu.branchPred.condPredicted 3423 # Number of conditional branches predicted @@ -254,7 +262,7 @@ system.cpu.branchPred.usedRAS 247 # Nu system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 39489 # number of cpu cycles simulated +system.cpu.numCycles 39357 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 10915 # Number of cycles fetch is stalled on an Icache miss @@ -285,8 +293,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 21893 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.086682 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.393223 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.086973 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.394542 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 10660 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 6840 # Number of cycles decode is blocked system.cpu.decode.RunCycles 3336 # Number of cycles decode is running @@ -409,7 +417,7 @@ system.cpu.iq.FU_type_0::MemWrite 1379 7.71% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 17897 # Type of FU issued -system.cpu.iq.rate 0.453215 # Inst issue rate +system.cpu.iq.rate 0.454735 # Inst issue rate system.cpu.iq.fu_busy_cnt 224 # FU busy when requested system.cpu.iq.fu_busy_rate 0.012516 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 57983 # Number of integer instruction queue reads @@ -453,13 +461,13 @@ system.cpu.iew.exec_nop 0 # nu system.cpu.iew.exec_refs 3251 # number of memory reference insts executed system.cpu.iew.exec_branches 1662 # Number of branches executed system.cpu.iew.exec_stores 1282 # Number of stores executed -system.cpu.iew.exec_rate 0.428626 # Inst execution rate +system.cpu.iew.exec_rate 0.430063 # Inst execution rate system.cpu.iew.wb_sent 16636 # cumulative count of insts sent to commit system.cpu.iew.wb_count 16374 # cumulative count of insts written-back system.cpu.iew.wb_producers 11006 # num instructions producing a value system.cpu.iew.wb_consumers 17135 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.414647 # insts written-back per cycle +system.cpu.iew.wb_rate 0.416038 # insts written-back per cycle system.cpu.iew.wb_fanout 0.642311 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 11720 # The number of squashed insts skipped by commit @@ -532,13 +540,13 @@ system.cpu.commit.bw_limited 0 # nu system.cpu.rob.rob_reads 41132 # The number of ROB reads system.cpu.rob.rob_writes 44928 # The number of ROB writes system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17596 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 17464 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.339963 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.339963 # CPI: Total CPI of All Threads -system.cpu.ipc 0.136240 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.136240 # IPC: Total IPC of All Threads +system.cpu.cpi 7.315428 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.315428 # CPI: Total CPI of All Threads +system.cpu.ipc 0.136697 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.136697 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 21340 # number of integer regfile reads system.cpu.int_regfile_writes 13120 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads @@ -546,7 +554,6 @@ system.cpu.cc_regfile_reads 8069 # nu system.cpu.cc_regfile_writes 5036 # number of cc regfile writes system.cpu.misc_regfile_reads 7491 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1351701783 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 78 # Transaction distribution @@ -554,26 +561,38 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 78 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 552 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 283 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 26688 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 418 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 462750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 234250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 462500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 234500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 131.753616 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 131.539722 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1800 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 276 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 6.521739 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 131.753616 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.064333 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.064333 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 131.539722 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.064228 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.064228 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 276 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id @@ -592,12 +611,12 @@ system.cpu.icache.demand_misses::cpu.inst 368 # n system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses system.cpu.icache.overall_misses::total 368 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25386000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25386000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25386000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25386000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25386000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25386000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25557250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25557250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25557250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25557250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25557250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25557250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2168 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2168 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2168 # number of demand (read+write) accesses @@ -610,12 +629,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.169742 system.cpu.icache.demand_miss_rate::total 0.169742 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.169742 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.169742 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68983.695652 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68983.695652 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68983.695652 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68983.695652 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68983.695652 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68983.695652 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69449.048913 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69449.048913 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69449.048913 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69449.048913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69449.048913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69449.048913 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -636,36 +655,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 276 system.cpu.icache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 276 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19887250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19887250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19887250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19887250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19887250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19887250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20059000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20059000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20059000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20059000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20059000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20059000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.127306 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.127306 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.127306 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72055.253623 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72055.253623 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72055.253623 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72055.253623 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72055.253623 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72055.253623 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72677.536232 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72677.536232 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72677.536232 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72677.536232 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72677.536232 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72677.536232 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 163.478116 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 163.220102 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 338 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002959 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.827183 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.650934 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004023 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000966 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004989 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.613484 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.606618 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004017 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004981 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id @@ -689,17 +708,17 @@ system.cpu.l2cache.demand_misses::total 417 # nu system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 417 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19600750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19772500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4946500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24547250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5508750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5508750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19600750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10455250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30056000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19600750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10455250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30056000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24719000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5510000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5510000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 19772500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10456500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30229000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 19772500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10456500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30229000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 276 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 340 # number of ReadReq accesses(hits+misses) @@ -722,17 +741,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997608 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996377 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71275.454545 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71900 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77289.062500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72410.766962 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70625 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70625 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71275.454545 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73628.521127 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72076.738609 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71275.454545 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73628.521127 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72076.738609 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72917.404130 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70641.025641 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70641.025641 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71900 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73637.323944 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72491.606715 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71900 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73637.323944 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72491.606715 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -752,17 +771,17 @@ system.cpu.l2cache.demand_mshr_misses::total 417 system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16144250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16317000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4156000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20300250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4539250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4539250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16144250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8695250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 24839500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16144250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8695250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24839500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20473000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4539500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4539500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16317000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8695500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25012500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16317000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8695500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25012500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997059 # mshr miss rate for ReadReq accesses @@ -774,27 +793,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58706.363636 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59334.545455 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64937.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59882.743363 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58195.512821 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58195.512821 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58706.363636 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61234.154930 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59567.146283 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58706.363636 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61234.154930 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59567.146283 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60392.330383 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58198.717949 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58198.717949 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59334.545455 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59334.545455 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.450988 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.331185 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 17.021277 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.450988 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020130 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020130 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 82.331185 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020100 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020100 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id @@ -819,12 +838,12 @@ system.cpu.dcache.overall_misses::cpu.data 214 # system.cpu.dcache.overall_misses::total 214 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 9815500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 9815500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5769250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5769250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15584750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15584750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15584750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15584750 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5771000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5771000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15586500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15586500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15586500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15586500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1679 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1679 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) @@ -843,12 +862,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.081867 system.cpu.dcache.overall_miss_rate::total 0.081867 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72172.794118 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 72172.794118 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73964.743590 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73964.743590 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72825.934579 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72825.934579 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72825.934579 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72825.934579 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73987.179487 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73987.179487 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72834.112150 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72834.112150 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -873,12 +892,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 142 system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5009500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 5009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5586750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5586750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10596250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10596250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10596250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10596250 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5588000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5588000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10597500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10597500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10597500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038118 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038118 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses @@ -889,12 +908,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054323 system.cpu.dcache.overall_mshr_miss_rate::total 0.054323 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78273.437500 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78273.437500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71625 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71625 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74621.478873 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74621.478873 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74621.478873 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74621.478873 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71641.025641 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71641.025641 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index 0a6735ef0..baff57318 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000006 # Nu sim_ticks 5615000 # Number of ticks simulated final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 478524 # Simulator instruction rate (inst/s) -host_op_rate 865796 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 498092788 # Simulator tick rate (ticks/s) -host_mem_usage 271572 # Number of bytes of host memory used +host_inst_rate 365210 # Simulator instruction rate (inst/s) +host_op_rate 661016 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 380445830 # Simulator tick rate (ticks/s) +host_mem_usage 292780 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated @@ -35,9 +35,33 @@ system.physmem.bw_write::total 1266607302 # Wr system.physmem.bw_total::cpu.inst 9779519145 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2525022262 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 12304541407 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 12304541407 # Throughput (bytes/s) -system.membus.data_through_bus 69090 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 7917 # Transaction distribution +system.membus.trans_dist::ReadResp 7917 # Transaction distribution +system.membus.trans_dist::WriteReq 935 # Transaction distribution +system.membus.trans_dist::WriteResp 935 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 13728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3976 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 3976 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 17704 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 54912 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 54912 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 14178 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 14178 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 69090 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 8852 # Request fanout histogram +system.membus.snoop_fanout::mean 2.775418 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.417330 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 1988 22.46% 22.46% # Request fanout histogram +system.membus.snoop_fanout::3 6864 77.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::total 8852 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index bc4d8d180..8118efe8c 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000028 # Nu sim_ticks 28358000 # Number of ticks simulated final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 260669 # Simulator instruction rate (inst/s) -host_op_rate 471875 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1371807276 # Simulator tick rate (ticks/s) -host_mem_usage 281320 # Number of bytes of host memory used +host_inst_rate 307468 # Simulator instruction rate (inst/s) +host_op_rate 556583 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1618053178 # Simulator tick rate (ticks/s) +host_mem_usage 302528 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated @@ -29,7 +29,6 @@ system.physmem.bw_inst_read::total 512306933 # In system.physmem.bw_total::cpu.inst 512306933 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 302419070 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 814726003 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 814726003 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 282 # Transaction distribution system.membus.trans_dist::ReadResp 282 # Transaction distribution system.membus.trans_dist::ReadExReq 79 # Transaction distribution @@ -37,11 +36,20 @@ system.membus.trans_dist::ReadExResp 79 # Tr system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 23104 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 361 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 361 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 361 # Request fanout histogram system.membus.reqLayer0.occupancy 361000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) system.membus.respLayer1.occupancy 3249000 # Layer occupancy (ticks) @@ -428,7 +436,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 816982862 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution @@ -436,11 +443,23 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 79 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 23168 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 362 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 921de5f0b..5f7cff1f0 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 23170000 # Number of ticks simulated -final_tick 23170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 23061500 # Number of ticks simulated +final_tick 23061500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 44420 # Simulator instruction rate (inst/s) -host_op_rate 44416 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 80747825 # Simulator tick rate (ticks/s) -host_mem_usage 237048 # Number of bytes of host memory used -host_seconds 0.29 # Real time elapsed on the host +host_inst_rate 90290 # Simulator instruction rate (inst/s) +host_op_rate 90281 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 163358622 # Simulator tick rate (ticks/s) +host_mem_usage 290460 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 12744 # Number of instructions simulated sim_ops 12744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 40384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 40576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22080 # Number of bytes read from this memory system.physmem.bytes_read::total 62656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 40384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 40384 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 631 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 348 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 40576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 40576 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 634 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 345 # Number of read requests responded to by this memory system.physmem.num_reads::total 979 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1742943461 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 961242987 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2704186448 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1742943461 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1742943461 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1742943461 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 961242987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2704186448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1759469245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 957439889 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2716909134 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1759469245 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1759469245 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1759469245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 957439889 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2716909134 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 979 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 979 # Number of DRAM read bursts, including those serviced by the write queue @@ -45,17 +45,17 @@ system.physmem.perBankRdBursts::0 84 # Pe system.physmem.perBankRdBursts::1 151 # Per bank write bursts system.physmem.perBankRdBursts::2 78 # Per bank write bursts system.physmem.perBankRdBursts::3 58 # Per bank write bursts -system.physmem.perBankRdBursts::4 88 # Per bank write bursts -system.physmem.perBankRdBursts::5 48 # Per bank write bursts +system.physmem.perBankRdBursts::4 89 # Per bank write bursts +system.physmem.perBankRdBursts::5 50 # Per bank write bursts system.physmem.perBankRdBursts::6 33 # Per bank write bursts system.physmem.perBankRdBursts::7 51 # Per bank write bursts system.physmem.perBankRdBursts::8 42 # Per bank write bursts system.physmem.perBankRdBursts::9 39 # Per bank write bursts -system.physmem.perBankRdBursts::10 31 # Per bank write bursts +system.physmem.perBankRdBursts::10 29 # Per bank write bursts system.physmem.perBankRdBursts::11 34 # Per bank write bursts system.physmem.perBankRdBursts::12 15 # Per bank write bursts system.physmem.perBankRdBursts::13 120 # Per bank write bursts -system.physmem.perBankRdBursts::14 70 # Per bank write bursts +system.physmem.perBankRdBursts::14 69 # Per bank write bursts system.physmem.perBankRdBursts::15 37 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 23015000 # Total gap between requests +system.physmem.totGap 22909000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 75 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 332 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 191 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 77 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -187,91 +187,99 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 196 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 289.959184 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 186.164854 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 288.512504 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 61 31.12% 31.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 60 30.61% 61.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 290.285714 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 185.772581 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 289.019279 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 62 31.63% 31.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 59 30.10% 61.73% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 22 11.22% 72.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 9 4.59% 77.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 16 8.16% 85.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6 3.06% 88.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5 2.55% 91.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 4.08% 77.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15 7.65% 84.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9 4.59% 89.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 2.04% 91.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 4 2.04% 93.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 13 6.63% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 196 # Bytes accessed per row activation -system.physmem.totQLat 11386250 # Total ticks spent queuing -system.physmem.totMemAccLat 29742500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 11811000 # Total ticks spent queuing +system.physmem.totMemAccLat 30167250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 4895000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11630.49 # Average queueing delay per DRAM burst +system.physmem.avgQLat 12064.35 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30380.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2704.19 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30814.35 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2716.91 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2704.19 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2716.91 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 21.13 # Data bus utilization in percentage -system.physmem.busUtilRead 21.13 # Data bus utilization in percentage for reads +system.physmem.busUtil 21.23 # Data bus utilization in percentage +system.physmem.busUtilRead 21.23 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.40 # Average read queue length when enqueuing +system.physmem.avgRdQLen 2.42 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 767 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 78.35 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 23508.68 # Average gap between requests +system.physmem.avgGap 23400.41 # Average gap between requests system.physmem.pageHitRate 78.35 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 25750 # Time in different power states system.physmem.memoryStateTime::REF 520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15300500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 2704186448 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 833 # Transaction distribution system.membus.trans_dist::ReadResp 833 # Transaction distribution system.membus.trans_dist::ReadExReq 146 # Transaction distribution system.membus.trans_dist::ReadExResp 146 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1958 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1958 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62656 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 62656 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 62656 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1208500 # Layer occupancy (ticks) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 62656 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 979 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 979 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 979 # Request fanout histogram +system.membus.reqLayer0.occupancy 1210000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 5.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 9081250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 39.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 9085500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 39.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 7166 # Number of BP lookups -system.cpu.branchPred.condPredicted 4000 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1467 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 5305 # Number of BTB lookups -system.cpu.branchPred.BTBHits 908 # Number of BTB hits +system.cpu.branchPred.lookups 6891 # Number of BP lookups +system.cpu.branchPred.condPredicted 3900 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1379 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 5156 # Number of BTB lookups +system.cpu.branchPred.BTBHits 960 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 17.115928 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 981 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 18.619085 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 963 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4855 # DTB read hits -system.cpu.dtb.read_misses 98 # DTB read misses +system.cpu.dtb.read_hits 4694 # DTB read hits +system.cpu.dtb.read_misses 106 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4953 # DTB read accesses -system.cpu.dtb.write_hits 2092 # DTB write hits +system.cpu.dtb.read_accesses 4800 # DTB read accesses +system.cpu.dtb.write_hits 2103 # DTB write hits system.cpu.dtb.write_misses 62 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2154 # DTB write accesses -system.cpu.dtb.data_hits 6947 # DTB hits -system.cpu.dtb.data_misses 160 # DTB misses +system.cpu.dtb.write_accesses 2165 # DTB write accesses +system.cpu.dtb.data_hits 6797 # DTB hits +system.cpu.dtb.data_misses 168 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 7107 # DTB accesses -system.cpu.itb.fetch_hits 5289 # ITB hits +system.cpu.dtb.data_accesses 6965 # DTB accesses +system.cpu.itb.fetch_hits 5123 # ITB hits system.cpu.itb.fetch_misses 59 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5348 # ITB accesses +system.cpu.itb.fetch_accesses 5182 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -286,318 +294,318 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 46341 # number of cpu cycles simulated +system.cpu.numCycles 46124 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 1308 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 39806 # Number of instructions fetch has processed -system.cpu.fetch.Branches 7166 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1889 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 11048 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1548 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 233 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5289 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 806 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 28474 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.397977 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.796585 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 1227 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 38336 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6891 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1923 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 10750 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1460 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 320 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5123 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 789 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 27999 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.369192 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.769631 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21786 76.51% 76.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 553 1.94% 78.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 412 1.45% 79.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 526 1.85% 81.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 512 1.80% 83.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 421 1.48% 85.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 497 1.75% 86.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 420 1.48% 88.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3347 11.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21530 76.90% 76.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 534 1.91% 78.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 415 1.48% 80.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 507 1.81% 82.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 495 1.77% 83.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 425 1.52% 85.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 487 1.74% 87.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 424 1.51% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3182 11.36% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 28474 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.154636 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.858980 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 37975 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 11845 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5079 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 648 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1147 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 634 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 427 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 32375 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 893 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1147 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 38612 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4919 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1229 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 5110 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5677 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 30348 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 40 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 343 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 655 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4509 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 22899 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 37890 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 37872 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 27999 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.149402 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.831151 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 37351 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 11762 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 4916 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 633 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1095 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 569 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 385 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 31322 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 859 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1095 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37970 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4830 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1235 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4957 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5670 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 29386 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 35 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 318 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 603 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4545 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 22134 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 36672 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 36654 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 13759 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 60 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 12994 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 62 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2110 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2877 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1488 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 42 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2903 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1354 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 6 # Number of conflicting loads. +system.cpu.rename.skidInsts 2157 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2815 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1467 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 39 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 26 # Number of conflicting stores. +system.cpu.memDep1.insertedLoads 2781 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1339 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 5 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 27058 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 26455 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 22518 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 66 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 13496 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7946 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 22074 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12913 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7569 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 28474 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.790827 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.507053 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 27999 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.788385 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.505249 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 20065 70.47% 70.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 2633 9.25% 79.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1896 6.66% 86.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1407 4.94% 91.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1291 4.53% 95.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 643 2.26% 98.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 327 1.15% 99.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 165 0.58% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 47 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19729 70.46% 70.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 2607 9.31% 79.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1874 6.69% 86.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1399 5.00% 91.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1239 4.43% 95.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 603 2.15% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 335 1.20% 99.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 163 0.58% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 50 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 28474 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 27999 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 21 6.95% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 199 65.89% 72.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 82 27.15% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 17 5.72% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 196 65.99% 71.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 84 28.28% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7409 65.93% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2656 23.63% 89.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1168 10.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7289 65.97% 65.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2595 23.49% 89.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1160 10.50% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 11238 # Type of FU issued +system.cpu.iq.FU_type_0::total 11049 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7461 66.14% 66.16% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.17% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2675 23.71% 89.90% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1139 10.10% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7322 66.41% 66.43% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.44% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.46% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2566 23.27% 89.73% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1132 10.27% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 11280 # Type of FU issued -system.cpu.iq.FU_type::total 22518 0.00% 0.00% # Type of FU issued -system.cpu.iq.rate 0.485920 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 151 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 151 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 302 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.006706 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.006706 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.013411 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 73836 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 40624 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19843 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_1::total 11025 # Type of FU issued +system.cpu.iq.FU_type::total 22074 0.00% 0.00% # Type of FU issued +system.cpu.iq.rate 0.478579 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 149 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 148 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 297 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.006750 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.006705 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.013455 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 72475 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 39437 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19551 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 22794 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 22345 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 70 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1694 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1632 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 623 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 602 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 321 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 81 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.cacheBlocked 311 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 78 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1720 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 21 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 489 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1598 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 20 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 474 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 265 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 263 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1147 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2751 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 416 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 27257 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 298 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 5780 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2842 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 1095 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2708 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 391 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 26654 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 299 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 5596 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2806 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 53 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 25 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 391 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 39 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 140 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1160 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1300 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 21263 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2485 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2477 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4962 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1255 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 29 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 359 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 38 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 141 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1078 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1219 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20887 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2420 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2389 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4809 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1187 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed system.cpu.iew.exec_nop::0 73 # number of nop insts executed system.cpu.iew.exec_nop::1 73 # number of nop insts executed system.cpu.iew.exec_nop::total 146 # number of nop insts executed -system.cpu.iew.exec_refs::0 3579 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3558 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 7137 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1685 # Number of branches executed -system.cpu.iew.exec_branches::1 1728 # Number of branches executed -system.cpu.iew.exec_branches::total 3413 # Number of branches executed -system.cpu.iew.exec_stores::0 1094 # Number of stores executed +system.cpu.iew.exec_refs::0 3521 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3470 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6991 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1644 # Number of branches executed +system.cpu.iew.exec_branches::1 1667 # Number of branches executed +system.cpu.iew.exec_branches::total 3311 # Number of branches executed +system.cpu.iew.exec_stores::0 1101 # Number of stores executed system.cpu.iew.exec_stores::1 1081 # Number of stores executed -system.cpu.iew.exec_stores::total 2175 # Number of stores executed -system.cpu.iew.exec_rate 0.458838 # Inst execution rate -system.cpu.iew.wb_sent::0 10071 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 10174 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 20245 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9887 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9976 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 19863 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 5227 # num instructions producing a value -system.cpu.iew.wb_producers::1 5224 # num instructions producing a value -system.cpu.iew.wb_producers::total 10451 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6995 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6944 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 13939 # num instructions consuming a value +system.cpu.iew.exec_stores::total 2182 # Number of stores executed +system.cpu.iew.exec_rate 0.452845 # Inst execution rate +system.cpu.iew.wb_sent::0 9956 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9970 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 19926 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9780 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9791 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 19571 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 5173 # num instructions producing a value +system.cpu.iew.wb_producers::1 5150 # num instructions producing a value +system.cpu.iew.wb_producers::total 10323 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6916 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6837 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 13753 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.213353 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.215274 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.428627 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.747248 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.752304 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.749767 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.212037 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.212276 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.424313 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.747976 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.753254 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.750600 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 14469 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 13856 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1066 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 28402 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.449898 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.318202 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1015 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 27930 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.457501 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.335540 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23341 82.18% 82.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2401 8.45% 90.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1094 3.85% 94.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 390 1.37% 95.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 322 1.13% 96.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 184 0.65% 97.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 208 0.73% 98.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 133 0.47% 98.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 329 1.16% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22902 82.00% 82.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2402 8.60% 90.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1059 3.79% 94.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 373 1.34% 95.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 324 1.16% 96.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 194 0.69% 97.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 197 0.71% 98.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 141 0.50% 98.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 338 1.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 28402 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 27930 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6389 # Number of instructions committed system.cpu.commit.committedInsts::1 6389 # Number of instructions committed system.cpu.commit.committedInsts::total 12778 # Number of instructions committed @@ -699,159 +707,168 @@ system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_1::total 6389 # Class of committed instruction system.cpu.commit.op_class::total 12778 0.00% 0.00% # Class of committed instruction -system.cpu.commit.bw_lim_events 329 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 338 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 131970 # The number of ROB reads -system.cpu.rob.rob_writes 57167 # The number of ROB writes -system.cpu.timesIdled 413 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17867 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 129256 # The number of ROB reads +system.cpu.rob.rob_writes 55848 # The number of ROB writes +system.cpu.timesIdled 409 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18125 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6372 # Number of Instructions Simulated system.cpu.committedInsts::1 6372 # Number of Instructions Simulated system.cpu.committedInsts::total 12744 # Number of Instructions Simulated system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::total 12744 # Number of Ops (including micro ops) Simulated -system.cpu.cpi::0 7.272599 # CPI: Cycles Per Instruction -system.cpu.cpi::1 7.272599 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.636299 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.137502 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.137502 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.275005 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 26712 # number of integer regfile reads -system.cpu.int_regfile_writes 15170 # number of integer regfile writes +system.cpu.cpi::0 7.238544 # CPI: Cycles Per Instruction +system.cpu.cpi::1 7.238544 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.619272 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.138149 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.138149 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.276299 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 26323 # number of integer regfile reads +system.cpu.int_regfile_writes 14897 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.toL2Bus.throughput 2709710833 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 835 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 835 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1266 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 696 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1272 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 690 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 1962 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 62784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 62784 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 62784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 981 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 981 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 981 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 490500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1042000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1047000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 4.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 550750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 547500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.4 # Layer utilization (%) system.cpu.icache.tags.replacements::0 7 # number of replacements system.cpu.icache.tags.replacements::1 0 # number of replacements system.cpu.icache.tags.replacements::total 7 # number of replacements -system.cpu.icache.tags.tagsinuse 316.397057 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4348 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 633 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.868878 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 316.469432 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4175 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 636 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.564465 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 316.397057 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.154491 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.154491 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 626 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 275 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.305664 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11201 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11201 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 4348 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4348 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4348 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4348 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4348 # number of overall hits -system.cpu.icache.overall_hits::total 4348 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 936 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 936 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 936 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 936 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 936 # number of overall misses -system.cpu.icache.overall_misses::total 936 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 64563991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 64563991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 64563991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 64563991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 64563991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 64563991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5284 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5284 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5284 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5284 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5284 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5284 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.177139 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.177139 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.177139 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.177139 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.177139 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.177139 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68978.622863 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68978.622863 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68978.622863 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68978.622863 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68978.622863 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68978.622863 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3153 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 316.469432 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.154526 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.154526 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 629 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 282 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 347 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.307129 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 10870 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10870 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 4175 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4175 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4175 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4175 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4175 # number of overall hits +system.cpu.icache.overall_hits::total 4175 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 942 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 942 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 942 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 942 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 942 # number of overall misses +system.cpu.icache.overall_misses::total 942 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 64530491 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 64530491 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 64530491 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 64530491 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 64530491 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 64530491 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5117 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5117 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5117 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5117 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5117 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5117 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184092 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.184092 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.184092 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.184092 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.184092 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.184092 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68503.705945 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68503.705945 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68503.705945 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68503.705945 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68503.705945 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68503.705945 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3163 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 83 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 86 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 37.987952 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 36.779070 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 303 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 303 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 303 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 303 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 303 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 303 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 633 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 633 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 633 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 633 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 633 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 633 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46517493 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46517493 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46517493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46517493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46517493 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46517493 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.119796 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.119796 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.119796 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.119796 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.119796 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.119796 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73487.350711 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73487.350711 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73487.350711 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73487.350711 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73487.350711 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73487.350711 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 306 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 306 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 306 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 306 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 306 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 306 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 636 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 636 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 636 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 636 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 636 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 636 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46571744 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46571744 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46571744 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46571744 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46571744 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46571744 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.124292 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.124292 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.124292 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.124292 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.124292 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.124292 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73226.012579 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73226.012579 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73226.012579 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73226.012579 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73226.012579 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73226.012579 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements::0 0 # number of replacements system.cpu.l2cache.tags.replacements::1 0 # number of replacements system.cpu.l2cache.tags.replacements::total 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 435.916526 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 435.675938 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 833 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002401 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 317.007070 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 118.909455 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009674 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.003629 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.013303 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 317.099899 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 118.576039 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009677 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.003619 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.013296 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 833 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 350 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 483 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 354 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 479 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025421 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 8827 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 8827 # Number of data accesses @@ -861,61 +878,61 @@ system.cpu.l2cache.demand_hits::cpu.inst 2 # nu system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 631 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 202 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 634 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 199 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 833 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 631 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 348 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 634 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 345 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 979 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 631 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 348 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 634 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 345 # number of overall misses system.cpu.l2cache.overall_misses::total 979 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45857000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16325500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 62182500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11847250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 11847250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 45857000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 28172750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 74029750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 45857000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 28172750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 74029750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 633 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 202 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45908000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16069250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 61977250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11885750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 11885750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 45908000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 27955000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 73863000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 45908000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 27955000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 73863000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 636 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 199 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 835 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 633 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 348 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 636 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 345 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 981 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 633 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 348 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 636 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 345 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 981 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996840 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996855 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.997605 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996840 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996855 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.997961 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996840 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996855 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997961 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72673.534073 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80819.306931 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74648.859544 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81145.547945 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81145.547945 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72673.534073 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80956.178161 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75617.722165 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72673.534073 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80956.178161 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75617.722165 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72410.094637 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80750 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74402.460984 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81409.246575 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81409.246575 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72410.094637 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81028.985507 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75447.395301 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72410.094637 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81028.985507 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75447.395301 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -924,164 +941,164 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 631 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 634 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 199 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 833 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 631 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 348 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 634 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 345 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 979 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 631 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 348 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 634 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 345 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 979 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 37981000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13848500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 51829500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10060750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10060750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37981000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23909250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 61890250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37981000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23909250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 61890250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996840 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 37994000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13623750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 51617750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10099750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10099750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37994000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23723500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 61717500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37994000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23723500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 61717500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996855 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997605 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996840 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996855 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.997961 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996840 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996855 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997961 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60191.759113 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68556.930693 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62220.288115 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68909.246575 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68909.246575 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60191.759113 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68704.741379 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63217.824311 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60191.759113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68704.741379 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63217.824311 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59927.444795 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68461.055276 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61966.086435 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69176.369863 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69176.369863 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59927.444795 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68763.768116 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63041.368744 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59927.444795 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68763.768116 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63041.368744 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements::0 0 # number of replacements system.cpu.dcache.tags.replacements::1 0 # number of replacements system.cpu.dcache.tags.replacements::total 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 212.136486 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4920 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 348 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.137931 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 211.551618 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4777 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 345 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.846377 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 212.136486 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.051791 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.051791 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.084961 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 12242 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 12242 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 3896 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3896 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1024 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1024 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4920 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4920 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4920 # number of overall hits -system.cpu.dcache.overall_hits::total 4920 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 321 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 321 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 706 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 706 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1027 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1027 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1027 # number of overall misses -system.cpu.dcache.overall_misses::total 1027 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 23379250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23379250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 51507169 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 51507169 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 74886419 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 74886419 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 74886419 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 74886419 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 4217 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 4217 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 211.551618 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.051648 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.051648 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 345 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 250 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.084229 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 11951 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 11951 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 3755 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3755 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1022 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 4777 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4777 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4777 # number of overall hits +system.cpu.dcache.overall_hits::total 4777 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 318 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 318 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 708 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 708 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1026 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1026 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1026 # number of overall misses +system.cpu.dcache.overall_misses::total 1026 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 22790250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22790250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 51585419 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 51585419 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 74375669 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 74375669 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 74375669 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 74375669 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 4073 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 4073 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5947 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5947 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5947 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5947 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076120 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076120 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.408092 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.408092 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.172692 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.172692 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.172692 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.172692 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72832.554517 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72832.554517 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72956.330028 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72956.330028 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72917.642648 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72917.642648 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72917.642648 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72917.642648 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5674 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 5803 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5803 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5803 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5803 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078075 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.078075 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409249 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.409249 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.176805 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.176805 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.176805 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.176805 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71667.452830 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71667.452830 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72860.761299 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72860.761299 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72490.905458 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72490.905458 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72490.905458 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72490.905458 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5512 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 139 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 138 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.820144 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.942029 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 119 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 560 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 560 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 679 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 679 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 679 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 679 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 562 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 562 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 681 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 681 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 681 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 681 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 199 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 199 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 348 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 348 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 348 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 348 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16537500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16537500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11999490 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11999490 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28536990 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28536990 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28536990 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28536990 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.047901 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.047901 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 345 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 345 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16277750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16277750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12037990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12037990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28315740 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28315740 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28315740 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28315740 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048858 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048858 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058517 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.058517 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058517 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.058517 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81868.811881 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81868.811881 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82188.287671 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82188.287671 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82002.844828 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 82002.844828 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82002.844828 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 82002.844828 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059452 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059452 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059452 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.059452 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81797.738693 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81797.738693 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82451.986301 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82451.986301 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82074.608696 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82074.608696 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82074.608696 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82074.608696 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 2ad955d95..bc6a50393 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27662000 # Number of ticks simulated -final_tick 27662000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 27671000 # Number of ticks simulated +final_tick 27671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71683 # Simulator instruction rate (inst/s) -host_op_rate 71677 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 130761776 # Simulator tick rate (ticks/s) -host_mem_usage 270740 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 87465 # Simulator instruction rate (inst/s) +host_op_rate 87458 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 159601098 # Simulator tick rate (ticks/s) +host_mem_usage 286440 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19008 # Nu system.physmem.num_reads::cpu.inst 297 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 435 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 687152050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 319282771 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1006434820 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 687152050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 687152050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 687152050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 319282771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1006434820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 686928553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 319178924 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1006107477 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 686928553 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 686928553 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 686928553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 319178924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1006107477 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 436 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 436 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 27628500 # Total gap between requests +system.physmem.totGap 27637500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -92,8 +92,8 @@ system.physmem.writePktSize::5 0 # Wr system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -199,44 +199,52 @@ system.physmem.bytesPerActivate::640-767 3 4.55% 78.79% # By system.physmem.bytesPerActivate::768-895 3 4.55% 83.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 11 16.67% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 66 # Bytes accessed per row activation -system.physmem.totQLat 2526750 # Total ticks spent queuing -system.physmem.totMemAccLat 10701750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2648750 # Total ticks spent queuing +system.physmem.totMemAccLat 10823750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2180000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5795.30 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6075.11 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24545.30 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1008.75 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24825.11 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1008.42 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1008.75 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1008.42 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 7.88 # Data bus utilization in percentage system.physmem.busUtilRead 7.88 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.49 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.50 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 362 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.03 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 63368.12 # Average gap between requests +system.physmem.avgGap 63388.76 # Average gap between requests system.physmem.pageHitRate 83.03 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 1258750 # Time in different power states system.physmem.memoryStateTime::REF 780000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 21617500 # Time in different power states +system.physmem.memoryStateTime::ACT 21626500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1006434820 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 351 # Transaction distribution system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 85 # Transaction distribution system.membus.trans_dist::ReadExResp 85 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 871 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 871 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27840 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 27840 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 27840 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 27840 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 436 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 436 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 436 # Request fanout histogram system.membus.reqLayer0.occupancy 519500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) system.membus.respLayer1.occupancy 4048500 # Layer occupancy (ticks) @@ -252,7 +260,7 @@ system.cpu.branchPred.BTBHitPct 66.317073 # BT system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 55325 # number of cpu cycles simulated +system.cpu.numCycles 55343 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True). @@ -274,12 +282,12 @@ system.cpu.execution_unit.executions 11045 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 21861 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 21863 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 438 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 37757 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 440 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 37775 # Number of cycles cpu's stages were not processed system.cpu.runCycles 17568 # Number of cycles cpu stages are processed. -system.cpu.activity 31.754180 # Percentage of cycles cpu is active +system.cpu.activity 31.743852 # Percentage of cycles cpu is active system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed @@ -291,36 +299,36 @@ system.cpu.committedInsts 15162 # Nu system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) -system.cpu.cpi 3.648925 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.650112 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 3.648925 # CPI: Total CPI of All Threads -system.cpu.ipc 0.274053 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.650112 # CPI: Total CPI of All Threads +system.cpu.ipc 0.273964 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.274053 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 41899 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.273964 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 41917 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 24.267510 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 45972 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 24.259617 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 45990 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 16.905558 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 46522 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 16.900060 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 46540 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 15.911432 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 52447 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 15.906257 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 52465 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 5.201988 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 46016 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 5.200296 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46034 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 16.826028 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 16.820555 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 168.857752 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 168.877638 # Cycle average of tags in use system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 10.046823 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 168.857752 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082450 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082450 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 168.877638 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082460 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082460 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 299 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id @@ -339,12 +347,12 @@ system.cpu.icache.demand_misses::cpu.inst 381 # n system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses system.cpu.icache.overall_misses::total 381 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25881500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25881500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25881500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25881500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25881500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25881500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25899500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25899500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25899500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25899500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25899500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25899500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses @@ -357,12 +365,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.112555 system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67930.446194 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67930.446194 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67930.446194 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67930.446194 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67930.446194 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67930.446194 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67977.690289 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67977.690289 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67977.690289 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67977.690289 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67977.690289 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67977.690289 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -383,26 +391,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301 system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20450500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20450500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20450500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20450500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20450500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20450500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20459500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20459500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20459500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20459500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20459500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20459500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67941.860465 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67941.860465 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67941.860465 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67941.860465 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67941.860465 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67941.860465 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67971.760797 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67971.760797 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67971.760797 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67971.760797 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67971.760797 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67971.760797 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1011062107 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 354 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution @@ -410,11 +417,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 85 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 600 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 876 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 439 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 439 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 439 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 500000 # Layer occupancy (ticks) @@ -422,16 +439,16 @@ system.cpu.toL2Bus.respLayer0.utilization 1.8 # L system.cpu.toL2Bus.respLayer1.occupancy 222000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 199.884332 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.907137 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005714 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.191422 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.692910 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.211200 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.695937 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005133 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000967 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006100 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006101 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id @@ -455,16 +472,16 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20127000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20136000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3695250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 23822250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6008750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6008750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20127000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9704000 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 23831250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5999750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5999750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20136000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9695000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 29831000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20127000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9704000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20136000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9695000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 29831000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) @@ -488,16 +505,16 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67314.381271 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67344.481605 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69721.698113 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67676.846591 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70691.176471 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70691.176471 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67314.381271 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70318.840580 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67702.414773 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70585.294118 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70585.294118 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67344.481605 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70253.623188 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 68263.157895 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67314.381271 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70318.840580 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67344.481605 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70253.623188 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 68263.157895 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -518,16 +535,16 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16410500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16419500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3036250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19446750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4964250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4964250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16410500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8000500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19455750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4955250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4955250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16419500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7991500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 24411000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16410500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8000500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16419500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7991500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 24411000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses @@ -540,27 +557,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54884.615385 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54914.715719 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57287.735849 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55246.448864 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58402.941176 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58402.941176 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54884.615385 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57974.637681 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55272.017045 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58297.058824 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58297.058824 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54914.715719 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57909.420290 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55860.411899 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54884.615385 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57974.637681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54914.715719 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57909.420290 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55860.411899 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.520897 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 98.529834 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.520897 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024053 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024053 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 98.529834 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024055 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024055 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id @@ -587,12 +604,12 @@ system.cpu.dcache.overall_misses::cpu.data 480 # system.cpu.dcache.overall_misses::total 480 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 4268250 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 4268250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25916250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25916250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30184500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30184500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30184500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30184500 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25898250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25898250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30166500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30166500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30166500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30166500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -613,12 +630,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73590.517241 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 73590.517241 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61412.914692 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61412.914692 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62884.375000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62884.375000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62884.375000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62884.375000 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61370.260664 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61370.260664 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62846.875000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62846.875000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62846.875000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62846.875000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 1102 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked @@ -645,12 +662,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 138 system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3749750 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 3749750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6096750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6096750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9846500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9846500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9846500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9846500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6087750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6087750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9837500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9837500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9837500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9837500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -661,12 +678,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70750 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70750 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71726.470588 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71726.470588 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71351.449275 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71351.449275 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71351.449275 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71351.449275 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71620.588235 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71620.588235 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71286.231884 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71286.231884 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71286.231884 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71286.231884 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 07c326366..5e7063deb 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu sim_ticks 25944000 # Number of ticks simulated final_tick 25944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 14664 # Simulator instruction rate (inst/s) -host_op_rate 14664 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26353337 # Simulator tick rate (ticks/s) -host_mem_usage 237548 # Number of bytes of host memory used -host_seconds 0.98 # Real time elapsed on the host +host_inst_rate 79125 # Simulator instruction rate (inst/s) +host_op_rate 79119 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 142180718 # Simulator tick rate (ticks/s) +host_mem_usage 289004 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -91,8 +91,8 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 6 8.33% 83.33% # By system.physmem.bytesPerActivate::896-1023 1 1.39% 84.72% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 11 15.28% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 72 # Bytes accessed per row activation -system.physmem.totQLat 2648500 # Total ticks spent queuing -system.physmem.totMemAccLat 11873500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2786000 # Total ticks spent queuing +system.physmem.totMemAccLat 12011000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2460000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5383.13 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5662.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24133.13 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24412.60 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1213.69 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1213.69 # Average system read bandwidth in MiByte/s @@ -227,17 +227,25 @@ system.physmem.memoryStateTime::REF 780000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 22761250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1211224175 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 409 # Transaction distribution system.membus.trans_dist::ReadResp 408 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution system.membus.trans_dist::ReadExResp 83 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 983 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 983 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 31424 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 492 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 492 # Request fanout histogram system.membus.reqLayer0.occupancy 611000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) system.membus.respLayer1.occupancy 4586750 # Layer occupancy (ticks) @@ -540,7 +548,6 @@ system.cpu.int_regfile_reads 33400 # nu system.cpu.int_regfile_writes 18599 # number of integer regfile writes system.cpu.misc_regfile_reads 7136 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1216157879 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution @@ -548,11 +555,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 83 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 295 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 987 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 31552 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 494 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 494 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 579250 # Layer occupancy (ticks) @@ -560,12 +577,12 @@ system.cpu.toL2Bus.respLayer0.utilization 2.2 # L system.cpu.toL2Bus.respLayer1.occupancy 233000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 192.510615 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 192.510962 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5925 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 346 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 17.124277 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 192.510615 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 192.510962 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.093999 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.093999 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id @@ -586,12 +603,12 @@ system.cpu.icache.demand_misses::cpu.inst 528 # n system.cpu.icache.demand_misses::total 528 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 528 # number of overall misses system.cpu.icache.overall_misses::total 528 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32454000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32454000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32454000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32454000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32454000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32454000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32445000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32445000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32445000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32445000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32445000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32445000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6453 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6453 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6453 # number of demand (read+write) accesses @@ -604,12 +621,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.081822 system.cpu.icache.demand_miss_rate::total 0.081822 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.081822 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.081822 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61465.909091 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61465.909091 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61465.909091 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61465.909091 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61465.909091 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61465.909091 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61448.863636 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61448.863636 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61448.863636 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61448.863636 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 42 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -630,24 +647,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 346 system.cpu.icache.demand_mshr_misses::total 346 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 346 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 346 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23048750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23048750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23048750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23048750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23048750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23048750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23039750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23039750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23039750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23039750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23039750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23039750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.053618 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.053618 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.053618 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66614.884393 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66614.884393 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66614.884393 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66614.884393 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66614.884393 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66614.884393 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66588.872832 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66588.872832 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66588.872832 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66588.872832 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66588.872832 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66588.872832 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 226.536653 # Cycle average of tags in use @@ -655,8 +672,8 @@ system.cpu.l2cache.tags.total_refs 2 # To system.cpu.l2cache.tags.sampled_refs 408 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.004902 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.902478 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 34.634175 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.902825 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 34.633828 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005856 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001057 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006913 # Average percentage of cache occupancy @@ -683,16 +700,16 @@ system.cpu.l2cache.demand_misses::total 492 # nu system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses system.cpu.l2cache.overall_misses::total 492 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22682250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4667500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22673250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 27349750 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6151000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 6151000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22682250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10818500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22673250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10827500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 33500750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22682250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10818500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22673250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10827500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 33500750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 346 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 65 # number of ReadReq accesses(hits+misses) @@ -716,16 +733,16 @@ system.cpu.l2cache.demand_miss_rate::total 0.995951 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994220 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995951 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65936.773256 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71807.692308 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65910.610465 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71946.153846 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 66869.804401 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74108.433735 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74108.433735 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65936.773256 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73097.972973 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65910.610465 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73158.783784 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 68090.955285 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65936.773256 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73097.972973 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65910.610465 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73158.783784 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 68090.955285 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -746,16 +763,16 @@ system.cpu.l2cache.demand_mshr_misses::total 492 system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 492 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18356250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3880500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18347250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3889500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22236750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5131500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5131500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18356250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9012000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18347250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9021000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 27368250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18356250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9012000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18347250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9021000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 27368250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses @@ -768,25 +785,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995951 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995951 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53361.191860 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59700 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53335.029070 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59838.461538 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54368.581907 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61825.301205 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61825.301205 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53361.191860 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60891.891892 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53361.191860 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60891.891892 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.823641 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 98.823294 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 4124 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 28.054422 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.823641 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 98.823294 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.024127 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.024127 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id @@ -813,14 +830,14 @@ system.cpu.dcache.demand_misses::cpu.data 548 # n system.cpu.dcache.demand_misses::total 548 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 548 # number of overall misses system.cpu.dcache.overall_misses::total 548 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8661750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8661750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8670750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8670750 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 26093224 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 26093224 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34754974 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34754974 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34754974 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34754974 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34763974 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34763974 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34763974 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34763974 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 3224 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 3224 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -839,14 +856,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.117445 system.cpu.dcache.demand_miss_rate::total 0.117445 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.117445 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.117445 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62314.748201 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62314.748201 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62379.496403 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62379.496403 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63797.613692 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 63797.613692 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63421.485401 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63421.485401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63421.485401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63421.485401 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63437.908759 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63437.908759 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 955 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked @@ -871,14 +888,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 148 system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4732000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4732000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6235500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 6235500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10967500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10967500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10967500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10967500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10976500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10976500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10976500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10976500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020161 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020161 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses @@ -887,14 +904,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031719 system.cpu.dcache.demand_mshr_miss_rate::total 0.031719 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.031719 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72800 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72800 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72938.461538 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72938.461538 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75126.506024 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75126.506024 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74104.729730 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74104.729730 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74104.729730 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74104.729730 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index 33f452573..8d8eb59bc 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000008 # Nu sim_ticks 7612000 # Number of ticks simulated final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 945144 # Simulator instruction rate (inst/s) -host_op_rate 944261 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 473677660 # Simulator tick rate (ticks/s) -host_mem_usage 260980 # Number of bytes of host memory used +host_inst_rate 893248 # Simulator instruction rate (inst/s) +host_op_rate 892512 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 447738368 # Simulator tick rate (ticks/s) +host_mem_usage 276192 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated @@ -37,9 +37,29 @@ system.physmem.bw_write::total 1187861272 # Wr system.physmem.bw_total::cpu.inst 7991066737 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2677877036 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10668943773 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 10676563321 # Throughput (bytes/s) -system.membus.data_through_bus 81270 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 17432 # Transaction distribution +system.membus.trans_dist::ReadResp 17432 # Transaction distribution +system.membus.trans_dist::WriteReq 1442 # Transaction distribution +system.membus.trans_dist::WriteResp 1442 # Transaction distribution +system.membus.trans_dist::SwapReq 6 # Transaction distribution +system.membus.trans_dist::SwapResp 6 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 30414 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 7346 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 37760 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 60828 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 20442 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 81270 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 18880 # Request fanout histogram +system.membus.snoop_fanout::mean 0.805456 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.395860 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3673 19.45% 19.45% # Request fanout histogram +system.membus.snoop_fanout::1 15207 80.55% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 18880 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 15225 # number of cpu cycles simulated diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 853f97527..6363c4d14 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000041 # Nu sim_ticks 41368000 # Number of ticks simulated final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 324057 # Simulator instruction rate (inst/s) -host_op_rate 323947 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 883591781 # Simulator tick rate (ticks/s) -host_mem_usage 269720 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 245276 # Simulator instruction rate (inst/s) +host_op_rate 245221 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 668919684 # Simulator tick rate (ticks/s) +host_mem_usage 285672 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 430090892 # In system.physmem.bw_total::cpu.inst 430090892 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 213498356 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 643589248 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 643589248 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 331 # Transaction distribution system.membus.trans_dist::ReadResp 331 # Transaction distribution system.membus.trans_dist::ReadExReq 85 # Transaction distribution system.membus.trans_dist::ReadExResp 85 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 26624 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 416 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 416 # Request fanout histogram system.membus.reqLayer0.occupancy 416000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) system.membus.respLayer1.occupancy 3744000 # Layer occupancy (ticks) @@ -427,7 +435,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 646683427 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 333 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution @@ -435,11 +442,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 85 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 418 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks) diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 3dcd489a6..2281d59b5 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000106 # Number of seconds simulated -sim_ticks 105639000 # Number of ticks simulated -final_tick 105639000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 105696000 # Number of ticks simulated +final_tick 105696000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115016 # Simulator instruction rate (inst/s) -host_op_rate 115016 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12246117 # Simulator tick rate (ticks/s) -host_mem_usage 253808 # Number of bytes of host memory used -host_seconds 8.63 # Real time elapsed on the host -sim_insts 992165 # Number of instructions simulated -sim_ops 992165 # Number of ops (including micro ops) simulated +host_inst_rate 162054 # Simulator instruction rate (inst/s) +host_op_rate 162054 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17251704 # Simulator tick rate (ticks/s) +host_mem_usage 304448 # Number of bytes of host memory used +host_seconds 6.13 # Real time elapsed on the host +sim_insts 992854 # Number of instructions simulated +sim_ops 992854 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 23104 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 896 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 4928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 4800 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory system.physmem.bytes_read::total 42752 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 23104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 4928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 4800 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 29056 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 361 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 14 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 77 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 75 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::total 668 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 218707106 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 101780592 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 7270042 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 7875879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 46649438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 12116737 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 2423347 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7875879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 404699022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 218707106 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 7270042 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 46649438 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 2423347 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 275049934 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 218707106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 101780592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 7270042 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7875879 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 46649438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 12116737 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 2423347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7875879 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 404699022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 218589161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 101725704 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 8477142 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 7871632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 45413261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 12110203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 2422041 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7871632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 404480775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 218589161 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 8477142 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 45413261 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 2422041 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 274901605 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 218589161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 101725704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 8477142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7871632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 45413261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 12110203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 2422041 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7871632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 404480775 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 669 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 669 # Number of DRAM read bursts, including those serviced by the write queue @@ -105,7 +105,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 105611000 # Total gap between requests +system.physmem.totGap 105668000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -120,8 +120,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 194 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see @@ -216,133 +216,141 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 144 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 278.222222 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.203281 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 257.152031 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 43 29.86% 29.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39 27.08% 56.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 24 16.67% 73.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 13 9.03% 82.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 4.17% 86.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6 4.17% 90.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6 4.17% 95.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 1.39% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 3.47% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 144 # Bytes accessed per row activation -system.physmem.totQLat 6117250 # Total ticks spent queuing -system.physmem.totMemAccLat 18661000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 143 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 280.167832 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 190.166692 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 257.214493 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 42 29.37% 29.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 39 27.27% 56.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 24 16.78% 73.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 13 9.09% 82.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 6 4.20% 86.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6 4.20% 90.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 4.20% 95.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 1.40% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 3.50% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 143 # Bytes accessed per row activation +system.physmem.totQLat 6392250 # Total ticks spent queuing +system.physmem.totMemAccLat 18936000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 3345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9143.87 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9554.93 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27893.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 405.30 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28304.93 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 405.09 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 405.30 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 405.09 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.17 # Data bus utilization in percentage -system.physmem.busUtilRead 3.17 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.16 # Data bus utilization in percentage +system.physmem.busUtilRead 3.16 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 514 # Number of row buffer hits during reads +system.physmem.readRowHits 515 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.83 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.98 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 157863.98 # Average gap between requests -system.physmem.pageHitRate 76.83 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 46009250 # Time in different power states +system.physmem.avgGap 157949.18 # Average gap between requests +system.physmem.pageHitRate 76.98 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 46119750 # Time in different power states system.physmem.memoryStateTime::REF 3380000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 52645250 # Time in different power states +system.physmem.memoryStateTime::ACT 52590250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 404699022 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 538 # Transaction distribution system.membus.trans_dist::ReadResp 537 # Transaction distribution -system.membus.trans_dist::UpgradeReq 272 # Transaction distribution +system.membus.trans_dist::UpgradeReq 276 # Transaction distribution system.membus.trans_dist::UpgradeResp 78 # Transaction distribution -system.membus.trans_dist::ReadExReq 182 # Transaction distribution +system.membus.trans_dist::ReadExReq 177 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1738 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1738 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42752 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 42752 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 42752 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 937500 # Layer occupancy (ticks) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1737 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1737 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42752 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 42752 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 244 # Total snoops (count) +system.membus.snoop_fanout::samples 991 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 991 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 991 # Request fanout histogram +system.membus.reqLayer0.occupancy 940500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 6389922 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 6384422 # Layer occupancy (ticks) system.membus.respLayer1.utilization 6.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 424.251527 # Cycle average of tags in use -system.l2c.tags.total_refs 1658 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 424.241443 # Cycle average of tags in use +system.l2c.tags.total_refs 1667 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 535 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.099065 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 3.115888 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.793481 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 289.756161 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.232417 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 9.250622 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.723175 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 57.184063 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 5.359898 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2.266069 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.685642 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.793516 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 289.763968 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.233930 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 9.364536 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 0.722908 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 57.054480 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 5.356180 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 2.266531 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.685395 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.004421 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.000889 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000141 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000143 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000873 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000871 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.000082 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.inst 0.000035 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.data 0.000010 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.006474 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.006473 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 535 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.008163 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 20037 # Number of tag accesses -system.l2c.tags.data_accesses 20037 # Number of data accesses +system.l2c.tags.tag_accesses 20109 # Number of tag accesses +system.l2c.tags.data_accesses 20109 # Number of data accesses system.l2c.ReadReq_hits::cpu0.inst 250 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 481 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 480 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 409 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 413 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 486 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 492 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1658 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1667 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits system.l2c.demand_hits::cpu0.inst 250 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 481 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 480 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 409 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 413 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 486 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 492 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 1658 # number of demand (read+write) hits +system.l2c.demand_hits::total 1667 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 250 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 481 # number of overall hits +system.l2c.overall_hits::cpu1.inst 480 # number of overall hits system.l2c.overall_hits::cpu1.data 11 # number of overall hits -system.l2c.overall_hits::cpu2.inst 409 # number of overall hits +system.l2c.overall_hits::cpu2.inst 413 # number of overall hits system.l2c.overall_hits::cpu2.data 5 # number of overall hits -system.l2c.overall_hits::cpu3.inst 486 # number of overall hits +system.l2c.overall_hits::cpu3.inst 492 # number of overall hits system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 1658 # number of overall hits +system.l2c.overall_hits::total 1667 # number of overall hits system.l2c.ReadReq_misses::cpu0.inst 363 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 16 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 17 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 81 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 80 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.inst 7 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses @@ -359,63 +367,63 @@ system.l2c.ReadExReq_misses::cpu3.data 12 # nu system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses system.l2c.demand_misses::cpu0.inst 363 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 16 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 17 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 81 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 80 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.inst 7 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses system.l2c.demand_misses::total 681 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.inst 363 # number of overall misses system.l2c.overall_misses::cpu0.data 168 # number of overall misses -system.l2c.overall_misses::cpu1.inst 16 # number of overall misses +system.l2c.overall_misses::cpu1.inst 17 # number of overall misses system.l2c.overall_misses::cpu1.data 13 # number of overall misses -system.l2c.overall_misses::cpu2.inst 81 # number of overall misses +system.l2c.overall_misses::cpu2.inst 80 # number of overall misses system.l2c.overall_misses::cpu2.data 20 # number of overall misses system.l2c.overall_misses::cpu3.inst 7 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses system.l2c.overall_misses::total 681 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 25055500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 5652750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 1295250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 25064250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 5642000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 1337250 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.data 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 5783750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 523250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 5652250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 765250 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.inst 458000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.data 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 38918500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 39069000 # number of ReadReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0.data 6921000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 852750 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu2.data 1047250 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 836500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9657500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 25055500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 12573750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 1295250 # number of demand (read+write) miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 837000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9658000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 25064250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 12563000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 1337250 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 927750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 5783750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1570500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 5652250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1812500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu3.inst 458000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 911500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 48576000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 25055500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 12573750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 1295250 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu3.data 912000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 48727000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 25064250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 12563000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 1337250 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 927750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 5783750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1570500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 5652250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1812500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu3.inst 458000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 911500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 48576000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 912000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 48727000 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 613 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 497 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 490 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 493 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 493 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 499 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2208 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2217 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 26 # number of UpgradeReq accesses(hits+misses) @@ -432,29 +440,29 @@ system.l2c.demand_accesses::cpu0.inst 613 # nu system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 497 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 490 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 493 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 493 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 499 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2339 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2348 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 613 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 497 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 490 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 493 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 493 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 499 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2339 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2348 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.592170 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.032193 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.034205 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.165306 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.162272 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.data 0.583333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.014199 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.014028 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.249094 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.248083 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.884615 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses @@ -467,54 +475,54 @@ system.l2c.ReadExReq_miss_rate::cpu3.data 1 # m system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.592170 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.032193 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.034205 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.165306 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.162272 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.800000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.014199 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.014028 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.291150 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.290034 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.592170 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.032193 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.034205 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.165306 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.162272 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.014199 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.014028 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.291150 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69023.415978 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 76388.513514 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80953.125000 # average ReadReq miss latency +system.l2c.overall_miss_rate::total 0.290034 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69047.520661 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 76243.243243 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78661.764706 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 71404.320988 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 74750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 70653.125000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 109321.428571 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.inst 65428.571429 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.data 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 70760.909091 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 71034.545455 # average ReadReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 73627.659574 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71062.500000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2.data 80557.692308 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 69708.333333 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 73721.374046 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 69023.415978 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 74843.750000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 80953.125000 # average overall miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 69750 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 73725.190840 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 69047.520661 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 74779.761905 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 78661.764706 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 71365.384615 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 71404.320988 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 78525 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 70653.125000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 90625 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu3.inst 65428.571429 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 70115.384615 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 71330.396476 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 69023.415978 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 74843.750000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 80953.125000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 70153.846154 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 71552.129222 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 69047.520661 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 74779.761905 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 78661.764706 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 71365.384615 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 71404.320988 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 78525 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 70653.125000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 90625 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3.inst 65428.571429 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 70115.384615 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 71330.396476 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 70153.846154 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 71552.129222 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -524,25 +532,25 @@ system.l2c.avg_blocked_cycles::no_targets nan # a system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.inst 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.inst 5 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu3.inst 3 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 12 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.inst 362 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 12 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 14 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 77 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 75 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu3.inst 4 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses @@ -559,31 +567,31 @@ system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.inst 362 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 12 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 14 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 77 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 75 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu3.inst 4 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 669 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.inst 362 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 12 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 14 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 77 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 75 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.inst 4 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 669 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 20468500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4740250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 904000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 20478250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4729000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 985000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.data 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4615250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 436250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4446750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 678750 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 236250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu3.data 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 31525500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 31679000 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 230023 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 170017 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 180018 # number of UpgradeReq MSHR miss cycles @@ -594,33 +602,33 @@ system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 701250 system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 888250 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 687000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::total 8038000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 20468500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 10501750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 904000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 20478250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 10490500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 985000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 763750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 4615250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 1324500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 4446750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 1567000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.inst 236250 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.data 749500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 39563500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 20468500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 10501750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 904000 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 39717000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 20478250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 10490500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 985000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 763750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 4615250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 1324500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 4446750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1567000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.inst 236250 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.data 749500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 39563500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 39717000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.590538 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.024145 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.028169 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.157143 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.152130 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.008114 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.008016 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.243659 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.242670 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.884615 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses @@ -633,31 +641,31 @@ system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.590538 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.024145 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.028169 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.157143 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.152130 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.008114 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.008016 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.286020 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.284923 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.590538 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.024145 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.028169 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.157143 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.152130 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.008114 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.008016 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.286020 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56542.817680 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64057.432432 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 75333.333333 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_rate::total 0.284923 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56569.751381 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63905.405405 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70357.142857 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 59938.311688 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 59290 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 96964.285714 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 59062.500000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 58597.583643 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 58882.899628 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency @@ -668,201 +676,216 @@ system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58437.500000 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68326.923077 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 57250 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 61358.778626 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56542.817680 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62510.416667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56569.751381 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62443.452381 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70357.142857 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 59938.311688 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 59290 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 78350 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 59062.500000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 57653.846154 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59138.266069 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56542.817680 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62510.416667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59367.713004 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56569.751381 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62443.452381 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70357.142857 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 59938.311688 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 59290 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 78350 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 59062.500000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 57653.846154 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59138.266069 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59367.713004 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.toL2Bus.throughput 1921108681 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2758 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2757 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2766 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2765 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 413 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 413 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 279 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 279 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 406 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 406 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1225 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 584 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 583 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 361 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 980 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 986 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 371 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5866 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39168 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31808 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31552 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 149696 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 149696 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 53248 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 1733986 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 986 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 353 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 998 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 375 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5880 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39168 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31808 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31552 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31936 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 150272 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1022 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3452 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 3452 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3452 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1739480 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2820249 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2819999 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1469763 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1460516 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 2240244 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 2239746 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 2.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1184253 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1188247 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 2220245 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 2234243 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 2.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 1188993 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 1152996 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2220246 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 2246748 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 2.1 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1196995 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 1204495 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%) -system.cpu0.branchPred.lookups 81365 # Number of BP lookups -system.cpu0.branchPred.condPredicted 78481 # Number of conditional branches predicted +system.cpu0.branchPred.lookups 81418 # Number of BP lookups +system.cpu0.branchPred.condPredicted 78534 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 1187 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 78090 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 75342 # Number of BTB hits +system.cpu0.branchPred.BTBLookups 78143 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 75395 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 96.480983 # BTB Hit Percentage +system.cpu0.branchPred.BTBHitPct 96.483370 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 733 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 211279 # number of cpu cycles simulated +system.cpu0.numCycles 211393 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 20058 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 480743 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 81365 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 76075 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 164045 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.icacheStallCycles 20064 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 481063 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 81418 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 76128 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 164143 # Number of cycles fetch has run and was not squashing or blocked system.cpu0.fetch.SquashCycles 2674 # Number of cycles fetch has spent squashing system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu0.fetch.PendingTrapStallCycles 1880 # Number of stall cycles due to pending traps system.cpu0.fetch.CacheLines 7123 # Number of cache lines fetched system.cpu0.fetch.IcacheSquashes 658 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 187323 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.566385 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.225399 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::samples 187427 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.566669 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.225288 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 30153 16.10% 16.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 77599 41.43% 57.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 30149 16.09% 16.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 77654 41.43% 57.52% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::2 823 0.44% 57.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1078 0.58% 58.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 624 0.33% 58.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 72927 38.93% 97.80% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1078 0.58% 58.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 624 0.33% 58.86% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 72980 38.94% 97.80% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::6 691 0.37% 98.17% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::7 437 0.23% 98.40% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::8 2991 1.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 187323 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.385107 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.275394 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 15731 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 17849 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 151731 # Number of cycles decode is running +system.cpu0.fetch.rateDist::total 187427 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.385150 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.275681 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 15737 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 17837 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 151841 # Number of cycles decode is running system.cpu0.decode.UnblockCycles 675 # Number of cycles decode is unblocking system.cpu0.decode.SquashCycles 1337 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 468882 # Number of instructions handled by decode +system.cpu0.decode.DecodedInsts 469212 # Number of instructions handled by decode system.cpu0.rename.SquashCycles 1337 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 16349 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2025 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14605 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 151742 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1265 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 465427 # Number of instructions processed by rename +system.cpu0.rename.IdleCycles 16355 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2021 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 14599 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 151852 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1263 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 465757 # Number of instructions processed by rename system.cpu0.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 18 # Number of times rename has blocked due to LQ full +system.cpu0.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full system.cpu0.rename.SQFullEvents 756 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 318792 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 928161 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 701504 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 304835 # Number of HB maps that are committed +system.cpu0.rename.RenamedOperands 319012 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 928821 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 701999 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 305055 # Number of HB maps that are committed system.cpu0.rename.UndoneMaps 13957 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 896 # count of serializing insts renamed system.cpu0.rename.tempSerializingInsts 905 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4588 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 148468 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 75131 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 72391 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 72142 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 389496 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.rename.skidInsts 4572 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 148578 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 75186 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 72446 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 72197 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 389771 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 964 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 386182 # Number of instructions issued +system.cpu0.iq.iqInstsIssued 386457 # Number of instructions issued system.cpu0.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued system.cpu0.iq.iqSquashedInstsExamined 12213 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 11099 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedOperandsExamined 11103 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 405 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 187323 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.061583 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.125394 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::samples 187427 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.061907 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.125198 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33109 17.67% 17.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4301 2.30% 19.97% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 73576 39.28% 59.25% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 73130 39.04% 98.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1662 0.89% 99.18% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 894 0.48% 99.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 408 0.22% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33106 17.66% 17.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4299 2.29% 19.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 73629 39.28% 59.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 73187 39.05% 98.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1656 0.88% 99.17% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 900 0.48% 99.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 407 0.22% 99.87% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 171 0.09% 99.96% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 72 0.04% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 187323 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 187427 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 97 34.15% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 34.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 84 29.58% 63.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 103 36.27% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 96 33.92% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 84 29.68% 63.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 103 36.40% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 163788 42.41% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 163898 42.41% 42.41% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.41% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.41% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.41% # Type of FU issued @@ -891,23 +914,23 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.41% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.41% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.41% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 147930 38.31% 80.72% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 74464 19.28% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 148040 38.31% 80.72% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 74519 19.28% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 386182 # Type of FU issued -system.cpu0.iq.rate 1.827830 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 284 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000735 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 959994 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 402726 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 384333 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 386457 # Type of FU issued +system.cpu0.iq.rate 1.828145 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 283 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000732 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 960647 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 403001 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 384607 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 386466 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 386740 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 71762 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 71819 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread0.squashedLoads 2461 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed @@ -919,68 +942,68 @@ system.cpu0.iew.lsq.thread0.rescheduledLoads 0 system.cpu0.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu0.iew.iewSquashCycles 1337 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1986 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 48 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 463277 # Number of instructions dispatched to IQ +system.cpu0.iew.iewBlockCycles 1980 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 463607 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 160 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 148468 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 75131 # Number of dispatched store instructions +system.cpu0.iew.iewDispLoadInsts 148578 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 75186 # Number of dispatched store instructions system.cpu0.iew.iewDispNonSpecInsts 843 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 43 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewIQFullEvents 45 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations system.cpu0.iew.predictedTakenIncorrect 323 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 1099 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.branchMispredicts 1422 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 385174 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 147630 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1008 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 385445 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 147736 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 72817 # number of nop insts executed -system.cpu0.iew.exec_refs 221956 # number of memory reference insts executed -system.cpu0.iew.exec_branches 76403 # Number of branches executed -system.cpu0.iew.exec_stores 74326 # Number of stores executed -system.cpu0.iew.exec_rate 1.823059 # Inst execution rate -system.cpu0.iew.wb_sent 384701 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 384333 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 227933 # num instructions producing a value -system.cpu0.iew.wb_consumers 231165 # num instructions consuming a value +system.cpu0.iew.exec_nop 72872 # number of nop insts executed +system.cpu0.iew.exec_refs 222117 # number of memory reference insts executed +system.cpu0.iew.exec_branches 76458 # Number of branches executed +system.cpu0.iew.exec_stores 74381 # Number of stores executed +system.cpu0.iew.exec_rate 1.823357 # Inst execution rate +system.cpu0.iew.wb_sent 384977 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 384607 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 228096 # num instructions producing a value +system.cpu0.iew.wb_consumers 231328 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.819078 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.986019 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.819393 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.986028 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu0.commit.commitSquashedInsts 13622 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 1187 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 184699 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.434252 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.147591 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::samples 184803 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.434668 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.147538 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33306 18.03% 18.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 75499 40.88% 58.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2011 1.09% 60.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 643 0.35% 60.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 527 0.29% 60.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 71457 38.69% 99.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 519 0.28% 99.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 33298 18.02% 18.02% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 75556 40.88% 58.90% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2014 1.09% 59.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 640 0.35% 60.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 527 0.29% 60.62% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 71511 38.70% 99.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 520 0.28% 99.60% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::7 249 0.13% 99.74% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::8 488 0.26% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 184699 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 449604 # Number of instructions committed -system.cpu0.commit.committedOps 449604 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 184803 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 449934 # Number of instructions committed +system.cpu0.commit.committedOps 449934 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 219517 # Number of memory references committed -system.cpu0.commit.loads 146007 # Number of loads committed +system.cpu0.commit.refs 219682 # Number of memory references committed +system.cpu0.commit.loads 146117 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 75397 # Number of branches committed +system.cpu0.commit.branches 75452 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 303166 # Number of committed integer instructions. +system.cpu0.commit.int_insts 303386 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 72129 16.04% 16.04% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 157874 35.11% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 72184 16.04% 16.04% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 157984 35.11% 51.16% # Class of committed instruction system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.16% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.16% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.16% # Class of committed instruction @@ -1009,37 +1032,37 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.16% system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.16% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.16% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 146091 32.49% 83.65% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 73510 16.35% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 146201 32.49% 83.65% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 73565 16.35% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 449604 # Class of committed instruction +system.cpu0.commit.op_class_0::total 449934 # Class of committed instruction system.cpu0.commit.bw_lim_events 488 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 646276 # The number of ROB reads -system.cpu0.rob.rob_writes 929096 # The number of ROB writes -system.cpu0.timesIdled 317 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 23956 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 377391 # Number of Instructions Simulated -system.cpu0.committedOps 377391 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.559841 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.559841 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.786221 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.786221 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 688854 # number of integer regfile reads -system.cpu0.int_regfile_writes 310766 # number of integer regfile writes +system.cpu0.rob.rob_reads 646710 # The number of ROB reads +system.cpu0.rob.rob_writes 929756 # The number of ROB writes +system.cpu0.timesIdled 318 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 23966 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 377666 # Number of Instructions Simulated +system.cpu0.committedOps 377666 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.559735 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.559735 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.786559 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.786559 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 689341 # number of integer regfile reads +system.cpu0.int_regfile_writes 310987 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 223843 # number of misc regfile reads +system.cpu0.misc_regfile_reads 224004 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.icache.tags.replacements 322 # number of replacements -system.cpu0.icache.tags.tagsinuse 240.566848 # Cycle average of tags in use +system.cpu0.icache.tags.tagsinuse 240.567538 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 6326 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 612 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 10.336601 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 240.566848 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.469857 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.469857 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 240.567538 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.469858 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.469858 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id @@ -1059,12 +1082,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 797 # system.cpu0.icache.demand_misses::total 797 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 797 # number of overall misses system.cpu0.icache.overall_misses::total 797 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 36681496 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 36681496 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 36681496 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 36681496 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 36681496 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 36681496 # number of overall miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 36689746 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 36689746 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 36689746 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 36689746 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 36689746 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 36689746 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 7123 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 7123 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 7123 # number of demand (read+write) accesses @@ -1077,12 +1100,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111891 system.cpu0.icache.demand_miss_rate::total 0.111891 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111891 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.111891 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46024.461731 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 46024.461731 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46024.461731 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 46024.461731 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46024.461731 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 46024.461731 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46034.813049 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 46034.813049 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46034.813049 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 46034.813049 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46034.813049 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 46034.813049 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 22 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1103,101 +1126,101 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 613 system.cpu0.icache.demand_mshr_misses::total 613 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 613 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 613 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 28176251 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 28176251 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 28176251 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 28176251 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 28176251 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 28176251 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 28185001 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 28185001 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 28185001 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 28185001 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 28185001 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 28185001 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086059 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.086059 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.086059 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45964.520392 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45964.520392 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45964.520392 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 45964.520392 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45964.520392 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 45964.520392 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45978.794454 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45978.794454 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45978.794454 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 45978.794454 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45978.794454 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 45978.794454 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 141.515257 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 148145 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 141.516453 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 148253 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 871.441176 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 872.076471 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.515257 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.276397 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.276397 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.516453 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.276399 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.276399 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 597526 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 597526 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75309 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 75309 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 72924 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 72924 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 597940 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 597940 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75362 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75362 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 72979 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 72979 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 20 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 20 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 148233 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 148233 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 148233 # number of overall hits -system.cpu0.dcache.overall_hits::total 148233 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 484 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 484 # number of ReadReq misses +system.cpu0.dcache.demand_hits::cpu0.data 148341 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 148341 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 148341 # number of overall hits +system.cpu0.dcache.overall_hits::total 148341 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 480 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 480 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 544 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 544 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 22 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 22 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1028 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1028 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1028 # number of overall misses -system.cpu0.dcache.overall_misses::total 1028 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15258131 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 15258131 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32871763 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 32871763 # number of WriteReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 1024 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1024 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1024 # number of overall misses +system.cpu0.dcache.overall_misses::total 1024 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15203420 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 15203420 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32866263 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 32866263 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 427750 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 427750 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 48129894 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 48129894 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 48129894 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 48129894 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 75793 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 75793 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 73468 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 73468 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 48069683 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 48069683 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 48069683 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 48069683 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 75842 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 75842 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 73523 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 73523 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 149261 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 149261 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 149261 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 149261 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006386 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006386 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007405 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007405 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 149365 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 149365 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 149365 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 149365 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006329 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006329 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007399 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007399 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.523810 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.523810 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006887 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006887 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006887 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006887 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31525.064050 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31525.064050 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60426.034926 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 60426.034926 # average WriteReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006856 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006856 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006856 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006856 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31673.791667 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 31673.791667 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60415.924632 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 60415.924632 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19443.181818 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 19443.181818 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46818.963035 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 46818.963035 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46818.963035 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 46818.963035 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46943.049805 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 46943.049805 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46943.049805 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 46943.049805 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 754 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked @@ -1208,405 +1231,405 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 301 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 301 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 298 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 298 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 365 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 365 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 666 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 666 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 666 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 666 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses +system.cpu0.dcache.demand_mshr_hits::cpu0.data 663 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 663 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 663 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 663 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 179 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 179 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 22 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 22 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6274260 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6274260 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7393227 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7393227 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6258507 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6258507 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7387727 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7387727 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 382250 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 382250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13667487 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13667487 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13667487 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13667487 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002414 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002414 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002436 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002436 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13646234 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13646234 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13646234 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13646234 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002400 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002400 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002435 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002435 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.523810 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.523810 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002425 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002425 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002425 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002425 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34285.573770 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34285.573770 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41302.944134 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41302.944134 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002417 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002417 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002417 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002417 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34387.401099 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34387.401099 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41272.217877 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41272.217877 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17375 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17375 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37755.488950 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37755.488950 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37755.488950 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37755.488950 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37801.202216 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37801.202216 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37801.202216 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37801.202216 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 54588 # Number of BP lookups -system.cpu1.branchPred.condPredicted 51200 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1286 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 47257 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 46317 # Number of BTB hits +system.cpu1.branchPred.lookups 52620 # Number of BP lookups +system.cpu1.branchPred.condPredicted 49209 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1295 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 45306 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 44357 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 98.010877 # BTB Hit Percentage +system.cpu1.branchPred.BTBHitPct 97.905355 # BTB Hit Percentage system.cpu1.branchPred.usedRAS 875 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.numCycles 167979 # number of cpu cycles simulated +system.cpu1.numCycles 161023 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 29917 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 303462 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 54588 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 47192 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 126841 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2730 # Number of cycles fetch has spent squashing +system.cpu1.fetch.icacheStallCycles 31247 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 289875 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 52620 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 45232 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 125550 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2747 # Number of cycles fetch has spent squashing system.cpu1.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 7060 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1096 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 21062 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 421 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 166282 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.824984 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.191628 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 1122 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 22380 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 446 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 159305 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.819623 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.179377 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 60365 36.30% 36.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 53424 32.13% 68.43% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 6309 3.79% 72.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3483 2.09% 74.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1022 0.61% 74.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 35711 21.48% 96.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1327 0.80% 97.21% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 762 0.46% 97.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3879 2.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 56744 35.62% 35.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 52063 32.68% 68.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 6924 4.35% 72.65% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3540 2.22% 74.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1103 0.69% 75.56% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 33079 20.76% 96.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1261 0.79% 97.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 757 0.48% 97.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3834 2.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 166282 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.324969 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.806547 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 17455 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 52641 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 84496 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3265 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1365 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 289136 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 1365 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 18178 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 24205 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 12371 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 85331 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 17772 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 285586 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 15350 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full +system.cpu1.fetch.rateDist::total 159305 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.326786 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.800209 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 17668 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 57241 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 79500 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3513 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1373 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 275603 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 1373 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 18384 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 26779 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 12577 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 80781 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 19401 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 272270 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 17163 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 27 # Number of times rename has blocked due to LQ full system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 200979 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 548958 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 426905 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 186309 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 14670 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1186 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1247 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 22653 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 80668 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 38514 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 38418 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 33330 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 237514 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 6089 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 238789 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 33 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12748 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 11558 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 612 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 166282 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.436048 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.378738 # Number of insts issued each cycle +system.cpu1.rename.RenamedOperands 191050 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 520032 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 405162 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 176680 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 14370 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1196 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1257 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 24088 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 76067 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 35939 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 36374 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 30769 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 225624 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 6666 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 227547 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 18 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12526 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 11238 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 649 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 159305 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.428373 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.374842 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 63923 38.44% 38.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 20825 12.52% 50.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 37813 22.74% 73.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 37389 22.49% 96.19% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3420 2.06% 98.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1614 0.97% 99.22% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 862 0.52% 99.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 239 0.14% 99.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 60375 37.90% 37.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 22487 14.12% 52.01% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 35297 22.16% 74.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 34879 21.89% 96.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3406 2.14% 98.20% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1579 0.99% 99.20% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 861 0.54% 99.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 224 0.14% 99.88% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 197 0.12% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 166282 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 159305 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 89 25.65% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 49 14.12% 39.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 209 60.23% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 89 26.49% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 26.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 38 11.31% 37.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 209 62.20% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 116312 48.71% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 84679 35.46% 84.17% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 37798 15.83% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 111688 49.08% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.08% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 80614 35.43% 84.51% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 35245 15.49% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 238789 # Type of FU issued -system.cpu1.iq.rate 1.421541 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 347 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001453 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 644240 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 256392 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 237045 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 227547 # Type of FU issued +system.cpu1.iq.rate 1.413134 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 336 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001477 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 614753 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 244854 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 225845 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 239136 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 227883 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 33095 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 30551 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2693 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2638 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1647 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1613 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1365 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 6579 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 282823 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 167 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 80668 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 38514 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1105 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 1373 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 7085 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 269526 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 186 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 76067 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 35939 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1117 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 476 # Number of branches that were predicted taken incorrectly system.cpu1.iew.predictedNotTakenIncorrect 1037 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1507 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 237631 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 79596 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1158 # Number of squashed instructions skipped in execute +system.cpu1.iew.branchMispredicts 1513 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 226408 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 75003 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1139 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 39220 # number of nop insts executed -system.cpu1.iew.exec_refs 117284 # number of memory reference insts executed -system.cpu1.iew.exec_branches 48640 # Number of branches executed -system.cpu1.iew.exec_stores 37688 # Number of stores executed -system.cpu1.iew.exec_rate 1.414647 # Inst execution rate -system.cpu1.iew.wb_sent 237349 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 237045 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 134973 # num instructions producing a value -system.cpu1.iew.wb_consumers 141559 # num instructions consuming a value +system.cpu1.iew.exec_nop 37236 # number of nop insts executed +system.cpu1.iew.exec_refs 110148 # number of memory reference insts executed +system.cpu1.iew.exec_branches 46633 # Number of branches executed +system.cpu1.iew.exec_stores 35145 # Number of stores executed +system.cpu1.iew.exec_rate 1.406060 # Inst execution rate +system.cpu1.iew.wb_sent 226126 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 225845 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 127804 # num instructions producing a value +system.cpu1.iew.wb_consumers 134338 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.411159 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.953475 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.402564 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.951361 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 14310 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 5477 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1286 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 156616 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.714129 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.075319 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 14108 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 6017 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1295 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 156709 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.629549 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.048246 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 61979 39.57% 39.57% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 45369 28.97% 68.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5243 3.35% 71.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 6285 4.01% 75.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1549 0.99% 76.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 33128 21.15% 98.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 818 0.52% 98.57% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 954 0.61% 99.18% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1291 0.82% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 66028 42.13% 42.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 43411 27.70% 69.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5268 3.36% 73.20% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 6809 4.34% 77.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1543 0.98% 78.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 30606 19.53% 98.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 798 0.51% 98.57% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 967 0.62% 99.18% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1279 0.82% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 156616 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 268460 # Number of instructions committed -system.cpu1.commit.committedOps 268460 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 156709 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 255365 # Number of instructions committed +system.cpu1.commit.committedOps 255365 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 114842 # Number of memory references committed -system.cpu1.commit.loads 77975 # Number of loads committed -system.cpu1.commit.membars 4761 # Number of memory barriers committed -system.cpu1.commit.branches 47591 # Number of branches committed +system.cpu1.commit.refs 107755 # Number of memory references committed +system.cpu1.commit.loads 73429 # Number of loads committed +system.cpu1.commit.membars 5300 # Number of memory barriers committed +system.cpu1.commit.branches 45589 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 184553 # Number of committed integer instructions. +system.cpu1.commit.int_insts 175463 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 38379 14.30% 14.30% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 110478 41.15% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.45% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 82736 30.82% 86.27% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 36867 13.73% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 36376 14.24% 14.24% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 105934 41.48% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 78729 30.83% 86.56% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 34326 13.44% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 268460 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1291 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 255365 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1279 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 437508 # The number of ROB reads -system.cpu1.rob.rob_writes 568153 # The number of ROB writes -system.cpu1.timesIdled 207 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1697 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 43298 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 225320 # Number of Instructions Simulated -system.cpu1.committedOps 225320 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.745513 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.745513 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.341358 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.341358 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 411671 # number of integer regfile reads -system.cpu1.int_regfile_writes 192443 # number of integer regfile writes +system.cpu1.rob.rob_reads 424317 # The number of ROB reads +system.cpu1.rob.rob_writes 541540 # The number of ROB writes +system.cpu1.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1718 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 43314 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 213689 # Number of Instructions Simulated +system.cpu1.committedOps 213689 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.753539 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.753539 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.327071 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.327071 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 390200 # number of integer regfile reads +system.cpu1.int_regfile_writes 182656 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 118908 # number of misc regfile reads +system.cpu1.misc_regfile_reads 111763 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.icache.tags.replacements 388 # number of replacements -system.cpu1.icache.tags.tagsinuse 78.688259 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 20497 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 78.707719 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 21821 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 497 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 41.241449 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 43.905433 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 78.688259 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.153688 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.153688 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 78.707719 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.153726 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.153726 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 109 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.212891 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 21559 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 21559 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 20497 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 20497 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 20497 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 20497 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 20497 # number of overall hits -system.cpu1.icache.overall_hits::total 20497 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 565 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 565 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 565 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 565 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 565 # number of overall misses -system.cpu1.icache.overall_misses::total 565 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8463744 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8463744 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8463744 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8463744 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8463744 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8463744 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 21062 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 21062 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 21062 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 21062 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 21062 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 21062 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026826 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.026826 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026826 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.026826 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026826 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.026826 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14980.077876 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14980.077876 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14980.077876 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14980.077876 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14980.077876 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14980.077876 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 22877 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 22877 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 21821 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 21821 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 21821 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 21821 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 21821 # number of overall hits +system.cpu1.icache.overall_hits::total 21821 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 559 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 559 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 559 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 559 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 559 # number of overall misses +system.cpu1.icache.overall_misses::total 559 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8425746 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8425746 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8425746 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8425746 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8425746 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8425746 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 22380 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 22380 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 22380 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 22380 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 22380 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 22380 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024978 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024978 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024978 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024978 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024978 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024978 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15072.890877 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15072.890877 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15072.890877 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15072.890877 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15072.890877 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15072.890877 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1615,112 +1638,111 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs 2 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 68 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 68 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 68 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 68 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 62 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 62 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 62 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 62 # number of overall MSHR hits system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 497 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 497 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 497 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 497 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 497 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 497 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6616756 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6616756 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6616756 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6616756 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6616756 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6616756 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023597 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023597 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023597 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.023597 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023597 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.023597 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13313.392354 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13313.392354 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13313.392354 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13313.392354 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13313.392354 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13313.392354 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6648254 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6648254 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6648254 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6648254 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6648254 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6648254 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022207 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022207 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022207 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.022207 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022207 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.022207 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13376.768612 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13376.768612 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13376.768612 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13376.768612 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13376.768612 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13376.768612 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 24.399537 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 43036 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1484 # Average number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 24.402316 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 40362 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1441.500000 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.399537 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.047655 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.047655 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.402316 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.047661 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.047661 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 333666 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 333666 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 46059 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 46059 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 36657 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 36657 # number of WriteReq hits +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 315306 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 315306 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 43998 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 43998 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 34119 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 34119 # number of WriteReq hits system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 82716 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 82716 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 82716 # number of overall hits -system.cpu1.dcache.overall_hits::total 82716 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 427 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 427 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 140 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 140 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 567 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 567 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 567 # number of overall misses -system.cpu1.dcache.overall_misses::total 567 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5717104 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 5717104 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2840511 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2840511 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 466006 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 466006 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8557615 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8557615 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8557615 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8557615 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 46486 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 46486 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 36797 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 36797 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 83283 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 83283 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 83283 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 83283 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009186 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.009186 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003805 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003805 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.814286 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.814286 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006808 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.006808 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006808 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.006808 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13389.002342 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13389.002342 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20289.364286 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20289.364286 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 8175.543860 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 8175.543860 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15092.795414 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15092.795414 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15092.795414 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15092.795414 # average overall miss latency +system.cpu1.dcache.demand_hits::cpu1.data 78117 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 78117 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 78117 # number of overall hits +system.cpu1.dcache.overall_hits::total 78117 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 439 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 439 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 136 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 136 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 58 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 58 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 575 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 575 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 575 # number of overall misses +system.cpu1.dcache.overall_misses::total 575 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5820038 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 5820038 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2819511 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2819511 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 502006 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 502006 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8639549 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8639549 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8639549 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8639549 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 44437 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 44437 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 34255 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 34255 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 78692 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 78692 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 78692 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 78692 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009879 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.009879 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003970 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.003970 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.816901 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007307 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.007307 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007307 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.007307 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13257.489749 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13257.489749 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20731.698529 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20731.698529 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 8655.275862 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 8655.275862 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15025.302609 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15025.302609 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15025.302609 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15025.302609 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1729,406 +1751,406 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 269 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 269 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 35 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 304 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 304 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 304 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 304 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 158 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1020514 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1020514 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1289239 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1289239 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 351994 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 351994 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2309753 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2309753 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2309753 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2309753 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003399 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003399 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002853 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002853 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.814286 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.814286 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003158 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003158 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003158 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003158 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6458.949367 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6458.949367 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12278.466667 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12278.466667 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6175.333333 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6175.333333 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 8782.330798 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 8782.330798 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 8782.330798 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 8782.330798 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 276 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 276 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 308 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 308 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 308 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 308 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 104 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 58 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 267 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 267 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1085520 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1085520 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1288239 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1288239 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 385994 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 385994 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2373759 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2373759 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2373759 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2373759 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003668 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003668 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003036 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003036 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.816901 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003393 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003393 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003393 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003393 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6659.631902 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6659.631902 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12386.913462 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12386.913462 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6655.068966 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6655.068966 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 8890.483146 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 8890.483146 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 8890.483146 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 8890.483146 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 50591 # Number of BP lookups -system.cpu2.branchPred.condPredicted 46824 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1298 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 43166 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 41772 # Number of BTB hits +system.cpu2.branchPred.lookups 52660 # Number of BP lookups +system.cpu2.branchPred.condPredicted 48877 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1286 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 45218 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 43881 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 96.770606 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 904 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 97.043213 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 913 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.numCycles 167617 # number of cpu cycles simulated +system.cpu2.numCycles 160663 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 31796 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 277876 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 50591 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 42676 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 121192 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2752 # Number of cycles fetch has spent squashing +system.cpu2.fetch.icacheStallCycles 30584 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 291962 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 52660 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 44794 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 122431 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2729 # Number of cycles fetch has spent squashing system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 7062 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1110 # Number of stall cycles due to pending traps +system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 1111 # Number of stall cycles due to pending traps system.cpu2.fetch.IcacheWaitRetryStallCycles 3 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 22366 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 459 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 162543 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.709554 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.176994 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.CacheLines 21169 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 445 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 155507 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.877485 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.219728 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 64711 39.81% 39.81% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 49634 30.54% 70.35% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 6798 4.18% 74.53% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3442 2.12% 76.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 952 0.59% 77.23% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 30771 18.93% 96.16% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1187 0.73% 96.89% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 849 0.52% 97.42% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 4199 2.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 53998 34.72% 34.72% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 51209 32.93% 67.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 6210 3.99% 71.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3413 2.19% 73.84% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 933 0.60% 74.44% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 33386 21.47% 95.91% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1293 0.83% 96.74% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 846 0.54% 97.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 4219 2.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 162543 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.301825 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.657803 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 17997 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 57677 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 74910 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 3521 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1376 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 262355 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 1376 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 18679 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 27128 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12799 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 76466 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 19033 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 259235 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 17033 # Number of times rename has blocked due to IQ full +system.cpu2.fetch.rateDist::total 155507 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.327767 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.817232 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 17863 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 52592 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 80411 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 3267 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1364 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 276853 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 1364 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 18564 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 24147 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 12636 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 81735 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 17051 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 273529 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 15090 # Number of times rename has blocked due to IQ full system.cpu2.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full system.cpu2.rename.FullRegisterEvents 6 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 182575 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 494395 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 386046 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 167620 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 14955 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1169 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1235 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 23554 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 71776 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 33725 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 34298 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 28594 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 214929 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 6621 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 216336 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 13228 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 12296 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 674 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 162543 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.330946 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.384454 # Number of insts issued each cycle +system.cpu2.rename.RenamedOperands 193256 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 525177 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 409210 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 178291 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 14965 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1175 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1247 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 21746 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 76624 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 36478 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 36325 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 31287 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 227715 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 6015 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 228842 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 34 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 13120 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11533 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 647 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 155507 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.471586 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.386146 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 68368 42.06% 42.06% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 22285 13.71% 55.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 32950 20.27% 76.04% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 32546 20.02% 96.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3459 2.13% 98.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1594 0.98% 99.17% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 888 0.55% 99.72% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 245 0.15% 99.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 208 0.13% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 57410 36.92% 36.92% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 20565 13.22% 50.14% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 35759 23.00% 73.14% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 35374 22.75% 95.89% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3397 2.18% 98.07% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1636 1.05% 99.12% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 896 0.58% 99.70% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 267 0.17% 99.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 203 0.13% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 162543 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 155507 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 90 24.93% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 24.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 62 17.17% 42.11% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 209 57.89% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 89 26.57% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 26.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 37 11.04% 37.61% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 209 62.39% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 107190 49.55% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.55% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 76124 35.19% 84.74% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 33022 15.26% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 112448 49.14% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.14% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 80571 35.21% 84.35% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 35823 15.65% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 216336 # Type of FU issued -system.cpu2.iq.rate 1.290657 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 361 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001669 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 595623 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 234822 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 214628 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 228842 # Type of FU issued +system.cpu2.iq.rate 1.424360 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 335 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001464 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 613560 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 246890 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 227101 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 216697 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 229177 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 28314 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 31107 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2909 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2702 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1648 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1596 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1376 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 7567 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 67 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 256538 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 192 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 71776 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 33725 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1099 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 1364 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 6807 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 270837 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 190 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 76624 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 36478 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1098 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 44 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 464 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1069 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1533 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 215226 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 70571 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1110 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1049 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1519 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 227700 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 75599 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1142 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 34988 # number of nop insts executed -system.cpu2.iew.exec_refs 103485 # number of memory reference insts executed -system.cpu2.iew.exec_branches 44292 # Number of branches executed -system.cpu2.iew.exec_stores 32914 # Number of stores executed -system.cpu2.iew.exec_rate 1.284034 # Inst execution rate -system.cpu2.iew.wb_sent 214935 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 214628 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 121102 # num instructions producing a value -system.cpu2.iew.wb_consumers 127756 # num instructions consuming a value +system.cpu2.iew.exec_nop 37107 # number of nop insts executed +system.cpu2.iew.exec_refs 111310 # number of memory reference insts executed +system.cpu2.iew.exec_branches 46563 # Number of branches executed +system.cpu2.iew.exec_stores 35711 # Number of stores executed +system.cpu2.iew.exec_rate 1.417252 # Inst execution rate +system.cpu2.iew.wb_sent 227402 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 227101 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 129036 # num instructions producing a value +system.cpu2.iew.wb_consumers 135804 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.280467 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.947916 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.413524 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.950163 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 14883 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 5947 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1298 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 152800 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.581165 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.037167 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 14614 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 5368 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1286 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 152859 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.675858 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.068536 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 66891 43.78% 43.78% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 41018 26.84% 70.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5166 3.38% 74.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6776 4.43% 78.44% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1516 0.99% 79.43% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 28304 18.52% 97.95% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 869 0.57% 98.52% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 954 0.62% 99.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1306 0.85% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 62472 40.87% 40.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 43239 28.29% 69.16% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5166 3.38% 72.54% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 6247 4.09% 76.62% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1528 1.00% 77.62% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 31073 20.33% 97.95% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 875 0.57% 98.52% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 941 0.62% 99.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1318 0.86% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 152800 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 241602 # Number of instructions committed -system.cpu2.commit.committedOps 241602 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 152859 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 256170 # Number of instructions committed +system.cpu2.commit.committedOps 256170 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 100944 # Number of memory references committed -system.cpu2.commit.loads 68867 # Number of loads committed -system.cpu2.commit.membars 5232 # Number of memory barriers committed -system.cpu2.commit.branches 43270 # Number of branches committed +system.cpu2.commit.refs 108804 # Number of memory references committed +system.cpu2.commit.loads 73922 # Number of loads committed +system.cpu2.commit.membars 4659 # Number of memory barriers committed +system.cpu2.commit.branches 45502 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 166336 # Number of committed integer instructions. +system.cpu2.commit.int_insts 176434 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 34059 14.10% 14.10% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 101367 41.96% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.05% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 74099 30.67% 86.72% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 32077 13.28% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 36297 14.17% 14.17% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 106410 41.54% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.71% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 78581 30.68% 86.38% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 34882 13.62% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 241602 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1306 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 256170 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1318 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 407392 # The number of ROB reads -system.cpu2.rob.rob_writes 515662 # The number of ROB writes -system.cpu2.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 5074 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 43660 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 202311 # Number of Instructions Simulated -system.cpu2.committedOps 202311 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.828512 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.828512 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.206984 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.206984 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 370344 # number of integer regfile reads -system.cpu2.int_regfile_writes 173891 # number of integer regfile writes +system.cpu2.rob.rob_reads 421739 # The number of ROB reads +system.cpu2.rob.rob_writes 544215 # The number of ROB writes +system.cpu2.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 5156 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 43676 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 215214 # Number of Instructions Simulated +system.cpu2.committedOps 215214 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.746527 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.746527 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.339537 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.339537 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 394013 # number of integer regfile reads +system.cpu2.int_regfile_writes 184721 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 105089 # number of misc regfile reads +system.cpu2.misc_regfile_reads 112958 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes -system.cpu2.icache.tags.replacements 378 # number of replacements -system.cpu2.icache.tags.tagsinuse 84.908829 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 21796 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 490 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 44.481633 # Average number of references to valid blocks. +system.cpu2.icache.tags.replacements 380 # number of replacements +system.cpu2.icache.tags.tagsinuse 85.367642 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 20592 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 493 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 41.768763 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 84.908829 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.165838 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.165838 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 112 # Occupied blocks per task id +system.cpu2.icache.tags.occ_blocks::cpu2.inst 85.367642 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.166734 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.166734 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.218750 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 22856 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 22856 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 21796 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 21796 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 21796 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 21796 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 21796 # number of overall hits -system.cpu2.icache.overall_hits::total 21796 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 570 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 570 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 570 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 570 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 570 # number of overall misses -system.cpu2.icache.overall_misses::total 570 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 13348494 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 13348494 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 13348494 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 13348494 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 13348494 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 13348494 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 22366 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 22366 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 22366 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 22366 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 22366 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 22366 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.025485 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.025485 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.025485 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.025485 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.025485 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.025485 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23418.410526 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 23418.410526 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23418.410526 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 23418.410526 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23418.410526 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 23418.410526 # average overall miss latency +system.cpu2.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 21662 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 21662 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 20592 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 20592 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 20592 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 20592 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 20592 # number of overall hits +system.cpu2.icache.overall_hits::total 20592 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 577 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 577 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 577 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 577 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 577 # number of overall misses +system.cpu2.icache.overall_misses::total 577 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 13065992 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 13065992 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 13065992 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 13065992 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 13065992 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 13065992 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 21169 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 21169 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 21169 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 21169 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 21169 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 21169 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.027257 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.027257 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.027257 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.027257 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.027257 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.027257 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22644.700173 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 22644.700173 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22644.700173 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 22644.700173 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22644.700173 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 22644.700173 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -2137,111 +2159,112 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs 42.666667 system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 80 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 80 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 80 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 80 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 490 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 490 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 490 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 490 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 490 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 490 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10380255 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 10380255 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10380255 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 10380255 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10380255 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 10380255 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021908 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021908 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021908 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.021908 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021908 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.021908 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21184.193878 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21184.193878 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21184.193878 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 21184.193878 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21184.193878 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 21184.193878 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 84 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 84 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 84 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 84 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 84 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 493 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 493 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 493 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 493 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 493 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 493 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10294257 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 10294257 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10294257 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 10294257 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10294257 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 10294257 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.023289 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.023289 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.023289 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.023289 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.023289 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.023289 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 20880.845842 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 20880.845842 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 20880.845842 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 20880.845842 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 20880.845842 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 20880.845842 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 25.893249 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 38186 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1363.785714 # Average number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 25.876504 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 41118 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1417.862069 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.893249 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.050573 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.050573 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.876504 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.050540 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.050540 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 297518 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 297518 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 41817 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 41817 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 31862 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 31862 # number of WriteReq hits +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 317671 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 317671 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 44059 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 44059 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 34671 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 34671 # number of WriteReq hits system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 73679 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 73679 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 73679 # number of overall hits -system.cpu2.dcache.overall_hits::total 73679 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 422 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 422 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 146 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 146 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 568 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 568 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 568 # number of overall misses -system.cpu2.dcache.overall_misses::total 568 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7291559 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 7291559 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3658011 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 3658011 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 499506 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 499506 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 10949570 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 10949570 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 10949570 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 10949570 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 42239 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 42239 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 32008 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 32008 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 74247 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 74247 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 74247 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 74247 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009991 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.009991 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004561 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.004561 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.797101 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.797101 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007650 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.007650 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007650 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.007650 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17278.575829 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 17278.575829 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 25054.869863 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 25054.869863 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9081.927273 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 9081.927273 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 19277.411972 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 19277.411972 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19277.411972 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 19277.411972 # average overall miss latency +system.cpu2.dcache.demand_hits::cpu2.data 78730 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 78730 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 78730 # number of overall hits +system.cpu2.dcache.overall_hits::total 78730 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 415 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 415 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 148 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 148 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 49 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 49 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 563 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 563 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 563 # number of overall misses +system.cpu2.dcache.overall_misses::total 563 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7441548 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 7441548 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3663511 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 3663511 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 451006 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 451006 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 11105059 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 11105059 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 11105059 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 11105059 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 44474 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 44474 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 34819 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 34819 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 63 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 63 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 79293 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 79293 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 79293 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 79293 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009331 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.009331 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004251 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004251 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.777778 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.777778 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007100 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.007100 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007100 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.007100 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17931.440964 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 17931.440964 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24753.452703 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 24753.452703 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9204.204082 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 9204.204082 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 19724.793961 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 19724.793961 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19724.793961 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 19724.793961 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2250,405 +2273,405 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 261 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 261 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 262 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 262 # number of ReadReq MSHR hits system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 40 # number of WriteReq MSHR hits system.cpu2.dcache.WriteReq_mshr_hits::total 40 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 301 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 301 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 301 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 301 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 55 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1541774 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1541774 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1509739 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1509739 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 389494 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 389494 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3051513 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3051513 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3051513 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3051513 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003812 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003812 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003312 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003312 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.797101 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.797101 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003596 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003596 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003596 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003596 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9576.236025 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9576.236025 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14242.820755 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14242.820755 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7081.709091 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7081.709091 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11428.887640 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11428.887640 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11428.887640 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11428.887640 # average overall mshr miss latency +system.cpu2.dcache.demand_mshr_hits::cpu2.data 302 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 302 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 302 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 302 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 153 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 49 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 49 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 261 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 261 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 261 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 261 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1686771 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1686771 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1511239 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1511239 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 352994 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 352994 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3198010 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3198010 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3198010 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3198010 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003440 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003440 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003102 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003102 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.777778 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.777778 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003292 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003292 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003292 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003292 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11024.647059 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11024.647059 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13992.953704 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13992.953704 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7203.959184 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7203.959184 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12252.911877 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12252.911877 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12252.911877 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12252.911877 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 48151 # Number of BP lookups -system.cpu3.branchPred.condPredicted 44685 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1287 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 41038 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 39836 # Number of BTB hits +system.cpu3.branchPred.lookups 48141 # Number of BP lookups +system.cpu3.branchPred.condPredicted 44605 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1305 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 40897 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 39710 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 97.071007 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 888 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 97.097587 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 884 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.numCycles 167273 # number of cpu cycles simulated +system.cpu3.numCycles 160319 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 33692 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 260486 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 48151 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 40724 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 122974 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 2726 # Number of cycles fetch has spent squashing +system.cpu3.fetch.icacheStallCycles 33851 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 260297 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 48141 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 40594 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 122891 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 2765 # Number of cycles fetch has spent squashing system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 7060 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from system.cpu3.fetch.PendingTrapStallCycles 1076 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 24907 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 418 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 166168 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.567606 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.102870 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.CacheLines 24972 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 417 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 159213 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.634898 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.125574 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 71279 42.90% 42.90% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 48852 29.40% 72.29% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 8282 4.98% 77.28% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3511 2.11% 79.39% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 1059 0.64% 80.03% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 27347 16.46% 96.49% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1190 0.72% 97.20% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 758 0.46% 97.66% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3890 2.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 64563 40.55% 40.55% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 48696 30.59% 71.14% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 8235 5.17% 76.31% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3504 2.20% 78.51% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 1064 0.67% 79.18% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 27204 17.09% 96.26% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1240 0.78% 97.04% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 753 0.47% 97.52% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3954 2.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 166168 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.287859 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.557251 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 17558 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 68128 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 67891 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 4168 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 1363 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 246104 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 1363 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 18233 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 33368 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 12463 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 69060 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 24621 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 242881 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 21589 # Number of times rename has blocked due to IQ full +system.cpu3.fetch.rateDist::total 159213 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.300283 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.623619 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 17777 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 68157 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 67726 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 4161 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 1382 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 245360 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 1382 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 18479 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 33142 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 12841 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 69300 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 24059 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 241885 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 21460 # Number of times rename has blocked due to IQ full system.cpu3.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 169259 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 456177 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 357242 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 154687 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 14572 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1184 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1245 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 29195 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 65863 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 30140 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 31966 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 25009 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 199372 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 7958 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 202308 # Number of instructions issued +system.cpu3.rename.RenamedOperands 168616 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 454082 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 355646 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 153987 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 14629 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1214 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1272 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 28919 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 65522 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 29976 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 31799 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 24828 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 198526 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 7988 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 201423 # Number of instructions issued system.cpu3.iq.iqSquashedInstsIssued 33 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 12859 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 11887 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 683 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 166168 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.217491 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.364227 # Number of insts issued each cycle +system.cpu3.iq.iqSquashedInstsExamined 12862 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 11999 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 692 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 159213 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.265117 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.367863 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 75148 45.22% 45.22% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 26256 15.80% 61.02% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 29417 17.70% 78.73% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 29010 17.46% 96.19% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3447 2.07% 98.26% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1582 0.95% 99.21% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 873 0.53% 99.74% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 228 0.14% 99.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 207 0.12% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 68514 43.03% 43.03% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 26230 16.47% 59.51% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 29303 18.40% 77.91% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 28880 18.14% 96.05% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3418 2.15% 98.20% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1568 0.98% 99.18% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 871 0.55% 99.73% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 223 0.14% 99.87% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 206 0.13% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 166168 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 159213 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 93 25.83% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 58 16.11% 41.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 209 58.06% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 92 26.36% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 48 13.75% 40.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 209 59.89% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 101290 50.07% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.07% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 71575 35.38% 85.45% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 29443 14.55% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 100972 50.13% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.13% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 71204 35.35% 85.48% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 29247 14.52% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 202308 # Type of FU issued -system.cpu3.iq.rate 1.209448 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 360 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001779 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 571177 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 220229 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 200600 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 201423 # Type of FU issued +system.cpu3.iq.rate 1.256389 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 349 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001733 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 562441 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 219414 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 199715 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 202668 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 201772 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 24749 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 24567 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2800 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2806 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1627 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1637 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 1363 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 8604 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 61 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 240098 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 201 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 65863 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 30140 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1100 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 1382 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 8523 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 239131 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 178 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 65522 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 29976 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1120 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 32 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 40 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 473 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1038 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1511 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 201185 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 64698 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1123 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 38 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 471 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1054 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1525 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 200291 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 64311 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1132 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 32768 # number of nop insts executed -system.cpu3.iew.exec_refs 94032 # number of memory reference insts executed -system.cpu3.iew.exec_branches 42068 # Number of branches executed -system.cpu3.iew.exec_stores 29334 # Number of stores executed -system.cpu3.iew.exec_rate 1.202734 # Inst execution rate -system.cpu3.iew.wb_sent 200904 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 200600 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 111689 # num instructions producing a value -system.cpu3.iew.wb_consumers 118263 # num instructions consuming a value +system.cpu3.iew.exec_nop 32617 # number of nop insts executed +system.cpu3.iew.exec_refs 93457 # number of memory reference insts executed +system.cpu3.iew.exec_branches 41928 # Number of branches executed +system.cpu3.iew.exec_stores 29146 # Number of stores executed +system.cpu3.iew.exec_rate 1.249328 # Inst execution rate +system.cpu3.iew.wb_sent 200012 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 199715 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 111117 # num instructions producing a value +system.cpu3.iew.wb_consumers 117670 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.199237 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.944412 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.245735 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.944310 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 14520 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7275 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1287 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 156480 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.441238 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.976154 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 14558 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7296 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1305 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 156559 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.434092 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.973064 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 74989 47.92% 47.92% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 38816 24.81% 72.73% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5199 3.32% 76.05% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8093 5.17% 81.22% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1536 0.98% 82.20% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 24757 15.82% 98.03% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 830 0.53% 98.56% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 957 0.61% 99.17% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1303 0.83% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 75373 48.14% 48.14% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 38673 24.70% 72.85% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5214 3.33% 76.18% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8076 5.16% 81.33% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1539 0.98% 82.32% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 24642 15.74% 98.06% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 775 0.50% 98.55% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 961 0.61% 99.17% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1306 0.83% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 156480 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 225525 # Number of instructions committed -system.cpu3.commit.committedOps 225525 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 156559 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 224520 # Number of instructions committed +system.cpu3.commit.committedOps 224520 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 91576 # Number of memory references committed -system.cpu3.commit.loads 63063 # Number of loads committed -system.cpu3.commit.membars 6559 # Number of memory barriers committed -system.cpu3.commit.branches 41035 # Number of branches committed +system.cpu3.commit.refs 91055 # Number of memory references committed +system.cpu3.commit.loads 62716 # Number of loads committed +system.cpu3.commit.membars 6575 # Number of memory barriers committed +system.cpu3.commit.branches 40877 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 154730 # Number of committed integer instructions. +system.cpu3.commit.int_insts 154046 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 31823 14.11% 14.11% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 95567 42.38% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.49% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 69622 30.87% 87.36% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 28513 12.64% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 31660 14.10% 14.10% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 95230 42.41% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.52% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 69291 30.86% 87.38% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 28339 12.62% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 225525 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1303 # number cycles where commit BW limit reached +system.cpu3.commit.op_class_0::total 224520 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1306 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 394635 # The number of ROB reads -system.cpu3.rob.rob_writes 482728 # The number of ROB writes -system.cpu3.timesIdled 203 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1105 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 44004 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 187143 # Number of Instructions Simulated -system.cpu3.committedOps 187143 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 0.893825 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.893825 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.118788 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.118788 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 341840 # number of integer regfile reads -system.cpu3.int_regfile_writes 160726 # number of integer regfile writes +system.cpu3.rob.rob_reads 393745 # The number of ROB reads +system.cpu3.rob.rob_writes 480811 # The number of ROB writes +system.cpu3.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1106 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 44020 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 186285 # Number of Instructions Simulated +system.cpu3.committedOps 186285 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.860611 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.860611 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.161965 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.161965 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 340113 # number of integer regfile reads +system.cpu3.int_regfile_writes 159981 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 95629 # number of misc regfile reads +system.cpu3.misc_regfile_reads 95078 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes -system.cpu3.icache.tags.replacements 380 # number of replacements -system.cpu3.icache.tags.tagsinuse 77.789470 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 24352 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 493 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 49.395538 # Average number of references to valid blocks. +system.cpu3.icache.tags.replacements 386 # number of replacements +system.cpu3.icache.tags.tagsinuse 77.771025 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 24411 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 499 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 48.919840 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.789470 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151933 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.151933 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.771025 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151897 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.151897 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 25400 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 25400 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 24352 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 24352 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 24352 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 24352 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 24352 # number of overall hits -system.cpu3.icache.overall_hits::total 24352 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 555 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 555 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 555 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 555 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 555 # number of overall misses -system.cpu3.icache.overall_misses::total 555 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7324995 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 7324995 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 7324995 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 7324995 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 7324995 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 7324995 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 24907 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 24907 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 24907 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 24907 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 24907 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 24907 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.022283 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.022283 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.022283 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.022283 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.022283 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.022283 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13198.189189 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13198.189189 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13198.189189 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13198.189189 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13198.189189 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13198.189189 # average overall miss latency +system.cpu3.icache.tags.tag_accesses 25471 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 25471 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 24411 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 24411 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 24411 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 24411 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 24411 # number of overall hits +system.cpu3.icache.overall_hits::total 24411 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 561 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 561 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 561 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 561 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 561 # number of overall misses +system.cpu3.icache.overall_misses::total 561 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7400997 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 7400997 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 7400997 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 7400997 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 7400997 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 7400997 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 24972 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 24972 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 24972 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 24972 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 24972 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 24972 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.022465 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.022465 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.022465 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.022465 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.022465 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.022465 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13192.508021 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13192.508021 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13192.508021 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13192.508021 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13192.508021 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13192.508021 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2663,105 +2686,105 @@ system.cpu3.icache.demand_mshr_hits::cpu3.inst 62 system.cpu3.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits system.cpu3.icache.overall_mshr_hits::cpu3.inst 62 # number of overall MSHR hits system.cpu3.icache.overall_mshr_hits::total 62 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 493 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 493 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 493 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 493 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 493 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 493 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5824754 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5824754 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5824754 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5824754 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5824754 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5824754 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.019794 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.019794 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.019794 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.019794 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.019794 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.019794 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11814.916836 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11814.916836 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11814.916836 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 11814.916836 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11814.916836 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 11814.916836 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 499 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 499 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 499 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 499 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 499 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 499 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5888752 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 5888752 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5888752 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 5888752 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5888752 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 5888752 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.019982 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.019982 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.019982 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.019982 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.019982 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.019982 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11801.106212 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11801.106212 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11801.106212 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 11801.106212 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11801.106212 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 11801.106212 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 23.433083 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 34557 # Total number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 23.453129 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 34358 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1234.178571 # Average number of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1227.071429 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.433083 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.045768 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.045768 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.453129 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.045807 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.045807 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 274000 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 274000 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 39491 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 39491 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 28303 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 28303 # number of WriteReq hits +system.cpu3.dcache.tags.tag_accesses 272485 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 272485 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 39283 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 39283 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 28128 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 28128 # number of WriteReq hits system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 67794 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 67794 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 67794 # number of overall hits -system.cpu3.dcache.overall_hits::total 67794 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 432 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 432 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 140 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 140 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 572 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 572 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 572 # number of overall misses -system.cpu3.dcache.overall_misses::total 572 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 5736963 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 5736963 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2764512 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2764512 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 515508 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 515508 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 8501475 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 8501475 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 8501475 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 8501475 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 39923 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 39923 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 28443 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 28443 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 68366 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 68366 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 68366 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 68366 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010821 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.010821 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004922 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.004922 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.814286 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.814286 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008367 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.008367 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008367 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.008367 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13280.006944 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 13280.006944 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19746.514286 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 19746.514286 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9044 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 9044 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14862.718531 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 14862.718531 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14862.718531 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 14862.718531 # average overall miss latency +system.cpu3.dcache.demand_hits::cpu3.data 67411 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 67411 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 67411 # number of overall hits +system.cpu3.dcache.overall_hits::total 67411 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 435 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 435 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 136 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 136 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 62 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 62 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 571 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 571 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 571 # number of overall misses +system.cpu3.dcache.overall_misses::total 571 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 5776999 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 5776999 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2748012 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2748012 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 544508 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 544508 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 8525011 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 8525011 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 8525011 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 8525011 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 39718 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 39718 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 28264 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 28264 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 75 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 75 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 67982 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 67982 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 67982 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 67982 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010952 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.010952 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004812 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.004812 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.826667 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.826667 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008399 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.008399 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008399 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.008399 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13280.457471 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 13280.457471 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20205.970588 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 20205.970588 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 8782.387097 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 8782.387097 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14929.966725 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 14929.966725 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14929.966725 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 14929.966725 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2778,46 +2801,46 @@ system.cpu3.dcache.demand_mshr_hits::cpu3.data 302 system.cpu3.dcache.demand_mshr_hits::total 302 # number of demand (read+write) MSHR hits system.cpu3.dcache.overall_mshr_hits::cpu3.data 302 # number of overall MSHR hits system.cpu3.dcache.overall_mshr_hits::total 302 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 270 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 270 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1168525 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1168525 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1299988 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1299988 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 401492 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 401492 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2468513 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2468513 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2468513 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2468513 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004083 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004083 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003762 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003762 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.814286 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.814286 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003949 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003949 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003949 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003949 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 7168.865031 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 7168.865031 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12149.420561 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12149.420561 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7043.719298 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7043.719298 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9142.640741 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9142.640741 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9142.640741 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9142.640741 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 166 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 103 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 62 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 62 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 269 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 269 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1189025 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1189025 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1291488 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1291488 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 420492 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 420492 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2480513 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2480513 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2480513 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2480513 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004179 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004179 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003644 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003644 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.826667 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.826667 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003957 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003957 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003957 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003957 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 7162.801205 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 7162.801205 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12538.718447 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12538.718447 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 6782.129032 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 6782.129032 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9221.237918 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9221.237918 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9221.237918 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9221.237918 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 3bc9d35ce..f16a9829d 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,86 +4,104 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1618143 # Simulator instruction rate (inst/s) -host_op_rate 1618081 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 209518099 # Simulator tick rate (ticks/s) -host_mem_usage 283888 # Number of bytes of host memory used -host_seconds 0.42 # Real time elapsed on the host -sim_insts 677327 # Number of instructions simulated -sim_ops 677327 # Number of ops (including micro ops) simulated +host_inst_rate 1398636 # Simulator instruction rate (inst/s) +host_op_rate 1398593 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 181097192 # Simulator tick rate (ticks/s) +host_mem_usage 299844 # Number of bytes of host memory used +host_seconds 0.48 # Real time elapsed on the host +sim_insts 677333 # Number of instructions simulated +sim_ops 677333 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory system.physmem.bytes_read::total 35776 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::total 559 # Number of read requests responded to by this memory system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 1459405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 2189107 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1459405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 729702 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 1459405 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1459405 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 2189107 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 729702 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 1459405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 2189107 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1459405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 729702 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 407903588 # Throughput (bytes/s) -system.membus.data_through_bus 35776 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 423 # Transaction distribution +system.membus.trans_dist::ReadResp 423 # Transaction distribution +system.membus.trans_dist::UpgradeReq 273 # Transaction distribution +system.membus.trans_dist::UpgradeResp 80 # Transaction distribution +system.membus.trans_dist::ReadExReq 412 # Transaction distribution +system.membus.trans_dist::ReadExResp 136 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1747 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1747 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1108 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1108 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1108 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use +system.l2c.tags.tagsinuse 366.582953 # Cycle average of tags in use system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 55.207589 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 6.721185 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.935416 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.905646 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy @@ -92,15 +110,15 @@ system.l2c.tags.occ_task_id_blocks::1024 421 # Oc system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.006424 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 15488 # Number of tag accesses -system.l2c.tags.data_accesses 15488 # Number of data accesses +system.l2c.tags.tag_accesses 15456 # Number of tag accesses +system.l2c.tags.data_accesses 15456 # Number of data accesses system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 355 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits @@ -111,34 +129,34 @@ system.l2c.demand_hits::cpu0.inst 185 # nu system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits system.l2c.demand_hits::total 1220 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 185 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits system.l2c.overall_hits::cpu1.inst 296 # number of overall hits system.l2c.overall_hits::cpu1.data 3 # number of overall hits -system.l2c.overall_hits::cpu2.inst 356 # number of overall hits +system.l2c.overall_hits::cpu2.inst 355 # number of overall hits system.l2c.overall_hits::cpu2.data 9 # number of overall hits -system.l2c.overall_hits::cpu3.inst 357 # number of overall hits +system.l2c.overall_hits::cpu3.inst 358 # number of overall hits system.l2c.overall_hits::cpu3.data 9 # number of overall hits system.l2c.overall_hits::total 1220 # number of overall hits system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 3 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.inst 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses system.l2c.ReadReq_misses::total 423 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses @@ -148,18 +166,18 @@ system.l2c.demand_misses::cpu0.inst 282 # nu system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 3 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses system.l2c.demand_misses::total 559 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.inst 282 # number of overall misses system.l2c.overall_misses::cpu0.data 165 # number of overall misses system.l2c.overall_misses::cpu1.inst 62 # number of overall misses system.l2c.overall_misses::cpu1.data 20 # number of overall misses -system.l2c.overall_misses::cpu2.inst 2 # number of overall misses +system.l2c.overall_misses::cpu2.inst 3 # number of overall misses system.l2c.overall_misses::cpu2.data 13 # number of overall misses -system.l2c.overall_misses::cpu3.inst 2 # number of overall misses +system.l2c.overall_misses::cpu3.inst 1 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses system.l2c.overall_misses::total 559 # number of overall misses system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) @@ -173,11 +191,11 @@ system.l2c.ReadReq_accesses::cpu3.data 10 # nu system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) @@ -205,16 +223,16 @@ system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # mi system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.008380 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.002786 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.975610 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses @@ -224,18 +242,18 @@ system.l2c.demand_miss_rate::cpu0.inst 0.603854 # mi system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.008380 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.002786 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.008380 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.002786 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -247,9 +265,49 @@ system.l2c.avg_blocked_cycles::no_targets nan # a system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.toL2Bus.throughput 1893577480 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 166080 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.toL2Bus.trans_dist::ReadReq 2179 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 711 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 716 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 716 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 718 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5733 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 22976 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 165888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 0 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2867 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 2867 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 2867 # Request fanout histogram system.cpu0.workload.num_syscalls 89 # Number of system calls system.cpu0.numCycles 175415 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started @@ -310,12 +368,12 @@ system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 175388 # Class of executed instruction system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use +system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772732 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id @@ -358,20 +416,20 @@ system.cpu0.icache.fast_writes 0 # nu system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 150.745705 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 81882 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 490.311377 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745705 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 329803 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 329803 # Number of data accesses +system.cpu0.dcache.tags.tag_accesses 329804 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 329804 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits @@ -423,31 +481,31 @@ system.cpu0.dcache.cache_copies 0 # nu system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 173295 # number of cpu cycles simulated +system.cpu1.numCycles 173297 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 167398 # Number of instructions committed -system.cpu1.committedOps 167398 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses +system.cpu1.committedInsts 167400 # Number of instructions committed +system.cpu1.committedOps 167400 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 107326 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 633 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 32743 # number of instructions that are conditional controls -system.cpu1.num_int_insts 109926 # number of integer instructions +system.cpu1.num_conditional_control_insts 34043 # number of instructions that are conditional controls +system.cpu1.num_int_insts 107326 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 270038 # number of times the integer registers were read -system.cpu1.num_int_register_writes 100721 # number of times the integer registers were written +system.cpu1.num_int_register_reads 254436 # number of times the integer registers were read +system.cpu1.num_int_register_writes 94218 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 53394 # number of memory refs -system.cpu1.num_load_insts 40652 # Number of load instructions -system.cpu1.num_store_insts 12742 # Number of store instructions -system.cpu1.num_idle_cycles 7873.724337 # Number of idle cycles -system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles -system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles -system.cpu1.Branches 34390 # Number of branches fetched -system.cpu1.op_class::No_OpClass 25177 15.04% 15.04% # Class of executed instruction -system.cpu1.op_class::IntAlu 73170 43.70% 58.74% # Class of executed instruction +system.cpu1.num_mem_refs 49494 # number of memory refs +system.cpu1.num_load_insts 39345 # Number of load instructions +system.cpu1.num_store_insts 10149 # Number of store instructions +system.cpu1.num_idle_cycles 7872.827276 # Number of idle cycles +system.cpu1.num_busy_cycles 165424.172724 # Number of busy cycles +system.cpu1.not_idle_fraction 0.954570 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.045430 # Percentage of idle cycles +system.cpu1.Branches 35694 # Number of branches fetched +system.cpu1.op_class::No_OpClass 26475 15.81% 15.81% # Class of executed instruction +system.cpu1.op_class::IntAlu 71873 42.93% 58.74% # Class of executed instruction system.cpu1.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction @@ -476,44 +534,44 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 58.74% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::MemRead 56341 33.65% 92.39% # Class of executed instruction -system.cpu1.op_class::MemWrite 12742 7.61% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 58935 35.20% 93.94% # Class of executed instruction +system.cpu1.op_class::MemWrite 10149 6.06% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 167430 # Class of executed instruction +system.cpu1.op_class::total 167432 # Class of executed instruction system.cpu1.icache.tags.replacements 278 # number of replacements -system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 466.687151 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.752158 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149907 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.149907 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 167788 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 167788 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 167072 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 167072 # number of overall hits -system.cpu1.icache.overall_hits::total 167072 # number of overall hits +system.cpu1.icache.tags.tag_accesses 167790 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 167790 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 167074 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 167074 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 167074 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 167074 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 167074 # number of overall hits +system.cpu1.icache.overall_hits::total 167074 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses system.cpu1.icache.overall_misses::total 358 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 167430 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 167430 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 167430 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 167430 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 167432 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 167432 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 167432 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 167432 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 167432 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 167432 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses @@ -530,59 +588,59 @@ system.cpu1.icache.fast_writes 0 # nu system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 30.295170 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 21529 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 828.038462 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.295170 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059170 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.059170 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 213800 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 213800 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 53033 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 53033 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 53033 # number of overall hits -system.cpu1.dcache.overall_hits::total 53033 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 174 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 174 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 280 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 280 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 280 # number of overall misses -system.cpu1.dcache.overall_misses::total 280 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 40644 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 40644 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 12669 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 12669 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 53313 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004281 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.004281 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.008367 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005252 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005252 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005252 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005252 # miss rate for overall accesses +system.cpu1.dcache.tags.tag_accesses 198211 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 198211 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 39152 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 39152 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 9968 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 9968 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 49120 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 49120 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 49120 # number of overall hits +system.cpu1.dcache.overall_hits::total 49120 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 185 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 185 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 102 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 102 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 61 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 61 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 287 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 287 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 287 # number of overall misses +system.cpu1.dcache.overall_misses::total 287 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 39337 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 39337 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 10070 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 10070 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 77 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 77 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 49407 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 49407 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 49407 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 49407 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004703 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.004703 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.010129 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.010129 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.792208 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.792208 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005809 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005809 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005809 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005809 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -592,31 +650,31 @@ system.cpu1.dcache.avg_blocked_cycles::no_targets nan system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 173295 # number of cpu cycles simulated +system.cpu2.numCycles 173296 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 167334 # Number of instructions committed -system.cpu2.committedOps 167334 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 113333 # Number of integer alu accesses +system.cpu2.committedInsts 167335 # Number of instructions committed +system.cpu2.committedOps 167335 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 114196 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 633 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 31007 # number of instructions that are conditional controls -system.cpu2.num_int_insts 113333 # number of integer instructions +system.cpu2.num_conditional_control_insts 30577 # number of instructions that are conditional controls +system.cpu2.num_int_insts 114196 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 290613 # number of times the integer registers were read -system.cpu2.num_int_register_writes 109308 # number of times the integer registers were written +system.cpu2.num_int_register_reads 295784 # number of times the integer registers were read +system.cpu2.num_int_register_writes 111461 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 58537 # number of memory refs -system.cpu2.num_load_insts 42362 # Number of load instructions -system.cpu2.num_store_insts 16175 # Number of store instructions -system.cpu2.num_idle_cycles 7936.951217 # Number of idle cycles -system.cpu2.num_busy_cycles 165358.048783 # Number of busy cycles +system.cpu2.num_mem_refs 59830 # number of memory refs +system.cpu2.num_load_insts 42793 # Number of load instructions +system.cpu2.num_store_insts 17037 # Number of store instructions +system.cpu2.num_idle_cycles 7936.997017 # Number of idle cycles +system.cpu2.num_busy_cycles 165359.002983 # Number of busy cycles system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles -system.cpu2.Branches 32652 # Number of branches fetched -system.cpu2.op_class::No_OpClass 23444 14.01% 14.01% # Class of executed instruction -system.cpu2.op_class::IntAlu 74873 44.74% 58.74% # Class of executed instruction +system.cpu2.Branches 32221 # Number of branches fetched +system.cpu2.op_class::No_OpClass 23013 13.75% 13.75% # Class of executed instruction +system.cpu2.op_class::IntAlu 75303 44.99% 58.74% # Class of executed instruction system.cpu2.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction system.cpu2.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction system.cpu2.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction @@ -645,44 +703,44 @@ system.cpu2.op_class::SimdFloatMisc 0 0.00% 58.74% # Cl system.cpu2.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction system.cpu2.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::MemRead 52874 31.59% 90.34% # Class of executed instruction -system.cpu2.op_class::MemWrite 16175 9.66% 100.00% # Class of executed instruction +system.cpu2.op_class::MemRead 52014 31.08% 89.82% # Class of executed instruction +system.cpu2.op_class::MemWrite 17037 10.18% 100.00% # Class of executed instruction system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 167366 # Class of executed instruction +system.cpu2.op_class::total 167367 # Class of executed instruction system.cpu2.icache.tags.replacements 278 # number of replacements -system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 466.505587 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781471 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146058 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.146058 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 167724 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 167724 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 167008 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 167008 # number of overall hits -system.cpu2.icache.overall_hits::total 167008 # number of overall hits +system.cpu2.icache.tags.tag_accesses 167725 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 167725 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 167009 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 167009 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 167009 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 167009 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 167009 # number of overall hits +system.cpu2.icache.overall_hits::total 167009 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses system.cpu2.icache.overall_misses::total 358 # number of overall misses -system.cpu2.icache.ReadReq_accesses::cpu2.inst 167366 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 167366 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 167366 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 167366 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 167366 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_accesses::cpu2.inst 167367 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 167367 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 167367 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 167367 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 167367 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 167367 # number of overall (read+write) accesses system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses @@ -699,59 +757,60 @@ system.cpu2.icache.fast_writes 0 # nu system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 29.575165 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 35457 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1313.222222 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.575165 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057764 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.057764 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 234360 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 234360 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 58192 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 58192 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 58192 # number of overall hits -system.cpu2.dcache.overall_hits::total 58192 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 160 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 160 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 269 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 269 # number of overall misses -system.cpu2.dcache.overall_misses::total 269 # number of overall misses -system.cpu2.dcache.ReadReq_accesses::cpu2.data 42354 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 42354 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 16107 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 16107 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 239521 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 239521 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 42635 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42635 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 16864 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 16864 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 59499 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 59499 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 59499 # number of overall hits +system.cpu2.dcache.overall_hits::total 59499 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 150 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 150 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 255 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 255 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 255 # number of overall misses +system.cpu2.dcache.overall_misses::total 255 # number of overall misses +system.cpu2.dcache.ReadReq_accesses::cpu2.data 42785 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 42785 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 16969 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 16969 # number of WriteReq accesses(hits+misses) system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 58461 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003778 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003778 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.006767 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004601 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004601 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004601 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004601 # miss rate for overall accesses +system.cpu2.dcache.demand_accesses::cpu2.data 59754 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 59754 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 59754 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 59754 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003506 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003506 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006188 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.006188 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.818182 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004267 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004267 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004267 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004267 # miss rate for overall accesses system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -761,31 +820,31 @@ system.cpu2.dcache.avg_blocked_cycles::no_targets nan system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 173294 # number of cpu cycles simulated +system.cpu3.numCycles 173297 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 167269 # Number of instructions committed -system.cpu3.committedOps 167269 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 111554 # Number of integer alu accesses +system.cpu3.committedInsts 167272 # Number of instructions committed +system.cpu3.committedOps 167272 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 113295 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 633 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 31865 # number of instructions that are conditional controls -system.cpu3.num_int_insts 111554 # number of integer instructions +system.cpu3.num_conditional_control_insts 30996 # number of instructions that are conditional controls +system.cpu3.num_int_insts 113295 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 280060 # number of times the integer registers were read -system.cpu3.num_int_register_writes 104916 # number of times the integer registers were written +system.cpu3.num_int_register_reads 290503 # number of times the integer registers were read +system.cpu3.num_int_register_writes 109270 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 55900 # number of memory refs -system.cpu3.num_load_insts 41466 # Number of load instructions -system.cpu3.num_store_insts 14434 # Number of store instructions -system.cpu3.num_idle_cycles 8001.119846 # Number of idle cycles -system.cpu3.num_busy_cycles 165292.880154 # Number of busy cycles -system.cpu3.not_idle_fraction 0.953829 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.046171 # Percentage of idle cycles -system.cpu3.Branches 33511 # Number of branches fetched -system.cpu3.op_class::No_OpClass 24299 14.52% 14.52% # Class of executed instruction -system.cpu3.op_class::IntAlu 73982 44.22% 58.75% # Class of executed instruction +system.cpu3.num_mem_refs 58510 # number of memory refs +system.cpu3.num_load_insts 42344 # Number of load instructions +system.cpu3.num_store_insts 16166 # Number of store instructions +system.cpu3.num_idle_cycles 7999.282495 # Number of idle cycles +system.cpu3.num_busy_cycles 165297.717505 # Number of busy cycles +system.cpu3.not_idle_fraction 0.953841 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.046159 # Percentage of idle cycles +system.cpu3.Branches 32639 # Number of branches fetched +system.cpu3.op_class::No_OpClass 23433 14.01% 14.01% # Class of executed instruction +system.cpu3.op_class::IntAlu 74851 44.74% 58.75% # Class of executed instruction system.cpu3.op_class::IntMult 0 0.00% 58.75% # Class of executed instruction system.cpu3.op_class::IntDiv 0 0.00% 58.75% # Class of executed instruction system.cpu3.op_class::FloatAdd 0 0.00% 58.75% # Class of executed instruction @@ -814,44 +873,44 @@ system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.75% # Cl system.cpu3.op_class::SimdFloatMult 0 0.00% 58.75% # Class of executed instruction system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.75% # Class of executed instruction system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::MemRead 54586 32.63% 91.37% # Class of executed instruction -system.cpu3.op_class::MemWrite 14434 8.63% 100.00% # Class of executed instruction +system.cpu3.op_class::MemRead 52854 31.59% 90.34% # Class of executed instruction +system.cpu3.op_class::MemWrite 16166 9.66% 100.00% # Class of executed instruction system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 167301 # Class of executed instruction +system.cpu3.op_class::total 167304 # Class of executed instruction system.cpu3.icache.tags.replacements 279 # number of replacements -system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks. +system.cpu3.icache.tags.avg_refs 465.027855 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874953 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142334 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.142334 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 167660 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 167660 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 166942 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 166942 # number of overall hits -system.cpu3.icache.overall_hits::total 166942 # number of overall hits +system.cpu3.icache.tags.tag_accesses 167663 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 167663 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 166945 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 166945 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 166945 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 166945 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 166945 # number of overall hits +system.cpu3.icache.overall_hits::total 166945 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses system.cpu3.icache.overall_misses::total 359 # number of overall misses -system.cpu3.icache.ReadReq_accesses::cpu3.inst 167301 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 167301 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 167301 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 167301 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 167301 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_accesses::cpu3.inst 167304 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 167304 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 167304 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 167304 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 167304 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 167304 # number of overall (read+write) accesses system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses @@ -868,60 +927,59 @@ system.cpu3.icache.fast_writes 0 # nu system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 28.848199 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 33595 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1292.115385 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.848199 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056344 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.056344 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 223805 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 223805 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 55561 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 55561 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 55561 # number of overall hits -system.cpu3.dcache.overall_hits::total 55561 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 102 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 102 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 259 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 259 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 259 # number of overall misses -system.cpu3.dcache.overall_misses::total 259 # number of overall misses -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41458 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41458 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 14362 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 14362 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 55820 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003787 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003787 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.007102 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004640 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.004640 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004640 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.004640 # miss rate for overall accesses +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 234241 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 234241 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 42185 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 42185 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 15991 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 15991 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 58176 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 58176 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 58176 # number of overall hits +system.cpu3.dcache.overall_hits::total 58176 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 151 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 151 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 260 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 260 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 260 # number of overall misses +system.cpu3.dcache.overall_misses::total 260 # number of overall misses +system.cpu3.dcache.ReadReq_accesses::cpu3.data 42336 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 42336 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 16100 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 16100 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 58436 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 58436 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 58436 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 58436 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003567 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003567 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006770 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.006770 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004449 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.004449 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004449 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.004449 # miss rate for overall accesses system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 704fea740..1641360b2 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000263 # Number of seconds simulated -sim_ticks 262794500 # Number of ticks simulated -final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 262793500 # Number of ticks simulated +final_tick 262793500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 985745 # Simulator instruction rate (inst/s) -host_op_rate 985721 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 390370221 # Simulator tick rate (ticks/s) -host_mem_usage 283880 # Number of bytes of host memory used -host_seconds 0.67 # Real time elapsed on the host +host_inst_rate 1021127 # Simulator instruction rate (inst/s) +host_op_rate 1021105 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 404381057 # Simulator tick rate (ticks/s) +host_mem_usage 299844 # Number of bytes of host memory used +host_seconds 0.65 # Real time elapsed on the host sim_insts 663567 # Number of instructions simulated sim_ops 663567 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,30 +36,29 @@ system.physmem.num_reads::cpu2.data 15 # Nu system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69407845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40183489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14368642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5357799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 487073 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 3653044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1948290 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3896581 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139302763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69407845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14368642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 487073 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1948290 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86211850 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69407845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40183489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14368642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 5357799 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 487073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 3653044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1948290 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3896581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 139302763 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 139302763 # Throughput (bytes/s) +system.physmem.bw_read::cpu0.inst 69408109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40183642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14368696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5357819 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 487074 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 3653058 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1948298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3896596 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139303293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69408109 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14368696 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 487074 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1948298 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86212178 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69408109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40183642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14368696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 5357819 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 487074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 3653058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1948298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3896596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 139303293 # Total bandwidth to/from this memory (bytes/s) system.membus.trans_dist::ReadReq 430 # Transaction distribution system.membus.trans_dist::ReadResp 430 # Transaction distribution system.membus.trans_dist::UpgradeReq 272 # Transaction distribution @@ -68,30 +67,39 @@ system.membus.trans_dist::ReadExReq 208 # Tr system.membus.trans_dist::ReadExResp 142 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36608 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 852296 # Layer occupancy (ticks) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 261 # Total snoops (count) +system.membus.snoop_fanout::samples 915 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 915 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 915 # Request fanout histogram +system.membus.reqLayer0.occupancy 852796 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) system.membus.respLayer1.occupancy 5420500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 349.046072 # Cycle average of tags in use +system.l2c.tags.tagsinuse 349.046261 # Cycle average of tags in use system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.889005 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 231.790437 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 54.207948 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 51.556673 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6.123914 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1.773020 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 0.843760 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 1.030292 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.831024 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.889004 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 231.790402 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 54.207937 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 51.556867 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 6.123938 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1.773027 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.843763 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 1.030296 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.831027 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.003537 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy @@ -178,36 +186,36 @@ system.l2c.overall_misses::cpu3.data 16 # nu system.l2c.overall_misses::total 592 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.inst 14927000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.data 3451500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 3434500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 3434000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.data 418000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.inst 595000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.data 103000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.inst 465000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.data 104500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 23498500 # number of ReadReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5174000 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::total 23498000 # number of ReadReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5172500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 800500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu2.data 746000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 730000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7450500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 730500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7449500 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.inst 14927000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 8625500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 3434500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 8624000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 3434000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 1218500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2.inst 595000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2.data 849000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu3.inst 465000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 834500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 30949000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 835000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 30947500 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.inst 14927000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 8625500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 3434500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 8624000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 3434000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 1218500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.inst 595000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.data 849000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu3.inst 465000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 834500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 30949000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 835000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 30947500 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) @@ -286,36 +294,36 @@ system.l2c.overall_miss_rate::cpu3.data 0.640000 # mi system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52375.438596 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52037.878788 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52030.303030 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 52250 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49583.333333 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.data 51500 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.inst 51666.666667 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.data 52250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52218.888889 # average ReadReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52262.626263 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52217.777778 # average ReadReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52247.474747 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53366.666667 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53285.714286 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52142.857143 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52468.309859 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52178.571429 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52461.267606 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52266.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52030.303030 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52278.716216 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 52187.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52276.182432 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52266.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52030.303030 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52278.716216 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 52187.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52276.182432 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -393,29 +401,29 @@ system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 600499 system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 763992 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 3084491 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3964000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3962500 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 576500 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5717500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5716000 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.inst 11414500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 6604000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 6602500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 2368500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 897000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.inst 80000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.data 616500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.inst 320000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.data 640000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 22940500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 22939000 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 11414500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 6604000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 6602500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 2368500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 897000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.inst 80000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.data 616500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.inst 320000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.data 640000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 22940500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 22939000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses @@ -467,31 +475,30 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40033.266667 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40025.252525 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41133.333333 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41178.571429 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40264.084507 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40253.521127 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40015.151515 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40103.146853 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40015.151515 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40103.146853 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.toL2Bus.throughput 646588875 # Throughput (bytes/s) system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution @@ -508,17 +515,33 @@ system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 734 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 401 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 4820 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 116032 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 53888 # Total snoop data (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1037 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2929 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 2929 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 2929 # Request fanout histogram system.toL2Bus.reqLayer0.occupancy 1473490 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 2101500 # Layer occupancy (ticks) @@ -538,7 +561,7 @@ system.toL2Bus.respLayer6.utilization 0.6 # La system.toL2Bus.respLayer7.occupancy 1327473 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.5 # Layer utilization (%) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 525589 # number of cpu cycles simulated +system.cpu0.numCycles 525587 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 158574 # Number of instructions committed @@ -557,7 +580,7 @@ system.cpu0.num_mem_refs 74021 # nu system.cpu0.num_load_insts 49007 # Number of load instructions system.cpu0.num_store_insts 25014 # Number of store instructions system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 525589 # Number of busy cycles +system.cpu0.num_busy_cycles 525587 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.Branches 26897 # Number of branches fetched @@ -597,12 +620,12 @@ system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 158636 # Class of executed instruction system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 212.401822 # Cycle average of tags in use +system.cpu0.icache.tags.tagsinuse 212.401858 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 158170 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 338.693790 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.401822 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.401858 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.414847 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id @@ -681,12 +704,12 @@ system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36860.813704 system.cpu0.icache.overall_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 145.571924 # Cycle average of tags in use +system.cpu0.dcache.tags.tagsinuse 145.571907 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 73489 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 440.053892 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.571924 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.571907 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.284320 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id @@ -717,14 +740,14 @@ system.cpu0.dcache.overall_misses::cpu0.data 353 system.cpu0.dcache.overall_misses::total 353 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4586981 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 4586981 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6974000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6974000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6973000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6973000 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 360500 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 360500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11560981 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11560981 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11560981 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11560981 # number of overall miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11559981 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11559981 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11559981 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11559981 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 48997 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 48997 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 24963 # number of WriteReq accesses(hits+misses) @@ -747,14 +770,14 @@ system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004773 system.cpu0.dcache.overall_miss_rate::total 0.004773 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26982.241176 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 26982.241176 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38109.289617 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38109.289617 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38103.825137 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38103.825137 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13865.384615 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 13865.384615 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32750.654391 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 32750.654391 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32750.654391 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 32750.654391 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32747.821530 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 32747.821530 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32747.821530 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 32747.821530 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -777,14 +800,14 @@ system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4237019 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4237019 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6608000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6608000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6607000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6607000 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 308500 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 308500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10845019 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10845019 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10845019 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10845019 # number of overall MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10844019 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10844019 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10844019 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10844019 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003470 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003470 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007331 # mshr miss rate for WriteReq accesses @@ -797,16 +820,16 @@ system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004773 system.cpu0.dcache.overall_mshr_miss_rate::total 0.004773 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24923.641176 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24923.641176 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36109.289617 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36109.289617 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36103.825137 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36103.825137 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11865.384615 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11865.384615 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30722.433428 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30722.433428 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30722.433428 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30722.433428 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30719.600567 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30719.600567 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30719.600567 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30719.600567 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 525588 # number of cpu cycles simulated +system.cpu1.numCycles 525586 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 163471 # Number of instructions committed @@ -824,8 +847,8 @@ system.cpu1.num_fp_register_writes 0 # nu system.cpu1.num_mem_refs 58020 # number of memory refs system.cpu1.num_load_insts 41540 # Number of load instructions system.cpu1.num_store_insts 16480 # Number of store instructions -system.cpu1.num_idle_cycles 69346.869795 # Number of idle cycles -system.cpu1.num_busy_cycles 456241.130205 # Number of busy cycles +system.cpu1.num_idle_cycles 69346.869794 # Number of idle cycles +system.cpu1.num_busy_cycles 456239.130206 # Number of busy cycles system.cpu1.not_idle_fraction 0.868058 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.131942 # Percentage of idle cycles system.cpu1.Branches 31528 # Number of branches fetched @@ -865,12 +888,12 @@ system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 163503 # Class of executed instruction system.cpu1.icache.tags.replacements 280 # number of replacements -system.cpu1.icache.tags.tagsinuse 70.017504 # Cycle average of tags in use +system.cpu1.icache.tags.tagsinuse 70.017769 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017504 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017769 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id @@ -892,12 +915,12 @@ system.cpu1.icache.demand_misses::cpu1.inst 366 # system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7544988 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7544988 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7544988 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7544988 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7544988 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7544988 # number of overall miss cycles +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7544488 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7544488 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7544488 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7544488 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7544488 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7544488 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 163504 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 163504 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 163504 # number of demand (read+write) accesses @@ -910,12 +933,12 @@ system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002238 system.cpu1.icache.demand_miss_rate::total 0.002238 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002238 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.002238 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20614.721311 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 20614.721311 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 20614.721311 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 20614.721311 # average overall miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20613.355191 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 20613.355191 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20613.355191 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 20613.355191 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20613.355191 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 20613.355191 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -930,32 +953,32 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6806012 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6806012 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6806012 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6806012 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6806012 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6806012 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6805512 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6805512 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6805512 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6805512 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6805512 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6805512 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.002238 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.002238 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18595.661202 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18594.295082 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 18594.295082 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 18594.295082 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 27.720196 # Cycle average of tags in use +system.cpu1.dcache.tags.tagsinuse 27.720301 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 35348 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. system.cpu1.dcache.tags.avg_refs 1178.266667 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720196 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720301 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.054141 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.054141 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id @@ -1073,7 +1096,7 @@ system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14948.733840 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 525588 # number of cpu cycles simulated +system.cpu2.numCycles 525586 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu2.committedInsts 164866 # Number of instructions committed @@ -1091,10 +1114,10 @@ system.cpu2.num_fp_register_writes 0 # nu system.cpu2.num_mem_refs 59208 # number of memory refs system.cpu2.num_load_insts 42171 # Number of load instructions system.cpu2.num_store_insts 17037 # Number of store instructions -system.cpu2.num_idle_cycles 69603.869305 # Number of idle cycles -system.cpu2.num_busy_cycles 455984.130695 # Number of busy cycles -system.cpu2.not_idle_fraction 0.867570 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.132430 # Percentage of idle cycles +system.cpu2.num_idle_cycles 69603.869304 # Number of idle cycles +system.cpu2.num_busy_cycles 455982.130696 # Number of busy cycles +system.cpu2.not_idle_fraction 0.867569 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.132431 # Percentage of idle cycles system.cpu2.Branches 31596 # Number of branches fetched system.cpu2.op_class::No_OpClass 22386 13.58% 13.58% # Class of executed instruction system.cpu2.op_class::IntAlu 75723 45.92% 59.50% # Class of executed instruction @@ -1132,12 +1155,12 @@ system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::total 164898 # Class of executed instruction system.cpu2.icache.tags.replacements 280 # number of replacements -system.cpu2.icache.tags.tagsinuse 67.624960 # Cycle average of tags in use +system.cpu2.icache.tags.tagsinuse 67.625211 # Cycle average of tags in use system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624960 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.625211 # Average occupied blocks per requestor system.cpu2.icache.tags.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id @@ -1159,12 +1182,12 @@ system.cpu2.icache.demand_misses::cpu2.inst 366 # system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses system.cpu2.icache.overall_misses::total 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5252488 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 5252488 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 5252488 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 5252488 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 5252488 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 5252488 # number of overall miss cycles +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5251988 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 5251988 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 5251988 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 5251988 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 5251988 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 5251988 # number of overall miss cycles system.cpu2.icache.ReadReq_accesses::cpu2.inst 164899 # number of ReadReq accesses(hits+misses) system.cpu2.icache.ReadReq_accesses::total 164899 # number of ReadReq accesses(hits+misses) system.cpu2.icache.demand_accesses::cpu2.inst 164899 # number of demand (read+write) accesses @@ -1177,12 +1200,12 @@ system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002220 system.cpu2.icache.demand_miss_rate::total 0.002220 # miss rate for demand accesses system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002220 # miss rate for overall accesses system.cpu2.icache.overall_miss_rate::total 0.002220 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14351.060109 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 14351.060109 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 14351.060109 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 14351.060109 # average overall miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14349.693989 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 14349.693989 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14349.693989 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 14349.693989 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14349.693989 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 14349.693989 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1197,32 +1220,32 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4510512 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 4510512 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4510512 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 4510512 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4510512 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 4510512 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4510012 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 4510012 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4510012 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 4510012 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4510012 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 4510012 # number of overall MSHR miss cycles system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for ReadReq accesses system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002220 # mshr miss rate for ReadReq accesses system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for demand accesses system.cpu2.icache.demand_mshr_miss_rate::total 0.002220 # mshr miss rate for demand accesses system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for overall accesses system.cpu2.icache.overall_mshr_miss_rate::total 0.002220 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12323.803279 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12322.437158 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 12322.437158 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 12322.437158 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 26.763890 # Cycle average of tags in use +system.cpu2.dcache.tags.tagsinuse 26.763988 # Cycle average of tags in use system.cpu2.dcache.tags.total_refs 36347 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. system.cpu2.dcache.tags.avg_refs 1253.344828 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763890 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763988 # Average occupied blocks per requestor system.cpu2.dcache.tags.occ_percent::cpu2.data 0.052273 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_percent::total 0.052273 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id @@ -1340,7 +1363,7 @@ system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13429.461832 system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 525588 # number of cpu cycles simulated +system.cpu3.numCycles 525586 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu3.committedInsts 176656 # Number of instructions committed @@ -1358,10 +1381,10 @@ system.cpu3.num_fp_register_writes 0 # nu system.cpu3.num_mem_refs 46164 # number of memory refs system.cpu3.num_load_insts 39753 # Number of load instructions system.cpu3.num_store_insts 6411 # Number of store instructions -system.cpu3.num_idle_cycles 69869.868798 # Number of idle cycles -system.cpu3.num_busy_cycles 455718.131202 # Number of busy cycles -system.cpu3.not_idle_fraction 0.867063 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.132937 # Percentage of idle cycles +system.cpu3.num_idle_cycles 69867.868801 # Number of idle cycles +system.cpu3.num_busy_cycles 455718.131199 # Number of busy cycles +system.cpu3.not_idle_fraction 0.867067 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.132933 # Percentage of idle cycles system.cpu3.Branches 39890 # Number of branches fetched system.cpu3.op_class::No_OpClass 30652 17.35% 17.35% # Class of executed instruction system.cpu3.op_class::IntAlu 73353 41.52% 58.86% # Class of executed instruction @@ -1399,12 +1422,12 @@ system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::total 176688 # Class of executed instruction system.cpu3.icache.tags.replacements 281 # number of replacements -system.cpu3.icache.tags.tagsinuse 65.598437 # Cycle average of tags in use +system.cpu3.icache.tags.tagsinuse 65.598702 # Cycle average of tags in use system.cpu3.icache.tags.total_refs 176322 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. system.cpu3.icache.tags.avg_refs 480.441417 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.598437 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.598702 # Average occupied blocks per requestor system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128122 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_percent::total 0.128122 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id @@ -1484,14 +1507,14 @@ system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12023.163488 system.cpu3.icache.overall_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 25.915086 # Cycle average of tags in use +system.cpu3.dcache.tags.tagsinuse 25.915188 # Cycle average of tags in use system.cpu3.dcache.tags.total_refs 15020 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. system.cpu3.dcache.tags.avg_refs 517.931034 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.915086 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050615 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.050615 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.915188 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050616 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.050616 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id @@ -1520,14 +1543,14 @@ system.cpu3.dcache.overall_misses::cpu3.data 288 system.cpu3.dcache.overall_misses::total 288 # number of overall misses system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3156473 # number of ReadReq miss cycles system.cpu3.dcache.ReadReq_miss_latency::total 3156473 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2098500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2098500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2099000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2099000 # number of WriteReq miss cycles system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 280000 # number of SwapReq miss cycles system.cpu3.dcache.SwapReq_miss_latency::total 280000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 5254973 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 5254973 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 5254973 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 5254973 # number of overall miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 5255473 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 5255473 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 5255473 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 5255473 # number of overall miss cycles system.cpu3.dcache.ReadReq_accesses::cpu3.data 39746 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.ReadReq_accesses::total 39746 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.WriteReq_accesses::cpu3.data 6321 # number of WriteReq accesses(hits+misses) @@ -1550,14 +1573,14 @@ system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006252 system.cpu3.dcache.overall_miss_rate::total 0.006252 # miss rate for overall accesses system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17248.486339 # average ReadReq miss latency system.cpu3.dcache.ReadReq_avg_miss_latency::total 17248.486339 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19985.714286 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 19985.714286 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19990.476190 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 19990.476190 # average WriteReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4057.971014 # average SwapReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::total 4057.971014 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18246.434028 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 18246.434028 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18246.434028 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 18246.434028 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18248.170139 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 18248.170139 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18248.170139 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 18248.170139 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1578,14 +1601,14 @@ system.cpu3.dcache.overall_mshr_misses::cpu3.data 288 system.cpu3.dcache.overall_mshr_misses::total 288 # number of overall MSHR misses system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2772527 # number of ReadReq MSHR miss cycles system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2772527 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1888500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1888500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1889000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1889000 # number of WriteReq MSHR miss cycles system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 142000 # number of SwapReq MSHR miss cycles system.cpu3.dcache.SwapReq_mshr_miss_latency::total 142000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4661027 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 4661027 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4661027 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 4661027 # number of overall MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4661527 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 4661527 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4661527 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 4661527 # number of overall MSHR miss cycles system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004604 # mshr miss rate for ReadReq accesses system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004604 # mshr miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.016611 # mshr miss rate for WriteReq accesses @@ -1598,14 +1621,14 @@ system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.006252 system.cpu3.dcache.overall_mshr_miss_rate::total 0.006252 # mshr miss rate for overall accesses system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15150.420765 # average ReadReq mshr miss latency system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15150.420765 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17985.714286 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17985.714286 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17990.476190 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17990.476190 # average WriteReq mshr miss latency system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2057.971014 # average SwapReq mshr miss latency system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2057.971014 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16185.857639 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16185.857639 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16185.857639 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16185.857639 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt index 61ee516ee..63e8b7d3a 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.007430 # Nu sim_ticks 7430292 # Number of ticks simulated final_tick 7430292 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 111636 # Simulator tick rate (ticks/s) -host_mem_usage 267664 # Number of bytes of host memory used -host_seconds 66.56 # Real time elapsed on the host +host_tick_rate 73095 # Simulator tick rate (ticks/s) +host_mem_usage 318168 # Number of bytes of host memory used +host_seconds 101.65 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.ruby.clk_domain.clock 1 # Clock period in ticks @@ -380,8 +380,6 @@ system.ruby.network.msg_byte.Response_Data 315144288 system.ruby.network.msg_byte.Response_Control 51426416 system.ruby.network.msg_byte.Writeback_Data 111484296 system.ruby.network.msg_byte.Writeback_Control 4869144 -system.funcbus.throughput 0 # Throughput (bytes/s) -system.funcbus.data_through_bus 0 # Total data (bytes) system.cpu0.num_reads 99258 # number of read accesses completed system.cpu0.num_writes 54534 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt index 9c9c7aca3..e0f3b655e 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.007646 # Nu sim_ticks 7645897 # Number of ticks simulated final_tick 7645897 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 53519 # Simulator tick rate (ticks/s) -host_mem_usage 294536 # Number of bytes of host memory used -host_seconds 142.86 # Real time elapsed on the host +host_tick_rate 46164 # Simulator tick rate (ticks/s) +host_mem_usage 322852 # Number of bytes of host memory used +host_seconds 165.63 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.ruby.clk_domain.clock 1 # Clock period in ticks @@ -47,6 +47,7 @@ system.ruby.l1_cntrl4.L1Dcache.demand_accesses 79152 system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.cpu_clk_domain.clock 1 # Clock period in ticks system.ruby.l1_cntrl5.L1Dcache.demand_hits 27 # Number of cache demand hits system.ruby.l1_cntrl5.L1Dcache.demand_misses 78996 # Number of cache demand misses system.ruby.l1_cntrl5.L1Dcache.demand_accesses 79023 # Number of cache demand accesses @@ -71,27 +72,6 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 79099 system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Dcache.demand_hits 9 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 78940 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78949 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl2.L1Dcache.demand_hits 26 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Dcache.demand_misses 79113 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Dcache.demand_accesses 79139 # Number of cache demand accesses -system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl3.L1Dcache.demand_hits 24 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Dcache.demand_misses 78765 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78789 # Number of cache demand accesses -system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l2_cntrl0.L2cache.demand_hits 6149 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 625832 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 631981 # Number of cache demand accesses system.ruby.network.routers00.percent_links_utilized 5.698442 system.ruby.network.routers00.msg_count.Request_Control::0 79077 system.ruby.network.routers00.msg_count.Response_Data::2 77245 @@ -113,6 +93,12 @@ system.ruby.network.routers00.msg_bytes.Writeback_Control::0 1264976 system.ruby.network.routers00.msg_bytes.Forwarded_Control::0 8736 system.ruby.network.routers00.msg_bytes.Invalidate_Control::0 24 system.ruby.network.routers00.msg_bytes.Unblock_Control::2 640168 +system.ruby.l1_cntrl1.L1Dcache.demand_hits 9 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 78940 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78949 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses system.ruby.network.routers01.percent_links_utilized 5.685628 system.ruby.network.routers01.msg_count.Request_Control::0 78939 system.ruby.network.routers01.msg_count.Response_Data::2 77083 @@ -134,6 +120,12 @@ system.ruby.network.routers01.msg_bytes.Writeback_Control::0 1262528 system.ruby.network.routers01.msg_bytes.Forwarded_Control::0 8496 system.ruby.network.routers01.msg_bytes.Invalidate_Control::0 8 system.ruby.network.routers01.msg_bytes.Unblock_Control::2 639464 +system.ruby.l1_cntrl2.L1Dcache.demand_hits 26 # Number of cache demand hits +system.ruby.l1_cntrl2.L1Dcache.demand_misses 79113 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Dcache.demand_accesses 79139 # Number of cache demand accesses +system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses system.ruby.network.routers02.percent_links_utilized 5.700427 system.ruby.network.routers02.msg_count.Request_Control::0 79113 system.ruby.network.routers02.msg_count.Response_Data::2 77289 @@ -155,6 +147,12 @@ system.ruby.network.routers02.msg_bytes.Writeback_Control::0 1265408 system.ruby.network.routers02.msg_bytes.Forwarded_Control::0 8720 system.ruby.network.routers02.msg_bytes.Invalidate_Control::0 8 system.ruby.network.routers02.msg_bytes.Unblock_Control::2 640512 +system.ruby.l1_cntrl3.L1Dcache.demand_hits 24 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Dcache.demand_misses 78765 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78789 # Number of cache demand accesses +system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses system.ruby.network.routers03.percent_links_utilized 5.674514 system.ruby.network.routers03.msg_count.Request_Control::0 78765 system.ruby.network.routers03.msg_count.Response_Data::2 76945 @@ -258,6 +256,9 @@ system.ruby.network.routers07.msg_bytes.Writeback_Data::2 5593464 system.ruby.network.routers07.msg_bytes.Writeback_Control::0 1259488 system.ruby.network.routers07.msg_bytes.Forwarded_Control::0 8512 system.ruby.network.routers07.msg_bytes.Unblock_Control::2 637968 +system.ruby.l2_cntrl0.L2cache.demand_hits 6149 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 625832 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 631981 # Number of cache demand accesses system.ruby.network.routers08.percent_links_utilized 79.115289 system.ruby.network.routers08.msg_count.Request_Control::0 631981 system.ruby.network.routers08.msg_count.Request_Control::1 617280 @@ -361,9 +362,6 @@ system.ruby.network.msg_byte.Writeback_Control 69377984 system.ruby.network.msg_byte.Forwarded_Control 205248 system.ruby.network.msg_byte.Invalidate_Control 264 system.ruby.network.msg_byte.Unblock_Control 30168336 -system.funcbus.throughput 0 # Throughput (bytes/s) -system.funcbus.data_through_bus 0 # Total data (bytes) -system.cpu_clk_domain.clock 1 # Clock period in ticks system.cpu0.num_reads 99316 # number of read accesses completed system.cpu0.num_writes 55500 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index 607213fd3..f3dea5b38 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.006285 # Nu sim_ticks 6284915 # Number of ticks simulated final_tick 6284915 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 64396 # Simulator tick rate (ticks/s) -host_mem_usage 293488 # Number of bytes of host memory used -host_seconds 97.60 # Real time elapsed on the host +host_tick_rate 51541 # Simulator tick rate (ticks/s) +host_mem_usage 318988 # Number of bytes of host memory used +host_seconds 121.94 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.ruby.clk_domain.clock 1 # Clock period in ticks @@ -50,6 +50,7 @@ system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78769 system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.cpu_clk_domain.clock 1 # Clock period in ticks system.ruby.l1_cntrl5.L1Dcache.demand_hits 26 # Number of cache demand hits system.ruby.l1_cntrl5.L1Dcache.demand_misses 78593 # Number of cache demand misses system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78619 # Number of cache demand accesses @@ -74,27 +75,6 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78396 system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Dcache.demand_hits 27 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 78895 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78922 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl2.L1Dcache.demand_hits 23 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Dcache.demand_misses 78341 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78364 # Number of cache demand accesses -system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl3.L1Dcache.demand_hits 22 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Dcache.demand_misses 78389 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78411 # Number of cache demand accesses -system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l2_cntrl0.L2cache.demand_hits 1540 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 626511 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 628051 # Number of cache demand accesses system.ruby.network.routers00.percent_links_utilized 9.881597 system.ruby.network.routers00.msg_count.Request_Control::1 78371 system.ruby.network.routers00.msg_count.Response_Data::4 78092 @@ -112,6 +92,12 @@ system.ruby.network.routers00.msg_bytes.Response_Control::4 1272 system.ruby.network.routers00.msg_bytes.Writeback_Data::4 6183216 system.ruby.network.routers00.msg_bytes.Broadcast_Control::1 5024408 system.ruby.network.routers00.msg_bytes.Persistent_Control::3 2375752 +system.ruby.l1_cntrl1.L1Dcache.demand_hits 27 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 78895 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78922 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses system.ruby.network.routers01.percent_links_utilized 9.921833 system.ruby.network.routers01.msg_count.Request_Control::1 78895 system.ruby.network.routers01.msg_count.Response_Data::4 78610 @@ -131,6 +117,12 @@ system.ruby.network.routers01.msg_bytes.Writeback_Data::4 6220944 system.ruby.network.routers01.msg_bytes.Writeback_Control::4 16 system.ruby.network.routers01.msg_bytes.Broadcast_Control::1 5024408 system.ruby.network.routers01.msg_bytes.Persistent_Control::3 2378952 +system.ruby.l1_cntrl2.L1Dcache.demand_hits 23 # Number of cache demand hits +system.ruby.l1_cntrl2.L1Dcache.demand_misses 78341 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78364 # Number of cache demand accesses +system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses system.ruby.network.routers02.percent_links_utilized 9.878833 system.ruby.network.routers02.msg_count.Request_Control::1 78341 system.ruby.network.routers02.msg_count.Response_Data::4 77980 @@ -148,6 +140,12 @@ system.ruby.network.routers02.msg_bytes.Response_Control::4 1360 system.ruby.network.routers02.msg_bytes.Writeback_Data::4 6178320 system.ruby.network.routers02.msg_bytes.Broadcast_Control::1 5024408 system.ruby.network.routers02.msg_bytes.Persistent_Control::3 2378600 +system.ruby.l1_cntrl3.L1Dcache.demand_hits 22 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Dcache.demand_misses 78389 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78411 # Number of cache demand accesses +system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses system.ruby.network.routers03.percent_links_utilized 9.881140 system.ruby.network.routers03.msg_count.Request_Control::1 78389 system.ruby.network.routers03.msg_count.Response_Data::4 78013 @@ -237,6 +235,9 @@ system.ruby.network.routers07.msg_bytes.Response_Control::4 1600 system.ruby.network.routers07.msg_bytes.Writeback_Data::4 6183144 system.ruby.network.routers07.msg_bytes.Broadcast_Control::1 5024408 system.ruby.network.routers07.msg_bytes.Persistent_Control::3 2376760 +system.ruby.l2_cntrl0.L2cache.demand_hits 1540 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 626511 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 628051 # Number of cache demand accesses system.ruby.network.routers08.percent_links_utilized 38.794550 system.ruby.network.routers08.msg_count.Request_Control::1 628051 system.ruby.network.routers08.msg_count.Request_Control::2 626511 @@ -326,9 +327,6 @@ system.ruby.network.msg_byte.Writeback_Data 194435640 system.ruby.network.msg_byte.Writeback_Control 9144888 system.ruby.network.msg_byte.Broadcast_Control 75366120 system.ruby.network.msg_byte.Persistent_Control 42271680 -system.funcbus.throughput 0 # Throughput (bytes/s) -system.funcbus.data_through_bus 0 # Total data (bytes) -system.cpu_clk_domain.clock 1 # Clock period in ticks system.cpu0.num_reads 100000 # number of read accesses completed system.cpu0.num_writes 55570 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index 2a34715b3..fa10b335e 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.005921 # Nu sim_ticks 5920895 # Number of ticks simulated final_tick 5920895 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 58624 # Simulator tick rate (ticks/s) -host_mem_usage 293400 # Number of bytes of host memory used -host_seconds 101.00 # Real time elapsed on the host +host_tick_rate 46540 # Simulator tick rate (ticks/s) +host_mem_usage 317888 # Number of bytes of host memory used +host_seconds 127.22 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.ruby.clk_domain.clock 1 # Clock period in ticks @@ -52,6 +52,7 @@ system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 system.ruby.l1_cntrl4.L2cache.demand_hits 77 # Number of cache demand hits system.ruby.l1_cntrl4.L2cache.demand_misses 78569 # Number of cache demand misses system.ruby.l1_cntrl4.L2cache.demand_accesses 78646 # Number of cache demand accesses +system.cpu_clk_domain.clock 1 # Clock period in ticks system.ruby.l1_cntrl5.L1Dcache.demand_hits 19 # Number of cache demand hits system.ruby.l1_cntrl5.L1Dcache.demand_misses 78666 # Number of cache demand misses system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78685 # Number of cache demand accesses @@ -88,33 +89,6 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 system.ruby.l1_cntrl0.L2cache.demand_hits 80 # Number of cache demand hits system.ruby.l1_cntrl0.L2cache.demand_misses 78315 # Number of cache demand misses system.ruby.l1_cntrl0.L2cache.demand_accesses 78395 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Dcache.demand_hits 15 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 78908 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78923 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl1.L2cache.demand_hits 80 # Number of cache demand hits -system.ruby.l1_cntrl1.L2cache.demand_misses 78828 # Number of cache demand misses -system.ruby.l1_cntrl1.L2cache.demand_accesses 78908 # Number of cache demand accesses -system.ruby.l1_cntrl2.L1Dcache.demand_hits 15 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Dcache.demand_misses 78622 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78637 # Number of cache demand accesses -system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl2.L2cache.demand_hits 77 # Number of cache demand hits -system.ruby.l1_cntrl2.L2cache.demand_misses 78545 # Number of cache demand misses -system.ruby.l1_cntrl2.L2cache.demand_accesses 78622 # Number of cache demand accesses -system.ruby.l1_cntrl3.L1Dcache.demand_hits 17 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Dcache.demand_misses 78711 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78728 # Number of cache demand accesses -system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl3.L2cache.demand_hits 72 # Number of cache demand hits -system.ruby.l1_cntrl3.L2cache.demand_misses 78639 # Number of cache demand misses -system.ruby.l1_cntrl3.L2cache.demand_accesses 78711 # Number of cache demand accesses system.ruby.network.routers0.percent_links_utilized 12.539882 system.ruby.network.routers0.msg_count.Request_Control::2 78315 system.ruby.network.routers0.msg_count.Request_Control::3 59 @@ -136,6 +110,15 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::3 591720 system.ruby.network.routers0.msg_bytes.Writeback_Control::5 370520 system.ruby.network.routers0.msg_bytes.Broadcast_Control::3 4397184 system.ruby.network.routers0.msg_bytes.Unblock_Control::5 626624 +system.ruby.l1_cntrl1.L1Dcache.demand_hits 15 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 78908 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78923 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl1.L2cache.demand_hits 80 # Number of cache demand hits +system.ruby.l1_cntrl1.L2cache.demand_misses 78828 # Number of cache demand misses +system.ruby.l1_cntrl1.L2cache.demand_accesses 78908 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 12.590850 system.ruby.network.routers1.msg_count.Request_Control::2 78828 system.ruby.network.routers1.msg_count.Request_Control::3 53 @@ -157,6 +140,15 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::3 594800 system.ruby.network.routers1.msg_bytes.Writeback_Control::5 370728 system.ruby.network.routers1.msg_bytes.Broadcast_Control::3 4392992 system.ruby.network.routers1.msg_bytes.Unblock_Control::5 630808 +system.ruby.l1_cntrl2.L1Dcache.demand_hits 15 # Number of cache demand hits +system.ruby.l1_cntrl2.L1Dcache.demand_misses 78622 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78637 # Number of cache demand accesses +system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl2.L2cache.demand_hits 77 # Number of cache demand hits +system.ruby.l1_cntrl2.L2cache.demand_misses 78545 # Number of cache demand misses +system.ruby.l1_cntrl2.L2cache.demand_accesses 78622 # Number of cache demand accesses system.ruby.network.routers2.percent_links_utilized 12.557548 system.ruby.network.routers2.msg_count.Request_Control::2 78545 system.ruby.network.routers2.msg_count.Request_Control::3 51 @@ -178,6 +170,15 @@ system.ruby.network.routers2.msg_bytes.Writeback_Control::3 593024 system.ruby.network.routers2.msg_bytes.Writeback_Control::5 371048 system.ruby.network.routers2.msg_bytes.Broadcast_Control::3 4395248 system.ruby.network.routers2.msg_bytes.Unblock_Control::5 628504 +system.ruby.l1_cntrl3.L1Dcache.demand_hits 17 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Dcache.demand_misses 78711 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78728 # Number of cache demand accesses +system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl3.L2cache.demand_hits 72 # Number of cache demand hits +system.ruby.l1_cntrl3.L2cache.demand_misses 78639 # Number of cache demand misses +system.ruby.l1_cntrl3.L2cache.demand_accesses 78711 # Number of cache demand accesses system.ruby.network.routers3.percent_links_utilized 12.569726 system.ruby.network.routers3.msg_count.Request_Control::2 78639 system.ruby.network.routers3.msg_count.Request_Control::3 54 @@ -358,9 +359,6 @@ system.ruby.network.msg_byte.Writeback_Data 47865816 system.ruby.network.msg_byte.Writeback_Control 37367352 system.ruby.network.msg_byte.Broadcast_Control 75348720 system.ruby.network.msg_byte.Unblock_Control 15084048 -system.funcbus.throughput 0 # Throughput (bytes/s) -system.funcbus.data_through_bus 0 # Total data (bytes) -system.cpu_clk_domain.clock 1 # Clock period in ticks system.cpu0.num_reads 99506 # number of read accesses completed system.cpu0.num_writes 55459 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index f296585bd..befc7837c 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.008851 # Nu sim_ticks 8851106 # Number of ticks simulated final_tick 8851106 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 251677 # Simulator tick rate (ticks/s) -host_mem_usage 263028 # Number of bytes of host memory used -host_seconds 35.17 # Real time elapsed on the host +host_tick_rate 185635 # Simulator tick rate (ticks/s) +host_mem_usage 317472 # Number of bytes of host memory used +host_seconds 47.68 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.ruby.clk_domain.clock 1 # Clock period in ticks @@ -46,6 +46,7 @@ system.ruby.Directory.incomplete_times 622362 system.ruby.l1_cntrl4.cacheMemory.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl4.cacheMemory.demand_misses 78801 # Number of cache demand misses system.ruby.l1_cntrl4.cacheMemory.demand_accesses 78801 # Number of cache demand accesses +system.cpu_clk_domain.clock 1 # Clock period in ticks system.ruby.l1_cntrl5.cacheMemory.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl5.cacheMemory.demand_misses 78712 # Number of cache demand misses system.ruby.l1_cntrl5.cacheMemory.demand_accesses 78712 # Number of cache demand accesses @@ -58,15 +59,6 @@ system.ruby.l1_cntrl7.cacheMemory.demand_accesses 79132 system.ruby.l1_cntrl0.cacheMemory.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 78906 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 78906 # Number of cache demand accesses -system.ruby.l1_cntrl1.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl1.cacheMemory.demand_misses 78862 # Number of cache demand misses -system.ruby.l1_cntrl1.cacheMemory.demand_accesses 78862 # Number of cache demand accesses -system.ruby.l1_cntrl2.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl2.cacheMemory.demand_misses 78717 # Number of cache demand misses -system.ruby.l1_cntrl2.cacheMemory.demand_accesses 78717 # Number of cache demand accesses -system.ruby.l1_cntrl3.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl3.cacheMemory.demand_misses 79057 # Number of cache demand misses -system.ruby.l1_cntrl3.cacheMemory.demand_accesses 79057 # Number of cache demand accesses system.ruby.network.routers0.percent_links_utilized 4.466411 system.ruby.network.routers0.msg_count.Control::2 78906 system.ruby.network.routers0.msg_count.Data::2 78209 @@ -76,6 +68,9 @@ system.ruby.network.routers0.msg_bytes.Control::2 631248 system.ruby.network.routers0.msg_bytes.Data::2 5631048 system.ruby.network.routers0.msg_bytes.Response_Data::4 5754384 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 633776 +system.ruby.l1_cntrl1.cacheMemory.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl1.cacheMemory.demand_misses 78862 # Number of cache demand misses +system.ruby.l1_cntrl1.cacheMemory.demand_accesses 78862 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 4.464072 system.ruby.network.routers1.msg_count.Control::2 78862 system.ruby.network.routers1.msg_count.Data::2 78116 @@ -85,6 +80,9 @@ system.ruby.network.routers1.msg_bytes.Control::2 630896 system.ruby.network.routers1.msg_bytes.Data::2 5624352 system.ruby.network.routers1.msg_bytes.Response_Data::4 5755104 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 633480 +system.ruby.l1_cntrl2.cacheMemory.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl2.cacheMemory.demand_misses 78717 # Number of cache demand misses +system.ruby.l1_cntrl2.cacheMemory.demand_accesses 78717 # Number of cache demand accesses system.ruby.network.routers2.percent_links_utilized 4.456923 system.ruby.network.routers2.msg_count.Control::2 78717 system.ruby.network.routers2.msg_count.Data::2 78011 @@ -94,6 +92,9 @@ system.ruby.network.routers2.msg_bytes.Control::2 629736 system.ruby.network.routers2.msg_bytes.Data::2 5616792 system.ruby.network.routers2.msg_bytes.Response_Data::4 5744448 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 632608 +system.ruby.l1_cntrl3.cacheMemory.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl3.cacheMemory.demand_misses 79057 # Number of cache demand misses +system.ruby.l1_cntrl3.cacheMemory.demand_accesses 79057 # Number of cache demand accesses system.ruby.network.routers3.percent_links_utilized 4.475147 system.ruby.network.routers3.msg_count.Control::2 79057 system.ruby.network.routers3.msg_count.Data::2 78335 @@ -183,9 +184,6 @@ system.ruby.network.msg_byte.Control 15140856 system.ruby.network.msg_byte.Data 135010584 system.ruby.network.msg_byte.Response_Data 136263888 system.ruby.network.msg_byte.Writeback_Control 15204144 -system.funcbus.throughput 0 # Throughput (bytes/s) -system.funcbus.data_through_bus 0 # Total data (bytes) -system.cpu_clk_domain.clock 1 # Clock period in ticks system.cpu0.num_reads 99672 # number of read accesses completed system.cpu0.num_writes 55456 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt index 03cf254c4..66986747e 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -1,678 +1,674 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.001466 # Number of seconds simulated -sim_ticks 1466014000 # Number of ticks simulated -final_tick 1466014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.001487 # Number of seconds simulated +sim_ticks 1486654500 # Number of ticks simulated +final_tick 1486654500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 362824283 # Simulator tick rate (ticks/s) -host_mem_usage 344492 # Number of bytes of host memory used -host_seconds 4.04 # Real time elapsed on the host +host_tick_rate 296727534 # Simulator tick rate (ticks/s) +host_mem_usage 404724 # Number of bytes of host memory used +host_seconds 5.01 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 81024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 82440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 87271 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 81468 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 83154 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 83511 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 83243 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 81362 # Number of bytes read from this memory -system.physmem.bytes_read::total 663473 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 418112 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5482 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5323 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5338 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5333 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5428 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5332 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5280 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5327 # Number of bytes written to this memory -system.physmem.bytes_written::total 460955 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11094 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 11124 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11230 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10971 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11082 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 11061 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 11171 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 11117 # Number of read requests responded to by this memory -system.physmem.num_reads::total 88850 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6533 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5482 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5323 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5338 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5333 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5428 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5332 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5280 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5327 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49376 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 55268231 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 56234115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 59529445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 55571093 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 56721150 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 56964667 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 56781859 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 55498788 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 452569348 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 285203279 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 3739391 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 3630934 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 3641166 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 3637755 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 3702557 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 3637073 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 3601603 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 3633662 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 314427420 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 285203279 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 59007622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 59865049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 63170611 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 59208848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 60423707 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 60601741 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 60383462 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 59132450 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 766996768 # Total bandwidth to/from this memory (bytes/s) -system.membus.snoop_filter.tot_requests 121068 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 119020 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.physmem.bytes_read::cpu0 76776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 78761 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 77348 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 78011 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 77583 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 76150 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 79121 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 75007 # Number of bytes read from this memory +system.physmem.bytes_read::total 618757 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 383744 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5329 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5414 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5336 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5424 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5535 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5438 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5327 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5496 # Number of bytes written to this memory +system.physmem.bytes_written::total 427043 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11067 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10847 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10757 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10790 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11118 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10756 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10829 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10873 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87037 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 5996 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5329 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5414 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5336 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5424 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5535 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5438 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5327 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5496 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49295 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 51643472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 52978685 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 52028228 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 52474196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 52186302 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 51222392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 53220839 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 50453552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 416207666 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 258125879 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 3584558 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 3641734 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 3589267 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 3648460 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 3723125 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 3657877 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 3583213 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 3696891 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 287251006 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 258125879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 55228030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 56620419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 55617496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 56122657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 55909426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 54880270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 56804052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 54150443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 703458672 # Total bandwidth to/from this memory (bytes/s) +system.membus.snoop_filter.tot_requests 122188 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 120140 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.throughput 766995404 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 85646 # Transaction distribution -system.membus.trans_dist::ReadResp 85644 # Transaction distribution -system.membus.trans_dist::WriteReq 42843 # Transaction distribution -system.membus.trans_dist::WriteResp 42842 # Transaction distribution -system.membus.trans_dist::Writeback 6533 # Transaction distribution -system.membus.trans_dist::UpgradeReq 57248 # Transaction distribution -system.membus.trans_dist::UpgradeResp 46699 # Transaction distribution -system.membus.trans_dist::ReadExReq 48957 # Transaction distribution -system.membus.trans_dist::ReadExResp 3204 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 419616 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 419616 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 1124426 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 1124426 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1124426 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.snoops_through_bus 56301 # Total snoops (count) -system.membus.snoop_fanout::samples 121068 # Request fanout histogram +system.membus.trans_dist::ReadReq 84101 # Transaction distribution +system.membus.trans_dist::ReadResp 84098 # Transaction distribution +system.membus.trans_dist::WriteReq 43299 # Transaction distribution +system.membus.trans_dist::WriteResp 43298 # Transaction distribution +system.membus.trans_dist::Writeback 5996 # Transaction distribution +system.membus.trans_dist::UpgradeReq 58155 # Transaction distribution +system.membus.trans_dist::UpgradeResp 47311 # Transaction distribution +system.membus.trans_dist::ReadExReq 50200 # Transaction distribution +system.membus.trans_dist::ReadExResp 2936 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 419394 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 419394 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1045797 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1045797 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 58108 # Total snoops (count) +system.membus.snoop_fanout::samples 122188 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 121068 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 122188 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 121068 # Request fanout histogram -system.membus.reqLayer0.occupancy 476149500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 32.5 # Layer utilization (%) -system.membus.respLayer0.occupancy 322630500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 22.0 # Layer utilization (%) +system.membus.snoop_fanout::total 122188 # Request fanout histogram +system.membus.reqLayer0.occupancy 471309000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 31.7 # Layer utilization (%) +system.membus.respLayer0.occupancy 318465500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 21.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 13552 # number of replacements -system.l2c.tags.tagsinuse 786.290427 # Cycle average of tags in use -system.l2c.tags.total_refs 149902 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14350 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.446132 # Average number of references to valid blocks. +system.l2c.tags.replacements 12651 # number of replacements +system.l2c.tags.tagsinuse 779.272325 # Cycle average of tags in use +system.l2c.tags.total_refs 149024 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 13435 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.092222 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 730.775276 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 6.840177 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 7.161871 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 6.892698 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 6.763865 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.714219 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.973391 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 7.262671 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 6.906259 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.713648 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006680 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006994 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.006731 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.006605 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.006557 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.006810 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.007092 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006744 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.767862 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 368 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 428 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 1950254 # Number of tag accesses -system.l2c.tags.data_accesses 1950254 # Number of data accesses -system.l2c.ReadReq_hits::cpu0 10780 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10796 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10830 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10794 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10743 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10804 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10680 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10909 # number of ReadReq hits -system.l2c.ReadReq_hits::total 86336 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 74514 # number of Writeback hits -system.l2c.Writeback_hits::total 74514 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 330 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 332 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 379 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 363 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 357 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 362 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 317 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 363 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2803 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1848 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1871 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1840 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1858 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1858 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1893 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1894 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1826 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 14888 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12628 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12667 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12670 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12652 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12601 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12697 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12574 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12735 # number of demand (read+write) hits -system.l2c.demand_hits::total 101224 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12628 # number of overall hits -system.l2c.overall_hits::cpu1 12667 # number of overall hits -system.l2c.overall_hits::cpu2 12670 # number of overall hits -system.l2c.overall_hits::cpu3 12652 # number of overall hits -system.l2c.overall_hits::cpu4 12601 # number of overall hits -system.l2c.overall_hits::cpu5 12697 # number of overall hits -system.l2c.overall_hits::cpu6 12574 # number of overall hits -system.l2c.overall_hits::cpu7 12735 # number of overall hits -system.l2c.overall_hits::total 101224 # number of overall hits -system.l2c.ReadReq_misses::cpu0 745 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 743 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 781 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 728 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 729 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 753 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 747 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 720 # number of ReadReq misses -system.l2c.ReadReq_misses::total 5946 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1905 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1885 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1879 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1905 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1913 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1875 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1933 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1894 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15189 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4304 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4329 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4371 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4347 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4382 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4378 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4299 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4310 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 34720 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5049 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5072 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5152 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5075 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5111 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5131 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5046 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5030 # number of demand (read+write) misses -system.l2c.demand_misses::total 40666 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5049 # number of overall misses -system.l2c.overall_misses::cpu1 5072 # number of overall misses -system.l2c.overall_misses::cpu2 5152 # number of overall misses -system.l2c.overall_misses::cpu3 5075 # number of overall misses -system.l2c.overall_misses::cpu4 5111 # number of overall misses -system.l2c.overall_misses::cpu5 5131 # number of overall misses -system.l2c.overall_misses::cpu6 5046 # number of overall misses -system.l2c.overall_misses::cpu7 5030 # number of overall misses -system.l2c.overall_misses::total 40666 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 43593500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 43998500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 45727000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 43059000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 43120000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 43827500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 44039000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 42172500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 349537000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 55121000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 55784000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 54929500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 55686500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 54924000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 54520000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 53558500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 55750500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 440274000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 230029000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 231291500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 233753500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 232262000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 233669000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 234419500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 229747500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 230546000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1855718000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 273622500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 275290000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 279480500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 275321000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 276789000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 278247000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 273786500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 272718500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2205255000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 273622500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 275290000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 279480500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 275321000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 276789000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 278247000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 273786500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 272718500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2205255000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0 11525 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1 11539 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2 11611 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3 11522 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu4 11472 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu5 11557 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu6 11427 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu7 11629 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 92282 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 74514 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 74514 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2235 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2217 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2258 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2268 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2270 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2237 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2250 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2257 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 17992 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6152 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6200 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6211 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6205 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6240 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6271 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6193 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6136 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 49608 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17677 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17739 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17822 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17727 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17712 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17828 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17620 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17765 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 141890 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17677 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17739 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17822 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17727 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17712 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17828 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17620 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17765 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 141890 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.064642 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.064390 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.067264 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.063183 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.063546 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.065155 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.065371 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.061914 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.064433 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.852349 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.850248 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.832152 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.839947 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.842731 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.838176 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.859111 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.839167 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.844209 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.699610 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.698226 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.703751 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.700564 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.702244 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.698134 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.694171 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.702412 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.699887 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.285625 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.285924 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.289081 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.286286 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.288561 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.287806 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.286379 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.283141 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.286602 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.285625 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.285924 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.289081 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.286286 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.288561 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.287806 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.286379 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.283141 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.286602 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 58514.765101 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 59217.362046 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 58549.295775 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 59146.978022 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 59149.519890 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 58203.851262 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 58954.484605 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 58572.916667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 58785.233771 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 28934.908136 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 29593.633952 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 29233.368813 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 29231.758530 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 28710.925248 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 29077.333333 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 27707.449560 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 29435.322070 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 28986.371716 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 53445.399628 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 53428.389928 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 53478.265843 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 53430.411778 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 53324.737563 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 53544.883508 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 53442.079553 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 53490.951276 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53448.099078 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 54193.404635 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 54276.419558 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 54246.991460 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 54250.443350 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 54155.546860 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 54228.610407 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 54258.125248 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 54218.389662 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 54228.470959 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 54193.404635 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 54276.419558 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 54246.991460 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 54250.443350 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 54155.546860 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 54228.610407 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 54258.125248 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 54218.389662 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 54228.470959 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 6449 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 728.440089 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 6.082080 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 6.684894 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 6.012810 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 6.146479 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.898409 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 6.253161 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 6.667903 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 6.086501 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.711367 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.005940 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.006528 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.005872 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.006002 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.006737 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.006107 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.006512 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.005944 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.761008 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 355 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 425 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 1945494 # Number of tag accesses +system.l2c.tags.data_accesses 1945494 # Number of data accesses +system.l2c.ReadReq_hits::cpu0 10666 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10663 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10584 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10758 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 10608 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10611 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10587 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 10524 # number of ReadReq hits +system.l2c.ReadReq_hits::total 85001 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 74943 # number of Writeback hits +system.l2c.Writeback_hits::total 74943 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 353 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 387 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 371 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 333 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 313 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 347 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 354 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 353 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2811 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1863 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1918 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1925 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 2036 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1873 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1894 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1840 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1970 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 15319 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12529 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12581 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12509 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12794 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12481 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12505 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12427 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12494 # number of demand (read+write) hits +system.l2c.demand_hits::total 100320 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12529 # number of overall hits +system.l2c.overall_hits::cpu1 12581 # number of overall hits +system.l2c.overall_hits::cpu2 12509 # number of overall hits +system.l2c.overall_hits::cpu3 12794 # number of overall hits +system.l2c.overall_hits::cpu4 12481 # number of overall hits +system.l2c.overall_hits::cpu5 12505 # number of overall hits +system.l2c.overall_hits::cpu6 12427 # number of overall hits +system.l2c.overall_hits::cpu7 12494 # number of overall hits +system.l2c.overall_hits::total 100320 # number of overall hits +system.l2c.ReadReq_misses::cpu0 689 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 724 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 665 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 684 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 722 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 677 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 706 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 668 # number of ReadReq misses +system.l2c.ReadReq_misses::total 5535 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1935 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1877 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1961 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1907 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1994 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1930 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1982 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1923 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15509 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4321 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4396 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4310 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4356 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4311 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4311 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4402 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4337 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 34744 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5010 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5120 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 4975 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5040 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5033 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 4988 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5108 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5005 # number of demand (read+write) misses +system.l2c.demand_misses::total 40279 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5010 # number of overall misses +system.l2c.overall_misses::cpu1 5120 # number of overall misses +system.l2c.overall_misses::cpu2 4975 # number of overall misses +system.l2c.overall_misses::cpu3 5040 # number of overall misses +system.l2c.overall_misses::cpu4 5033 # number of overall misses +system.l2c.overall_misses::cpu5 4988 # number of overall misses +system.l2c.overall_misses::cpu6 5108 # number of overall misses +system.l2c.overall_misses::cpu7 5005 # number of overall misses +system.l2c.overall_misses::total 40279 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 40501462 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 42600959 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 38646963 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 40375453 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 42613457 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 39385955 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 41558456 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 39362459 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 325045164 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 54709000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 52877000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 54939000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 53407500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 55477000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 54482500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 56188000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 56111500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 438191500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 230273476 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 234927475 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 230453472 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 232391973 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 230081970 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 230389480 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 234880982 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 230954980 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1854353808 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 270774938 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 277528434 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 269100435 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 272767426 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 272695427 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 269775435 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 276439438 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 270317439 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2179398972 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 270774938 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 277528434 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 269100435 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 272767426 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 272695427 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 269775435 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 276439438 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 270317439 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2179398972 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11355 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11387 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11249 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11442 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11330 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11288 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11293 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11192 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 90536 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 74943 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 74943 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2288 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2264 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2332 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2240 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2307 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2277 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2336 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2276 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18320 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6184 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6314 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6235 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6392 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6184 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6205 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6242 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6307 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50063 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17539 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17701 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17484 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17834 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17514 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17493 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17535 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17499 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 140599 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17539 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17701 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17484 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17834 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17514 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17493 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17535 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17499 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 140599 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.060678 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.063581 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.059116 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.059780 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.063725 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.059975 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.062517 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.059685 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.061136 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.845717 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.829064 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.840909 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.851339 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.864326 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.847606 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.848459 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.844903 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.846561 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.698739 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.696231 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.691259 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.681477 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.697122 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.694762 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.705223 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.687649 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.694006 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.285649 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.289249 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.284546 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.282606 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.287370 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.285143 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.291303 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.286016 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.286481 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.285649 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.289249 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.284546 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.282606 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.287370 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.285143 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.291303 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.286016 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.286481 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 58782.963716 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 58841.103591 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 58115.733835 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 59028.440058 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 59021.408587 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 58177.186115 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 58864.668555 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 58925.836826 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 58725.413550 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 28273.385013 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 28171.017581 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 28015.808261 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 28006.030414 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 27821.965898 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 28229.274611 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 28349.142281 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 29179.147166 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 28254.013798 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 53291.709327 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 53441.190855 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 53469.483063 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 53349.856061 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 53370.904662 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 53442.236140 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 53357.787824 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 53252.243486 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53371.914805 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 54046.893812 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 54204.772266 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 54090.539698 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 54120.521032 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 54181.487582 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 54084.890738 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 54118.918951 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 54009.478322 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 54107.573972 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 54046.893812 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 54204.772266 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 54090.539698 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 54120.521032 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 54181.487582 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 54084.890738 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 54118.918951 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 54009.478322 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 54107.573972 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 6195 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 908 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 845 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.102423 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 7.331361 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6534 # number of writebacks -system.l2c.writebacks::total 6534 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 2 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 5996 # number of writebacks +system.l2c.writebacks::total 5996 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 4 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu6 3 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu7 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 23 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu1 2 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 1 # number of ReadExReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 30 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 1 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 1 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu6 1 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu7 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 8 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 2 # number of demand (read+write) MSHR hits +system.l2c.ReadExReq_mshr_hits::total 6 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 4 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu4 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 5 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu6 4 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu7 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 31 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 2 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 36 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 4 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu4 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 5 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu6 4 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu7 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 31 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 742 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 739 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 778 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 726 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 727 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 751 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 744 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 716 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 5923 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1905 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1883 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1879 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1904 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1913 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1875 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1933 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1894 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15186 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4301 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4329 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4369 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4347 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4381 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4378 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4298 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4309 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 34712 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5043 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5068 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5147 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5073 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5108 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5129 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5042 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5025 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40635 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5043 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5068 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5147 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5073 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5108 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5129 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5042 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5025 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40635 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 34436500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 34879500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 36206000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 34201000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 34228500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 34696500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 34883500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 33321000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 276852500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 77532500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 76774000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 76435500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 77640000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 77802000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 76297000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 78806000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 77127500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 618414500 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 177611500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 178666500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 180593500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 179431000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 180375000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 181189000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 177424500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 178121500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1433412500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 212048000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 213546000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 216799500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 213632000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 214603500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 215885500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 212308000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 211442500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1710265000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 212048000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 213546000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 216799500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 213632000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 214603500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 215885500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 212308000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 211442500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1710265000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 408522500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 408718000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 409944000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 402597000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 406388000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 405037500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 409992000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 408869000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3260068000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 227084000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 222076000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 221597500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 223921500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 226980000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 223544500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 219891000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 221144500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1786239000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 635606500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 630794000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 631541500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 626518500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 633368000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 628582000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 629883000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 630013500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5046307000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.064382 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.064044 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.067005 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.063010 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.063372 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.064982 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.065109 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.061570 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.064184 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.852349 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.849346 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.832152 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.839506 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.842731 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.838176 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.859111 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.839167 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.844042 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.699122 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.698226 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.703429 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.700564 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.702083 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.698134 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.694009 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.702249 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.699726 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.285286 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.285698 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.288800 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.286174 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.288392 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.287694 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.286152 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.282860 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.286384 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.285286 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.285698 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.288800 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.286174 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.288392 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.287694 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.286152 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.282860 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.286384 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 46410.377358 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 47198.240866 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 46537.275064 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 47108.815427 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 47081.843191 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 46200.399467 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 46886.424731 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 46537.709497 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 46741.938207 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40699.475066 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40772.172066 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40678.818520 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40777.310924 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40670.151594 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40691.733333 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40768.753233 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40722.016895 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40722.672198 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41295.396419 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41272.002772 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41335.202564 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41276.972625 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41172.106825 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41386.249429 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41280.711959 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41337.085171 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41294.437082 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 42047.987309 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 42136.148382 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 42121.527103 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 42111.571062 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 42013.214565 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 42091.148372 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 42107.893693 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 42078.109453 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42088.470530 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 42047.987309 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 42136.148382 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 42121.527103 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 42111.571062 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 42013.214565 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 42091.148372 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 42107.893693 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 42078.109453 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42088.470530 # average overall mshr miss latency +system.l2c.overall_mshr_hits::total 36 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 684 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 719 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 663 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 680 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 719 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 673 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 703 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 664 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5505 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1935 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1877 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1961 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1907 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1994 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1930 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1982 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1922 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15508 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4319 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4396 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4309 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4356 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4311 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4310 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4401 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4336 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 34738 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5003 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5115 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 4972 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5036 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5030 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 4983 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5104 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5000 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40243 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5003 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5115 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 4972 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5036 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5030 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 4983 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5104 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5000 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40243 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 32025962 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 33726459 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 30538463 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 31944953 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 33774957 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 31159456 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 32933456 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 31147460 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 257251166 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 78877000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 76396500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 79743000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 77708000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 81134500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 78512000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 80594000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 78369500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 631334500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 177684976 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 181467975 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 178041472 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 179439473 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 177646470 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 177921480 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 181358982 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 178204480 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1431765308 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 209710938 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 215194434 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 208579935 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 211384426 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 211421427 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 209080936 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 214292438 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 209351940 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1689016474 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 209710938 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 215194434 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 208579935 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 211384426 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 211421427 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 209080936 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 214292438 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 209351940 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1689016474 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 409314490 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 398776491 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 396170985 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 396900494 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 410851489 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 396740988 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 397751989 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 402422989 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3208929915 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 221607995 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 223708999 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 220357996 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 224036997 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 228210498 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 226077994 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 220622999 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 228291489 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1792914967 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 630922485 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 622485490 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 616528981 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 620937491 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 639061987 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 622818982 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 618374988 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 630714478 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5001844882 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.060238 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.063142 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.058939 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.059430 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.063460 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.059621 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.062251 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.059328 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.060805 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.845717 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.829064 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.840909 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.851339 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.864326 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.847606 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.848459 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.844464 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.846507 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.698415 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.696231 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.691099 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.681477 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.697122 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.694601 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.705062 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.687490 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.693886 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.285250 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.288967 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.284374 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.282382 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.287199 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.284857 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.291075 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.285731 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.286225 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.285250 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.288967 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.284374 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.282382 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.287199 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.284857 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.291075 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.285731 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.286225 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 46821.581871 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 46907.453408 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 46061.030166 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 46977.872059 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 46974.905424 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 46299.340267 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 46847.021337 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 46908.825301 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 46730.457039 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40763.307494 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40701.385189 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40664.456910 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40748.820136 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40689.317954 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40679.792746 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40662.966700 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40774.973985 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40710.246324 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41140.304700 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41280.249090 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41318.512880 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41193.634757 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41207.717467 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41281.085847 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41208.584867 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41098.819188 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41216.112269 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 41917.037378 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 42071.248094 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 41950.912108 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 41974.667593 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 42032.092843 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 41958.847281 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 41985.195533 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 41870.388000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 41970.441418 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 41917.037378 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 42071.248094 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 41950.912108 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 41974.667593 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 42032.092843 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 41958.847281 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 41985.195533 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 41870.388000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 41970.441418 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -701,194 +697,189 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.funcbus.throughput 0 # Throughput (bytes/s) -system.funcbus.data_through_bus 0 # Total data (bytes) -system.toL2Bus.snoop_filter.tot_requests 548567 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 252509 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 294010 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 556652 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 259205 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 295399 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.throughput 22759385654 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 368934 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 368931 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 42843 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 42841 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 74514 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 28540 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28540 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 155707 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 155704 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 118962 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 119173 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 119464 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 119154 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 118978 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 119360 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 119013 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 118881 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 952985 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1734762 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1749843 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1754305 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1751569 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1739334 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1759819 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1742411 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1740191 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 13972234 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 13972234 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 19393344 # Total snoop data (bytes) -system.toL2Bus.snoops_through_bus 313569 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 548567 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.700997 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.184770 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 369106 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 369100 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43299 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43298 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 74943 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29164 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29164 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 161428 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 161427 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120001 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 119693 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 119622 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120026 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120574 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 119580 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 119572 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 119681 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 958749 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1736824 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1745103 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1743099 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1764010 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1727854 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1727156 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1741472 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1730998 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 13916516 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 322180 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 556652 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.686233 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.173674 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 51420 9.37% 9.37% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 243442 44.38% 53.75% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 138727 25.29% 79.04% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 68606 12.51% 91.55% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 30441 5.55% 97.10% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 11622 2.12% 99.21% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 3640 0.66% 99.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 669 0.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 52178 9.37% 9.37% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 250105 44.93% 54.30% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 140101 25.17% 79.47% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 69083 12.41% 91.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 29746 5.34% 97.23% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 11224 2.02% 99.24% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 3520 0.63% 99.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 695 0.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 548567 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1466016000 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 100.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 156116317 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 10.6 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 156768205 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 556652 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1484170768 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 99.8 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 158821901 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 10.7 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 158474081 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 10.7 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 156913339 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 158663989 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 10.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 156965244 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 158858134 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 10.7 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 156103724 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 10.6 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 156986709 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 159553082 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 10.7 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 158926155 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 10.7 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 156696078 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 158642094 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 10.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 156271715 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 10.7 # Layer utilization (%) -system.cpu0.num_reads 99418 # number of read accesses completed -system.cpu0.num_writes 53245 # number of write accesses completed +system.toL2Bus.respLayer7.occupancy 158326604 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 10.6 # Layer utilization (%) +system.cpu0.num_reads 99884 # number of read accesses completed +system.cpu0.num_writes 54722 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.tags.replacements 22099 # number of replacements -system.cpu0.l1c.tags.tagsinuse 397.065512 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13209 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22488 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.587380 # Average number of references to valid blocks. +system.cpu0.l1c.tags.replacements 22159 # number of replacements +system.cpu0.l1c.tags.tagsinuse 396.508288 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13572 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22560 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.601596 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 397.065512 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.775519 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.775519 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 259 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 330123 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 330123 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8700 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8700 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1042 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1042 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9742 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9742 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9742 # number of overall hits -system.cpu0.l1c.overall_hits::total 9742 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 35979 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 35979 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 22956 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 22956 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 58935 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 58935 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 58935 # number of overall misses -system.cpu0.l1c.overall_misses::total 58935 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 2431275055 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 2431275055 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 1798190271 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 1798190271 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 4229465326 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 4229465326 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 4229465326 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 4229465326 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44679 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44679 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 23998 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 23998 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 68677 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 68677 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 68677 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 68677 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805278 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.805278 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956580 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.956580 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.858148 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.858148 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.858148 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.858148 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 67574.836849 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 67574.836849 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 78332.038291 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 78332.038291 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 71764.916026 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 71764.916026 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 71764.916026 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 71764.916026 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 2152877 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 396.508288 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.774430 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.774430 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 266 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 336605 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 336605 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8851 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8851 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1088 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1088 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9939 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9939 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9939 # number of overall hits +system.cpu0.l1c.overall_hits::total 9939 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36351 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36351 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23761 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23761 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60112 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60112 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60112 # number of overall misses +system.cpu0.l1c.overall_misses::total 60112 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 2463515507 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 2463515507 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 1861288603 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 1861288603 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 4324804110 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 4324804110 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 4324804110 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 4324804110 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45202 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45202 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24849 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24849 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70051 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70051 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70051 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70051 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.804190 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.804190 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956216 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.956216 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.858118 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.858118 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.858118 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.858118 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 67770.226596 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 67770.226596 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 78333.765540 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 78333.765540 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 71945.769730 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 71945.769730 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 71945.769730 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 71945.769730 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 2211784 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 58943 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 60234 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 36.524727 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 36.719859 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9551 # number of writebacks -system.cpu0.l1c.writebacks::total 9551 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35979 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 35979 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 22956 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 22956 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 58935 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 58935 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 58935 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 58935 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 2355407447 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 2355407447 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1750135961 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1750135961 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 4105543408 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 4105543408 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 4105543408 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 4105543408 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 1091154570 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 1091154570 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 4041529643 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 4041529643 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 5132684213 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 5132684213 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805278 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805278 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956580 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956580 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858148 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.858148 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858148 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.858148 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 65466.173240 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 65466.173240 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 76238.715848 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 76238.715848 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 69662.228014 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 69662.228014 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 69662.228014 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 69662.228014 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9764 # number of writebacks +system.cpu0.l1c.writebacks::total 9764 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36351 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36351 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23761 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23761 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60112 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60112 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60112 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60112 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 2386706389 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 2386706389 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1811452635 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1811452635 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 4198159024 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 4198159024 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 4198159024 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 4198159024 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 1102233368 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 1102233368 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 3973496829 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 3973496829 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 5075730197 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 5075730197 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.804190 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.804190 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956216 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956216 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858118 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.858118 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858118 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.858118 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 65657.241589 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 65657.241589 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 76236.380413 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 76236.380413 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 69838.951025 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 69838.951025 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 69838.951025 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 69838.951025 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -896,120 +887,120 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99768 # number of read accesses completed -system.cpu1.num_writes 53422 # number of write accesses completed +system.cpu1.num_reads 99113 # number of read accesses completed +system.cpu1.num_writes 54702 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.tags.replacements 22481 # number of replacements -system.cpu1.l1c.tags.tagsinuse 398.933743 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13300 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22873 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.581472 # Average number of references to valid blocks. +system.cpu1.l1c.tags.replacements 22065 # number of replacements +system.cpu1.l1c.tags.tagsinuse 395.289903 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13538 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22464 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.602653 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 398.933743 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.779167 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.779167 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 392 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 265 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 331866 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 331866 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8705 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8705 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1116 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1116 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9821 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9821 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9821 # number of overall hits -system.cpu1.l1c.overall_hits::total 9821 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36262 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36262 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 22965 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 22965 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 59227 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 59227 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 59227 # number of overall misses -system.cpu1.l1c.overall_misses::total 59227 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 2445520804 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 2445520804 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 1800113040 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 1800113040 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 4245633844 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 4245633844 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 4245633844 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 4245633844 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 44967 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 44967 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24081 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24081 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 69048 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 69048 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 69048 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 69048 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.806414 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.806414 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953656 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.953656 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.857766 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.857766 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.857766 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.857766 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 67440.317798 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 67440.317798 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 78385.065970 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 78385.065970 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 71684.094146 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 71684.094146 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 71684.094146 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 71684.094146 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 2169051 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 395.289903 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.772051 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.772051 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 336364 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 336364 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8820 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8820 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1137 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1137 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9957 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9957 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9957 # number of overall hits +system.cpu1.l1c.overall_hits::total 9957 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36159 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36159 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23877 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23877 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60036 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60036 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60036 # number of overall misses +system.cpu1.l1c.overall_misses::total 60036 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 2464134844 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 2464134844 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 1871949720 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 1871949720 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 4336084564 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 4336084564 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 4336084564 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 4336084564 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 44979 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 44979 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 25014 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 25014 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 69993 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 69993 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 69993 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 69993 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.803908 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.803908 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954545 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954545 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.857743 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.857743 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.857743 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.857743 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 68147.206615 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 68147.206615 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 78399.703480 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 78399.703480 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 72224.741222 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 72224.741222 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 72224.741222 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 72224.741222 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 2199257 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 59314 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 59892 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 36.568955 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 36.720380 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9774 # number of writebacks -system.cpu1.l1c.writebacks::total 9774 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36262 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36262 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22965 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 22965 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 59227 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 59227 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 59227 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 59227 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 2368901584 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 2368901584 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1752103572 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1752103572 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 4121005156 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 4121005156 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 4121005156 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 4121005156 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1095385986 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1095385986 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 3917382799 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 3917382799 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 5012768785 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 5012768785 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.806414 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.806414 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953656 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953656 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857766 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.857766 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857766 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.857766 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 65327.383597 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 65327.383597 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 76294.516525 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 76294.516525 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 69579.839533 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 69579.839533 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 69579.839533 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 69579.839533 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9710 # number of writebacks +system.cpu1.l1c.writebacks::total 9710 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36159 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36159 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23877 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23877 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60036 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60036 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60036 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60036 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 2387770588 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 2387770588 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1821987516 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1821987516 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 4209758104 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 4209758104 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 4209758104 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 4209758104 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1078285196 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1078285196 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 4031598145 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 4031598145 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 5109883341 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 5109883341 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.803908 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.803908 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954545 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954545 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857743 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.857743 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857743 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.857743 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 66035.304848 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 66035.304848 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 76307.221008 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 76307.221008 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 70120.562729 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 70120.562729 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 70120.562729 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 70120.562729 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -1017,120 +1008,120 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 100000 # number of read accesses completed -system.cpu2.num_writes 53603 # number of write accesses completed +system.cpu2.num_reads 98176 # number of read accesses completed +system.cpu2.num_writes 54646 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.tags.replacements 22539 # number of replacements -system.cpu2.l1c.tags.tagsinuse 397.267456 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13362 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22949 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.582248 # Average number of references to valid blocks. +system.cpu2.l1c.tags.replacements 22558 # number of replacements +system.cpu2.l1c.tags.tagsinuse 395.943086 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13415 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22958 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.584328 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 397.267456 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.775913 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.775913 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 285 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 332293 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 332293 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8761 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8761 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1062 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1062 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9823 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9823 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9823 # number of overall hits -system.cpu2.l1c.overall_hits::total 9823 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36321 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36321 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 22996 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 22996 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 59317 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 59317 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 59317 # number of overall misses -system.cpu2.l1c.overall_misses::total 59317 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 2442264018 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 2442264018 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 1799405026 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 1799405026 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 4241669044 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 4241669044 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 4241669044 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 4241669044 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45082 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45082 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 24058 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 24058 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 69140 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 69140 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 69140 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 69140 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805665 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.805665 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955857 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.955857 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.857926 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.857926 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.857926 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.857926 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 67241.100686 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 67241.100686 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 78248.609584 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 78248.609584 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 71508.489033 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 71508.489033 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 71508.489033 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 71508.489033 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 2171204 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 395.943086 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.773326 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.773326 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 274 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 336254 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 336254 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8574 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8574 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1152 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1152 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9726 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9726 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9726 # number of overall hits +system.cpu2.l1c.overall_hits::total 9726 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36359 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36359 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23860 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23860 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60219 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60219 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60219 # number of overall misses +system.cpu2.l1c.overall_misses::total 60219 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 2471651596 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 2471651596 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 1874289110 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 1874289110 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 4345940706 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 4345940706 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 4345940706 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 4345940706 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44933 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44933 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25012 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25012 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 69945 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 69945 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 69945 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 69945 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.809183 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.809183 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953942 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.953942 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.860948 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.860948 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.860948 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.860948 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 67979.086223 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 67979.086223 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 78553.608969 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 78553.608969 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 72168.928511 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 72168.928511 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 72168.928511 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 72168.928511 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 2198300 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 59435 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 59965 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 36.530731 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 36.659718 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9704 # number of writebacks -system.cpu2.l1c.writebacks::total 9704 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36321 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36321 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22996 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 22996 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 59317 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 59317 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 59317 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 59317 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 2365672458 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 2365672458 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1751310602 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1751310602 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 4116983060 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 4116983060 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 4116983060 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 4116983060 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1097675449 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1097675449 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 3894001300 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 3894001300 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 4991676749 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 4991676749 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805665 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805665 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955857 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955857 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.857926 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.857926 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.857926 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.857926 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 65132.360287 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 65132.360287 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 76157.183945 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 76157.183945 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 69406.461217 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 69406.461217 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 69406.461217 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 69406.461217 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9891 # number of writebacks +system.cpu2.l1c.writebacks::total 9891 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36359 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36359 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23860 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23860 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60219 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60219 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60219 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60219 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 2394908316 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 2394908316 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1824229170 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1824229170 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 4219137486 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 4219137486 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 4219137486 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 4219137486 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1069659636 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1069659636 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 3964277301 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 3964277301 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 5033936937 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 5033936937 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.809183 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.809183 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953942 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953942 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.860948 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.860948 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.860948 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.860948 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 65868.376908 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 65868.376908 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 76455.539396 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 76455.539396 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 70063.227320 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 70063.227320 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 70063.227320 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 70063.227320 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -1138,120 +1129,120 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99664 # number of read accesses completed -system.cpu3.num_writes 53618 # number of write accesses completed +system.cpu3.num_reads 98913 # number of read accesses completed +system.cpu3.num_writes 55212 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.tags.replacements 22539 # number of replacements -system.cpu3.l1c.tags.tagsinuse 397.521626 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13272 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22952 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.578250 # Average number of references to valid blocks. +system.cpu3.l1c.tags.replacements 22225 # number of replacements +system.cpu3.l1c.tags.tagsinuse 393.873430 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13306 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22621 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.588214 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 397.521626 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.776409 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.776409 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 413 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 263 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.806641 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 332331 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 332331 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8701 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8701 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1040 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1040 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9741 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9741 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9741 # number of overall hits -system.cpu3.l1c.overall_hits::total 9741 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36310 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36310 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23079 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23079 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 59389 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 59389 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 59389 # number of overall misses -system.cpu3.l1c.overall_misses::total 59389 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 2444229866 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 2444229866 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 1811981579 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 1811981579 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 4256211445 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 4256211445 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 4256211445 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 4256211445 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45011 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45011 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24119 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24119 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 69130 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 69130 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 69130 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 69130 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.806692 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.806692 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.956880 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.956880 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.859092 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.859092 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.859092 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.859092 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 67315.611842 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 67315.611842 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 78512.135664 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 78512.135664 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 71666.662934 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 71666.662934 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 71666.662934 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 71666.662934 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 2167444 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 393.873430 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.769284 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.769284 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 274 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 336364 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 336364 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8580 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8580 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1197 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1197 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9777 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9777 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9777 # number of overall hits +system.cpu3.l1c.overall_hits::total 9777 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36212 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36212 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23956 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23956 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60168 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60168 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60168 # number of overall misses +system.cpu3.l1c.overall_misses::total 60168 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 2456007015 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 2456007015 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 1878963119 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 1878963119 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 4334970134 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 4334970134 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 4334970134 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 4334970134 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 44792 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 44792 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25153 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25153 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 69945 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 69945 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 69945 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 69945 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.808448 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.808448 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.952411 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.952411 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.860219 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.860219 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.860219 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.860219 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 67823.014885 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 67823.014885 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 78433.925488 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 78433.925488 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 72047.768482 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 72047.768482 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 72047.768482 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 72047.768482 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 2191987 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 59346 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 59750 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 36.522158 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 36.685975 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9755 # number of writebacks -system.cpu3.l1c.writebacks::total 9755 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36310 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36310 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23079 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23079 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 59389 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 59389 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 59389 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 59389 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 2367603538 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 2367603538 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1763687167 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1763687167 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 4131290705 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 4131290705 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 4131290705 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 4131290705 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 1080268673 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 1080268673 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 3893349735 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 3893349735 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 4973618408 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 4973618408 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.806692 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.806692 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.956880 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.956880 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859092 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.859092 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859092 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.859092 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 65205.275076 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 65205.275076 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 76419.566142 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 76419.566142 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 69563.230649 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 69563.230649 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 69563.230649 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 69563.230649 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9841 # number of writebacks +system.cpu3.l1c.writebacks::total 9841 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36212 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36212 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23956 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23956 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60168 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60168 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60168 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60168 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 2379648497 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 2379648497 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1828763107 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1828763107 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 4208411604 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 4208411604 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 4208411604 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 4208411604 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 1072329681 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 1072329681 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 3992913639 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 3992913639 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 5065243320 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 5065243320 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808448 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808448 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.952411 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.952411 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860219 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.860219 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860219 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.860219 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 65714.362559 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 65714.362559 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 76338.416555 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 76338.416555 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 69944.349222 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 69944.349222 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 69944.349222 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 69944.349222 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -1259,120 +1250,120 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99015 # number of read accesses completed -system.cpu4.num_writes 53820 # number of write accesses completed +system.cpu4.num_reads 100000 # number of read accesses completed +system.cpu4.num_writes 54692 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.tags.replacements 22084 # number of replacements -system.cpu4.l1c.tags.tagsinuse 396.195798 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13300 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22488 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.591427 # Average number of references to valid blocks. +system.cpu4.l1c.tags.replacements 22289 # number of replacements +system.cpu4.l1c.tags.tagsinuse 395.541537 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13462 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22679 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.593589 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 396.195798 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.773820 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.773820 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 265 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 330427 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 330427 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8669 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8669 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1045 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1045 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9714 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9714 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9714 # number of overall hits -system.cpu4.l1c.overall_hits::total 9714 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 35948 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 35948 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23093 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23093 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 59041 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 59041 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 59041 # number of overall misses -system.cpu4.l1c.overall_misses::total 59041 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 2417278257 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 2417278257 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 1822150466 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 1822150466 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 4239428723 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 4239428723 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 4239428723 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 4239428723 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 44617 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 44617 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24138 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24138 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 68755 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 68755 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 68755 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 68755 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805702 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.805702 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.956707 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.956707 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.858716 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.858716 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.858716 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.858716 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 67243.748108 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 67243.748108 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 78904.883125 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 78904.883125 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 71804.825850 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 71804.825850 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 71804.825850 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 71804.825850 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 2163506 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 395.541537 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.772542 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.772542 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 390 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 278 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 112 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 337633 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 337633 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8739 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8739 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1176 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1176 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9915 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9915 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9915 # number of overall hits +system.cpu4.l1c.overall_hits::total 9915 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36692 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36692 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23629 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23629 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60321 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60321 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60321 # number of overall misses +system.cpu4.l1c.overall_misses::total 60321 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 2465146363 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 2465146363 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 1837411479 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 1837411479 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 4302557842 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 4302557842 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 4302557842 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 4302557842 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45431 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45431 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24805 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24805 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70236 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70236 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70236 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70236 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807642 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.807642 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952590 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.952590 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.858833 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.858833 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.858833 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.858833 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 67184.845825 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 67184.845825 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 77760.864996 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 77760.864996 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 71327.694203 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 71327.694203 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 71327.694203 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 71327.694203 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 2196199 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 58921 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 60342 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 36.718759 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 36.395860 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9586 # number of writebacks -system.cpu4.l1c.writebacks::total 9586 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35948 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 35948 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23093 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23093 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 59041 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 59041 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 59041 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 59041 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 2341432849 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 2341432849 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1773798174 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1773798174 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 4115231023 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 4115231023 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 4115231023 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 4115231023 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 1089200967 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 1089200967 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 3986639198 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 3986639198 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 5075840165 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 5075840165 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805702 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805702 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.956707 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.956707 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858716 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.858716 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858716 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.858716 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 65133.883637 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 65133.883637 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 76811.075824 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 76811.075824 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 69701.241900 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 69701.241900 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 69701.241900 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 69701.241900 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9615 # number of writebacks +system.cpu4.l1c.writebacks::total 9615 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36692 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36692 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23629 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23629 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60321 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60321 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60321 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60321 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 2387693175 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 2387693175 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1788001185 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1788001185 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 4175694360 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 4175694360 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 4175694360 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 4175694360 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 1103066428 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 1103066428 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 4057809634 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 4057809634 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 5160876062 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 5160876062 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807642 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807642 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952590 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952590 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858833 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.858833 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858833 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.858833 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 65073.944593 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 65073.944593 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 75669.778027 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 75669.778027 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 69224.554633 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 69224.554633 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 69224.554633 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 69224.554633 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -1380,120 +1371,120 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99463 # number of read accesses completed -system.cpu5.num_writes 53761 # number of write accesses completed +system.cpu5.num_reads 98940 # number of read accesses completed +system.cpu5.num_writes 55179 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.tags.replacements 22236 # number of replacements -system.cpu5.l1c.tags.tagsinuse 396.818591 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13326 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22643 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.588526 # Average number of references to valid blocks. +system.cpu5.l1c.tags.replacements 22195 # number of replacements +system.cpu5.l1c.tags.tagsinuse 395.048373 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13447 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22597 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.595079 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 396.818591 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.775036 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.775036 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 407 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_blocks::cpu5 395.048373 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.771579 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.771579 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id system.cpu5.l1c.tags.age_task_id_blocks_1024::0 275 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 332464 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 332464 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8698 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8698 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1095 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1095 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9793 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9793 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9793 # number of overall hits -system.cpu5.l1c.overall_hits::total 9793 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36190 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36190 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23188 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23188 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 59378 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 59378 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 59378 # number of overall misses -system.cpu5.l1c.overall_misses::total 59378 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 2440787473 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 2440787473 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 1818333892 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 1818333892 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 4259121365 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 4259121365 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 4259121365 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 4259121365 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44888 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44888 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24283 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24283 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 69171 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 69171 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 69171 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 69171 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806229 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.806229 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954907 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.954907 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.858423 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.858423 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.858423 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.858423 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 67443.699171 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 67443.699171 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 78417.021390 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 78417.021390 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 71728.946159 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 71728.946159 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 71728.946159 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 71728.946159 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 2173855 # number of cycles access was blocked +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 337000 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 337000 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8717 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8717 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1138 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1138 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9855 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9855 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9855 # number of overall hits +system.cpu5.l1c.overall_hits::total 9855 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36402 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36402 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23842 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23842 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60244 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60244 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60244 # number of overall misses +system.cpu5.l1c.overall_misses::total 60244 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 2469941136 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 2469941136 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 1867542812 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 1867542812 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 4337483948 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 4337483948 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 4337483948 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 4337483948 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45119 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45119 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24980 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24980 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70099 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70099 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70099 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70099 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806800 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.806800 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954444 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.954444 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.859413 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.859413 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.859413 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.859413 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 67851.797594 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 67851.797594 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 78329.956044 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 78329.956044 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 71998.604807 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 71998.604807 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 71998.604807 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 71998.604807 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 2193553 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 59485 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 59918 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 36.544591 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 36.609249 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9794 # number of writebacks -system.cpu5.l1c.writebacks::total 9794 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36190 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36190 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23188 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23188 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 59378 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 59378 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 59378 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 59378 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 2364411063 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 2364411063 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1769767596 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1769767596 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 4134178659 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 4134178659 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 4134178659 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 4134178659 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 1083354468 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 1083354468 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 3885222198 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 3885222198 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 4968576666 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 4968576666 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806229 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806229 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954907 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954907 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858423 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.858423 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858423 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.858423 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 65333.270600 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 65333.270600 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 76322.563222 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 76322.563222 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 69624.754269 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 69624.754269 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 69624.754269 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 69624.754269 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9638 # number of writebacks +system.cpu5.l1c.writebacks::total 9638 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36402 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36402 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23842 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23842 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60244 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60244 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60244 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60244 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 2393170720 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 2393170720 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1817634658 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1817634658 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 4210805378 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 4210805378 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 4210805378 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 4210805378 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 1069731206 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 1069731206 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 4068656749 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 4068656749 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 5138387955 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 5138387955 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806800 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806800 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954444 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954444 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859413 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.859413 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859413 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.859413 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 65742.836108 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 65742.836108 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 76236.668820 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 76236.668820 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 69895.846524 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 69895.846524 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 69895.846524 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 69895.846524 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -1501,120 +1492,120 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99150 # number of read accesses completed -system.cpu6.num_writes 53258 # number of write accesses completed +system.cpu6.num_reads 98989 # number of read accesses completed +system.cpu6.num_writes 55088 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.tags.replacements 22399 # number of replacements -system.cpu6.l1c.tags.tagsinuse 397.638402 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13152 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22779 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.577374 # Average number of references to valid blocks. +system.cpu6.l1c.tags.replacements 22403 # number of replacements +system.cpu6.l1c.tags.tagsinuse 396.761014 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13429 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22803 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.588914 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 397.638402 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.776638 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.776638 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 246 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.742188 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 330920 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 330920 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8542 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8542 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1117 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1117 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9659 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9659 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9659 # number of overall hits -system.cpu6.l1c.overall_hits::total 9659 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36110 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36110 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23056 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23056 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 59166 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 59166 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 59166 # number of overall misses -system.cpu6.l1c.overall_misses::total 59166 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 2440095733 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 2440095733 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 1804973992 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 1804973992 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 4245069725 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 4245069725 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 4245069725 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 4245069725 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 44652 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 44652 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24173 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24173 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 68825 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 68825 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 68825 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 68825 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808698 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.808698 # miss rate for ReadReq accesses +system.cpu6.l1c.tags.occ_blocks::cpu6 396.761014 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.774924 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.774924 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 257 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 336438 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 336438 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8710 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8710 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1155 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1155 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9865 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9865 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9865 # number of overall hits +system.cpu6.l1c.overall_hits::total 9865 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36281 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36281 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23840 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23840 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60121 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60121 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60121 # number of overall misses +system.cpu6.l1c.overall_misses::total 60121 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 2471222602 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 2471222602 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 1877806304 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 1877806304 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 4349028906 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 4349028906 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 4349028906 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 4349028906 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 44991 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 44991 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24995 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24995 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 69986 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 69986 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 69986 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 69986 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806406 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.806406 # miss rate for ReadReq accesses system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953791 # miss rate for WriteReq accesses system.cpu6.l1c.WriteReq_miss_rate::total 0.953791 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.859659 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.859659 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.859659 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.859659 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 67573.961036 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 67573.961036 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 78286.519431 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 78286.519431 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 71748.465757 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 71748.465757 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 71748.465757 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 71748.465757 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 2172077 # number of cycles access was blocked +system.cpu6.l1c.demand_miss_rate::cpu6 0.859043 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.859043 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.859043 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.859043 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 68113.409278 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 68113.409278 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 78767.042953 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 78767.042953 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 72337.933601 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 72337.933601 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 72337.933601 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 72337.933601 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 2205749 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 59435 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 59981 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 36.545419 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 36.774128 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9755 # number of writebacks -system.cpu6.l1c.writebacks::total 9755 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36110 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36110 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23056 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23056 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 59166 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 59166 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 59166 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 59166 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 2363759609 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 2363759609 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1756697682 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1756697682 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 4120457291 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 4120457291 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 4120457291 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 4120457291 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 1098306924 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 1098306924 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 3880453768 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 3880453768 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 4978760692 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 4978760692 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808698 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808698 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.writebacks::writebacks 9866 # number of writebacks +system.cpu6.l1c.writebacks::total 9866 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36281 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36281 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23840 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23840 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60121 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60121 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60121 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60121 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 2394594434 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 2394594434 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1827956004 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1827956004 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 4222550438 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 4222550438 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 4222550438 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 4222550438 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 1072935197 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 1072935197 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 3927350232 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 3927350232 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 5000285429 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 5000285429 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806406 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806406 # mshr miss rate for ReadReq accesses system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953791 # mshr miss rate for WriteReq accesses system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953791 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859659 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.859659 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859659 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.859659 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 65459.972556 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 65459.972556 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 76192.647554 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 76192.647554 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 69642.316381 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 69642.316381 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 69642.316381 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 69642.316381 # average overall mshr miss latency +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859043 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.859043 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859043 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.859043 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 66001.334969 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 66001.334969 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 76676.006879 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 76676.006879 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 70234.201660 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 70234.201660 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 70234.201660 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 70234.201660 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -1622,120 +1613,120 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99292 # number of read accesses completed -system.cpu7.num_writes 53734 # number of write accesses completed +system.cpu7.num_reads 98627 # number of read accesses completed +system.cpu7.num_writes 54842 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.tags.replacements 22176 # number of replacements -system.cpu7.l1c.tags.tagsinuse 397.484138 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13353 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22564 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.591783 # Average number of references to valid blocks. +system.cpu7.l1c.tags.replacements 22131 # number of replacements +system.cpu7.l1c.tags.tagsinuse 396.248772 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13292 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22531 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.589943 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 397.484138 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.776336 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.776336 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_blocks::cpu7 396.248772 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.773923 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.773923 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 273 # Occupied blocks per task id system.cpu7.l1c.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 330932 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 330932 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8693 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8693 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1154 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1154 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9847 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9847 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9847 # number of overall hits -system.cpu7.l1c.overall_hits::total 9847 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36097 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36097 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 22922 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 22922 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 59019 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 59019 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 59019 # number of overall misses -system.cpu7.l1c.overall_misses::total 59019 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 2444006416 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 2444006416 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 1801319117 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 1801319117 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 4245325533 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 4245325533 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 4245325533 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 4245325533 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44790 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44790 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24076 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24076 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 68866 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 68866 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 68866 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 68866 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805916 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.805916 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.952068 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.952068 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.857012 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.857012 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.857012 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.857012 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 67706.635344 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 67706.635344 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 78584.727205 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 78584.727205 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 71931.505668 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 71931.505668 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 71931.505668 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 71931.505668 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 2180293 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 334904 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 334904 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8595 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8595 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1159 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1159 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9754 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9754 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9754 # number of overall hits +system.cpu7.l1c.overall_hits::total 9754 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36066 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36066 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23832 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23832 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 59898 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 59898 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 59898 # number of overall misses +system.cpu7.l1c.overall_misses::total 59898 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 2444451917 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 2444451917 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 1868936724 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 1868936724 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 4313388641 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 4313388641 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 4313388641 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 4313388641 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 44661 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 44661 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24991 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24991 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 69652 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 69652 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 69652 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 69652 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807550 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.807550 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953623 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953623 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.859961 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.859961 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.859961 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.859961 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 67777.183968 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 67777.183968 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 78421.312689 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 78421.312689 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 72012.231477 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 72012.231477 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 72012.231477 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 72012.231477 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 2189961 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 59208 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 59729 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 36.824297 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 36.664953 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9569 # number of writebacks -system.cpu7.l1c.writebacks::total 9569 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36097 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36097 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 22922 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 22922 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 59019 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 59019 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 59019 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 59019 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 2367752098 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 2367752098 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1753332745 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1753332745 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 4121084843 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 4121084843 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 4121084843 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 4121084843 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 1099641500 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 1099641500 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 3936158285 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 3936158285 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 5035799785 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 5035799785 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805916 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805916 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.952068 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.952068 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857012 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.857012 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857012 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.857012 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 65594.151813 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 65594.151813 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 76491.263633 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 76491.263633 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 69826.409173 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 69826.409173 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 69826.409173 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 69826.409173 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9741 # number of writebacks +system.cpu7.l1c.writebacks::total 9741 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36066 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36066 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23832 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23832 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 59898 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 59898 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 59898 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 59898 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 2368349491 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 2368349491 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1818980712 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1818980712 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 4187330203 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 4187330203 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 4187330203 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 4187330203 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 1090983062 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 1090983062 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 4047348155 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 4047348155 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 5138331217 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 5138331217 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807550 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807550 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953623 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953623 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859961 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.859961 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859961 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.859961 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 65667.096185 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 65667.096185 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 76325.138973 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 76325.138973 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 69907.679772 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 69907.679772 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 69907.679772 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 69907.679772 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index ee0a55e41..3816114a8 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000667 # Nu sim_ticks 666669000 # Number of ticks simulated final_tick 666669000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 89799840 # Simulator tick rate (ticks/s) -host_mem_usage 343700 # Number of bytes of host memory used -host_seconds 7.42 # Real time elapsed on the host +host_tick_rate 141005098 # Simulator tick rate (ticks/s) +host_mem_usage 405228 # Number of bytes of host memory used +host_seconds 4.73 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0 77587 # Number of bytes read from this memory @@ -76,7 +76,6 @@ system.physmem.bw_total::cpu5 124247565 # To system.physmem.bw_total::cpu6 125875059 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu7 125110062 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1591465930 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 1591365430 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 83865 # Transaction distribution system.membus.trans_dist::ReadResp 83861 # Transaction distribution system.membus.trans_dist::WriteReq 43929 # Transaction distribution @@ -88,10 +87,19 @@ system.membus.trans_dist::ReadExReq 50259 # Tr system.membus.trans_dist::ReadExResp 3073 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 420880 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 420880 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 1060914 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 1060914 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1060914 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1060914 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1060914 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 57934 # Total snoops (count) +system.membus.snoop_fanout::samples 123225 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 123225 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 123225 # Request fanout histogram system.membus.reqLayer0.occupancy 288472152 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 43.3 # Layer utilization (%) system.membus.respLayer0.occupancy 310892000 # Layer occupancy (ticks) @@ -687,9 +695,6 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.funcbus.throughput 0 # Throughput (bytes/s) -system.funcbus.data_through_bus 0 # Total data (bytes) -system.toL2Bus.throughput 51067763763 # Throughput (bytes/s) system.toL2Bus.trans_dist::ReadReq 370706 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 370692 # Transaction distribution system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution @@ -709,17 +714,33 @@ system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120 system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120880 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120421 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 963916 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1756245 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1754904 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1765350 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1754211 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1769359 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1771216 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1757581 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1758989 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 14087855 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 14087855 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 19957440 # Total snoop data (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1756245 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1754904 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1765350 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1754211 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1769359 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1771216 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1757581 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1758989 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14087855 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 322583 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 561153 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 561153 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 561153 # Request fanout histogram system.toL2Bus.reqLayer0.occupancy 655042579 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 98.3 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 160407425 # Layer occupancy (ticks) diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt index 779d261ee..3240ac711 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 10849136429 # Simulator tick rate (ticks/s) -host_mem_usage 200176 # Number of bytes of host memory used -host_seconds 9.22 # Real time elapsed on the host +host_tick_rate 14153017614 # Simulator tick rate (ticks/s) +host_mem_usage 261088 # Number of bytes of host memory used +host_seconds 7.07 # Real time elapsed on the host system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu 106649408 # Number of bytes read from this memory @@ -27,46 +27,46 @@ system.physmem.readReqs 1666397 # Nu system.physmem.writeReqs 1666879 # Number of write requests accepted system.physmem.readBursts 1666397 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 1666879 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 106647616 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1792 # Total number of bytes read from write queue -system.physmem.bytesWritten 106676608 # Total number of bytes written to DRAM +system.physmem.bytesReadDRAM 106647872 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1536 # Total number of bytes read from write queue +system.physmem.bytesWritten 106676864 # Total number of bytes written to DRAM system.physmem.bytesReadSys 106649408 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 106680256 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 28 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 33 # Number of DRAM write bursts merged with an existing one +system.physmem.servicedByWrQ 24 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 30 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 104030 # Per bank write bursts -system.physmem.perBankRdBursts::1 103995 # Per bank write bursts +system.physmem.perBankRdBursts::1 103994 # Per bank write bursts system.physmem.perBankRdBursts::2 104918 # Per bank write bursts -system.physmem.perBankRdBursts::3 104597 # Per bank write bursts -system.physmem.perBankRdBursts::4 103868 # Per bank write bursts -system.physmem.perBankRdBursts::5 103934 # Per bank write bursts +system.physmem.perBankRdBursts::3 104596 # Per bank write bursts +system.physmem.perBankRdBursts::4 103869 # Per bank write bursts +system.physmem.perBankRdBursts::5 103935 # Per bank write bursts system.physmem.perBankRdBursts::6 103649 # Per bank write bursts -system.physmem.perBankRdBursts::7 104312 # Per bank write bursts +system.physmem.perBankRdBursts::7 104313 # Per bank write bursts system.physmem.perBankRdBursts::8 103869 # Per bank write bursts -system.physmem.perBankRdBursts::9 104353 # Per bank write bursts -system.physmem.perBankRdBursts::10 103834 # Per bank write bursts +system.physmem.perBankRdBursts::9 104354 # Per bank write bursts +system.physmem.perBankRdBursts::10 103835 # Per bank write bursts system.physmem.perBankRdBursts::11 104272 # Per bank write bursts -system.physmem.perBankRdBursts::12 104075 # Per bank write bursts +system.physmem.perBankRdBursts::12 104076 # Per bank write bursts system.physmem.perBankRdBursts::13 104034 # Per bank write bursts system.physmem.perBankRdBursts::14 104583 # Per bank write bursts system.physmem.perBankRdBursts::15 104046 # Per bank write bursts -system.physmem.perBankWrBursts::0 104355 # Per bank write bursts +system.physmem.perBankWrBursts::0 104357 # Per bank write bursts system.physmem.perBankWrBursts::1 104090 # Per bank write bursts system.physmem.perBankWrBursts::2 104175 # Per bank write bursts system.physmem.perBankWrBursts::3 103885 # Per bank write bursts system.physmem.perBankWrBursts::4 104730 # Per bank write bursts -system.physmem.perBankWrBursts::5 104507 # Per bank write bursts -system.physmem.perBankWrBursts::6 104082 # Per bank write bursts -system.physmem.perBankWrBursts::7 104224 # Per bank write bursts -system.physmem.perBankWrBursts::8 104318 # Per bank write bursts +system.physmem.perBankWrBursts::5 104508 # Per bank write bursts +system.physmem.perBankWrBursts::6 104083 # Per bank write bursts +system.physmem.perBankWrBursts::7 104226 # Per bank write bursts +system.physmem.perBankWrBursts::8 104319 # Per bank write bursts system.physmem.perBankWrBursts::9 104219 # Per bank write bursts -system.physmem.perBankWrBursts::10 104228 # Per bank write bursts +system.physmem.perBankWrBursts::10 104229 # Per bank write bursts system.physmem.perBankWrBursts::11 103701 # Per bank write bursts -system.physmem.perBankWrBursts::12 104103 # Per bank write bursts -system.physmem.perBankWrBursts::13 103984 # Per bank write bursts -system.physmem.perBankWrBursts::14 104297 # Per bank write bursts -system.physmem.perBankWrBursts::15 103924 # Per bank write bursts +system.physmem.perBankWrBursts::12 104102 # Per bank write bursts +system.physmem.perBankWrBursts::13 103983 # Per bank write bursts +system.physmem.perBankWrBursts::14 104296 # Per bank write bursts +system.physmem.perBankWrBursts::15 103923 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 99999956143 # Total gap between requests @@ -84,21 +84,21 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1666879 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 765065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 778270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 73012 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10950 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2026 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 361 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 749477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 767791 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 84595 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 34424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 14110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7738 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4506 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2212 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -131,31 +131,31 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 21652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 26132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 101252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 110536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 109573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 103779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 100515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 100211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 122657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 111795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 105251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 100593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 98735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 98656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 98627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 98577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 98503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 11355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 15130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 38121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 87361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 105787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 108512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 113649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 112259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 107672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 105658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 125741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 107375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 108402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 107991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 100241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 100173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 100040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 100007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 69 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see @@ -180,12 +180,12 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 3296334 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 64.715403 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 64.191581 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 23.992085 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3288433 99.76% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 5746 0.17% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 3296263 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 64.716933 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 64.192638 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 23.994317 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3288284 99.76% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 5824 0.18% 99.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 32 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 32 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 32 0.00% 99.94% # Bytes accessed per row activation @@ -193,40 +193,41 @@ system.physmem.bytesPerActivate::640-767 32 0.00% 99.94% # By system.physmem.bytesPerActivate::768-895 32 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 32 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 1963 0.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 3296334 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 97889 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 17.022975 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 15.667690 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 106.738588 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 97888 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::total 3296263 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 99238 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.791612 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 15.446176 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 106.010489 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 99237 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 97889 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 97889 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.027674 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.937663 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.829790 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 73237 74.82% 74.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 524 0.54% 75.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 736 0.75% 76.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1545 1.58% 77.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 16291 16.64% 94.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 5161 5.27% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 155 0.16% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 78 0.08% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 59 0.06% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 41 0.04% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 31 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 13 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 9 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 6 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 97889 # Writes before turning the bus around for reads -system.physmem.totQLat 57937365003 # Total ticks spent queuing -system.physmem.totMemAccLat 89181783753 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8331845000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34768.63 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 99238 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 99238 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.796247 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.714914 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.763911 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 78818 79.42% 79.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3091 3.11% 82.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3042 3.07% 85.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1750 1.76% 87.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1374 1.38% 88.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 8750 8.82% 97.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1949 1.96% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 293 0.30% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 65 0.07% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 43 0.04% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 29 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 17 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 10 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 99238 # Writes before turning the bus around for reads +system.physmem.totQLat 61644213329 # Total ticks spent queuing +system.physmem.totMemAccLat 92888707079 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8331865000 # Total ticks spent in databus transfers +system.physmem.avgQLat 36993.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53518.63 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 55743.05 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1066.48 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1066.77 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1066.49 # Average system read bandwidth in MiByte/s @@ -235,32 +236,30 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 16.67 # Data bus utilization in percentage system.physmem.busUtilRead 8.33 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 8.33 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.19 # Average write queue length when enqueuing -system.physmem.readRowHits 32168 # Number of row buffer hits during reads -system.physmem.writeRowHits 4679 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.44 # Average write queue length when enqueuing +system.physmem.readRowHits 32184 # Number of row buffer hits during reads +system.physmem.writeRowHits 4741 # Number of row buffer hits during writes system.physmem.readRowHitRate 1.93 # Row buffer hit rate for reads system.physmem.writeRowHitRate 0.28 # Row buffer hit rate for writes system.physmem.avgGap 30000.50 # Average gap between requests system.physmem.pageHitRate 1.11 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 5459951 # Time in different power states +system.physmem.memoryStateTime::IDLE 5342990 # Time in different power states system.physmem.memoryStateTime::REF 3339180000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 96654442549 # Time in different power states +system.physmem.memoryStateTime::ACT 96654559510 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 2133296640 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 1666397 # Transaction distribution system.membus.trans_dist::ReadResp 1666397 # Transaction distribution system.membus.trans_dist::WriteReq 1666879 # Transaction distribution system.membus.trans_dist::WriteResp 1666879 # Transaction distribution system.membus.pkt_count_system.monitor-master::system.physmem.port 6666552 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 6666552 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.monitor-master::system.physmem.port 213329664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 213329664 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 213329664 # Total data (bytes) +system.membus.pkt_size_system.monitor-master::system.physmem.port 213329664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 213329664 # Cumulative packet size per connected master and slave (bytes) system.membus.reqLayer0.occupancy 11679751447 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 11.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 11400175366 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 11427712781 # Layer occupancy (ticks) system.membus.respLayer0.utilization 11.4 # Layer utilization (%) system.monitor.readBurstLengthHist::samples 1666397 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets @@ -314,8 +313,8 @@ system.monitor.writeBurstLengthHist::76-79 0 0.00% 100.00% # system.monitor.writeBurstLengthHist::total 1666879 # Histogram of burst lengths of transmitted packets system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::mean 1066494080 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::gmean 1063154518.573643 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::stdev 107916008.948195 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::gmean 1063154546.015704 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::stdev 107915737.892311 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) @@ -367,34 +366,34 @@ system.monitor.writeBandwidthHist::total 100 # Hi system.monitor.averageWriteBandwidth 1066802560 0.00% 0.00% # Average write bandwidth (bytes/s) system.monitor.totalWrittenBytes 106680256 # Number of bytes written system.monitor.readLatencyHist::samples 1666397 # Read request-response latency -system.monitor.readLatencyHist::mean 73557.268741 # Read request-response latency -system.monitor.readLatencyHist::gmean 68501.179139 # Read request-response latency -system.monitor.readLatencyHist::stdev 39156.791762 # Read request-response latency -system.monitor.readLatencyHist::0-32767 28 0.00% 0.00% # Read request-response latency -system.monitor.readLatencyHist::32768-65535 454399 27.27% 27.27% # Read request-response latency -system.monitor.readLatencyHist::65536-98303 1040506 62.44% 89.71% # Read request-response latency -system.monitor.readLatencyHist::98304-131071 73250 4.40% 94.11% # Read request-response latency -system.monitor.readLatencyHist::131072-163839 47036 2.82% 96.93% # Read request-response latency -system.monitor.readLatencyHist::163840-196607 12641 0.76% 97.69% # Read request-response latency -system.monitor.readLatencyHist::196608-229375 7802 0.47% 98.16% # Read request-response latency -system.monitor.readLatencyHist::229376-262143 7940 0.48% 98.63% # Read request-response latency -system.monitor.readLatencyHist::262144-294911 8093 0.49% 99.12% # Read request-response latency -system.monitor.readLatencyHist::294912-327679 7856 0.47% 99.59% # Read request-response latency -system.monitor.readLatencyHist::327680-360447 4214 0.25% 99.84% # Read request-response latency -system.monitor.readLatencyHist::360448-393215 1043 0.06% 99.90% # Read request-response latency -system.monitor.readLatencyHist::393216-425983 827 0.05% 99.95% # Read request-response latency -system.monitor.readLatencyHist::425984-458751 590 0.04% 99.99% # Read request-response latency -system.monitor.readLatencyHist::458752-491519 166 0.01% 100.00% # Read request-response latency -system.monitor.readLatencyHist::491520-524287 6 0.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::524288-557055 0 0.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::557056-589823 0 0.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::589824-622591 0 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::mean 75762.275031 # Read request-response latency +system.monitor.readLatencyHist::gmean 69897.504803 # Read request-response latency +system.monitor.readLatencyHist::stdev 42102.080811 # Read request-response latency +system.monitor.readLatencyHist::0-32767 24 0.00% 0.00% # Read request-response latency +system.monitor.readLatencyHist::32768-65535 443180 26.60% 26.60% # Read request-response latency +system.monitor.readLatencyHist::65536-98303 1020210 61.22% 87.82% # Read request-response latency +system.monitor.readLatencyHist::98304-131071 76869 4.61% 92.43% # Read request-response latency +system.monitor.readLatencyHist::131072-163839 59066 3.54% 95.98% # Read request-response latency +system.monitor.readLatencyHist::163840-196607 25573 1.53% 97.51% # Read request-response latency +system.monitor.readLatencyHist::196608-229375 9468 0.57% 98.08% # Read request-response latency +system.monitor.readLatencyHist::229376-262143 7856 0.47% 98.55% # Read request-response latency +system.monitor.readLatencyHist::262144-294911 8007 0.48% 99.03% # Read request-response latency +system.monitor.readLatencyHist::294912-327679 7912 0.47% 99.51% # Read request-response latency +system.monitor.readLatencyHist::327680-360447 4865 0.29% 99.80% # Read request-response latency +system.monitor.readLatencyHist::360448-393215 1179 0.07% 99.87% # Read request-response latency +system.monitor.readLatencyHist::393216-425983 915 0.05% 99.92% # Read request-response latency +system.monitor.readLatencyHist::425984-458751 775 0.05% 99.97% # Read request-response latency +system.monitor.readLatencyHist::458752-491519 416 0.02% 100.00% # Read request-response latency +system.monitor.readLatencyHist::491520-524287 74 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::524288-557055 5 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::557056-589823 1 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::589824-622591 2 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::622592-655359 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::total 1666397 # Read request-response latency system.monitor.writeLatencyHist::samples 1666879 # Write request-response latency -system.monitor.writeLatencyHist::mean 10569.121768 # Write request-response latency -system.monitor.writeLatencyHist::gmean 10510.211461 # Write request-response latency -system.monitor.writeLatencyHist::stdev 1197.318213 # Write request-response latency +system.monitor.writeLatencyHist::mean 10554.999998 # Write request-response latency +system.monitor.writeLatencyHist::gmean 10497.332887 # Write request-response latency +system.monitor.writeLatencyHist::stdev 1184.671741 # Write request-response latency system.monitor.writeLatencyHist::0-1023 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::1024-2047 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::2048-3071 0 0.00% 0.00% # Write request-response latency @@ -404,13 +403,13 @@ system.monitor.writeLatencyHist::5120-6143 0 0.00% 0.00% # system.monitor.writeLatencyHist::6144-7167 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::7168-8191 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::8192-9215 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::9216-10239 1268910 76.12% 76.12% # Write request-response latency -system.monitor.writeLatencyHist::10240-11263 92420 5.54% 81.67% # Write request-response latency -system.monitor.writeLatencyHist::11264-12287 113112 6.79% 88.46% # Write request-response latency -system.monitor.writeLatencyHist::12288-13311 92715 5.56% 94.02% # Write request-response latency -system.monitor.writeLatencyHist::13312-14335 62904 3.77% 97.79% # Write request-response latency -system.monitor.writeLatencyHist::14336-15359 32645 1.96% 99.75% # Write request-response latency -system.monitor.writeLatencyHist::15360-16383 4173 0.25% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::9216-10239 1277601 76.65% 76.65% # Write request-response latency +system.monitor.writeLatencyHist::10240-11263 91250 5.47% 82.12% # Write request-response latency +system.monitor.writeLatencyHist::11264-12287 110692 6.64% 88.76% # Write request-response latency +system.monitor.writeLatencyHist::12288-13311 90268 5.42% 94.18% # Write request-response latency +system.monitor.writeLatencyHist::13312-14335 61253 3.67% 97.85% # Write request-response latency +system.monitor.writeLatencyHist::14336-15359 31832 1.91% 99.76% # Write request-response latency +system.monitor.writeLatencyHist::15360-16383 3983 0.24% 100.00% # Write request-response latency system.monitor.writeLatencyHist::16384-17407 0 0.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::17408-18431 0 0.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::18432-19455 0 0.00% 100.00% # Write request-response latency @@ -501,15 +500,15 @@ system.monitor.ittReqReq::min_value 28000 # Re system.monitor.ittReqReq::max_value 1041309 # Request-to-request inter transaction time system.monitor.ittReqReq::total 3333275 # Request-to-request inter transaction time system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions -system.monitor.outstandingReadsHist::mean 1.160000 # Outstanding read transactions +system.monitor.outstandingReadsHist::mean 1.230000 # Outstanding read transactions system.monitor.outstandingReadsHist::gmean 0 # Outstanding read transactions -system.monitor.outstandingReadsHist::stdev 1.212061 # Outstanding read transactions +system.monitor.outstandingReadsHist::stdev 1.309291 # Outstanding read transactions system.monitor.outstandingReadsHist::0 28 28.00% 28.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::1 45 45.00% 73.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::2 19 19.00% 92.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::3 5 5.00% 97.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::4 0 0.00% 97.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::5 2 2.00% 99.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::1 44 44.00% 72.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::2 17 17.00% 89.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::3 6 6.00% 95.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::4 1 1.00% 96.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::5 3 3.00% 99.00% # Outstanding read transactions system.monitor.outstandingReadsHist::6 0 0.00% 99.00% # Outstanding read transactions system.monitor.outstandingReadsHist::7 0 0.00% 99.00% # Outstanding read transactions system.monitor.outstandingReadsHist::8 1 1.00% 100.00% # Outstanding read transactions diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt index ead00396f..936a2fa90 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 14364594493 # Simulator tick rate (ticks/s) -host_mem_usage 195500 # Number of bytes of host memory used -host_seconds 6.96 # Real time elapsed on the host +host_tick_rate 11160095249 # Simulator tick rate (ticks/s) +host_mem_usage 262112 # Number of bytes of host memory used +host_seconds 8.96 # Real time elapsed on the host system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory @@ -23,16 +23,14 @@ system.physmem.bw_write::cpu 2133291520 # Wr system.physmem.bw_write::total 2133291520 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu 2133292160 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2133292160 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 2133292160 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 1 # Transaction distribution system.membus.trans_dist::ReadResp 1 # Transaction distribution system.membus.trans_dist::WriteReq 3333268 # Transaction distribution system.membus.trans_dist::WriteResp 3333267 # Transaction distribution system.membus.pkt_count_system.monitor-master::system.physmem.port 6666537 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 6666537 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.monitor-master::system.physmem.port 213329216 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 213329216 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 213329216 # Total data (bytes) +system.membus.pkt_size_system.monitor-master::system.physmem.port 213329216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 213329216 # Cumulative packet size per connected master and slave (bytes) system.membus.reqLayer0.occupancy 16666342328 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 16.7 # Layer utilization (%) system.membus.respLayer0.occupancy 3333272000 # Layer occupancy (ticks) |