diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
| commit | c6cede244b431c167ac0213d89ad2bd7a0abbd96 (patch) | |
| tree | fb0e63d4172746d5b1a8edeb859f7ee68cfe13a6 /tests/quick/se | |
| parent | 83a5977481d55916b200740cf03748a20777bdf1 (diff) | |
| download | gem5-c6cede244b431c167ac0213d89ad2bd7a0abbd96.tar.xz | |
stats: Update stats to reflect changes to cache and crossbar
Diffstat (limited to 'tests/quick/se')
30 files changed, 6572 insertions, 6575 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt index 0ee8e01b1..dc74457ff 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000121 # Nu sim_ticks 121460 # Number of ticks simulated final_tick 121460 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 19821 # Simulator instruction rate (inst/s) -host_op_rate 19819 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 376677 # Simulator tick rate (ticks/s) -host_mem_usage 390876 # Number of bytes of host memory used -host_seconds 0.32 # Real time elapsed on the host +host_inst_rate 58804 # Simulator instruction rate (inst/s) +host_op_rate 58798 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1117518 # Simulator tick rate (ticks/s) +host_mem_usage 412400 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 8c7fdbc65..adb01be8a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000109 # Nu sim_ticks 108694 # Number of ticks simulated final_tick 108694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 18329 # Simulator instruction rate (inst/s) -host_op_rate 18327 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 311726 # Simulator tick rate (ticks/s) -host_mem_usage 397240 # Number of bytes of host memory used -host_seconds 0.35 # Real time elapsed on the host +host_inst_rate 71872 # Simulator instruction rate (inst/s) +host_op_rate 71865 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1222276 # Simulator tick rate (ticks/s) +host_mem_usage 417856 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index d98266934..fc2b85717 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000087 # Nu sim_ticks 86673 # Number of ticks simulated final_tick 86673 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 26202 # Simulator instruction rate (inst/s) -host_op_rate 26199 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 355322 # Simulator tick rate (ticks/s) -host_mem_usage 391844 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host +host_inst_rate 58973 # Simulator instruction rate (inst/s) +host_op_rate 58962 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 799609 # Simulator tick rate (ticks/s) +host_mem_usage 411856 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index ee921f3ab..cf623ae19 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000107 # Nu sim_ticks 107210 # Number of ticks simulated final_tick 107210 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 29228 # Simulator instruction rate (inst/s) -host_op_rate 29224 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 490268 # Simulator tick rate (ticks/s) -host_mem_usage 394320 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 108799 # Simulator instruction rate (inst/s) +host_op_rate 108769 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1824399 # Simulator tick rate (ticks/s) +host_mem_usage 416280 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt index 55628ad16..a9f8176e1 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000046 # Nu sim_ticks 45733 # Number of ticks simulated final_tick 45733 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 16358 # Simulator instruction rate (inst/s) -host_op_rate 16355 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 290200 # Simulator tick rate (ticks/s) -host_mem_usage 389816 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 42490 # Simulator instruction rate (inst/s) +host_op_rate 42477 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 753627 # Simulator tick rate (ticks/s) +host_mem_usage 411088 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 4855f53c1..be4c58d22 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000042 # Nu sim_ticks 41712 # Number of ticks simulated final_tick 41712 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 12099 # Simulator instruction rate (inst/s) -host_op_rate 12098 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 195791 # Simulator tick rate (ticks/s) -host_mem_usage 393888 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 38081 # Simulator instruction rate (inst/s) +host_op_rate 38070 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 616024 # Simulator tick rate (ticks/s) +host_mem_usage 414508 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index a8631d9c5..08266d48d 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000033 # Nu sim_ticks 32936 # Number of ticks simulated final_tick 32936 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 22566 # Simulator instruction rate (inst/s) -host_op_rate 22561 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 288279 # Simulator tick rate (ticks/s) -host_mem_usage 390660 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 52774 # Simulator instruction rate (inst/s) +host_op_rate 52753 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 673978 # Simulator tick rate (ticks/s) +host_mem_usage 411572 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index 7f8b12151..c437c6665 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000042 # Nu sim_ticks 41659 # Number of ticks simulated final_tick 41659 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 23573 # Simulator instruction rate (inst/s) -host_op_rate 23567 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 380874 # Simulator tick rate (ticks/s) -host_mem_usage 390976 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 41992 # Simulator instruction rate (inst/s) +host_op_rate 41979 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 678429 # Simulator tick rate (ticks/s) +host_mem_usage 412928 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 5c45eaf46..586c80689 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000030 # Nu sim_ticks 29949500 # Number of ticks simulated final_tick 29949500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25443 # Simulator instruction rate (inst/s) -host_op_rate 29781 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 165422007 # Simulator tick rate (ticks/s) -host_mem_usage 247956 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 167534 # Simulator instruction rate (inst/s) +host_op_rate 196036 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1088591965 # Simulator tick rate (ticks/s) +host_mem_usage 269228 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -755,17 +755,17 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 647 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 938 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 939 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20800 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.100427 # Request fanout histogram diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 3b3a0c7c5..f429492e1 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 17170000 # Number of ticks simulated final_tick 17170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24070 # Simulator instruction rate (inst/s) -host_op_rate 28186 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 89974051 # Simulator tick rate (ticks/s) -host_mem_usage 249040 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 56453 # Simulator instruction rate (inst/s) +host_op_rate 66106 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 211025109 # Simulator tick rate (ticks/s) +host_mem_usage 270504 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1167,16 +1167,17 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 586 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 587 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 880 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28224 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.100000 # Request fanout histogram diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 4d42e5502..63280507a 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18741000 # Number of ticks simulated final_tick 18741000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27191 # Simulator instruction rate (inst/s) -host_op_rate 31839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 110934081 # Simulator tick rate (ticks/s) -host_mem_usage 245436 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 84742 # Simulator instruction rate (inst/s) +host_op_rate 99228 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 345728368 # Simulator tick rate (ticks/s) +host_mem_usage 266024 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1082,19 +1082,19 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 409 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 368 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 41 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 44 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 383 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 297 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 626 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 913 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 636 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 288 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 924 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30912 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 452 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 893 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.549832 # Request fanout histogram diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index be08dbe1d..83487a6ff 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 28298500 # Number of ticks simulated final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76228 # Simulator instruction rate (inst/s) -host_op_rate 88939 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 471979620 # Simulator tick rate (ticks/s) -host_mem_usage 246976 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 286813 # Simulator instruction rate (inst/s) +host_op_rate 333728 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1769783602 # Simulator tick rate (ticks/s) +host_mem_usage 267436 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 4566 # Number of instructions simulated sim_ops 5330 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -556,16 +556,17 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 482 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 764 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 765 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15488 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 24512 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.083770 # Request fanout histogram diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt index 338e36e87..f933f7176 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000050 # Nu sim_ticks 49855000 # Number of ticks simulated final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93266 # Simulator instruction rate (inst/s) -host_op_rate 107828 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 931188295 # Simulator tick rate (ticks/s) -host_mem_usage 634440 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 411650 # Simulator instruction rate (inst/s) +host_op_rate 475781 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4107877451 # Simulator tick rate (ticks/s) +host_mem_usage 655016 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -629,13 +629,13 @@ system.l2bus.snoop_filter.tot_snoops 0 # To system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.trans_dist::ReadResp 348 # Transaction distribution -system.l2bus.trans_dist::CleanEvict 60 # Transaction distribution +system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution system.l2bus.trans_dist::ReadExResp 43 # Transaction distribution system.l2bus.trans_dist::ReadSharedReq 348 # Transaction distribution -system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 568 # Packet count per connected master and slave (bytes) system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count::total 842 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15936 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt index bf796f4ef..010db5b17 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000053 # Nu sim_ticks 53334000 # Number of ticks simulated final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 45290 # Simulator instruction rate (inst/s) -host_op_rate 45279 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 435170568 # Simulator tick rate (ticks/s) -host_mem_usage 616512 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 486070 # Simulator instruction rate (inst/s) +host_op_rate 485474 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4661655450 # Simulator tick rate (ticks/s) +host_mem_usage 680524 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -508,13 +508,13 @@ system.l2bus.snoop_filter.tot_snoops 0 # To system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.trans_dist::ReadResp 315 # Transaction distribution -system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution +system.l2bus.trans_dist::CleanEvict 71 # Transaction distribution system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution system.l2bus.trans_dist::ReadExResp 82 # Transaction distribution system.l2bus.trans_dist::ReadSharedReq 315 # Transaction distribution -system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 589 # Packet count per connected master and slave (bytes) system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count::total 864 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_count::total 865 # Packet count per connected master and slave (bytes) system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 16576 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 7302f4619..7b63e03f4 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.147149 # Nu sim_ticks 147148719500 # Number of ticks simulated final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 392484 # Simulator instruction rate (inst/s) -host_op_rate 394434 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 637618235 # Simulator tick rate (ticks/s) -host_mem_usage 382304 # Number of bytes of host memory used -host_seconds 230.78 # Real time elapsed on the host +host_inst_rate 1174056 # Simulator instruction rate (inst/s) +host_op_rate 1179890 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1907338487 # Simulator tick rate (ticks/s) +host_mem_usage 402756 # Number of bytes of host memory used +host_seconds 77.15 # Real time elapsed on the host sim_insts 90576862 # Number of instructions simulated sim_ops 91026991 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -600,18 +600,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 255 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 368 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1199 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836185 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2837384 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1200 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836298 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2837498 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38464 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 120942848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 120942912 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 947397 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000132 # Request fanout histogram diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 459938f5d..31446f740 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000108 # Number of seconds simulated -sim_ticks 107836000 # Number of ticks simulated -final_tick 107836000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 107700000 # Number of ticks simulated +final_tick 107700000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 68965 # Simulator instruction rate (inst/s) -host_op_rate 68965 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7480497 # Simulator tick rate (ticks/s) -host_mem_usage 247424 # Number of bytes of host memory used -host_seconds 14.42 # Real time elapsed on the host -sim_insts 994171 # Number of instructions simulated -sim_ops 994171 # Number of ops (including micro ops) simulated +host_inst_rate 155633 # Simulator instruction rate (inst/s) +host_op_rate 155632 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16853882 # Simulator tick rate (ticks/s) +host_mem_usage 312924 # Number of bytes of host memory used +host_seconds 6.39 # Real time elapsed on the host +sim_insts 994522 # Number of instructions simulated +sim_ops 994522 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5248 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory system.physmem.bytes_read::total 42560 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 82 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::total 665 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 213657777 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 100300456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 47479506 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11869876 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 1780481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7715420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 4154457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7715420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 394673393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 213657777 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 47479506 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 1780481 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 4154457 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267072221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 213657777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 100300456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 47479506 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11869876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 1780481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7715420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 4154457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7715420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 394673393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213927577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 100427112 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 48727948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11884865 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 3565460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7725162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1188487 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7725162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 395171773 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213927577 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 48727948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 3565460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1188487 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267409471 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213927577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 100427112 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 48727948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11884865 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 3565460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7725162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1188487 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7725162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 395171773 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 666 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 666 # Number of DRAM read bursts, including those serviced by the write queue @@ -70,7 +70,7 @@ system.physmem.bytesReadSys 42624 # To system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 89 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 114 # Per bank write bursts system.physmem.perBankRdBursts::1 42 # Per bank write bursts system.physmem.perBankRdBursts::2 30 # Per bank write bursts @@ -105,7 +105,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 107808000 # Total gap between requests +system.physmem.totGap 107672000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -230,15 +230,15 @@ system.physmem.bytesPerActivate::768-895 2 1.38% 94.48% # By system.physmem.bytesPerActivate::896-1023 3 2.07% 96.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 3.45% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 145 # Bytes accessed per row activation -system.physmem.totQLat 6565250 # Total ticks spent queuing -system.physmem.totMemAccLat 19052750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 6586250 # Total ticks spent queuing +system.physmem.totMemAccLat 19073750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 3330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9857.73 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9889.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28607.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 395.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28639.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 395.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 395.27 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 395.77 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.09 # Data bus utilization in percentage @@ -250,169 +250,169 @@ system.physmem.readRowHits 510 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 161873.87 # Average gap between requests +system.physmem.avgGap 161669.67 # Average gap between requests system.physmem.pageHitRate 76.58 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 710640 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 387750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2769000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 38088540 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27477750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 76044960 # Total energy per rank (pJ) -system.physmem_0.averagePower 749.349855 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 47969250 # Time in different power states +system.physmem_0.actBackEnergy 38199690 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27380250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 76058610 # Total energy per rank (pJ) +system.physmem_0.averagePower 749.484363 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 47670750 # Time in different power states system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 52649750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 52812250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 2028000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 32065065 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32761500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 74015040 # Total energy per rank (pJ) -system.physmem_1.averagePower 729.346948 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57811250 # Time in different power states +system.physmem_1.actBackEnergy 32151420 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32685750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 74025645 # Total energy per rank (pJ) +system.physmem_1.averagePower 729.451450 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57549250 # Time in different power states system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 43803750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 43929750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 81652 # Number of BP lookups -system.cpu0.branchPred.condPredicted 79008 # Number of conditional branches predicted +system.cpu0.branchPred.lookups 81595 # Number of BP lookups +system.cpu0.branchPred.condPredicted 78953 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 1100 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 78985 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 76270 # Number of BTB hits +system.cpu0.branchPred.BTBLookups 78929 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 76214 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 96.562638 # BTB Hit Percentage +system.cpu0.branchPred.BTBHitPct 96.560200 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 645 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 215673 # number of cpu cycles simulated +system.cpu0.numCycles 215401 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 19729 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 482689 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 81652 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 76915 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 165939 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.icacheStallCycles 19727 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 482343 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 81595 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 76859 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 165670 # Number of cycles fetch has run and was not squashing or blocked system.cpu0.fetch.SquashCycles 2501 # Number of cycles fetch has spent squashing system.cpu0.fetch.TlbCycles 96 # Number of cycles fetch has spent waiting for tlb system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1994 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 6734 # Number of cache lines fetched +system.cpu0.fetch.PendingTrapStallCycles 1993 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 6732 # Number of cache lines fetched system.cpu0.fetch.IcacheSquashes 621 # Number of outstanding Icache misses that were squashed system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 189011 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.553761 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.213837 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::samples 188739 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.555609 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.213598 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 30617 16.20% 16.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 78326 41.44% 57.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 798 0.42% 58.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1203 0.64% 58.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 614 0.32% 59.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 73725 39.01% 98.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 672 0.36% 98.38% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 403 0.21% 98.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2653 1.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 30459 16.14% 16.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 78270 41.47% 57.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 797 0.42% 58.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1203 0.64% 58.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 613 0.32% 58.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 73671 39.03% 98.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 671 0.36% 98.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 403 0.21% 98.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2652 1.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 189011 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.378592 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.238059 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 15475 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 18570 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 153063 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 653 # Number of cycles decode is unblocking +system.cpu0.fetch.rateDist::total 188739 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.378805 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.239279 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 15463 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 18382 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 152999 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 645 # Number of cycles decode is unblocking system.cpu0.decode.SquashCycles 1250 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 472193 # Number of instructions handled by decode +system.cpu0.decode.DecodedInsts 471851 # Number of instructions handled by decode system.cpu0.rename.SquashCycles 1250 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 16079 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2117 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 15116 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 153063 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1386 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 469016 # Number of instructions processed by rename +system.cpu0.rename.IdleCycles 16060 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2005 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 15072 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 152998 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1354 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 468673 # Number of instructions processed by rename system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 883 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 320676 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 935403 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 706479 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 307583 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13093 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 822 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 832 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4383 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 150037 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 75873 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 73364 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 72959 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 392343 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.rename.SQFullEvents 851 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 320440 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 934717 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 705961 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 307367 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13073 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 821 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 831 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4337 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 149926 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 75817 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 73307 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 72919 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 392051 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 889 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 388906 # Number of instructions issued +system.cpu0.iq.iqInstsIssued 388622 # Number of instructions issued system.cpu0.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 12322 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 11733 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedInstsExamined 12300 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 11714 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 330 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 189011 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.057584 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.125737 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::samples 188739 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.059045 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.124370 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33687 17.82% 17.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4243 2.24% 20.07% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 74165 39.24% 59.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 73776 39.03% 98.34% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1622 0.86% 99.20% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 890 0.47% 99.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 405 0.21% 99.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33524 17.76% 17.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4207 2.23% 19.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 74141 39.28% 59.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 73776 39.09% 98.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1579 0.84% 99.20% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 884 0.47% 99.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 404 0.21% 99.88% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 147 0.08% 99.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 76 0.04% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 77 0.04% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 189011 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 188739 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 62 21.45% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 124 42.91% 64.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 61 21.18% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 124 43.06% 64.24% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 103 35.76% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 164396 42.27% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 164274 42.27% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.27% # Type of FU issued @@ -441,40 +441,40 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.27% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 149390 38.41% 80.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 75120 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 149282 38.41% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 75066 19.32% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 388906 # Type of FU issued -system.cpu0.iq.rate 1.803221 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000743 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 967143 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 405616 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 387054 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 388622 # Type of FU issued +system.cpu0.iq.rate 1.804179 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 288 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000741 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 966302 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 405302 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 386770 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 389195 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 388910 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 72474 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 72419 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2656 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2653 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 63 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1676 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedStores 1674 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu0.iew.iewSquashCycles 1250 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 2081 # Number of cycles IEW is blocking +system.cpu0.iew.iewBlockCycles 1969 # Number of cycles IEW is blocking system.cpu0.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 466895 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispatchedInsts 466549 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 243 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 150037 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 75873 # Number of dispatched store instructions +system.cpu0.iew.iewDispLoadInsts 149926 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 75817 # Number of dispatched store instructions system.cpu0.iew.iewDispNonSpecInsts 770 # Number of dispatched non-speculative instructions system.cpu0.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -482,53 +482,53 @@ system.cpu0.iew.memOrderViolationEvents 63 # Nu system.cpu0.iew.predictedTakenIncorrect 318 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 991 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.branchMispredicts 1309 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 387894 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 149051 # Number of load instructions executed +system.cpu0.iew.iewExecutedInsts 387610 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 148943 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 73663 # number of nop insts executed -system.cpu0.iew.exec_refs 224021 # number of memory reference insts executed -system.cpu0.iew.exec_branches 76988 # Number of branches executed -system.cpu0.iew.exec_stores 74970 # Number of stores executed -system.cpu0.iew.exec_rate 1.798528 # Inst execution rate -system.cpu0.iew.wb_sent 387462 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 387054 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 229603 # num instructions producing a value -system.cpu0.iew.wb_consumers 232649 # num instructions consuming a value -system.cpu0.iew.wb_rate 1.794634 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.986907 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 13111 # The number of squashed insts skipped by commit +system.cpu0.iew.exec_nop 73609 # number of nop insts executed +system.cpu0.iew.exec_refs 223859 # number of memory reference insts executed +system.cpu0.iew.exec_branches 76931 # Number of branches executed +system.cpu0.iew.exec_stores 74916 # Number of stores executed +system.cpu0.iew.exec_rate 1.799481 # Inst execution rate +system.cpu0.iew.wb_sent 387178 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 386770 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 229443 # num instructions producing a value +system.cpu0.iew.wb_consumers 232488 # num instructions consuming a value +system.cpu0.iew.wb_rate 1.795581 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.986903 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 13089 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 1100 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 186547 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.432234 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.149146 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::samples 186278 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.434007 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.148610 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33930 18.19% 18.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 76047 40.77% 58.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1940 1.04% 59.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 670 0.36% 60.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 524 0.28% 60.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 72154 38.68% 99.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 534 0.29% 99.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 265 0.14% 99.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 33753 18.12% 18.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 76007 40.80% 58.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1940 1.04% 59.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 664 0.36% 60.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 518 0.28% 60.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 72154 38.73% 99.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 496 0.27% 99.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 263 0.14% 99.74% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::8 483 0.26% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 186547 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 453726 # Number of instructions committed -system.cpu0.commit.committedOps 453726 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 186278 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 453402 # Number of instructions committed +system.cpu0.commit.committedOps 453402 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 221578 # Number of memory references committed -system.cpu0.commit.loads 147381 # Number of loads committed +system.cpu0.commit.refs 221416 # Number of memory references committed +system.cpu0.commit.loads 147273 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 76084 # Number of branches committed +system.cpu0.commit.branches 76030 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 305914 # Number of committed integer instructions. +system.cpu0.commit.int_insts 305698 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 72816 16.05% 16.05% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 159248 35.10% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 72762 16.05% 16.05% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 159140 35.10% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction @@ -557,103 +557,103 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 147465 32.50% 83.65% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 74197 16.35% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 147357 32.50% 83.65% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 74143 16.35% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 453726 # Class of committed instruction +system.cpu0.commit.op_class_0::total 453402 # Class of committed instruction system.cpu0.commit.bw_lim_events 483 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 651740 # The number of ROB reads -system.cpu0.rob.rob_writes 936154 # The number of ROB writes +system.cpu0.rob.rob_reads 651125 # The number of ROB reads +system.cpu0.rob.rob_writes 935459 # The number of ROB writes system.cpu0.timesIdled 313 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu0.idleCycles 26662 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 380826 # Number of Instructions Simulated -system.cpu0.committedOps 380826 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.566330 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.566330 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.765756 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.765756 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 693989 # number of integer regfile reads -system.cpu0.int_regfile_writes 312909 # number of integer regfile writes +system.cpu0.committedInsts 380556 # Number of Instructions Simulated +system.cpu0.committedOps 380556 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.566017 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.566017 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.766733 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.766733 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 693485 # number of integer regfile reads +system.cpu0.int_regfile_writes 312678 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 225890 # number of misc regfile reads +system.cpu0.misc_regfile_reads 225727 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 141.137199 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 149509 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 141.118700 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 149407 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 874.321637 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 873.725146 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.137199 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275659 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.275659 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.118700 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275622 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.275622 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 603167 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 603167 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75961 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 75961 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 73598 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 73598 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 602739 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 602739 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75912 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75912 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73546 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73546 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 149559 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 149559 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 149559 # number of overall hits -system.cpu0.dcache.overall_hits::total 149559 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 557 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 557 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 557 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 557 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 149458 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 149458 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 149458 # number of overall hits +system.cpu0.dcache.overall_hits::total 149458 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 553 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 553 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 555 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 555 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1114 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1114 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1114 # number of overall misses -system.cpu0.dcache.overall_misses::total 1114 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17293500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 17293500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34774980 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 34774980 # number of WriteReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 1108 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1108 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1108 # number of overall misses +system.cpu0.dcache.overall_misses::total 1108 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16789000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 16789000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34744480 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 34744480 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 472500 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 472500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 52068480 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 52068480 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 52068480 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 52068480 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 76518 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 76518 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74155 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 74155 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 51533480 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 51533480 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 51533480 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 51533480 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 76465 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 76465 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74101 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 74101 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 150673 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 150673 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 150673 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 150673 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007279 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.007279 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007511 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007511 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 150566 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 150566 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 150566 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 150566 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007232 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.007232 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007490 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007490 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007393 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.007393 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007393 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.007393 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31047.576302 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31047.576302 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62432.639138 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 62432.639138 # average WriteReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007359 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.007359 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007359 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.007359 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30359.855335 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 30359.855335 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62602.666667 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 62602.666667 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18173.076923 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 18173.076923 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46740.107720 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 46740.107720 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46740.107720 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 46740.107720 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46510.361011 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 46510.361011 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46510.361011 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 46510.361011 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 891 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked @@ -664,107 +664,107 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 375 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 375 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 379 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 379 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 754 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 754 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 754 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 754 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 178 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 178 # number of WriteReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 370 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 370 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 378 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 378 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 748 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 748 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 748 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 748 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 177 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 177 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6892000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6892000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8487000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8487000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6853000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6853000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8423500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8423500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 446500 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 446500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15379000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15379000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15379000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15379000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002379 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002379 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002400 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002400 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15276500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15276500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15276500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15276500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002393 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002393 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002389 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002389 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002389 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002389 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002389 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002389 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37868.131868 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37868.131868 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47679.775281 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47679.775281 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002391 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002391 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002391 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002391 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37448.087432 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37448.087432 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47590.395480 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47590.395480 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17173.076923 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17173.076923 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42719.444444 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42719.444444 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42719.444444 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42719.444444 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42434.722222 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42434.722222 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42434.722222 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42434.722222 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 315 # number of replacements -system.cpu0.icache.tags.tagsinuse 241.200073 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 5951 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 241.159002 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 5949 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 607 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.803954 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.800659 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.200073 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471094 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.471094 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.159002 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471014 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.471014 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.570312 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 7341 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 7341 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 5951 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5951 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5951 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5951 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5951 # number of overall hits -system.cpu0.icache.overall_hits::total 5951 # number of overall hits +system.cpu0.icache.tags.tag_accesses 7339 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 7339 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 5949 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5949 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5949 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5949 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5949 # number of overall hits +system.cpu0.icache.overall_hits::total 5949 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 783 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 783 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 783 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 783 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 783 # number of overall misses system.cpu0.icache.overall_misses::total 783 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40367500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 40367500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 40367500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 40367500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 40367500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 40367500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6734 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6734 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6734 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6734 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6734 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6734 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116276 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.116276 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116276 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.116276 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116276 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.116276 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51554.916986 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 51554.916986 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51554.916986 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 51554.916986 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51554.916986 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 51554.916986 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40394500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 40394500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 40394500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 40394500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 40394500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 40394500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6732 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6732 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6732 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6732 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6732 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6732 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116310 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.116310 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116310 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.116310 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116310 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.116310 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51589.399745 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 51589.399745 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51589.399745 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 51589.399745 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51589.399745 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 51589.399745 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -787,396 +787,397 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 608 system.cpu0.icache.demand_mshr_misses::total 608 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 608 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 608 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31309500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 31309500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31309500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 31309500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31309500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 31309500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090288 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090288 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090288 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.090288 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090288 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.090288 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51495.888158 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51495.888158 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51495.888158 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 51495.888158 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51495.888158 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 51495.888158 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31312500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 31312500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31312500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 31312500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31312500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 31312500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090315 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090315 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090315 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.090315 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090315 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.090315 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51500.822368 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51500.822368 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51500.822368 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 51500.822368 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51500.822368 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 51500.822368 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 53782 # Number of BP lookups -system.cpu1.branchPred.condPredicted 50347 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1277 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 46315 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 45397 # Number of BTB hits +system.cpu1.branchPred.lookups 52270 # Number of BP lookups +system.cpu1.branchPred.condPredicted 48857 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1261 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 45038 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 43957 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 98.017921 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 899 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 97.599805 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 912 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.numCycles 162898 # number of cpu cycles simulated +system.cpu1.numCycles 162626 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 29679 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 299544 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 53782 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 46296 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 124703 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2711 # Number of cycles fetch has spent squashing +system.cpu1.fetch.icacheStallCycles 30636 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 289541 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 52270 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 44869 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 123502 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2677 # Number of cycles fetch has spent squashing system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from system.cpu1.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps system.cpu1.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 20165 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 457 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 156846 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.909797 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.217375 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 21117 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 458 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 156585 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.849098 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.199028 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 53057 33.83% 33.83% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 52143 33.24% 67.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 5878 3.75% 70.82% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3526 2.25% 73.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 939 0.60% 73.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 35272 22.49% 96.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1247 0.80% 96.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 803 0.51% 97.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3981 2.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 55186 35.24% 35.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 51235 32.72% 67.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 6397 4.09% 72.05% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3507 2.24% 74.29% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 942 0.60% 74.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 33361 21.31% 96.20% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1213 0.77% 96.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 812 0.52% 97.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3932 2.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 156846 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.330158 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.838844 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 17882 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 51023 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 83554 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3022 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1355 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 284108 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 1355 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 18601 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 22664 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 13899 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 84840 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 15477 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 280728 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 13732 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full +system.cpu1.fetch.rateDist::total 156585 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.321412 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.780410 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 17913 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 54188 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 79912 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3224 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1338 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 274398 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 1338 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 18610 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 24678 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13550 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 81416 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 16983 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 271226 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 15241 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 198394 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 541219 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 420944 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 184552 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13842 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1192 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1257 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 20109 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 79403 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 38032 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 37516 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 32939 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 234221 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 5649 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 235400 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 7 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12841 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10393 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 661 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 156846 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.500835 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.378978 # Number of insts issued each cycle +system.cpu1.rename.RenamedOperands 191192 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 520363 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 405271 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 177667 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13525 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1180 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1251 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 21370 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 76128 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 36144 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 36135 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 31079 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 225686 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 6135 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 227404 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 8 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12625 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10115 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 706 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 156585 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.452272 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.380275 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 56627 36.10% 36.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 19405 12.37% 48.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 37510 23.92% 72.39% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 37026 23.61% 96.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3380 2.15% 98.15% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1607 1.02% 99.18% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 891 0.57% 99.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 204 0.13% 99.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 196 0.12% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 58755 37.52% 37.52% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 20747 13.25% 50.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 35642 22.76% 73.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 35172 22.46% 96.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3374 2.15% 98.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1612 1.03% 99.18% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 878 0.56% 99.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 207 0.13% 99.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 198 0.13% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 156846 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 156585 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 79 24.38% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 36 11.11% 35.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 209 64.51% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 79 24.01% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 41 12.46% 36.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 209 63.53% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 114995 48.85% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 82971 35.25% 84.10% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 37434 15.90% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 111654 49.10% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 80158 35.25% 84.35% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 35592 15.65% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 235400 # Type of FU issued -system.cpu1.iq.rate 1.445076 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 324 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001376 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 627977 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 252747 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 233879 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 227404 # Type of FU issued +system.cpu1.iq.rate 1.398325 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 329 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001447 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 611730 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 244482 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 225916 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 235724 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 227733 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 32768 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 30932 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2551 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2495 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1483 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedStores 1427 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1355 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 6889 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 69 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 278263 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 133 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 79403 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 38032 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1130 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 43 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 1338 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 7175 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 268817 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 146 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 76128 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 36144 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1126 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu1.iew.memOrderViolationEvents 36 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 442 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1069 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1511 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 234388 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 78381 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute +system.cpu1.iew.predictedTakenIncorrect 440 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1052 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1492 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 226425 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 75137 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 979 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 38393 # number of nop insts executed -system.cpu1.iew.exec_refs 115730 # number of memory reference insts executed -system.cpu1.iew.exec_branches 47858 # Number of branches executed -system.cpu1.iew.exec_stores 37349 # Number of stores executed -system.cpu1.iew.exec_rate 1.438864 # Inst execution rate -system.cpu1.iew.wb_sent 234148 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 233879 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 133368 # num instructions producing a value -system.cpu1.iew.wb_consumers 139978 # num instructions consuming a value -system.cpu1.iew.wb_rate 1.435739 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.952778 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 13605 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 4988 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1277 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 154309 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.714761 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.081585 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 36996 # number of nop insts executed +system.cpu1.iew.exec_refs 110644 # number of memory reference insts executed +system.cpu1.iew.exec_branches 46426 # Number of branches executed +system.cpu1.iew.exec_stores 35507 # Number of stores executed +system.cpu1.iew.exec_rate 1.392305 # Inst execution rate +system.cpu1.iew.wb_sent 226182 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 225916 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 128242 # num instructions producing a value +system.cpu1.iew.wb_consumers 134834 # num instructions consuming a value +system.cpu1.iew.wb_rate 1.389175 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.951110 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 13383 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 5429 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1261 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 154086 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.657380 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.063453 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 61394 39.79% 39.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 44430 28.79% 68.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5247 3.40% 71.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 5803 3.76% 75.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1533 0.99% 76.73% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 32828 21.27% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 824 0.53% 98.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 946 0.61% 99.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1304 0.85% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 63982 41.52% 41.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 43006 27.91% 69.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5237 3.40% 72.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 6258 4.06% 76.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1532 0.99% 77.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 30979 20.11% 97.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 844 0.55% 98.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 946 0.61% 99.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1302 0.84% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 154309 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 264603 # Number of instructions committed -system.cpu1.commit.committedOps 264603 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 154086 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 255379 # Number of instructions committed +system.cpu1.commit.committedOps 255379 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 113401 # Number of memory references committed -system.cpu1.commit.loads 76852 # Number of loads committed -system.cpu1.commit.membars 4272 # Number of memory barriers committed -system.cpu1.commit.branches 46786 # Number of branches committed +system.cpu1.commit.refs 108350 # Number of memory references committed +system.cpu1.commit.loads 73633 # Number of loads committed +system.cpu1.commit.membars 4715 # Number of memory barriers committed +system.cpu1.commit.branches 45393 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 182306 # Number of committed integer instructions. +system.cpu1.commit.int_insts 175866 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 37574 14.20% 14.20% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 109356 41.33% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 81124 30.66% 86.19% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 36549 13.81% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 36183 14.17% 14.17% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 106131 41.56% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 78348 30.68% 86.41% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 34717 13.59% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 264603 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1304 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 430627 # The number of ROB reads -system.cpu1.rob.rob_writes 558953 # The number of ROB writes -system.cpu1.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 6052 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.commit.op_class_0::total 255379 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1302 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 420960 # The number of ROB reads +system.cpu1.rob.rob_writes 540023 # The number of ROB writes +system.cpu1.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 6041 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu1.quiesceCycles 45271 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 222757 # Number of Instructions Simulated -system.cpu1.committedOps 222757 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.731281 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.731281 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.367463 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.367463 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 407061 # number of integer regfile reads -system.cpu1.int_regfile_writes 190501 # number of integer regfile writes +system.cpu1.committedInsts 214481 # Number of Instructions Simulated +system.cpu1.committedOps 214481 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.758230 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.758230 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.318860 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.318860 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 391734 # number of integer regfile reads +system.cpu1.int_regfile_writes 183502 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 117378 # number of misc regfile reads +system.cpu1.misc_regfile_reads 112279 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 25.769381 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 42560 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1520 # Average number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 25.736588 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 40830 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1407.931034 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.769381 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050331 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.050331 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.736588 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050267 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.050267 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 328816 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 328816 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 45076 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 45076 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 36319 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 36319 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 81395 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 81395 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 81395 # number of overall hits -system.cpu1.dcache.overall_hits::total 81395 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 515 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 515 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 160 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 160 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 675 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 675 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 675 # number of overall misses -system.cpu1.dcache.overall_misses::total 675 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 10357000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 10357000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3384000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3384000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 705000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 705000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 13741000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 13741000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 13741000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 13741000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 45591 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 45591 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 36479 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 36479 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 82070 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 82070 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 82070 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 82070 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011296 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.011296 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004386 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.004386 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.800000 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.800000 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.008225 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.008225 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.008225 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.008225 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20110.679612 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 20110.679612 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21150 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21150 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 12589.285714 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 12589.285714 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20357.037037 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20357.037037 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20357.037037 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20357.037037 # average overall miss latency +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 315852 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 315852 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 43688 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 43688 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 34492 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 34492 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 17 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 17 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 78180 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 78180 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 78180 # number of overall hits +system.cpu1.dcache.overall_hits::total 78180 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 495 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 495 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 157 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 157 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 51 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 51 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 652 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 652 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 652 # number of overall misses +system.cpu1.dcache.overall_misses::total 652 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8967000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 8967000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3364000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3364000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 599000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 599000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12331000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12331000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12331000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12331000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 44183 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 44183 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 34649 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 34649 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 78832 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 78832 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 78832 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 78832 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011203 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.011203 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004531 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004531 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.750000 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.750000 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.008271 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.008271 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.008271 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.008271 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18115.151515 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 18115.151515 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21426.751592 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21426.751592 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11745.098039 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 11745.098039 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18912.576687 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18912.576687 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18912.576687 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18912.576687 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1185,106 +1186,106 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 349 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 349 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 402 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 402 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 402 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 402 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 273 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 273 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 273 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 273 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2153500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2153500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1760500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1760500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 649000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 649000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3914000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3914000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3914000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3914000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003641 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003641 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002933 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002933 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.800000 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003326 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003326 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003326 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003326 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12972.891566 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12972.891566 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16453.271028 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16453.271028 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 11589.285714 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 11589.285714 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14336.996337 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14336.996337 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14336.996337 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14336.996337 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 331 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 331 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 51 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 51 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 382 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 382 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 382 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 382 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 51 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1988000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1988000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1748500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1748500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 548000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 548000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3736500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3736500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3736500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3736500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003712 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003712 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003059 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003059 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.750000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.750000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003425 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003425 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003425 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003425 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12121.951220 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12121.951220 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16495.283019 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16495.283019 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10745.098039 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10745.098039 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13838.888889 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13838.888889 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13838.888889 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13838.888889 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 383 # number of replacements -system.cpu1.icache.tags.tagsinuse 84.449474 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 19585 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 84.417280 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 20534 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 496 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.485887 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 41.399194 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.449474 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164940 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.164940 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.417280 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164877 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.164877 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 20661 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 20661 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 19585 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 19585 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 19585 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 19585 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 19585 # number of overall hits -system.cpu1.icache.overall_hits::total 19585 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 580 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 580 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 580 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 580 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 580 # number of overall misses -system.cpu1.icache.overall_misses::total 580 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14033000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 14033000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 14033000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 14033000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 14033000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 14033000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 20165 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 20165 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 20165 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 20165 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 20165 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 20165 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028763 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.028763 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028763 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.028763 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028763 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.028763 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24194.827586 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 24194.827586 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24194.827586 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 24194.827586 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24194.827586 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 24194.827586 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 21613 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 21613 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 20534 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 20534 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 20534 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 20534 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 20534 # number of overall hits +system.cpu1.icache.overall_hits::total 20534 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 583 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 583 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 583 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 583 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 583 # number of overall misses +system.cpu1.icache.overall_misses::total 583 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14299500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 14299500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 14299500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 14299500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 14299500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 14299500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 21117 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 21117 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 21117 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 21117 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 21117 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 21117 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027608 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.027608 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027608 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.027608 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027608 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.027608 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24527.444254 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 24527.444254 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24527.444254 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 24527.444254 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24527.444254 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 24527.444254 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -1295,408 +1296,407 @@ system.cpu1.icache.fast_writes 0 # nu system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks::writebacks 383 # number of writebacks system.cpu1.icache.writebacks::total 383 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 84 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 84 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 84 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 84 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 84 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 87 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 87 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 87 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 87 # number of overall MSHR hits system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 496 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 496 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 496 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 496 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 496 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 496 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11668000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 11668000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11668000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 11668000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11668000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 11668000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024597 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024597 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024597 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024597 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024597 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024597 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23524.193548 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23524.193548 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23524.193548 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 23524.193548 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23524.193548 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 23524.193548 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11785500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 11785500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11785500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 11785500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11785500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 11785500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023488 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023488 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023488 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023488 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023488 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023488 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23761.088710 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23761.088710 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23761.088710 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 23761.088710 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23761.088710 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 23761.088710 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 46151 # Number of BP lookups -system.cpu2.branchPred.condPredicted 42669 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1261 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 38744 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 37721 # Number of BTB hits +system.cpu2.branchPred.lookups 51016 # Number of BP lookups +system.cpu2.branchPred.condPredicted 47608 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1273 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 43707 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 42688 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.359591 # BTB Hit Percentage +system.cpu2.branchPred.BTBHitPct 97.668566 # BTB Hit Percentage system.cpu2.branchPred.usedRAS 903 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.numCycles 162526 # number of cpu cycles simulated +system.cpu2.numCycles 162253 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 35053 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 247865 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 46151 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 38624 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 123337 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2679 # Number of cycles fetch has spent squashing +system.cpu2.fetch.icacheStallCycles 31836 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 280333 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 51016 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 43591 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 126252 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2703 # Number of cycles fetch has spent squashing system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1154 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 26088 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 455 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 160896 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.540529 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.092892 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.PendingTrapStallCycles 1153 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 22874 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 441 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 160605 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.745481 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.165535 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 69454 43.17% 43.17% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 47444 29.49% 72.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 8853 5.50% 78.16% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3439 2.14% 80.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 969 0.60% 80.90% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 24720 15.36% 96.26% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1203 0.75% 97.01% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 808 0.50% 97.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 4006 2.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 60810 37.86% 37.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 50841 31.66% 69.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 7311 4.55% 74.07% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3498 2.18% 76.25% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 961 0.60% 76.85% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 31234 19.45% 96.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1226 0.76% 97.06% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 786 0.49% 97.55% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3938 2.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 160896 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.283961 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.525079 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 17877 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 74268 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 63015 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4387 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1339 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 232406 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 1339 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 18566 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 36272 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13923 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 64728 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 26058 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 229231 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 23352 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full +system.cpu2.fetch.rateDist::total 160605 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.314423 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.727752 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 17488 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 62772 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 75260 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 3724 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1351 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 265175 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 1351 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 18185 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 29493 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13900 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 76790 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 20876 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 262017 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 18650 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full system.cpu2.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 159189 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 426806 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 335096 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 145681 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 13508 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1198 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1266 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 30557 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 61312 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 27565 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 29913 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 22477 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 187400 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 8554 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 191519 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 13 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 12551 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10065 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 731 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 160896 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.190328 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.355636 # Number of insts issued each cycle +system.cpu2.rename.RenamedOperands 183428 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 498093 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 388599 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 169446 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 13982 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1189 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1258 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 25354 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 72684 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 33991 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 34917 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 28890 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 216663 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 7106 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 219007 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 13119 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11098 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 687 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 160605 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.363637 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.376138 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 73129 45.45% 45.45% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 27885 17.33% 62.78% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 27023 16.80% 79.58% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 26608 16.54% 96.11% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3367 2.09% 98.21% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1611 1.00% 99.21% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 866 0.54% 99.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 211 0.13% 99.88% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 196 0.12% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 64456 40.13% 40.13% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 23625 14.71% 54.84% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 33318 20.75% 75.59% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 32915 20.49% 96.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3374 2.10% 98.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1611 1.00% 99.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 893 0.56% 99.74% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 212 0.13% 99.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 201 0.13% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 160896 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 160605 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 80 24.02% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 44 13.21% 37.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 209 62.76% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 80 23.32% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 54 15.74% 39.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 209 60.93% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 96792 50.54% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 67722 35.36% 85.90% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 27005 14.10% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 108075 49.35% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 77606 35.44% 84.78% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 33326 15.22% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 191519 # Type of FU issued -system.cpu2.iq.rate 1.178390 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 333 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001739 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 544280 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 208542 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 190032 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 219007 # Type of FU issued +system.cpu2.iq.rate 1.349787 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 343 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001566 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 598981 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 236927 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 217448 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 191852 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 219350 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 22329 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 28643 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2475 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2671 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1441 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1575 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1339 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 9482 # Number of cycles IEW is blocking +system.cpu2.iew.iewSquashCycles 1351 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 8096 # Number of cycles IEW is blocking system.cpu2.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 226726 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 191 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 61312 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 27565 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1142 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewDispatchedInsts 259522 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 168 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 72684 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 33991 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1139 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 430 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1052 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1482 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 190532 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 60316 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 987 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 39 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 443 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1062 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1505 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 217972 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 71586 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1035 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 30772 # number of nop insts executed -system.cpu2.iew.exec_refs 87235 # number of memory reference insts executed -system.cpu2.iew.exec_branches 40210 # Number of branches executed -system.cpu2.iew.exec_stores 26919 # Number of stores executed -system.cpu2.iew.exec_rate 1.172317 # Inst execution rate -system.cpu2.iew.wb_sent 190296 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 190032 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 104798 # num instructions producing a value -system.cpu2.iew.wb_consumers 111375 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.169241 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.940947 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 13298 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 7823 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1261 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 158397 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.347140 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.933730 # Number of insts commited each cycle +system.cpu2.iew.exec_nop 35753 # number of nop insts executed +system.cpu2.iew.exec_refs 104818 # number of memory reference insts executed +system.cpu2.iew.exec_branches 45124 # Number of branches executed +system.cpu2.iew.exec_stores 33232 # Number of stores executed +system.cpu2.iew.exec_rate 1.343408 # Inst execution rate +system.cpu2.iew.wb_sent 217734 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 217448 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 122408 # num instructions producing a value +system.cpu2.iew.wb_consumers 129014 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.340179 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.948796 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 13957 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 6419 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1273 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 158015 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.553777 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.025126 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 80708 50.95% 50.95% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 36780 23.22% 74.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5258 3.32% 77.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 8633 5.45% 82.94% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1531 0.97% 83.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 22393 14.14% 98.05% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 849 0.54% 98.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 955 0.60% 99.19% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1290 0.81% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 70555 44.65% 44.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 41677 26.38% 71.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5250 3.32% 74.35% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 7214 4.57% 78.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1535 0.97% 79.89% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 28695 18.16% 98.05% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 838 0.53% 98.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 950 0.60% 99.18% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1301 0.82% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 158397 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 213383 # Number of instructions committed -system.cpu2.commit.committedOps 213383 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 158015 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 245520 # Number of instructions committed +system.cpu2.commit.committedOps 245520 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 84961 # Number of memory references committed -system.cpu2.commit.loads 58837 # Number of loads committed -system.cpu2.commit.membars 7109 # Number of memory barriers committed -system.cpu2.commit.branches 39190 # Number of branches committed +system.cpu2.commit.refs 102429 # Number of memory references committed +system.cpu2.commit.loads 70013 # Number of loads committed +system.cpu2.commit.membars 5702 # Number of memory barriers committed +system.cpu2.commit.branches 44083 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 146276 # Number of committed integer instructions. +system.cpu2.commit.int_insts 168630 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 29980 14.05% 14.05% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 91333 42.80% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 65946 30.90% 87.76% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 26124 12.24% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 34870 14.20% 14.20% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 102519 41.76% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 75715 30.84% 86.80% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 32416 13.20% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 213383 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1290 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 383202 # The number of ROB reads -system.cpu2.rob.rob_writes 455861 # The number of ROB writes -system.cpu2.timesIdled 213 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1630 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.commit.op_class_0::total 245520 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1301 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 415605 # The number of ROB reads +system.cpu2.rob.rob_writes 521544 # The number of ROB writes +system.cpu2.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1648 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu2.quiesceCycles 45643 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 176294 # Number of Instructions Simulated -system.cpu2.committedOps 176294 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.921903 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.921903 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.084713 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.084713 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 321409 # number of integer regfile reads -system.cpu2.int_regfile_writes 151400 # number of integer regfile writes +system.cpu2.committedInsts 204948 # Number of Instructions Simulated +system.cpu2.committedOps 204948 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.791679 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.791679 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.263138 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.263138 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 374158 # number of integer regfile reads +system.cpu2.int_regfile_writes 175347 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 88848 # number of misc regfile reads +system.cpu2.misc_regfile_reads 106430 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 23.120660 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 32242 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1111.793103 # Average number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 23.147052 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 38440 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1372.857143 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.120660 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045158 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.045158 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.147052 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045209 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.045209 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 256599 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 256599 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 37491 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 37491 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 25903 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 25903 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 19 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 19 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 63394 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 63394 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 63394 # number of overall hits -system.cpu2.dcache.overall_hits::total 63394 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 473 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 473 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 153 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 153 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 49 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 49 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 626 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 626 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 626 # number of overall misses -system.cpu2.dcache.overall_misses::total 626 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7957500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 7957500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3701500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 3701500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 605000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 605000 # 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number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 64020 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 64020 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 64020 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.012459 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.012459 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.005872 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.005872 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.720588 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.720588 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.009778 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.009778 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.009778 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.009778 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16823.467230 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 16823.467230 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24192.810458 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 24192.810458 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 12346.938776 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 12346.938776 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 18624.600639 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 18624.600639 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 18624.600639 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 18624.600639 # average overall miss latency +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 301603 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 301603 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 42391 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42391 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 32186 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 32186 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 74577 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 74577 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 74577 # number of overall hits +system.cpu2.dcache.overall_hits::total 74577 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 529 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 529 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 159 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 159 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 688 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 688 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 688 # number of overall misses +system.cpu2.dcache.overall_misses::total 688 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 8601000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 8601000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3593000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 3593000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 655000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 655000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 12194000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 12194000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 12194000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 12194000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 42920 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 42920 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 32345 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 32345 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 75265 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 75265 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 75265 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 75265 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.012325 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.012325 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004916 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004916 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.816901 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.009141 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.009141 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.009141 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.009141 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16258.979206 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 16258.979206 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22597.484277 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 22597.484277 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 11293.103448 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 11293.103448 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17723.837209 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17723.837209 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17723.837209 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17723.837209 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1705,106 +1705,106 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 311 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 50 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 50 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 361 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 361 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 361 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 361 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 103 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 49 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 49 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 265 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 265 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1647500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1647500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1967500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1967500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 556000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 556000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3615000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3615000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3615000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3615000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004267 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004267 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003953 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003953 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.720588 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.720588 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004139 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004139 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004139 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004139 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10169.753086 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10169.753086 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19101.941748 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19101.941748 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 11346.938776 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 11346.938776 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13641.509434 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13641.509434 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13641.509434 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13641.509434 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 359 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 359 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 53 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 412 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 412 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 412 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 412 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 170 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 276 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 276 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 276 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1653000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1653000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1845000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1845000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 597000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 597000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3498000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3498000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3498000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3498000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003961 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003961 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003277 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003277 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.816901 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003667 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003667 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003667 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003667 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9723.529412 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9723.529412 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 17405.660377 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 17405.660377 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 10293.103448 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 10293.103448 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12673.913043 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12673.913043 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12673.913043 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12673.913043 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 386 # number of replacements -system.cpu2.icache.tags.tagsinuse 77.580266 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 25515 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 77.661611 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 22304 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 500 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 51.030000 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 44.608000 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 77.580266 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.151524 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.151524 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_blocks::cpu2.inst 77.661611 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.151683 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.151683 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu2.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 26588 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 26588 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 25515 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 25515 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 25515 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 25515 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 25515 # number of overall hits -system.cpu2.icache.overall_hits::total 25515 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 573 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 573 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 573 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 573 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 573 # number of overall misses -system.cpu2.icache.overall_misses::total 573 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7955500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 7955500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 7955500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 7955500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 7955500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 7955500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 26088 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 26088 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 26088 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 26088 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 26088 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 26088 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.021964 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.021964 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.021964 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.021964 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.021964 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.021964 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13883.944154 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 13883.944154 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13883.944154 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 13883.944154 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13883.944154 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 13883.944154 # average overall miss latency +system.cpu2.icache.tags.tag_accesses 23374 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 23374 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 22304 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 22304 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 22304 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 22304 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 22304 # number of overall hits +system.cpu2.icache.overall_hits::total 22304 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 570 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 570 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 570 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 570 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 570 # number of overall misses +system.cpu2.icache.overall_misses::total 570 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8095000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 8095000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 8095000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 8095000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 8095000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 8095000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 22874 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 22874 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 22874 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 22874 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 22874 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 22874 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024919 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.024919 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024919 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.024919 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024919 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.024919 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14201.754386 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 14201.754386 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14201.754386 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 14201.754386 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14201.754386 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 14201.754386 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1815,407 +1815,407 @@ system.cpu2.icache.fast_writes 0 # nu system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.writebacks::writebacks 386 # number of writebacks system.cpu2.icache.writebacks::total 386 # number of writebacks -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 73 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 73 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 73 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 73 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 70 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 70 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 70 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 70 # number of overall MSHR hits system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 500 # number of ReadReq MSHR misses system.cpu2.icache.ReadReq_mshr_misses::total 500 # number of ReadReq MSHR misses system.cpu2.icache.demand_mshr_misses::cpu2.inst 500 # number of demand (read+write) MSHR misses system.cpu2.icache.demand_mshr_misses::total 500 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 500 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 500 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6895000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 6895000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6895000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 6895000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6895000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 6895000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.019166 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.019166 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.019166 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.019166 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.019166 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.019166 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13790 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13790 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13790 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 13790 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13790 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 13790 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7049500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 7049500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7049500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 7049500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7049500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 7049500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021859 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021859 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021859 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.021859 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021859 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.021859 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 14099 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 14099 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 14099 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 14099 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 14099 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 14099 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 52678 # Number of BP lookups -system.cpu3.branchPred.condPredicted 49211 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1284 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 45275 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 44303 # Number of BTB hits +system.cpu3.branchPred.lookups 49230 # Number of BP lookups +system.cpu3.branchPred.condPredicted 45728 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1271 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 41796 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 40803 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 97.853120 # BTB Hit Percentage +system.cpu3.branchPred.BTBHitPct 97.624175 # BTB Hit Percentage system.cpu3.branchPred.usedRAS 906 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.numCycles 162161 # number of cpu cycles simulated +system.cpu3.numCycles 161890 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 30846 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 291154 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 52678 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 45209 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 126827 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 2723 # Number of cycles fetch has spent squashing +system.cpu3.fetch.icacheStallCycles 32992 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 268412 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 49230 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 41709 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 124419 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 2697 # Number of cycles fetch has spent squashing system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1166 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 21882 # Number of cache lines fetched +system.cpu3.fetch.PendingTrapStallCycles 1165 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 24017 # Number of cache lines fetched system.cpu3.fetch.IcacheSquashes 451 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 160213 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.817293 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.188011 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::samples 159937 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.678236 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.146445 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 57700 36.01% 36.01% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 51927 32.41% 68.43% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 6814 4.25% 72.68% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3535 2.21% 74.89% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 932 0.58% 75.47% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 33301 20.79% 96.25% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1242 0.78% 97.03% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 787 0.49% 97.52% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3975 2.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 63357 39.61% 39.61% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 49486 30.94% 70.55% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 7847 4.91% 75.46% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3455 2.16% 77.62% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 942 0.59% 78.21% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 28830 18.03% 96.24% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1207 0.75% 96.99% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 797 0.50% 97.49% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 4016 2.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 160213 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.324850 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.795463 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 17433 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 58368 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 79576 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 3465 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 1361 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 275763 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 1361 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 18155 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 26788 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 14101 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 81078 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 18720 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 272367 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 16743 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full +system.cpu3.fetch.rateDist::total 159937 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.304095 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.657990 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 17620 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 66098 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 70935 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 3926 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 1348 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 252986 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 1348 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 18323 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 31370 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 13970 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 72885 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 22031 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 249675 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 20026 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 191251 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 520897 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 405695 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 177247 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 14004 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1196 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1267 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 23402 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 76309 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 36069 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 36463 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 30962 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 226032 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 6585 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 227862 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 13 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 13164 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 10986 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 709 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 160213 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.422244 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.377526 # Number of insts issued each cycle +system.cpu3.rename.RenamedOperands 174506 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 471658 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 368736 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 160859 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 13647 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1202 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1275 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 26657 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 68456 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 31644 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 33001 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 26549 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 205848 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 7559 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 208921 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 12739 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10220 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 712 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 159937 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.306271 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.372225 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 61467 38.37% 38.37% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 22016 13.74% 52.11% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 35438 22.12% 74.23% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 35000 21.85% 96.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3395 2.12% 98.19% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1603 1.00% 99.19% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 883 0.55% 99.74% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 211 0.13% 99.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 200 0.12% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 67005 41.89% 41.89% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 24940 15.59% 57.49% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 31075 19.43% 76.92% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 30637 19.16% 96.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3376 2.11% 98.18% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1620 1.01% 99.20% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 871 0.54% 99.74% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 214 0.13% 99.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 199 0.12% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 160213 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 159937 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 82 24.12% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 49 14.41% 38.53% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 209 61.47% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 82 24.70% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 41 12.35% 37.05% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 209 62.95% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 111773 49.05% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 80677 35.41% 84.46% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 35412 15.54% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 103999 49.78% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 73864 35.35% 85.13% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 31058 14.87% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 227862 # Type of FU issued -system.cpu3.iq.rate 1.405159 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 340 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001492 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 616290 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 245818 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 226322 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 208921 # Type of FU issued +system.cpu3.iq.rate 1.290512 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 332 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001589 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 578115 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 226182 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 207437 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 228202 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 209253 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 30727 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 26373 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2667 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2521 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1566 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1480 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 1361 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 7576 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 269910 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 166 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 76309 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 36069 # Number of dispatched store instructions +system.cpu3.iew.iewSquashCycles 1348 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 8395 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 63 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 247262 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 160 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 68456 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 31644 # Number of dispatched store instructions system.cpu3.iew.iewDispNonSpecInsts 1148 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 41 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 37 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 452 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1067 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1519 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 226838 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 75201 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1024 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 36 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 438 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1065 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 207928 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 67431 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 993 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 37293 # number of nop insts executed -system.cpu3.iew.exec_refs 110524 # number of memory reference insts executed -system.cpu3.iew.exec_branches 46686 # Number of branches executed -system.cpu3.iew.exec_stores 35323 # Number of stores executed -system.cpu3.iew.exec_rate 1.398844 # Inst execution rate -system.cpu3.iew.wb_sent 226605 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 226322 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 128132 # num instructions producing a value -system.cpu3.iew.wb_consumers 134738 # num instructions consuming a value -system.cpu3.iew.wb_rate 1.395662 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.950972 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 13998 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 5876 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1284 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 157615 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.623367 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.050526 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 33855 # number of nop insts executed +system.cpu3.iew.exec_refs 98404 # number of memory reference insts executed +system.cpu3.iew.exec_branches 43312 # Number of branches executed +system.cpu3.iew.exec_stores 30973 # Number of stores executed +system.cpu3.iew.exec_rate 1.284378 # Inst execution rate +system.cpu3.iew.wb_sent 207701 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 207437 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 116002 # num instructions producing a value +system.cpu3.iew.wb_consumers 122598 # num instructions consuming a value +system.cpu3.iew.wb_rate 1.281345 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.946198 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 13505 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 6847 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1271 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 157409 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.484744 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.997930 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 67043 42.54% 42.54% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 43238 27.43% 69.97% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5262 3.34% 73.31% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 6673 4.23% 77.54% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1534 0.97% 78.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 30788 19.53% 98.05% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 827 0.52% 98.57% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 952 0.60% 99.18% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1298 0.82% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 73609 46.76% 46.76% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 39844 25.31% 72.08% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5242 3.33% 75.41% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 7652 4.86% 80.27% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1542 0.98% 81.25% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 26417 16.78% 98.03% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 849 0.54% 98.57% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 951 0.60% 99.17% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1303 0.83% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 157615 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 255867 # Number of instructions committed -system.cpu3.commit.committedOps 255867 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 157409 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 233712 # Number of instructions committed +system.cpu3.commit.committedOps 233712 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 108145 # Number of memory references committed -system.cpu3.commit.loads 73642 # Number of loads committed -system.cpu3.commit.membars 5159 # Number of memory barriers committed -system.cpu3.commit.branches 45627 # Number of branches committed +system.cpu3.commit.refs 96099 # Number of memory references committed +system.cpu3.commit.loads 65935 # Number of loads committed +system.cpu3.commit.membars 6131 # Number of memory barriers committed +system.cpu3.commit.branches 42256 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 175889 # Number of committed integer instructions. +system.cpu3.commit.int_insts 160475 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 36414 14.23% 14.23% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 106149 41.49% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 78801 30.80% 86.52% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 34503 13.48% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 33044 14.14% 14.14% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 98438 42.12% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 72066 30.84% 87.09% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 30164 12.91% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 255867 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1298 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 425596 # The number of ROB reads -system.cpu3.rob.rob_writes 542328 # The number of ROB writes -system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1948 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.commit.op_class_0::total 233712 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1303 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 402737 # The number of ROB reads +system.cpu3.rob.rob_writes 496962 # The number of ROB writes +system.cpu3.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1953 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu3.quiesceCycles 46007 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 214294 # Number of Instructions Simulated -system.cpu3.committedOps 214294 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 0.756722 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.756722 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.321489 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.321489 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 391365 # number of integer regfile reads -system.cpu3.int_regfile_writes 183208 # number of integer regfile writes +system.cpu3.committedInsts 194537 # Number of Instructions Simulated +system.cpu3.committedOps 194537 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.832181 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.832181 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.201662 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.201662 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 355006 # number of integer regfile reads +system.cpu3.int_regfile_writes 166699 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 112150 # number of misc regfile reads +system.cpu3.misc_regfile_reads 100037 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 24.277315 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 40522 # Total number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 24.251319 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 36167 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1447.214286 # Average number of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1291.678571 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.277315 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047417 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.047417 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.251319 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047366 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.047366 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 316074 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 316074 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 43937 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 43937 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 34273 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 34273 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 78210 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 78210 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 78210 # number of overall hits -system.cpu3.dcache.overall_hits::total 78210 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 514 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 514 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 159 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 159 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 673 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 673 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 673 # number of overall misses -system.cpu3.dcache.overall_misses::total 673 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 9349000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 9349000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3790500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 3790500 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 680500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 680500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 13139500 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 13139500 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 13139500 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 13139500 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 44451 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 44451 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 34432 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 34432 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 78883 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 78883 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 78883 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 78883 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.011563 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.011563 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004618 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.004618 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008532 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.008532 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008532 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.008532 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 18188.715953 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 18188.715953 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23839.622642 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 23839.622642 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 11938.596491 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 11938.596491 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 19523.774146 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 19523.774146 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 19523.774146 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 19523.774146 # average overall miss latency +system.cpu3.dcache.tags.tag_accesses 285043 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 285043 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 40546 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 40546 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 29945 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 29945 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 17 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 17 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 70491 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 70491 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 70491 # number of overall hits +system.cpu3.dcache.overall_hits::total 70491 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 489 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 489 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 149 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 149 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 53 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 53 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 638 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 638 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 638 # number of overall misses +system.cpu3.dcache.overall_misses::total 638 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8138500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 8138500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3781500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3781500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 606500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 606500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 11920000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 11920000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 11920000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 11920000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41035 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41035 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 30094 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 30094 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 71129 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 71129 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 71129 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 71129 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.011917 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.011917 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004951 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.004951 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.757143 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.757143 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008970 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.008970 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008970 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.008970 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16643.149284 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 16643.149284 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25379.194631 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 25379.194631 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 11443.396226 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 11443.396226 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18683.385580 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 18683.385580 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18683.385580 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 18683.385580 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2224,106 +2224,106 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 347 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 347 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 52 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 399 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 399 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 399 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 399 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 167 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 274 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 274 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1719000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1719000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2129500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2129500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 623500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 623500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3848500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3848500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3848500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3848500 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003757 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003757 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003108 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003108 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003473 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003473 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003473 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003473 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10293.413174 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10293.413174 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19901.869159 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19901.869159 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 10938.596491 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 10938.596491 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14045.620438 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14045.620438 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14045.620438 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14045.620438 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 328 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 328 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 46 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 46 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 374 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 374 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 161 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 103 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 53 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 264 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 264 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 264 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1609000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1609000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2139500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2139500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 553500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 553500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3748500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3748500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3748500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3748500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003923 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003923 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003423 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003423 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.757143 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.757143 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003712 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003712 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003712 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003712 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9993.788820 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9993.788820 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 20771.844660 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 20771.844660 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 10443.396226 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 10443.396226 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14198.863636 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14198.863636 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14198.863636 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14198.863636 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 384 # number of replacements -system.cpu3.icache.tags.tagsinuse 81.046367 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 21310 # Total number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 80.879647 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 23443 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 42.791165 # Average number of references to valid blocks. +system.cpu3.icache.tags.avg_refs 47.074297 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 81.046367 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.158294 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.158294 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 80.879647 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.157968 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.157968 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 22380 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 22380 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 21310 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 21310 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 21310 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 21310 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 21310 # number of overall hits -system.cpu3.icache.overall_hits::total 21310 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 572 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 572 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 572 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 572 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 572 # number of overall misses -system.cpu3.icache.overall_misses::total 572 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 8104500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 8104500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 8104500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 8104500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 8104500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 8104500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 21882 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 21882 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 21882 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 21882 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 21882 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 21882 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.026140 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.026140 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.026140 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.026140 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.026140 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.026140 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14168.706294 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 14168.706294 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14168.706294 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 14168.706294 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14168.706294 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 14168.706294 # average overall miss latency +system.cpu3.icache.tags.tag_accesses 24515 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 24515 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 23443 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 23443 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 23443 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 23443 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 23443 # number of overall hits +system.cpu3.icache.overall_hits::total 23443 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 574 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 574 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 574 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 574 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 574 # number of overall misses +system.cpu3.icache.overall_misses::total 574 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7717500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 7717500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 7717500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 7717500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 7717500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 7717500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 24017 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 24017 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 24017 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 24017 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 24017 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 24017 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023900 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.023900 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023900 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.023900 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023900 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.023900 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13445.121951 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13445.121951 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13445.121951 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13445.121951 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13445.121951 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13445.121951 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2334,66 +2334,66 @@ system.cpu3.icache.fast_writes 0 # nu system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.writebacks::writebacks 384 # number of writebacks system.cpu3.icache.writebacks::total 384 # number of writebacks -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 74 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 74 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 74 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 74 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 76 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 76 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 76 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 76 # number of overall MSHR hits system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 498 # number of ReadReq MSHR misses system.cpu3.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6912000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 6912000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6912000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 6912000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6912000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 6912000 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.022758 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.022758 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.022758 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.022758 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.022758 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.022758 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13879.518072 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13879.518072 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13879.518072 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 13879.518072 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13879.518072 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 13879.518072 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6640500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 6640500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6640500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 6640500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6640500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 6640500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020735 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020735 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020735 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.020735 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020735 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.020735 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13334.337349 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13334.337349 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13334.337349 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 13334.337349 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13334.337349 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 13334.337349 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 419.218954 # Cycle average of tags in use +system.l2c.tags.tagsinuse 419.138543 # Cycle average of tags in use system.l2c.tags.total_refs 2347 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 532 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 4.411654 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.788461 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 288.048945 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.083381 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 60.484959 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 5.324168 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2.350458 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 0.677584 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2.742702 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.718294 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.788194 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 288.006073 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.075910 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 61.760427 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 5.322052 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2.559109 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.677187 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 1.231634 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.717957 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.004395 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.000886 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000923 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000942 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000081 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000039 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.000010 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000019 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.006397 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.006396 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 141 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 138 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.008118 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 25618 # Number of tag accesses system.l2c.tags.data_accesses 25618 # Number of data accesses @@ -2404,9 +2404,9 @@ system.l2c.WritebackClean_hits::total 676 # nu system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits system.l2c.ReadCleanReq_hits::cpu0.inst 246 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 412 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 491 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 489 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 410 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 489 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 493 # number of ReadCleanReq hits system.l2c.ReadCleanReq_hits::total 1638 # number of ReadCleanReq hits system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits @@ -2415,26 +2415,26 @@ system.l2c.ReadSharedReq_hits::cpu3.data 11 # nu system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.inst 246 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 410 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 491 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 489 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 489 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 493 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits system.l2c.demand_hits::total 1670 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 246 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 412 # 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number of overall miss cycles +system.l2c.overall_miss_latency::total 53244500 # number of overall miss cycles system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackClean_accesses::writebacks 676 # number of WritebackClean accesses(hits+misses) system.l2c.WritebackClean_accesses::total 676 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu2.data 21 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 21 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 22 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 92 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) @@ -2555,9 +2555,9 @@ system.l2c.ReadExReq_miss_rate::cpu2.data 1 # m system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.595395 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.169355 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.018000 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.018072 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173387 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.022000 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.010040 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::total 0.220742 # miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadSharedReq accesses @@ -2566,55 +2566,55 @@ system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.083333 system.l2c.ReadSharedReq_miss_rate::total 0.724138 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.595395 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.169355 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.173387 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.018000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.022000 # 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number of ReadExReq MSHR misses @@ -2649,9 +2649,9 @@ system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 361 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 80 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 3 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 7 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 82 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 6 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 2 # number of ReadCleanReq MSHR misses system.l2c.ReadCleanReq_mshr_misses::total 451 # number of ReadCleanReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.data 75 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1162500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 145500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 1371000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 45737000 # number of overall MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.900000 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses @@ -2725,9 +2725,9 @@ system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.161290 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.014056 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.012000 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_mshr_miss_rate::total 0.214558 # mshr miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadSharedReq accesses @@ -2736,129 +2736,128 @@ system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.083333 system.l2c.ReadSharedReq_mshr_miss_rate::total 0.724138 # mshr miss rate for ReadSharedReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161290 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012000 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.014056 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # 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average ReadCleanReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69753.333333 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 67142.857143 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 86500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69767.857143 # average ReadSharedReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66174.515235 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 70428.994083 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66068.750000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 70497.041420 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66091.463415 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69950 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 89461.538462 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 70785.714286 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 105038.461538 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 68647.147147 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 89423.076923 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 72750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 105461.538462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 68674.174174 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66174.515235 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70428.994083 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66068.750000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70497.041420 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66091.463415 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69950 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 89461.538462 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 70785.714286 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 105038.461538 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 68647.147147 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 89423.076923 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 105461.538462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 68674.174174 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 534 # Transaction distribution -system.membus.trans_dist::UpgradeReq 290 # Transaction distribution -system.membus.trans_dist::UpgradeResp 89 # Transaction distribution -system.membus.trans_dist::ReadExReq 162 # Transaction distribution +system.membus.trans_dist::UpgradeReq 291 # Transaction distribution +system.membus.trans_dist::ReadExReq 159 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution system.membus.trans_dist::ReadSharedReq 535 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1741 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1741 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1650 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1650 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42560 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 42560 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 232 # Total snoops (count) -system.membus.snoop_fanout::samples 987 # Request fanout histogram +system.membus.snoops 230 # Total snoops (count) +system.membus.snoop_fanout::samples 985 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 987 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 985 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 987 # Request fanout histogram -system.membus.reqLayer0.occupancy 936504 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 985 # Request fanout histogram +system.membus.reqLayer0.occupancy 928501 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 3712661 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.4 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4933 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1339 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2364 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.respLayer1.occupancy 3534750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.3 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 4931 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1335 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2366 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadResp 2778 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2779 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 676 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1468 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 293 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 293 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 391 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 391 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 294 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 294 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 387 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 387 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 2102 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 677 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1448 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 592 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1140 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 374 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1151 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 360 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1140 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 376 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6581 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 53760 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadSharedReq 678 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1530 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 593 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1375 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1386 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 379 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1380 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 363 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7371 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 59008 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41216 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 56256 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 56704 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41088 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 193600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1022 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3463 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.289633 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.182691 # Request fanout histogram +system.toL2Bus.pkt_size::total 244288 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1020 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3461 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.293268 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.185819 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1230 35.52% 35.52% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 835 24.11% 59.63% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 563 16.26% 75.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 835 24.11% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1230 35.54% 35.54% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 830 23.98% 59.52% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 557 16.09% 75.61% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 844 24.39% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram @@ -2867,24 +2866,24 @@ system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3463 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3953462 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3461 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3950967 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 3.7 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 911498 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) system.toL2Bus.respLayer1.occupancy 505495 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 746495 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 746494 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 439455 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 429965 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 752991 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 752493 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 419474 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 440466 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 747998 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 748497 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 434475 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 422962 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 903a3bff1..1d3cbd064 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140858 # Simulator instruction rate (inst/s) -host_op_rate 140857 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18239325 # Simulator tick rate (ticks/s) -host_mem_usage 243264 # Number of bytes of host memory used -host_seconds 4.81 # Real time elapsed on the host +host_inst_rate 1830828 # Simulator instruction rate (inst/s) +host_op_rate 1830758 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 237054275 # Simulator tick rate (ticks/s) +host_mem_usage 306784 # Number of bytes of host memory used +host_seconds 0.37 # Real time elapsed on the host sim_insts 677333 # Number of instructions simulated sim_ops 677333 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -750,14 +750,14 @@ system.cpu3.icache.writebacks::writebacks 279 # n system.cpu3.icache.writebacks::total 279 # number of writebacks system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 366.582953 # Cycle average of tags in use +system.l2c.tags.tagsinuse 367.545675 # Cycle average of tags in use system.l2c.tags.total_refs 1716 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.076010 # Average number of references to valid blocks. +system.l2c.tags.sampled_refs 422 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.066351 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 55.207589 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 56.170311 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.data 6.721185 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor @@ -766,18 +766,18 @@ system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Av system.l2c.tags.occ_blocks::cpu3.data 0.905646 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000857 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id +system.l2c.tags.occ_percent::total 0.005608 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 422 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.006424 # Percentage of cache occupancy per task id +system.l2c.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.006439 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 19424 # Number of tag accesses system.l2c.tags.data_accesses 19424 # Number of data accesses system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits @@ -944,24 +944,24 @@ system.l2c.no_allocate_misses 0 # Nu system.membus.trans_dist::ReadResp 423 # Transaction distribution system.membus.trans_dist::UpgradeReq 273 # Transaction distribution system.membus.trans_dist::UpgradeResp 80 # Transaction distribution -system.membus.trans_dist::ReadExReq 412 # Transaction distribution +system.membus.trans_dist::ReadExReq 183 # Transaction distribution system.membus.trans_dist::ReadExResp 136 # Transaction distribution system.membus.trans_dist::ReadSharedReq 423 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1747 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1747 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1518 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1518 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1108 # Request fanout histogram +system.membus.snoop_fanout::samples 879 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1108 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 879 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1108 # Request fanout histogram +system.membus.snoop_fanout::total 879 # Request fanout histogram system.toL2Bus.snoop_filter.tot_requests 3918 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 1221 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 1709 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -970,7 +970,7 @@ system.toL2Bus.snoop_filter.hit_single_snoops 0 system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 495 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1050 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution @@ -978,24 +978,24 @@ system.toL2Bus.trans_dist::ReadExReq 412 # Tr system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1542 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 637 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 712 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 838 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 830 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 834 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 997 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6229 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39040 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6784 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 30208 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 30400 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 197568 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 233088 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 0 # Total snoops (count) system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 1.246554 # Request fanout histogram diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 813d17b05..eb0bc0573 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,91 +1,91 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000265 # Number of seconds simulated -sim_ticks 264840500 # Number of ticks simulated -final_tick 264840500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000264 # Number of seconds simulated +sim_ticks 263565500 # Number of ticks simulated +final_tick 263565500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 127010 # Simulator instruction rate (inst/s) -host_op_rate 127009 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50783237 # Simulator tick rate (ticks/s) -host_mem_usage 243272 # Number of bytes of host memory used -host_seconds 5.22 # Real time elapsed on the host -sim_insts 662366 # Number of instructions simulated -sim_ops 662366 # Number of ops (including micro ops) simulated +host_inst_rate 798172 # Simulator instruction rate (inst/s) +host_op_rate 798158 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 317271660 # Simulator tick rate (ticks/s) +host_mem_usage 306776 # Number of bytes of host memory used +host_seconds 0.83 # Real time elapsed on the host +sim_insts 663039 # Number of instructions simulated +sim_ops 663039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 3712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 3456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory system.physmem.bytes_read::total 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 3712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 3456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 320 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 58 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 54 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 22 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 68871642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 39873056 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 1691584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3624823 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 14015983 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 5558062 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 966620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3624823 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 138226593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 68871642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 1691584 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 14015983 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 966620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 85545829 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 68871642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 39873056 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 1691584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3624823 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 14015983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 5558062 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 966620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3624823 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 138226593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 69204809 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40065942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 2428239 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3642358 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 13112490 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 5342126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1214119 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3885182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 138895265 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69204809 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 2428239 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 13112490 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1214119 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 85959657 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69204809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40065942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 2428239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3642358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 13112490 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 5342126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1214119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3885182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 138895265 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 529681 # number of cpu cycles simulated +system.cpu0.numCycles 527131 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 158238 # Number of instructions committed -system.cpu0.committedOps 158238 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 108984 # Number of integer alu accesses +system.cpu0.committedInsts 158196 # Number of instructions committed +system.cpu0.committedOps 158196 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 108956 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 25976 # number of instructions that are conditional controls -system.cpu0.num_int_insts 108984 # number of integer instructions +system.cpu0.num_conditional_control_insts 25969 # number of instructions that are conditional controls +system.cpu0.num_int_insts 108956 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 315110 # number of times the integer registers were read -system.cpu0.num_int_register_writes 110590 # number of times the integer registers were written +system.cpu0.num_int_register_reads 315026 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110562 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 73853 # number of memory refs -system.cpu0.num_load_insts 48895 # Number of load instructions -system.cpu0.num_store_insts 24958 # Number of store instructions +system.cpu0.num_mem_refs 73832 # number of memory refs +system.cpu0.num_load_insts 48881 # Number of load instructions +system.cpu0.num_store_insts 24951 # Number of store instructions system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu0.num_busy_cycles 529680.998000 # Number of busy cycles +system.cpu0.num_busy_cycles 527130.998000 # Number of busy cycles system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu0.Branches 26841 # Number of branches fetched -system.cpu0.op_class::No_OpClass 23568 14.89% 14.89% # Class of executed instruction -system.cpu0.op_class::IntAlu 60795 38.40% 53.29% # Class of executed instruction +system.cpu0.Branches 26834 # Number of branches fetched +system.cpu0.op_class::No_OpClass 23561 14.89% 14.89% # Class of executed instruction +system.cpu0.op_class::IntAlu 60781 38.41% 53.29% # Class of executed instruction system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction @@ -114,36 +114,36 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::MemRead 48979 30.94% 84.23% # Class of executed instruction -system.cpu0.op_class::MemWrite 24958 15.77% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 48965 30.94% 84.23% # Class of executed instruction +system.cpu0.op_class::MemWrite 24951 15.77% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 158300 # Class of executed instruction +system.cpu0.op_class::total 158258 # Class of executed instruction system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 145.090849 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 73323 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 145.050771 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 73302 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 439.059880 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 438.934132 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.090849 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283381 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.283381 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.050771 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283302 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.283302 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 295643 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 295643 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 48717 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 48717 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 24724 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 24724 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 295559 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 295559 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 48703 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48703 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 24717 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 24717 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 73441 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 73441 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 73441 # number of overall hits -system.cpu0.dcache.overall_hits::total 73441 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 73420 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 73420 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 73420 # number of overall hits +system.cpu0.dcache.overall_hits::total 73420 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 168 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 168 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses @@ -154,46 +154,46 @@ system.cpu0.dcache.demand_misses::cpu0.data 351 # system.cpu0.dcache.demand_misses::total 351 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 351 # number of overall misses system.cpu0.dcache.overall_misses::total 351 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5149000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5149000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7867000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7867000 # number of WriteReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4817500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4817500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6985500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6985500 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 395000 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 395000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 13016000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 13016000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 13016000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 13016000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 48885 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 48885 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 24907 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 24907 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 11803000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11803000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11803000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11803000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48871 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48871 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24900 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24900 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 73792 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 73792 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 73792 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 73792 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003437 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007347 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007347 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 73771 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73771 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73771 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73771 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003438 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003438 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007349 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007349 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004757 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004757 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004757 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004757 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30648.809524 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 30648.809524 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42989.071038 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42989.071038 # average WriteReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004758 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004758 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004758 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004758 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28675.595238 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28675.595238 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38172.131148 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38172.131148 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15192.307692 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 15192.307692 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37082.621083 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 37082.621083 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37082.621083 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 37082.621083 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33626.780627 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33626.780627 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33626.780627 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33626.780627 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -214,88 +214,88 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 351 system.cpu0.dcache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 351 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4981000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4981000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7684000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7684000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4649500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4649500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6802500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6802500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 369000 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 369000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12665000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12665000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12665000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12665000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003437 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003437 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007347 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007347 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11452000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11452000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11452000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11452000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003438 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003438 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007349 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007349 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004757 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004757 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004757 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004757 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29648.809524 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29648.809524 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41989.071038 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41989.071038 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004758 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004758 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004758 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004758 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27675.595238 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27675.595238 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37172.131148 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37172.131148 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14192.307692 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14192.307692 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36082.621083 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 36082.621083 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36082.621083 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 36082.621083 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32626.780627 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32626.780627 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32626.780627 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32626.780627 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 211.456411 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 157834 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 211.380247 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 157792 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 337.974304 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 337.884368 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.456411 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.413001 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.413001 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.380247 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.412852 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.412852 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 158768 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 158768 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 157834 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 157834 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 157834 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 157834 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 157834 # number of overall hits -system.cpu0.icache.overall_hits::total 157834 # number of overall hits +system.cpu0.icache.tags.tag_accesses 158726 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 158726 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 157792 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 157792 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 157792 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 157792 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 157792 # number of overall hits +system.cpu0.icache.overall_hits::total 157792 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20139500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 20139500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 20139500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 20139500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 20139500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 20139500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 158301 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 158301 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 158301 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 158301 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 158301 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 158301 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002950 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002950 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002950 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002950 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002950 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002950 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43125.267666 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 43125.267666 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43125.267666 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 43125.267666 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43125.267666 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 43125.267666 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20140500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 20140500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 20140500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 20140500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 20140500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 20140500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 158259 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 158259 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 158259 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 158259 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 158259 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 158259 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002951 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002951 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002951 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002951 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002951 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002951 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43127.408994 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 43127.408994 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43127.408994 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 43127.408994 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43127.408994 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 43127.408994 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -312,158 +312,158 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19672500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 19672500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19672500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 19672500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19672500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 19672500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002950 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002950 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002950 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42125.267666 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 42125.267666 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 42125.267666 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19673500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 19673500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19673500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 19673500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19673500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 19673500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002951 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002951 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002951 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.002951 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002951 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.002951 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42127.408994 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42127.408994 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42127.408994 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 42127.408994 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42127.408994 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 42127.408994 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 529680 # number of cpu cycles simulated +system.cpu1.numCycles 527130 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 168829 # Number of instructions committed -system.cpu1.committedOps 168829 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 111193 # Number of integer alu accesses +system.cpu1.committedInsts 170790 # Number of instructions committed +system.cpu1.committedOps 170790 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 110708 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 32827 # number of instructions that are conditional controls -system.cpu1.num_int_insts 111193 # number of integer instructions +system.cpu1.num_conditional_control_insts 34050 # number of instructions that are conditional controls +system.cpu1.num_int_insts 110708 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 275699 # number of times the integer registers were read -system.cpu1.num_int_register_writes 104505 # number of times the integer registers were written +system.cpu1.num_int_register_reads 268858 # number of times the integer registers were read +system.cpu1.num_int_register_writes 101318 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 54535 # number of memory refs -system.cpu1.num_load_insts 41264 # Number of load instructions -system.cpu1.num_store_insts 13271 # Number of store instructions -system.cpu1.num_idle_cycles 73879.862241 # Number of idle cycles -system.cpu1.num_busy_cycles 455800.137759 # Number of busy cycles -system.cpu1.not_idle_fraction 0.860520 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.139480 # Percentage of idle cycles -system.cpu1.Branches 34479 # Number of branches fetched -system.cpu1.op_class::No_OpClass 25261 14.96% 14.96% # Class of executed instruction -system.cpu1.op_class::IntAlu 74858 44.33% 59.29% # Class of executed instruction -system.cpu1.op_class::IntMult 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::MemRead 55471 32.85% 92.14% # Class of executed instruction -system.cpu1.op_class::MemWrite 13271 7.86% 100.00% # Class of executed instruction +system.cpu1.num_mem_refs 52827 # number of memory refs +system.cpu1.num_load_insts 41019 # Number of load instructions +system.cpu1.num_store_insts 11808 # Number of store instructions +system.cpu1.num_idle_cycles 73818.861681 # Number of idle cycles +system.cpu1.num_busy_cycles 453311.138319 # Number of busy cycles +system.cpu1.not_idle_fraction 0.859961 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.140039 # Percentage of idle cycles +system.cpu1.Branches 35703 # Number of branches fetched +system.cpu1.op_class::No_OpClass 26483 15.50% 15.50% # Class of executed instruction +system.cpu1.op_class::IntAlu 74610 43.68% 59.18% # Class of executed instruction +system.cpu1.op_class::IntMult 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::MemRead 57921 33.91% 93.09% # Class of executed instruction +system.cpu1.op_class::MemWrite 11808 6.91% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 168861 # Class of executed instruction +system.cpu1.op_class::total 170822 # Class of executed instruction system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 26.495164 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 28944 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 964.800000 # Average number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 26.474097 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 25884 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 892.551724 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.495164 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051748 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.051748 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.474097 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051707 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.051707 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 218364 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 218364 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 41094 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 41094 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 13094 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 13094 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 54188 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 54188 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 54188 # number of overall hits -system.cpu1.dcache.overall_hits::total 54188 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 163 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 163 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 107 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 107 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 270 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 270 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 270 # number of overall misses -system.cpu1.dcache.overall_misses::total 270 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2920000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2920000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2149500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2149500 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 245500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 245500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5069500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5069500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5069500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5069500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 41257 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 41257 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 13201 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 13201 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 54458 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 54458 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 54458 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 54458 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003951 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.003951 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008105 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.008105 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.808824 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.808824 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004958 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.004958 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004958 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.004958 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17914.110429 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 17914.110429 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20088.785047 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20088.785047 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4463.636364 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 4463.636364 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18775.925926 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18775.925926 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18775.925926 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18775.925926 # average overall miss latency +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 211529 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 211529 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 40844 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 40844 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 11631 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 11631 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 52475 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 52475 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 52475 # number of overall hits +system.cpu1.dcache.overall_hits::total 52475 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 167 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 167 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 105 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 105 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 272 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 272 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 272 # number of overall misses +system.cpu1.dcache.overall_misses::total 272 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1891500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1891500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1642500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1642500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 250000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 250000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 3534000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 3534000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 3534000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 3534000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 41011 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 41011 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 11736 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 11736 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 52747 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 52747 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 52747 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 52747 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004072 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.004072 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008947 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.008947 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.800000 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.800000 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005157 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005157 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005157 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005157 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11326.347305 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 11326.347305 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 15642.857143 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 15642.857143 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4464.285714 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 4464.285714 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 12992.647059 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 12992.647059 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12992.647059 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 12992.647059 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,99 +472,99 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2757000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2757000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2042500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2042500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 190500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 190500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4799500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4799500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4799500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4799500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003951 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003951 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008105 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008105 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.808824 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.808824 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004958 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.004958 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004958 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.004958 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16914.110429 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16914.110429 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19088.785047 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19088.785047 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3463.636364 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3463.636364 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17775.925926 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17775.925926 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17775.925926 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17775.925926 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 167 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 272 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 272 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1724500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1724500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1537500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1537500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 194000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 194000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3262000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3262000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3262000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3262000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004072 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004072 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008947 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008947 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.800000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005157 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.005157 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005157 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.005157 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10326.347305 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10326.347305 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14642.857143 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14642.857143 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3464.285714 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3464.285714 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11992.647059 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11992.647059 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11992.647059 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11992.647059 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 280 # number of replacements -system.cpu1.icache.tags.tagsinuse 67.000483 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 168496 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 66.953040 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 170457 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 460.371585 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 465.729508 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 67.000483 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130860 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.130860 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 66.953040 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130768 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.130768 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 169228 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 169228 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 168496 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 168496 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 168496 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 168496 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 168496 # number of overall hits -system.cpu1.icache.overall_hits::total 168496 # number of overall hits +system.cpu1.icache.tags.tag_accesses 171189 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 171189 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 170457 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 170457 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 170457 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 170457 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 170457 # number of overall hits +system.cpu1.icache.overall_hits::total 170457 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5681500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5681500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5681500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5681500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5681500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5681500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 168862 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 168862 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 168862 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 168862 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 168862 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 168862 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002167 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002167 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002167 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002167 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002167 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002167 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15523.224044 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15523.224044 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15523.224044 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15523.224044 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15523.224044 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15523.224044 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5688500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5688500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5688500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5688500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5688500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5688500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 170823 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 170823 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 170823 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 170823 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 170823 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 170823 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002143 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002143 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002143 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002143 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002143 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002143 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15542.349727 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15542.349727 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15542.349727 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15542.349727 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15542.349727 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15542.349727 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -581,158 +581,158 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5315500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5315500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5315500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5315500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5315500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5315500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002167 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002167 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002167 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14523.224044 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 14523.224044 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 14523.224044 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5322500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5322500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5322500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5322500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5322500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5322500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002143 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002143 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002143 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002143 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002143 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002143 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14542.349727 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14542.349727 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14542.349727 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 14542.349727 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14542.349727 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 14542.349727 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 529681 # number of cpu cycles simulated +system.cpu2.numCycles 527130 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 165415 # Number of instructions committed -system.cpu2.committedOps 165415 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 110386 # Number of integer alu accesses +system.cpu2.committedInsts 168244 # Number of instructions committed +system.cpu2.committedOps 168244 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 109603 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 31522 # number of instructions that are conditional controls -system.cpu2.num_int_insts 110386 # number of integer instructions +system.cpu2.num_conditional_control_insts 33329 # number of instructions that are conditional controls +system.cpu2.num_int_insts 109603 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 277687 # number of times the integer registers were read -system.cpu2.num_int_register_writes 105904 # number of times the integer registers were written +system.cpu2.num_int_register_reads 267321 # number of times the integer registers were read +system.cpu2.num_int_register_writes 101101 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 55033 # number of memory refs -system.cpu2.num_load_insts 40858 # Number of load instructions -system.cpu2.num_store_insts 14175 # Number of store instructions -system.cpu2.num_idle_cycles 74150.001720 # Number of idle cycles -system.cpu2.num_busy_cycles 455530.998280 # Number of busy cycles -system.cpu2.not_idle_fraction 0.860010 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.139990 # Percentage of idle cycles -system.cpu2.Branches 33177 # Number of branches fetched -system.cpu2.op_class::No_OpClass 23956 14.48% 14.48% # Class of executed instruction -system.cpu2.op_class::IntAlu 74457 45.00% 59.48% # Class of executed instruction -system.cpu2.op_class::IntMult 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatAdd 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatCmp 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatMult 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::MemRead 52859 31.95% 91.43% # Class of executed instruction -system.cpu2.op_class::MemWrite 14175 8.57% 100.00% # Class of executed instruction +system.cpu2.num_mem_refs 52443 # number of memory refs +system.cpu2.num_load_insts 40463 # Number of load instructions +system.cpu2.num_store_insts 11980 # Number of store instructions +system.cpu2.num_idle_cycles 74087.861169 # Number of idle cycles +system.cpu2.num_busy_cycles 453042.138831 # Number of busy cycles +system.cpu2.not_idle_fraction 0.859450 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.140550 # Percentage of idle cycles +system.cpu2.Branches 34984 # Number of branches fetched +system.cpu2.op_class::No_OpClass 25761 15.31% 15.31% # Class of executed instruction +system.cpu2.op_class::IntAlu 74059 44.01% 59.32% # Class of executed instruction +system.cpu2.op_class::IntMult 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::IntDiv 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::FloatAdd 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::FloatCmp 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::FloatCvt 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::FloatMult 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::FloatDiv 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::FloatSqrt 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdAdd 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdAddAcc 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdAlu 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdCmp 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdCvt 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdMisc 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdMult 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdMultAcc 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdShift 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdSqrt 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatMult 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::MemRead 56476 33.56% 92.88% # Class of executed instruction +system.cpu2.op_class::MemWrite 11980 7.12% 100.00% # Class of executed instruction system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 165447 # Class of executed instruction +system.cpu2.op_class::total 168276 # Class of executed instruction system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 27.486829 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 30625 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1056.034483 # Average number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 27.444081 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 26343 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 878.100000 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.486829 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053685 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.053685 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.444081 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053602 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.053602 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 220352 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 220352 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 40687 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 40687 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 13994 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 13994 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 54681 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 54681 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 54681 # number of overall hits -system.cpu2.dcache.overall_hits::total 54681 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 163 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 163 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 108 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 108 # number of WriteReq misses +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 209996 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 209996 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 40285 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 40285 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 11801 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 11801 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 15 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 15 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 52086 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 52086 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 52086 # number of overall hits +system.cpu2.dcache.overall_hits::total 52086 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 170 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 170 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 104 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 104 # number of WriteReq misses system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 271 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 271 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 271 # number of overall misses -system.cpu2.dcache.overall_misses::total 271 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3093500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 3093500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2328000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2328000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 260500 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 260500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 5421500 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 5421500 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 5421500 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 5421500 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 40850 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 40850 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 14102 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 14102 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 54952 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 54952 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 54952 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 54952 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003990 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003990 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007658 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.007658 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.816901 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004932 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004932 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004932 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004932 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 18978.527607 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 18978.527607 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21555.555556 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 21555.555556 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4491.379310 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 4491.379310 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 20005.535055 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 20005.535055 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 20005.535055 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 20005.535055 # average overall miss latency +system.cpu2.dcache.demand_misses::cpu2.data 274 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 274 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 274 # number of overall misses +system.cpu2.dcache.overall_misses::total 274 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2220000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 2220000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1703000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 1703000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 260000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 260000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 3923000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 3923000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 3923000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 3923000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 40455 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 40455 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 11905 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 11905 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 73 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 73 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 52360 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 52360 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 52360 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 52360 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.004202 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.004202 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.008736 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.008736 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.794521 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.794521 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005233 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.005233 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005233 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.005233 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13058.823529 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 13058.823529 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 16375 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 16375 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4482.758621 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 4482.758621 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14317.518248 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 14317.518248 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14317.518248 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 14317.518248 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -741,99 +741,99 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 163 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 170 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 104 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2930500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2930500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2220000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2220000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 202500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 202500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 5150500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 5150500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 5150500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 5150500 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003990 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003990 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007658 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007658 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.816901 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004932 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004932 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004932 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004932 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17978.527607 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 17978.527607 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 20555.555556 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 20555.555556 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3491.379310 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3491.379310 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 19005.535055 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 19005.535055 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 19005.535055 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 19005.535055 # average overall mshr miss latency +system.cpu2.dcache.demand_mshr_misses::cpu2.data 274 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 274 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2050000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2050000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1599000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1599000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 202000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 202000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3649000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3649000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3649000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3649000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004202 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004202 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.008736 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.008736 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.794521 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.794521 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.005233 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.005233 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.005233 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.005233 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12058.823529 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 12058.823529 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15375 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15375 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3482.758621 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3482.758621 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13317.518248 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13317.518248 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13317.518248 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13317.518248 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 280 # number of replacements -system.cpu2.icache.tags.tagsinuse 69.407713 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 165082 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 69.363893 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 167911 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 451.043716 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 458.773224 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.407713 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135562 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.135562 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.363893 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135476 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.135476 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 165814 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 165814 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 165082 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 165082 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 165082 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 165082 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 165082 # number of overall hits -system.cpu2.icache.overall_hits::total 165082 # number of overall hits +system.cpu2.icache.tags.tag_accesses 168643 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 168643 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 167911 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 167911 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 167911 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 167911 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 167911 # number of overall hits +system.cpu2.icache.overall_hits::total 167911 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses system.cpu2.icache.overall_misses::total 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8101000 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 8101000 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 8101000 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 8101000 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 8101000 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 8101000 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 165448 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 165448 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 165448 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 165448 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 165448 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 165448 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002212 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002212 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002212 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002212 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002212 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002212 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22133.879781 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 22133.879781 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22133.879781 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 22133.879781 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22133.879781 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 22133.879781 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8088500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 8088500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 8088500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 8088500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 8088500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 8088500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 168277 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 168277 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 168277 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 168277 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 168277 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 168277 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002175 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002175 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002175 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002175 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002175 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002175 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22099.726776 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 22099.726776 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22099.726776 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 22099.726776 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22099.726776 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 22099.726776 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -850,158 +850,158 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7735000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 7735000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7735000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 7735000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7735000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 7735000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002212 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002212 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002212 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21133.879781 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 21133.879781 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 21133.879781 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7722500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 7722500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7722500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 7722500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7722500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 7722500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002175 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002175 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002175 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002175 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002175 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002175 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21099.726776 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21099.726776 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21099.726776 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 21099.726776 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21099.726776 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 21099.726776 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 529680 # number of cpu cycles simulated +system.cpu3.numCycles 527131 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 169884 # Number of instructions committed -system.cpu3.committedOps 169884 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 110793 # Number of integer alu accesses +system.cpu3.committedInsts 165809 # Number of instructions committed +system.cpu3.committedOps 165809 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 112442 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 33553 # number of instructions that are conditional controls -system.cpu3.num_int_insts 110793 # number of integer instructions +system.cpu3.num_conditional_control_insts 30690 # number of instructions that are conditional controls +system.cpu3.num_int_insts 112442 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 271193 # number of times the integer registers were read -system.cpu3.num_int_register_writes 102450 # number of times the integer registers were written +system.cpu3.num_int_register_reads 289238 # number of times the integer registers were read +system.cpu3.num_int_register_writes 110642 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 53409 # number of memory refs -system.cpu3.num_load_insts 41060 # Number of load instructions -system.cpu3.num_store_insts 12349 # Number of store instructions -system.cpu3.num_idle_cycles 74420.861217 # Number of idle cycles -system.cpu3.num_busy_cycles 455259.138783 # Number of busy cycles -system.cpu3.not_idle_fraction 0.859498 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.140502 # Percentage of idle cycles -system.cpu3.Branches 35208 # Number of branches fetched -system.cpu3.op_class::No_OpClass 25987 15.29% 15.29% # Class of executed instruction -system.cpu3.op_class::IntAlu 74660 43.94% 59.23% # Class of executed instruction -system.cpu3.op_class::IntMult 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::FloatAdd 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::FloatCmp 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::FloatMult 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::MemRead 56920 33.50% 92.73% # Class of executed instruction -system.cpu3.op_class::MemWrite 12349 7.27% 100.00% # Class of executed instruction +system.cpu3.num_mem_refs 57921 # number of memory refs +system.cpu3.num_load_insts 41890 # Number of load instructions +system.cpu3.num_store_insts 16031 # Number of store instructions +system.cpu3.num_idle_cycles 74358.001718 # Number of idle cycles +system.cpu3.num_busy_cycles 452772.998282 # Number of busy cycles +system.cpu3.not_idle_fraction 0.858938 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.141062 # Percentage of idle cycles +system.cpu3.Branches 32344 # Number of branches fetched +system.cpu3.op_class::No_OpClass 23127 13.95% 13.95% # Class of executed instruction +system.cpu3.op_class::IntAlu 75479 45.51% 59.46% # Class of executed instruction +system.cpu3.op_class::IntMult 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::IntDiv 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::FloatAdd 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::FloatCmp 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::FloatCvt 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::FloatMult 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::FloatDiv 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::FloatSqrt 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdAdd 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdAddAcc 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdAlu 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdCmp 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdCvt 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdMisc 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdMult 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdMultAcc 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdShift 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdSqrt 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatMult 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::MemRead 51204 30.88% 90.33% # Class of executed instruction +system.cpu3.op_class::MemWrite 16031 9.67% 100.00% # Class of executed instruction system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 169916 # Class of executed instruction +system.cpu3.op_class::total 165841 # Class of executed instruction system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 25.679518 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 26969 # Total number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 25.704074 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 34341 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 929.965517 # Average number of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1184.172414 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.679518 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050155 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.050155 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.704074 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050203 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.050203 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 213856 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 213856 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 40892 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 40892 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 12169 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 12169 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 53061 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 53061 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 53061 # number of overall hits -system.cpu3.dcache.overall_hits::total 53061 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 161 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 161 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 107 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 107 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses -system.cpu3.dcache.overall_misses::total 268 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2856500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 2856500 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2210000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2210000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 258500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 258500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 5066500 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 5066500 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 5066500 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 5066500 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41053 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41053 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 12276 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 12276 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 53329 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 53329 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 53329 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 53329 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003922 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003922 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008716 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.008716 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005025 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.005025 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005025 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.005025 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17742.236025 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 17742.236025 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20654.205607 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 20654.205607 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4535.087719 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 4535.087719 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18904.850746 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 18904.850746 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18904.850746 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 18904.850746 # average overall miss latency +system.cpu3.dcache.tags.tag_accesses 231895 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 231895 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 41733 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41733 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 15853 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 15853 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 57586 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 57586 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 57586 # number of overall hits +system.cpu3.dcache.overall_hits::total 57586 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 150 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 150 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 259 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 259 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 259 # number of overall misses +system.cpu3.dcache.overall_misses::total 259 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 1542500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 1542500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1810500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 1810500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 250500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 250500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 3353000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 3353000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 3353000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 3353000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41883 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41883 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 15962 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 15962 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 57845 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 57845 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 57845 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 57845 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003581 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003581 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006829 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.006829 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.835821 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.835821 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004477 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.004477 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004477 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.004477 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 10283.333333 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 10283.333333 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16610.091743 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 16610.091743 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4473.214286 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 4473.214286 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 12945.945946 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 12945.945946 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 12945.945946 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 12945.945946 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1010,69 +1010,69 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 161 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2695500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2695500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2103000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2103000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 201500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 201500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4798500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 4798500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4798500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 4798500 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003922 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003922 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008716 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008716 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005025 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.005025 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005025 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.005025 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16742.236025 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16742.236025 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19654.205607 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19654.205607 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3535.087719 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3535.087719 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 17904.850746 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 17904.850746 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 17904.850746 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 17904.850746 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 150 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 150 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 109 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 259 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 259 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1392500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1392500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1701500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1701500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 194500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 194500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3094000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3094000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3094000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3094000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003581 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003581 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.006829 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.006829 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.835821 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.835821 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004477 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.004477 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004477 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.004477 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9283.333333 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9283.333333 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15610.091743 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15610.091743 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3473.214286 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3473.214286 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 11945.945946 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 11945.945946 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 11945.945946 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 11945.945946 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 281 # number of replacements -system.cpu3.icache.tags.tagsinuse 64.991831 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 169550 # Total number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 64.942208 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 165475 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 461.989101 # Average number of references to valid blocks. +system.cpu3.icache.tags.avg_refs 450.885559 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.991831 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126937 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.126937 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.942208 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126840 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.126840 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 170284 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 170284 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 169550 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 169550 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 169550 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 169550 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 169550 # number of overall hits -system.cpu3.icache.overall_hits::total 169550 # number of overall hits +system.cpu3.icache.tags.tag_accesses 166209 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 166209 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 165475 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 165475 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 165475 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 165475 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 165475 # number of overall hits +system.cpu3.icache.overall_hits::total 165475 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses @@ -1085,18 +1085,18 @@ system.cpu3.icache.demand_miss_latency::cpu3.inst 5473500 system.cpu3.icache.demand_miss_latency::total 5473500 # number of demand (read+write) miss cycles system.cpu3.icache.overall_miss_latency::cpu3.inst 5473500 # number of overall miss cycles system.cpu3.icache.overall_miss_latency::total 5473500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 169917 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 169917 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 169917 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 169917 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 169917 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 169917 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002160 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002160 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002160 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002160 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002160 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002160 # miss rate for overall accesses +system.cpu3.icache.ReadReq_accesses::cpu3.inst 165842 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 165842 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 165842 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 165842 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 165842 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 165842 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002213 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002213 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002213 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002213 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002213 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002213 # miss rate for overall accesses system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14914.168937 # average ReadReq miss latency system.cpu3.icache.ReadReq_avg_miss_latency::total 14914.168937 # average ReadReq miss latency system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14914.168937 # average overall miss latency @@ -1125,12 +1125,12 @@ system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5106500 system.cpu3.icache.demand_mshr_miss_latency::total 5106500 # number of demand (read+write) MSHR miss cycles system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5106500 # number of overall MSHR miss cycles system.cpu3.icache.overall_mshr_miss_latency::total 5106500 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002160 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002160 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002160 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002160 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002160 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002160 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002213 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002213 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002213 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002213 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002213 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002213 # mshr miss rate for overall accesses system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average ReadReq mshr miss latency system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13914.168937 # average ReadReq mshr miss latency system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average overall mshr miss latency @@ -1139,30 +1139,30 @@ system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13914.168937 system.cpu3.icache.overall_avg_mshr_miss_latency::total 13914.168937 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 347.318197 # Cycle average of tags in use +system.l2c.tags.tagsinuse 347.185045 # Cycle average of tags in use system.l2c.tags.total_refs 1714 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 3.995338 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.882018 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 230.794628 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 54.021394 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 6.166785 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.835671 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 46.779239 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 6.090035 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.944334 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.804093 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.881447 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 230.714883 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 54.006864 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 6.227742 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 0.835119 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 46.668024 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 6.066881 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 0.961095 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.822991 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.003522 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.003520 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.000824 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000094 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000095 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000714 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000712 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.000093 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.005300 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.005298 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id @@ -1204,9 +1204,9 @@ system.l2c.overall_hits::cpu3.inst 357 # nu system.l2c.overall_hits::cpu3.data 9 # number of overall hits system.l2c.overall_hits::total 1218 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 14 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 14 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses @@ -1242,46 +1242,46 @@ system.l2c.overall_misses::cpu3.inst 10 # nu system.l2c.overall_misses::cpu3.data 16 # number of overall misses system.l2c.overall_misses::total 594 # number of overall misses system.l2c.ReadExReq_miss_latency::cpu0.data 5892000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 842000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 896000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 840000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 8470000 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 16964000 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 28350000 # number of overall MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses @@ -1501,80 +1501,79 @@ system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.010899 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 49562.937063 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 430 # Transaction distribution system.membus.trans_dist::UpgradeReq 271 # Transaction distribution -system.membus.trans_dist::UpgradeResp 76 # Transaction distribution system.membus.trans_dist::ReadExReq 208 # Transaction distribution system.membus.trans_dist::ReadExResp 142 # Transaction distribution system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1557 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1557 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1481 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1481 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 261 # Total snoops (count) @@ -1588,53 +1587,53 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 915 # Request fanout histogram -system.membus.reqLayer0.occupancy 677632 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 685132 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2936000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2860000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 3980 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1113 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 3976 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1120 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1854 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadResp 2221 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 495 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1056 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 273 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 273 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 428 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 428 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 424 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 424 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 655 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 579 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 849 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 849 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 852 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5309 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39040 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1015 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 360 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5866 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 30912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31040 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41472 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 147712 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1032 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2922 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.269678 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.154527 # Request fanout histogram +system.toL2Bus.pkt_size::total 183616 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1028 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2918 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.265250 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.153418 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1002 34.29% 34.29% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 787 26.93% 61.23% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 476 16.29% 77.52% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 657 22.48% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1002 34.34% 34.34% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 794 27.21% 61.55% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 468 16.04% 77.59% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 654 22.41% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram @@ -1643,24 +1642,24 @@ system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2922 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3050992 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2918 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3048992 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 700999 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 495500 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 500989 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 552489 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 550995 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 432972 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 435970 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 552491 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 554485 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 434474 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 441968 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 553492 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 552992 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 427974 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 411482 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt index 1566487a2..7c2d41959 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.010022 # Nu sim_ticks 10021833 # Number of ticks simulated final_tick 10021833 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 66575 # Simulator tick rate (ticks/s) -host_mem_usage 401248 # Number of bytes of host memory used -host_seconds 150.54 # Real time elapsed on the host +host_tick_rate 141404 # Simulator tick rate (ticks/s) +host_mem_usage 425972 # Number of bytes of host memory used +host_seconds 70.87 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39622272 # Number of bytes read from this memory diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index 760ab889a..02b6c9c1b 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.004723 # Nu sim_ticks 4722948 # Number of ticks simulated final_tick 4722948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 22839 # Simulator tick rate (ticks/s) -host_mem_usage 403984 # Number of bytes of host memory used -host_seconds 206.79 # Real time elapsed on the host +host_tick_rate 43612 # Simulator tick rate (ticks/s) +host_mem_usage 429416 # Number of bytes of host memory used +host_seconds 108.30 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 38973248 # Number of bytes read from this memory diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index edf017693..ac17b1f35 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.007679 # Nu sim_ticks 7678882 # Number of ticks simulated final_tick 7678882 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 60394 # Simulator tick rate (ticks/s) -host_mem_usage 401808 # Number of bytes of host memory used -host_seconds 127.15 # Real time elapsed on the host +host_tick_rate 131227 # Simulator tick rate (ticks/s) +host_mem_usage 425824 # Number of bytes of host memory used +host_seconds 58.52 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39687936 # Number of bytes read from this memory diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt index 6281c21fd..64e77dffe 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -1,1819 +1,1816 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000541 # Number of seconds simulated -sim_ticks 540820000 # Number of ticks simulated -final_tick 540820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000535 # Number of seconds simulated +sim_ticks 535115500 # Number of ticks simulated +final_tick 535115500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 46544616 # Simulator tick rate (ticks/s) -host_mem_usage 216108 # Number of bytes of host memory used -host_seconds 11.62 # Real time elapsed on the host +host_tick_rate 114251239 # Simulator tick rate (ticks/s) +host_mem_usage 237088 # Number of bytes of host memory used +host_seconds 4.68 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 88157 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 82701 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 84142 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 82645 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 83993 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 79749 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 78765 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 84222 # Number of bytes read from this memory -system.physmem.bytes_read::total 664374 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 426368 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5567 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5462 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5416 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5447 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5329 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5472 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5531 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5421 # Number of bytes written to this memory -system.physmem.bytes_written::total 470013 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11108 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10881 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10936 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10951 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11102 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10890 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10914 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 11079 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87861 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6662 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5567 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5462 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5416 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5447 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5329 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5472 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5531 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5421 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50307 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 163006176 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 152917792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 155582264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 152814245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 155306756 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 147459413 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 145639954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 155730187 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1228456788 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 788373211 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 10293628 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 10099479 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 10014423 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 10071743 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 9853556 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 10117969 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 10227063 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 10023668 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 869074738 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 788373211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 173299804 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 163017270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 165596687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 162885988 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 165160312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 157577382 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 155867017 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 165753855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2097531526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 81574 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 80110 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 79121 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 81238 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 80899 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 79820 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 79202 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 79066 # Number of bytes read from this memory +system.physmem.bytes_read::total 641030 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 406208 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5473 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5509 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5540 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5388 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5404 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5375 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5435 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5475 # Number of bytes written to this memory +system.physmem.bytes_written::total 449807 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11077 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10999 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10829 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10993 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11032 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10961 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10910 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11026 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87827 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6347 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5473 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5509 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5540 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5388 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5404 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5375 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5435 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5475 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49946 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 152441856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 149705998 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 147857799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 151813954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 151180446 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 149164059 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 148009168 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 147755017 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1197928298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 759103409 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 10227699 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 10294974 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 10352905 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 10068854 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 10098754 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 10044560 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 10156686 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 10231436 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 840579277 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 759103409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 162669555 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 160000972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 158210704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 161882808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 161279200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 159208619 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 158165854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 157986453 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2038507575 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 99596 # number of read accesses completed -system.cpu0.num_writes 55268 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22066 # number of replacements -system.cpu0.l1c.tags.tagsinuse 391.486377 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13717 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22459 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.610757 # Average number of references to valid blocks. +system.cpu0.num_reads 100000 # number of read accesses completed +system.cpu0.num_writes 55271 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22387 # number of replacements +system.cpu0.l1c.tags.tagsinuse 391.751313 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13331 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22793 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.584873 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 391.486377 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.764622 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.764622 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 338295 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 338295 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8878 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8878 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1162 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1162 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 10040 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 10040 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 10040 # number of overall hits -system.cpu0.l1c.overall_hits::total 10040 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36478 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36478 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23899 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23899 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60377 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60377 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60377 # number of overall misses -system.cpu0.l1c.overall_misses::total 60377 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 603408975 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 603408975 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 722750184 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 722750184 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1326159159 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1326159159 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1326159159 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1326159159 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45356 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45356 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25061 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25061 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70417 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70417 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70417 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70417 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.804260 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.804260 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953633 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.953633 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.857421 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.857421 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.857421 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.857421 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16541.723093 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 16541.723093 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 30241.858823 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 30241.858823 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 21964.641486 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 21964.641486 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 21964.641486 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 21964.641486 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 828428 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 391.751313 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.765139 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.765139 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 406 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 338274 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 338274 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8660 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8660 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1174 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1174 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9834 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9834 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9834 # number of overall hits +system.cpu0.l1c.overall_hits::total 9834 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36517 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36517 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23979 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23979 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60496 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60496 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60496 # number of overall misses +system.cpu0.l1c.overall_misses::total 60496 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 647463503 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 647463503 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 554640697 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 554640697 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1202104200 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1202104200 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1202104200 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1202104200 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45177 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45177 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25153 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25153 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70330 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70330 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70330 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70330 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.808310 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.808310 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953326 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.953326 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.860173 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.860173 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.860173 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.860173 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 17730.468083 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 17730.468083 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 23130.268026 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 23130.268026 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 19870.804681 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 19870.804681 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 19870.804681 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 19870.804681 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 749854 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 62795 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 59820 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 13.192579 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.535172 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9669 # number of writebacks -system.cpu0.l1c.writebacks::total 9669 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36478 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36478 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23899 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23899 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60377 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60377 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60377 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60377 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9885 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9885 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5567 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5567 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15452 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15452 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 566933975 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 566933975 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 698852184 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 698852184 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1265786159 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1265786159 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1265786159 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1265786159 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 722511018 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 722511018 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 853790554 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 853790554 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1576301572 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1576301572 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.804260 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.804260 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953633 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953633 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.857421 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.857421 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.857421 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.857421 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15541.805335 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15541.805335 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 29241.900665 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 29241.900665 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20964.707736 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20964.707736 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20964.707736 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20964.707736 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 73091.655842 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73091.655842 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 153366.365008 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 153366.365008 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 102012.786177 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 102012.786177 # average overall mshr uncacheable latency +system.cpu0.l1c.writebacks::writebacks 9840 # number of writebacks +system.cpu0.l1c.writebacks::total 9840 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36517 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36517 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23979 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23979 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60496 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60496 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60496 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60496 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9959 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9959 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5475 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5475 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15434 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15434 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 610946503 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 610946503 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 530662697 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 530662697 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1141609200 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1141609200 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1141609200 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1141609200 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 751203683 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 751203683 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 933372844 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 933372844 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1684576527 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1684576527 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.808310 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.808310 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953326 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953326 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860173 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.860173 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860173 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.860173 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 16730.468083 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 16730.468083 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 22130.309729 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 22130.309729 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 18870.821211 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 18870.821211 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 18870.821211 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 18870.821211 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 75429.629782 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75429.629782 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 170479.058265 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 170479.058265 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 109147.112025 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 109147.112025 # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 98929 # number of read accesses completed -system.cpu1.num_writes 55238 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22532 # number of replacements -system.cpu1.l1c.tags.tagsinuse 392.132482 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13440 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22931 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.586106 # Average number of references to valid blocks. +system.cpu1.num_reads 99085 # number of read accesses completed +system.cpu1.num_writes 54836 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22258 # number of replacements +system.cpu1.l1c.tags.tagsinuse 391.296117 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13378 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22654 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.590536 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 392.132482 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.765884 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.765884 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 387 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 338385 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 338385 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8754 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8754 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1152 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1152 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9906 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9906 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9906 # number of overall hits -system.cpu1.l1c.overall_hits::total 9906 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36277 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36277 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 24198 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 24198 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60475 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60475 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60475 # number of overall misses -system.cpu1.l1c.overall_misses::total 60475 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 602891984 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 602891984 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 733995398 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 733995398 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1336887382 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1336887382 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1336887382 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1336887382 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45031 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45031 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 25350 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 25350 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70381 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70381 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70381 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70381 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805601 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.805601 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954556 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954556 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.859252 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.859252 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.859252 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.859252 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16619.124624 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 16619.124624 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 30332.895198 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 30332.895198 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 22106.446995 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 22106.446995 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 22106.446995 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 22106.446995 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 828861 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 391.296117 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.764250 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.764250 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 336817 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 336817 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8647 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8647 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1131 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1131 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9778 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9778 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9778 # number of overall hits +system.cpu1.l1c.overall_hits::total 9778 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36589 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36589 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23685 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23685 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60274 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60274 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60274 # number of overall misses +system.cpu1.l1c.overall_misses::total 60274 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 652011208 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 652011208 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 548619495 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 548619495 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1200630703 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1200630703 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1200630703 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1200630703 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45236 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45236 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24816 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24816 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70052 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70052 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70052 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70052 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.808847 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.808847 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954425 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954425 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.860418 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.860418 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.860418 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.860418 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 17819.869578 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 17819.869578 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 23163.162128 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 23163.162128 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 19919.545791 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 19919.545791 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 19919.545791 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 19919.545791 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 748495 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 62856 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 59422 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 13.186665 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.596261 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9918 # number of writebacks -system.cpu1.l1c.writebacks::total 9918 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36277 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36277 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 24198 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 24198 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60475 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60475 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60475 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60475 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9741 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9741 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5463 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5463 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15204 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15204 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 566614984 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 566614984 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 709800398 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 709800398 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1276415382 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1276415382 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1276415382 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1276415382 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 713705140 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 713705140 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 858653101 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 858653101 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1572358241 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1572358241 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805601 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805601 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954556 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954556 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859252 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.859252 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859252 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.859252 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15619.124624 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15619.124624 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 29333.019175 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 29333.019175 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 21106.496602 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 21106.496602 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 21106.496602 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 21106.496602 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 73268.159327 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73268.159327 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 157176.112209 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157176.112209 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 103417.406012 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 103417.406012 # average overall mshr uncacheable latency +system.cpu1.l1c.writebacks::writebacks 9809 # number of writebacks +system.cpu1.l1c.writebacks::total 9809 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36589 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36589 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23685 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23685 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60274 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60274 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60274 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60274 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9902 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9902 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5511 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5511 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15413 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15413 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 615423208 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 615423208 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 524934495 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 524934495 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1140357703 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1140357703 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1140357703 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1140357703 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 747152224 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 747152224 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 944376752 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 944376752 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1691528976 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1691528976 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.808847 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.808847 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954425 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954425 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860418 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.860418 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860418 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.860418 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 16819.896909 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 16819.896909 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 22163.162128 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 22163.162128 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 18919.562382 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 18919.562382 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 18919.562382 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 18919.562382 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 75454.678247 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75454.678247 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 171362.139721 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 171362.139721 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 109746.900409 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 109746.900409 # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99726 # number of read accesses completed -system.cpu2.num_writes 55227 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22340 # number of replacements -system.cpu2.l1c.tags.tagsinuse 393.100704 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13463 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22750 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.591780 # Average number of references to valid blocks. +system.cpu2.num_reads 99705 # number of read accesses completed +system.cpu2.num_writes 55132 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22489 # number of replacements +system.cpu2.l1c.tags.tagsinuse 393.363987 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13472 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22889 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.588580 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 393.100704 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.767775 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.767775 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 400 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 338035 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 338035 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8657 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8657 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1109 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1109 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9766 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9766 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9766 # number of overall hits -system.cpu2.l1c.overall_hits::total 9766 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36622 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36622 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23922 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23922 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60544 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60544 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60544 # number of overall misses -system.cpu2.l1c.overall_misses::total 60544 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 606579368 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 606579368 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 739451035 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 739451035 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1346030403 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1346030403 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1346030403 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1346030403 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45279 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45279 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25031 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25031 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70310 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70310 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70310 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70310 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.808808 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.808808 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955695 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.955695 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.861101 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.861101 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.861101 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.861101 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16563.250724 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 16563.250724 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 30910.920283 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 30910.920283 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 22232.267491 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 22232.267491 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 22232.267491 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 22232.267491 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 834628 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 393.363987 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.768289 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.768289 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 387 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 339330 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 339330 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8744 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8744 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1142 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1142 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9886 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9886 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9886 # number of overall hits +system.cpu2.l1c.overall_hits::total 9886 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36705 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36705 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23982 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23982 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60687 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60687 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60687 # number of overall misses +system.cpu2.l1c.overall_misses::total 60687 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 655863609 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 655863609 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 555301116 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 555301116 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1211164725 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1211164725 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1211164725 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1211164725 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45449 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45449 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25124 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25124 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70573 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70573 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70573 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70573 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.807609 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.807609 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954545 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.954545 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.859918 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.859918 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.859918 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.859918 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 17868.508623 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 17868.508623 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 23154.912685 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 23154.912685 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 19957.564635 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 19957.564635 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 19957.564635 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 19957.564635 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 744784 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 63193 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 59741 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 13.207602 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.466882 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9768 # number of writebacks -system.cpu2.l1c.writebacks::total 9768 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36622 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36622 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23922 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23922 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60544 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60544 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60544 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60544 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9774 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9774 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5417 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5417 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15191 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15191 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 569957368 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 569957368 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 715531035 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 715531035 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1285488403 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1285488403 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1285488403 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1285488403 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 714145091 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 714145091 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 834952155 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 834952155 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1549097246 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1549097246 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.808808 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.808808 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955695 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955695 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.861101 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.861101 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.861101 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.861101 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15563.250724 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15563.250724 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 29911.003888 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 29911.003888 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 21232.300525 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 21232.300525 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 21232.300525 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 21232.300525 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 73065.796092 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73065.796092 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 154135.527968 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154135.527968 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 101974.672240 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 101974.672240 # average overall mshr uncacheable latency +system.cpu2.l1c.writebacks::writebacks 9941 # number of writebacks +system.cpu2.l1c.writebacks::total 9941 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36705 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36705 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23982 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23982 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60687 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60687 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60687 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60687 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9745 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9745 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5541 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5541 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15286 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15286 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 619160609 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 619160609 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 531319116 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 531319116 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1150479725 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1150479725 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1150479725 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1150479725 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 736103391 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 736103391 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 958643718 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 958643718 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1694747109 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1694747109 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.807609 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.807609 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954545 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954545 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859918 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.859918 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859918 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.859918 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 16868.563111 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 16868.563111 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 22154.912685 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 22154.912685 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 18957.597591 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 18957.597591 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 18957.597591 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 18957.597591 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 75536.520369 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75536.520369 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 173009.153221 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173009.153221 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 110869.233874 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 110869.233874 # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99494 # number of read accesses completed -system.cpu3.num_writes 54686 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22431 # number of replacements -system.cpu3.l1c.tags.tagsinuse 392.658378 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13393 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22832 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.586589 # Average number of references to valid blocks. +system.cpu3.num_reads 99493 # number of read accesses completed +system.cpu3.num_writes 55186 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22493 # number of replacements +system.cpu3.l1c.tags.tagsinuse 393.330553 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13483 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22894 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.588932 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 392.658378 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.766911 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.766911 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_blocks::cpu3 393.330553 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.768224 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.768224 # Average percentage of cache occupancy system.cpu3.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 390 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id system.cpu3.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 337999 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 337999 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8615 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8615 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1106 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1106 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9721 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9721 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9721 # number of overall hits -system.cpu3.l1c.overall_hits::total 9721 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36594 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36594 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23974 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23974 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60568 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60568 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60568 # number of overall misses -system.cpu3.l1c.overall_misses::total 60568 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 607642440 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 607642440 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 730577546 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 730577546 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1338219986 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1338219986 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1338219986 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1338219986 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45209 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45209 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25080 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25080 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70289 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70289 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70289 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70289 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.809441 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.809441 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955901 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.955901 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.861700 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.861700 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.861700 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.861700 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16604.974586 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 16604.974586 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 30473.744306 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 30473.744306 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 22094.505118 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 22094.505118 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 22094.505118 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 22094.505118 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 833585 # number of cycles access was blocked +system.cpu3.l1c.tags.tag_accesses 338296 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 338296 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8738 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8738 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1110 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1110 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9848 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9848 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9848 # number of overall hits +system.cpu3.l1c.overall_hits::total 9848 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36582 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36582 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23939 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23939 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60521 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60521 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60521 # number of overall misses +system.cpu3.l1c.overall_misses::total 60521 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 654319900 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 654319900 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 552232159 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 552232159 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1206552059 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1206552059 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1206552059 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1206552059 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45320 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45320 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25049 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25049 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70369 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70369 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70369 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70369 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807193 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.807193 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955687 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.955687 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.860052 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.860052 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.860052 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.860052 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 17886.389481 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 17886.389481 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 23068.305234 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 23068.305234 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 19936.089275 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 19936.089275 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 19936.089275 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 19936.089275 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 748969 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 63208 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 59958 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 13.187967 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.491561 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9871 # number of writebacks -system.cpu3.l1c.writebacks::total 9871 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36594 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36594 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23974 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23974 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60568 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60568 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60568 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60568 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9814 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9814 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5449 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5449 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15263 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15263 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 571049440 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 571049440 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 706605546 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 706605546 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1277654986 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1277654986 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1277654986 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1277654986 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 718813002 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 718813002 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 842609106 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 842609106 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1561422108 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1561422108 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.809441 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.809441 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955901 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955901 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861700 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.861700 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861700 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.861700 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15605.001913 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15605.001913 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 29473.827730 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 29473.827730 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 21094.554649 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 21094.554649 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 21094.554649 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 21094.554649 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 73243.631751 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73243.631751 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 154635.548908 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154635.548908 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 102301.127432 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 102301.127432 # average overall mshr uncacheable latency +system.cpu3.l1c.writebacks::writebacks 9953 # number of writebacks +system.cpu3.l1c.writebacks::total 9953 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36582 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36582 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23939 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23939 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60521 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60521 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60521 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60521 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9878 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9878 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5388 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5388 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15266 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15266 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 617737900 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 617737900 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 528295159 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 528295159 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1146033059 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1146033059 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1146033059 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1146033059 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 746486832 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 746486832 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 927844496 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 927844496 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1674331328 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1674331328 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807193 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807193 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955687 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955687 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860052 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.860052 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860052 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.860052 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 16886.389481 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 16886.389481 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 22068.388780 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 22068.388780 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 18936.122321 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 18936.122321 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 18936.122321 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 18936.122321 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 75570.645070 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75570.645070 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 172205.734224 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 172205.734224 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 109677.147124 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 109677.147124 # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99490 # number of read accesses completed -system.cpu4.num_writes 54928 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22277 # number of replacements -system.cpu4.l1c.tags.tagsinuse 391.439470 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13388 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22671 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.590534 # Average number of references to valid blocks. +system.cpu4.num_reads 99921 # number of read accesses completed +system.cpu4.num_writes 55196 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22380 # number of replacements +system.cpu4.l1c.tags.tagsinuse 392.777413 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13581 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22786 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.596024 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 391.439470 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.764530 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.764530 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 337649 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 337649 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8692 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8692 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1145 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1145 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9837 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9837 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9837 # number of overall hits -system.cpu4.l1c.overall_hits::total 9837 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36462 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36462 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23928 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23928 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60390 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60390 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60390 # number of overall misses -system.cpu4.l1c.overall_misses::total 60390 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 604688688 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 604688688 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 724847511 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 724847511 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1329536199 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1329536199 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1329536199 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1329536199 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45154 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45154 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25073 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25073 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70227 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70227 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70227 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70227 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807503 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.807503 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954333 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.954333 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.859926 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.859926 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.859926 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.859926 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16584.078986 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 16584.078986 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 30292.858200 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 30292.858200 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 22015.833731 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 22015.833731 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 22015.833731 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 22015.833731 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 834109 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 392.777413 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.767143 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.767143 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 406 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 394 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 339211 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 339211 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8862 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8862 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1132 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1132 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9994 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9994 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9994 # number of overall hits +system.cpu4.l1c.overall_hits::total 9994 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36800 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36800 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23778 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23778 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60578 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60578 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60578 # number of overall misses +system.cpu4.l1c.overall_misses::total 60578 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 655197570 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 655197570 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 548908934 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 548908934 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1204106504 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1204106504 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1204106504 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1204106504 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45662 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45662 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24910 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24910 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70572 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70572 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70572 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70572 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805922 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.805922 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954556 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.954556 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.858386 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.858386 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.858386 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.858386 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 17804.281793 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 17804.281793 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 23084.739423 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 23084.739423 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 19876.960349 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 19876.960349 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 19876.960349 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 19876.960349 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 750268 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 63123 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 59848 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 13.214027 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.536225 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9949 # number of writebacks -system.cpu4.l1c.writebacks::total 9949 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36462 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36462 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23928 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23928 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60390 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60390 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60390 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60390 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9946 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9946 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5329 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5329 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15275 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15275 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 568228688 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 568228688 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 700919511 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 700919511 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1269148199 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1269148199 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1269148199 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1269148199 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 727166434 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 727166434 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 837934166 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 837934166 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1565100600 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1565100600 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807503 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807503 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954333 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954333 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859926 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.859926 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859926 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.859926 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15584.133838 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15584.133838 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 29292.858200 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 29292.858200 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 21015.866849 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 21015.866849 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 21015.866849 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 21015.866849 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 73111.445204 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73111.445204 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157240.413961 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157240.413961 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 102461.577741 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 102461.577741 # average overall mshr uncacheable latency +system.cpu4.l1c.writebacks::writebacks 9770 # number of writebacks +system.cpu4.l1c.writebacks::total 9770 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36800 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36800 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23778 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23778 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60578 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60578 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60578 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60578 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9925 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9925 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5406 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5406 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15331 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15331 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 618398570 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 618398570 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 525131934 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 525131934 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1143530504 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1143530504 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1143530504 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1143530504 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 750294225 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 750294225 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 944567825 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 944567825 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1694862050 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1694862050 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805922 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805922 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954556 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954556 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858386 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.858386 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858386 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.858386 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 16804.308967 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 16804.308967 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 22084.781479 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 22084.781479 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 18876.993364 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 18876.993364 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 18876.993364 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 18876.993364 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 75596.395466 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75596.395466 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 174725.827784 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174725.827784 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 110551.304546 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 110551.304546 # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99495 # number of read accesses completed -system.cpu5.num_writes 55318 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22409 # number of replacements -system.cpu5.l1c.tags.tagsinuse 392.682039 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13393 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22790 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.587670 # Average number of references to valid blocks. +system.cpu5.num_reads 99482 # number of read accesses completed +system.cpu5.num_writes 55607 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22456 # number of replacements +system.cpu5.l1c.tags.tagsinuse 392.242325 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13457 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22866 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.588516 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 392.682039 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.766957 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.766957 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 381 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.744141 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 337688 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 337688 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8637 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8637 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1146 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1146 # number of WriteReq hits +system.cpu5.l1c.tags.occ_blocks::cpu5 392.242325 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.766098 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.766098 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 397 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 338143 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 338143 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8578 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8578 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1205 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1205 # number of WriteReq hits system.cpu5.l1c.demand_hits::cpu5 9783 # number of demand (read+write) hits system.cpu5.l1c.demand_hits::total 9783 # number of demand (read+write) hits system.cpu5.l1c.overall_hits::cpu5 9783 # number of overall hits system.cpu5.l1c.overall_hits::total 9783 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36329 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36329 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 24118 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 24118 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60447 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60447 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60447 # number of overall misses -system.cpu5.l1c.overall_misses::total 60447 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 601479868 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 601479868 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 729882091 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 729882091 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1331361959 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1331361959 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1331361959 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1331361959 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44966 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44966 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25264 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25264 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70230 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70230 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70230 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70230 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.807922 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.807922 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954639 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.954639 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.860701 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.860701 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.860701 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.860701 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16556.466404 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 16556.466404 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 30262.960901 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 30262.960901 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 22025.277665 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 22025.277665 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 22025.277665 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 22025.277665 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 826632 # number of cycles access was blocked +system.cpu5.l1c.ReadReq_misses::cpu5 36239 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36239 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 24308 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 24308 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60547 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60547 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60547 # number of overall misses +system.cpu5.l1c.overall_misses::total 60547 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 647043171 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 647043171 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 559180438 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 559180438 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1206223609 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1206223609 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1206223609 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1206223609 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44817 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44817 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25513 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25513 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70330 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70330 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70330 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70330 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808599 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.808599 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952769 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.952769 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.860899 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.860899 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.860899 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.860899 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 17854.884820 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 17854.884820 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 23003.967336 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 23003.967336 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 19922.103638 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 19922.103638 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 19922.103638 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 19922.103638 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 749399 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 62727 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 59952 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 13.178249 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.499983 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9995 # number of writebacks -system.cpu5.l1c.writebacks::total 9995 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36329 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36329 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24118 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 24118 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60447 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60447 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60447 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60447 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9798 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9798 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5473 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5473 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15271 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15271 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 565152868 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 565152868 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 705764091 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 705764091 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1270916959 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1270916959 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1270916959 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1270916959 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 717311081 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 717311081 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 861132955 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 861132955 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1578444036 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1578444036 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.807922 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.807922 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954639 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954639 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860701 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.860701 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860701 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.860701 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15556.521457 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15556.521457 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 29262.960901 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 29262.960901 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 21025.310752 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 21025.310752 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 21025.310752 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 21025.310752 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 73209.949071 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73209.949071 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 157342.034533 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157342.034533 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 103362.192129 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 103362.192129 # average overall mshr uncacheable latency +system.cpu5.l1c.writebacks::writebacks 10051 # number of writebacks +system.cpu5.l1c.writebacks::total 10051 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36239 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36239 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24308 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 24308 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60547 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60547 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60547 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60547 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9869 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9869 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5375 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5375 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15244 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15244 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 610804171 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 610804171 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 534872438 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 534872438 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1145676609 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1145676609 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1145676609 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1145676609 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 745114179 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 745114179 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 938602875 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 938602875 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1683717054 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1683717054 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808599 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808599 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952769 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952769 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860899 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.860899 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860899 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.860899 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 16854.884820 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 16854.884820 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 22003.967336 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 22003.967336 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 18922.103638 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 18922.103638 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 18922.103638 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 18922.103638 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 75500.474111 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75500.474111 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 174623.790698 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174623.790698 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 110451.131855 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 110451.131855 # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 100000 # number of read accesses completed -system.cpu6.num_writes 55059 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22318 # number of replacements -system.cpu6.l1c.tags.tagsinuse 390.741535 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13451 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22720 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.592033 # Average number of references to valid blocks. +system.cpu6.num_reads 99231 # number of read accesses completed +system.cpu6.num_writes 55266 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22476 # number of replacements +system.cpu6.l1c.tags.tagsinuse 393.210816 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13488 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22863 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.589949 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 390.741535 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.763167 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.763167 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 338536 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 338536 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8731 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8731 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1150 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1150 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9881 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9881 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9881 # number of overall hits -system.cpu6.l1c.overall_hits::total 9881 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36733 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36733 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23795 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23795 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60528 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60528 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60528 # number of overall misses -system.cpu6.l1c.overall_misses::total 60528 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 609896687 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 609896687 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 716784676 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 716784676 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1326681363 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1326681363 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1326681363 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1326681363 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45464 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45464 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24945 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24945 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70409 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70409 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70409 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70409 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807958 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.807958 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953899 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.953899 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.859663 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.859663 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.859663 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.859663 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16603.508752 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 16603.508752 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 30123.331624 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 30123.331624 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 21918.473483 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 21918.473483 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 21918.473483 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 21918.473483 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 822803 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 393.210816 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.767990 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.767990 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 339081 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 339081 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8703 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8703 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1207 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1207 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9910 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9910 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9910 # number of overall hits +system.cpu6.l1c.overall_hits::total 9910 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36605 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36605 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 24011 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 24011 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60616 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60616 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60616 # number of overall misses +system.cpu6.l1c.overall_misses::total 60616 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 653690176 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 653690176 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 554778070 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 554778070 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1208468246 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1208468246 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1208468246 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1208468246 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45308 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45308 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25218 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25218 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70526 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70526 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70526 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70526 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807915 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.807915 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.952137 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.952137 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.859484 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.859484 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.859484 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.859484 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 17857.947712 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 17857.947712 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 23105.163050 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 23105.163050 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 19936.456480 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 19936.456480 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 19936.456480 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 19936.456480 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 748048 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 62827 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 59929 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 13.096328 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.482237 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9777 # number of writebacks -system.cpu6.l1c.writebacks::total 9777 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36733 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36733 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23795 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23795 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60528 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60528 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60528 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60528 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9837 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9837 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5532 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5532 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15369 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15369 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 573164687 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 573164687 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 692991676 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 692991676 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1266156363 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1266156363 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1266156363 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1266156363 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 718909036 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 718909036 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 867837123 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 867837123 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1586746159 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1586746159 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807958 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807958 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953899 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953899 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859663 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.859663 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859663 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.859663 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15603.535976 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15603.535976 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 29123.415676 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 29123.415676 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20918.523047 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20918.523047 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20918.523047 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20918.523047 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 73082.142523 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73082.142523 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 156875.835683 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156875.835683 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 103243.292277 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 103243.292277 # average overall mshr uncacheable latency +system.cpu6.l1c.writebacks::writebacks 9811 # number of writebacks +system.cpu6.l1c.writebacks::total 9811 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36605 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36605 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24011 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 24011 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60616 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60616 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60616 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60616 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9828 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9828 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5436 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5436 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15264 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15264 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 617085176 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 617085176 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 530767070 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 530767070 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1147852246 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1147852246 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1147852246 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1147852246 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 743889866 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 743889866 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 938428736 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 938428736 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1682318602 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1682318602 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807915 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807915 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.952137 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.952137 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859484 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.859484 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859484 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.859484 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 16857.947712 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 16857.947712 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 22105.163050 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 22105.163050 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 18936.456480 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 18936.456480 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 18936.456480 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 18936.456480 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 75690.869556 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75690.869556 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 172632.217807 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 172632.217807 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 110214.793108 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 110214.793108 # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99734 # number of read accesses completed -system.cpu7.num_writes 54921 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22329 # number of replacements -system.cpu7.l1c.tags.tagsinuse 392.290074 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13499 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22713 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.594329 # Average number of references to valid blocks. +system.cpu7.num_reads 99956 # number of read accesses completed +system.cpu7.num_writes 55531 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22312 # number of replacements +system.cpu7.l1c.tags.tagsinuse 393.161929 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13691 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22714 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.602756 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 392.290074 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.766192 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.766192 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 338596 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 338596 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8795 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8795 # number of ReadReq hits +system.cpu7.l1c.tags.occ_blocks::cpu7 393.161929 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.767894 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.767894 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 338939 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 338939 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8916 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8916 # number of ReadReq hits system.cpu7.l1c.WriteReq_hits::cpu7 1165 # number of WriteReq hits system.cpu7.l1c.WriteReq_hits::total 1165 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9960 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9960 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9960 # number of overall hits -system.cpu7.l1c.overall_hits::total 9960 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36684 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36684 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23790 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23790 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60474 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60474 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60474 # number of overall misses -system.cpu7.l1c.overall_misses::total 60474 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 611011013 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 611011013 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 715403706 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 715403706 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1326414719 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1326414719 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1326414719 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1326414719 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45479 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45479 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24955 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24955 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70434 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70434 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70434 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70434 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806614 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.806614 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953316 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.953316 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.858591 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.858591 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.858591 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.858591 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16656.062943 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 16656.062943 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 30071.614376 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 30071.614376 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 21933.636257 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 21933.636257 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 21933.636257 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 21933.636257 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 829723 # number of cycles access was blocked +system.cpu7.l1c.demand_hits::cpu7 10081 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 10081 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 10081 # number of overall hits +system.cpu7.l1c.overall_hits::total 10081 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36493 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36493 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23963 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23963 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60456 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60456 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60456 # number of overall misses +system.cpu7.l1c.overall_misses::total 60456 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 649044669 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 649044669 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 555516702 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 555516702 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1204561371 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1204561371 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1204561371 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1204561371 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45409 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45409 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25128 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25128 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70537 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70537 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70537 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70537 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.803651 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.803651 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953637 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953637 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.857082 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.857082 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.857082 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.857082 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 17785.456636 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 17785.456636 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 23182.268581 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 23182.268581 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 19924.595921 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 19924.595921 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 19924.595921 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 19924.595921 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 753584 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 63058 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 60106 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 13.158093 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.537584 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9746 # number of writebacks -system.cpu7.l1c.writebacks::total 9746 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36684 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36684 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23790 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23790 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60474 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60474 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60474 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60474 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9918 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9918 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5421 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5421 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15339 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15339 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 574327013 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 574327013 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 691615706 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 691615706 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1265942719 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1265942719 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1265942719 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1265942719 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 726668427 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 726668427 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 847371643 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 847371643 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1574040070 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1574040070 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806614 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806614 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953316 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953316 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858591 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.858591 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858591 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.858591 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15656.062943 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15656.062943 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 29071.698445 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 29071.698445 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20933.669329 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20933.669329 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20933.669329 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20933.669329 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 73267.637326 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73267.637326 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 156312.791551 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156312.791551 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 102616.863550 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 102616.863550 # average overall mshr uncacheable latency +system.cpu7.l1c.writebacks::writebacks 9825 # number of writebacks +system.cpu7.l1c.writebacks::total 9825 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36493 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36493 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23963 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23963 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60456 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60456 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60456 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60456 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9946 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9946 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5477 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5477 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15423 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15423 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 612553669 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 612553669 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 531553702 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 531553702 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1144107371 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1144107371 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1144107371 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1144107371 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 750008205 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 750008205 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 931574803 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 931574803 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1681583008 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1681583008 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.803651 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.803651 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953637 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953637 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857082 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.857082 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857082 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.857082 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 16785.511441 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 16785.511441 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 22182.268581 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 22182.268581 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 18924.629003 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 18924.629003 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 18924.629003 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 18924.629003 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 75408.023829 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75408.023829 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 170088.516158 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 170088.516158 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 109030.863516 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 109030.863516 # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 14328 # number of replacements -system.l2c.tags.tagsinuse 791.177993 # Cycle average of tags in use -system.l2c.tags.total_refs 163940 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 15120 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.842593 # Average number of references to valid blocks. +system.l2c.tags.replacements 13679 # number of replacements +system.l2c.tags.tagsinuse 785.030982 # Cycle average of tags in use +system.l2c.tags.total_refs 164295 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14481 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.345556 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 732.189847 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 7.660754 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 7.418431 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 7.928491 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 7.181835 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 7.391664 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.508374 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 7.134486 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 7.764111 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.715029 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.007481 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.007245 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.007743 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.007014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.007218 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.006356 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006967 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.007582 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.772635 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 792 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 650 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 2105170 # Number of tag accesses -system.l2c.tags.data_accesses 2105170 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 77576 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 77576 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0 276 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 259 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 279 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 261 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 303 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 269 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 291 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 289 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2227 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1751 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1771 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1804 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1773 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1863 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1769 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1750 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1757 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 14238 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0 10760 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1 10778 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2 10893 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3 11049 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu4 10672 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu5 10913 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu6 11141 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu7 10949 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 87155 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0 12511 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12549 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12697 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12822 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12535 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12682 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12891 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12706 # number of demand (read+write) hits -system.l2c.demand_hits::total 101393 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12511 # number of overall hits -system.l2c.overall_hits::cpu1 12549 # number of overall hits -system.l2c.overall_hits::cpu2 12697 # number of overall hits -system.l2c.overall_hits::cpu3 12822 # number of overall hits -system.l2c.overall_hits::cpu4 12535 # number of overall hits -system.l2c.overall_hits::cpu5 12682 # number of overall hits -system.l2c.overall_hits::cpu6 12891 # number of overall hits -system.l2c.overall_hits::cpu7 12706 # number of overall hits -system.l2c.overall_hits::total 101393 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0 2046 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 2029 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 2111 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 2056 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 2033 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 2090 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 2030 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1987 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 16382 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4599 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4725 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4817 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4668 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4596 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4594 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4511 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4557 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 37067 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0 771 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1 761 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2 769 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3 709 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu4 779 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu5 699 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu6 722 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu7 759 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 5969 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0 5370 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5486 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5586 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5377 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5375 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5293 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5233 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5316 # number of demand (read+write) misses -system.l2c.demand_misses::total 43036 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5370 # number of overall misses -system.l2c.overall_misses::cpu1 5486 # number of overall misses -system.l2c.overall_misses::cpu2 5586 # number of overall misses -system.l2c.overall_misses::cpu3 5377 # number of overall misses -system.l2c.overall_misses::cpu4 5375 # number of overall misses -system.l2c.overall_misses::cpu5 5293 # number of overall misses -system.l2c.overall_misses::cpu6 5233 # number of overall misses -system.l2c.overall_misses::cpu7 5316 # number of overall misses -system.l2c.overall_misses::total 43036 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0 72840477 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 70862981 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 74683475 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 72897976 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 72564980 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 68905302 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 71238981 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 72107979 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 576102151 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 293596847 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 301266861 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 306960376 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 297631356 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 293263365 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 292806382 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 287321715 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 290617373 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2363464275 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0 53018410 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1 52427412 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2 53340392 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3 48936413 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu4 53163418 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu5 48227901 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu6 50021405 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu7 52163904 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 411299255 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0 346615257 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 353694273 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 360300768 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 346567769 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 346426783 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 341034283 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 337343120 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 342781277 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2774763530 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 346615257 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 353694273 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 360300768 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 346567769 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 346426783 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 341034283 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 337343120 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 342781277 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2774763530 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 77576 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 77576 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2322 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2288 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2390 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2317 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2336 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2359 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2321 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2276 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18609 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6350 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6496 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6621 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6441 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6459 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6363 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6261 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6314 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 51305 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0 11531 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1 11539 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2 11662 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3 11758 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu4 11451 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu5 11612 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu6 11863 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu7 11708 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 93124 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17881 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 18035 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 18283 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 18199 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17910 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17975 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 18124 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 18022 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 144429 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17881 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 18035 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 18283 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 18199 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17910 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17975 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 18124 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 18022 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 144429 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.881137 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.886801 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.883264 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.887354 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.870291 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.885969 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.874623 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.873023 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.880327 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.724252 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.727371 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.727534 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.724732 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.711565 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.721986 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.720492 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.721729 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.722483 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0 0.066863 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1 0.065950 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2 0.065941 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3 0.060299 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu4 0.068029 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu5 0.060196 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu6 0.060862 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu7 0.064827 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.064097 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0 0.300319 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.304186 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.305530 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.295456 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.300112 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.294465 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.288733 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.294973 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.297973 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.300319 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.304186 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.305530 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.295456 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.300112 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.294465 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.288733 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.294973 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.297973 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0 35601.406158 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 34925.076885 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 35378.244908 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 35456.214008 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 35693.546483 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 32969.044019 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 35093.094089 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 36289.873679 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 35166.777622 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 63839.279626 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 63760.182222 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 63724.387793 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 63759.930591 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 63808.390992 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 63736.696125 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 63693.574595 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 63773.836515 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 63761.952006 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0 68765.771725 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1 68892.788436 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2 69363.318596 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69021.739069 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu4 68245.722721 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu5 68995.566524 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu6 69281.724377 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu7 68727.146245 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 68905.889596 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 64546.602793 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 64472.160591 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 64500.674544 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 64453.741678 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 64451.494512 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 64431.188929 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 64464.574814 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 64481.052859 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 64475.405010 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 64546.602793 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 64472.160591 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 64500.674544 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 64453.741678 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 64451.494512 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 64431.188929 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 64464.574814 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 64481.052859 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 64475.405010 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 37689 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 728.912576 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 7.109869 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 7.264593 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.067016 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 7.280147 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.468572 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 6.873708 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 6.969066 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 7.085434 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.711829 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.006943 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.007094 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.006901 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.007110 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.006317 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.006713 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.006806 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.006919 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.766632 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 802 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 674 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 2100989 # Number of tag accesses +system.l2c.tags.data_accesses 2100989 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 77660 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 77660 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0 265 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 275 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 255 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 290 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 283 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 292 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 297 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 302 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2259 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1784 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1764 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1831 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1735 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1757 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1864 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1767 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1780 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 14282 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0 10784 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1 10837 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2 10882 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3 10814 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu4 10969 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu5 10782 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu6 10825 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu7 10836 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 86729 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0 12568 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12601 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12713 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12549 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12726 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12646 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12592 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12616 # number of demand (read+write) hits +system.l2c.demand_hits::total 101011 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12568 # number of overall hits +system.l2c.overall_hits::cpu1 12601 # number of overall hits +system.l2c.overall_hits::cpu2 12713 # number of overall hits +system.l2c.overall_hits::cpu3 12549 # number of overall hits +system.l2c.overall_hits::cpu4 12726 # number of overall hits +system.l2c.overall_hits::cpu5 12646 # number of overall hits +system.l2c.overall_hits::cpu6 12592 # number of overall hits +system.l2c.overall_hits::cpu7 12616 # number of overall hits +system.l2c.overall_hits::total 101011 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0 1935 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 2063 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 2062 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 2061 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 2025 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 2056 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1973 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 2050 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 16225 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4717 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4573 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4643 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4618 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4604 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4681 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4664 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4698 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 37198 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0 701 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1 741 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2 707 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3 750 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu4 700 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu5 714 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu6 696 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu7 703 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 5712 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0 5418 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5314 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5350 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5368 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5304 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5395 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5360 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5401 # number of demand (read+write) misses +system.l2c.demand_misses::total 42910 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5418 # number of overall misses +system.l2c.overall_misses::cpu1 5314 # number of overall misses +system.l2c.overall_misses::cpu2 5350 # number of overall misses +system.l2c.overall_misses::cpu3 5368 # number of overall misses +system.l2c.overall_misses::cpu4 5304 # number of overall misses +system.l2c.overall_misses::cpu5 5395 # number of overall misses +system.l2c.overall_misses::cpu6 5360 # number of overall misses +system.l2c.overall_misses::cpu7 5401 # number of overall misses +system.l2c.overall_misses::total 42910 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0 33570299 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 36327486 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 35657979 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 35008978 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 34589470 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 34691475 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 32410475 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 35465977 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 277722139 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 161829189 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 155335873 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 157770030 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 156623200 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 158516385 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 158789879 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 159063367 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 159738542 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1267666465 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0 49231417 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1 51778912 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2 49960071 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3 52497915 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu4 48409406 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu5 49972406 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu6 48755897 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu7 49161911 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 399767935 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0 211060606 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 207114785 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 207730101 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 209121115 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 206925791 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 208762285 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 207819264 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 208900453 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 1667434400 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 211060606 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 207114785 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 207730101 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 209121115 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 206925791 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 208762285 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 207819264 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 208900453 # number of overall miss cycles +system.l2c.overall_miss_latency::total 1667434400 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 77660 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 77660 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2200 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2338 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2317 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2351 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2308 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2348 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2270 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2352 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18484 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6501 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6337 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6474 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6353 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6361 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6545 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6431 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6478 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 51480 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0 11485 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1 11578 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2 11589 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3 11564 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu4 11669 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu5 11496 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu6 11521 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu7 11539 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 92441 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17986 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17915 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18063 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17917 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18030 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 18041 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17952 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 18017 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 143921 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17986 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17915 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18063 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17917 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 18030 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 18041 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17952 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18017 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 143921 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.879545 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.882378 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.889944 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.876648 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.877383 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.875639 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.869163 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.871599 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.877786 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.725581 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.721635 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.717176 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.726901 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.723786 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.715202 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.725237 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.725224 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.722572 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0 0.061036 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1 0.064001 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2 0.061006 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3 0.064856 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu4 0.059988 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu5 0.062109 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu6 0.060411 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu7 0.060924 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.061791 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0 0.301234 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.296623 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.296186 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.299604 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.294176 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.299041 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.298574 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.299772 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.298150 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.301234 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.296623 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.296186 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.299604 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.294176 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.299041 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.298574 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.299772 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.298150 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0 17348.991731 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 17609.057683 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 17292.909311 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 16986.403688 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 17081.219753 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 16873.285506 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 16427.002027 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 17300.476585 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 17116.926903 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 34307.650837 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 33968.045703 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 33980.191686 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 33915.807709 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 34430.144440 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 33922.212989 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 34104.495497 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 34001.392507 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 34078.887709 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0 70230.266762 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1 69877.074224 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2 70664.881188 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69997.220000 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu4 69156.294286 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu5 69989.364146 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu6 70051.576149 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu7 69931.594595 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 69987.383578 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 38955.445921 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 38975.307678 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 38828.056262 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 38956.988636 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 39013.158183 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 38695.511585 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 38772.250746 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 38678.106462 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 38858.876719 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 38955.445921 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 38975.307678 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 38828.056262 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 38956.988636 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 39013.158183 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 38695.511585 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 38772.250746 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 38678.106462 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 38858.876719 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 15775 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 7229 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 2328 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 5.213584 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 6.776203 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6662 # number of writebacks -system.l2c.writebacks::total 6662 # number of writebacks +system.l2c.writebacks::writebacks 6347 # number of writebacks +system.l2c.writebacks::total 6347 # number of writebacks system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu1 5 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 8 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 6 # number of ReadExReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 7 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 8 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 8 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 9 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::total 45 # number of ReadExReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0 9 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1 9 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2 12 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu3 7 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu4 14 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu5 5 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu6 8 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu7 8 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 72 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 19 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 17 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 117 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 16 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 19 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 17 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 117 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 1261 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 1261 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 2045 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 2024 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2111 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2055 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 2032 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2090 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 2030 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1987 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 16374 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4592 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4720 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4810 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4661 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4593 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4590 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4505 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4551 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 37022 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0 762 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1 752 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2 757 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu3 702 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu4 765 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu5 694 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu6 714 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu7 751 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 5897 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5354 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5472 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5567 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5363 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5358 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5284 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5219 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5302 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 42919 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5354 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5472 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5567 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5363 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5358 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5284 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5219 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5302 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 42919 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0 9885 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1 9741 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2 9774 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu3 9813 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu4 9945 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu5 9798 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu6 9837 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu7 9918 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 78711 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0 5567 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1 5462 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2 5416 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu3 5447 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu4 5329 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu5 5472 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu6 5532 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu7 5421 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 43646 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0 15452 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1 15203 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu2 15190 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu3 15260 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu4 15274 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu5 15270 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu6 15369 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu7 15339 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 122357 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 109082461 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 108150960 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 112626780 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 109540787 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 108317960 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 111427287 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 108309961 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 105900964 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 873357160 # 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number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2383994734 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 823836500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 813457138 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 811229154 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 815435638 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 815524158 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 816491950 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 822926154 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 820135467 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 6539036159 # number of overall MSHR uncacheable cycles +system.l2c.ReadSharedReq_mshr_hits::cpu0 7 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1 13 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu2 7 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu3 10 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu4 13 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu5 8 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu6 9 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu7 4 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 71 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 20 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 15 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 13 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 18 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 16 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 13 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 20 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 15 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 13 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 18 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 16 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 13 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 116 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 1217 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 1217 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1934 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 2063 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 2062 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 2060 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 2025 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 2055 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1973 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 2050 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 16222 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4714 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4566 # 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number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu6 687 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu7 699 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 5641 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5408 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5294 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5335 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5355 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5286 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5379 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5349 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5388 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 42794 # 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number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 111132111 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 110326921 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 112301120 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 111711839 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 112344259 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 112421561 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 894040481 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 41942368 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 43799223 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 42582401 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 44577742 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 40998173 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 42436532 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 41443209 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 41880731 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 339660379 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 156425796 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 153118465 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 153714512 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 154904663 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 153299293 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 154148371 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 153787468 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 154302292 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1233700860 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 156425796 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 153118465 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 153714512 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 154904663 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 153299293 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 154148371 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 153787468 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 154302292 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1233700860 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 532537334 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 530034961 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 522091524 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 528677272 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 531067932 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 528334987 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 526505398 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 532738235 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 4231987643 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 302507401 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 304491446 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 306673088 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 296941482 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 299721877 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 297975047 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 302462757 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 303375300 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2414148398 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 835044735 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 834526407 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 828764612 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 825618754 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 830789809 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 826310034 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 828968155 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 836113535 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 6646136041 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.880706 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.884615 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.883264 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.886923 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.869863 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.885969 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.874623 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.873023 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.879897 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.723150 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.726601 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.726476 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.723645 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.711101 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.721358 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.719534 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.720779 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.721606 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.066083 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.065170 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.064912 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.059704 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.066806 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.059766 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.060187 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.064144 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063324 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.299424 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.303410 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.304491 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.294687 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.299162 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.293964 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.287961 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.294196 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.297163 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.299424 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.303410 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.304491 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.294687 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.299162 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.293964 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.287961 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.294196 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.297163 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 53341.056724 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 53434.268775 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 53352.335386 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 53304.519221 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 53306.082677 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 53314.491388 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 53354.660591 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 53296.911928 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 53338.045682 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 53883.459930 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 53797.322458 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 53787.708108 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 53824.577558 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 53807.612671 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 53775.355556 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 53766.751387 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 53809.574379 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 53806.527929 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 59102.244094 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 59354.937500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59851.245707 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59219.962963 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 58804.469281 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 59213.835735 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59609.813725 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 58991.884154 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59266.536035 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 54626.215540 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 54561.088268 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 54612.227232 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 54530.816707 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 54521.049645 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 54489.644966 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 54566.127994 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 54543.620898 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 54556.724062 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 54626.215540 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 54561.088268 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 54612.227232 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 54530.816707 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 54521.049645 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 54489.644966 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 54566.127994 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 54543.620898 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 54556.724062 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 52764.098533 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 52785.315368 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 52765.784326 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 52785.004688 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 52769.356762 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 52816.364564 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 52783.700823 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 52838.805102 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 52788.573706 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 54295.560625 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 54792.270414 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 54559.892541 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 54609.213696 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 54556.747044 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 54641.302997 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 54897.485358 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 54617.265818 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 54621.150483 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 53315.849081 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 53506.356509 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 53405.474259 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 53436.149279 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 53392.965693 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 53470.330714 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 53544.547726 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 53467.336006 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 53442.272686 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.879091 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.882378 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.889944 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.876223 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.877383 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.875213 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.869163 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.871599 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.877624 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.725119 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.720530 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.715941 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.726428 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.723000 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.713980 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.724926 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.723835 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.721698 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.060427 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.062878 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.060402 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.063992 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.058874 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.061413 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.059630 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.060577 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.061023 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.300678 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.295507 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.295355 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.298878 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.293178 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.298154 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.297961 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.299051 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.297344 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.300678 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.295507 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.295355 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.298878 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.293178 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.298154 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.297961 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.299051 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.297344 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 20793.145295 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 20771.712555 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 20719.084384 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 20737.336893 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 20718.154568 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 20760.129440 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 20722.885454 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 20708.580488 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20741.143139 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 24285.835384 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 23942.015331 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 23976.722977 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 23906.158397 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 24418.595347 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 23905.807618 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 24097.867653 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 23975.594157 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 24063.749388 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 60435.688761 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 60163.767857 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 60832.001429 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 60240.191892 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 59677.107715 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 60108.402266 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 60324.903930 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59915.208870 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 60212.795426 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 28924.888314 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 28923.019456 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 28812.467104 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 28927.107937 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 29001.001324 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 28657.440231 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 28750.695083 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 28638.138827 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 28828.827873 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 28924.888314 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 28923.019456 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 28812.467104 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 28927.107937 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 29001.001324 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 28657.440231 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 28750.695083 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 28638.138827 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 28828.827873 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 53478.342438 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 53528.071198 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 53575.323140 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 53520.679490 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 53508.103980 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 53534.804641 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 53571.977818 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 53563.064046 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 53534.903328 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 55252.493333 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 55271.636595 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 55356.153069 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 55111.633630 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 55462.967617 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 55437.218047 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 55650.921251 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 55411.013699 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 55369.106167 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 54107.738936 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 54151.346895 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 54220.779326 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 54082.192716 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 54197.260682 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 54205.591315 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 54312.268558 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 54219.151482 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 54186.935729 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.snoop_filter.tot_requests 127545 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 121489 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 125196 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 119242 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.trans_dist::ReadReq 78710 # Transaction distribution -system.membus.trans_dist::ReadResp 84594 # Transaction distribution -system.membus.trans_dist::WriteReq 43645 # Transaction distribution -system.membus.trans_dist::WriteResp 43644 # Transaction distribution -system.membus.trans_dist::WritebackDirty 6662 # Transaction distribution -system.membus.trans_dist::CleanEvict 1288 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60944 # Transaction distribution -system.membus.trans_dist::UpgradeResp 50160 # Transaction distribution -system.membus.trans_dist::ReadExReq 49324 # Transaction distribution -system.membus.trans_dist::ReadExResp 3261 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 5890 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 428122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 428122 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1134381 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1134381 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 56843 # Total snoops (count) -system.membus.snoop_fanout::samples 246442 # Request fanout histogram +system.membus.trans_dist::ReadReq 79046 # Transaction distribution +system.membus.trans_dist::ReadResp 84668 # Transaction distribution +system.membus.trans_dist::WriteReq 43599 # Transaction distribution +system.membus.trans_dist::WriteResp 43596 # Transaction distribution +system.membus.trans_dist::WritebackDirty 6347 # Transaction distribution +system.membus.trans_dist::CleanEvict 1243 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60999 # Transaction distribution +system.membus.trans_dist::ReadExReq 49250 # Transaction distribution +system.membus.trans_dist::ReadExResp 3150 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 5631 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 377529 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 377529 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1090828 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1090828 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 56847 # Total snoops (count) +system.membus.snoop_fanout::samples 245688 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 246442 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 245688 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 246442 # Request fanout histogram -system.membus.reqLayer0.occupancy 292771939 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 54.1 # Layer utilization (%) -system.membus.respLayer0.occupancy 296967000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 54.9 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 667370 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 284034 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 336982 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 12889 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 5997 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 6892 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 78711 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 370868 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 5 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43646 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43643 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 84238 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 20479 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29389 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29387 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 162232 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 162225 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 292173 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122572 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122578 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122851 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122953 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122545 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122770 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122967 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122678 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 981914 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1769628 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1794530 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1801428 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1802844 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1789097 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1796324 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1791880 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1784489 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14330220 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 335082 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 628739 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.148986 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.990092 # Request fanout histogram +system.membus.snoop_fanout::total 245688 # Request fanout histogram +system.membus.reqLayer0.occupancy 290283631 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 54.2 # Layer utilization (%) +system.membus.respLayer0.occupancy 245575000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 45.9 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 665524 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 283935 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 335837 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 12315 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 5744 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 6571 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 79051 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 371557 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43601 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43596 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 84007 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 105887 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29231 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29230 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 162413 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 162411 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 292528 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133547 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 133251 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 133734 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133419 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 133559 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133487 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133484 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 133586 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1068067 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1785416 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1780080 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1798067 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1787232 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1784031 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1801672 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1781660 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1785403 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14303561 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 335445 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 626448 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.148675 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.987271 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 176143 28.02% 28.02% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 257926 41.02% 69.04% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 134453 21.38% 90.42% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 47224 7.51% 97.93% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 11211 1.78% 99.72% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 1632 0.26% 99.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 146 0.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 174709 27.89% 27.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 258191 41.22% 69.10% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 133874 21.37% 90.47% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 46929 7.49% 97.97% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 11007 1.76% 99.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 1601 0.26% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 133 0.02% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::7 4 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 628739 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 500695190 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 92.6 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 101141048 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 18.7 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 101214213 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 18.7 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 101195728 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 18.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 101296930 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 18.7 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 101179412 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 18.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 101203668 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 18.7 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 101388789 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 18.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 101354632 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 18.7 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 626448 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 498178453 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 93.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 102533331 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 19.2 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 102040683 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 19.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 102532818 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 19.2 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 102294677 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 19.1 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 102527849 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 19.2 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 102329742 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 19.1 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 102510939 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 19.2 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 102349372 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 19.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index ffbbc56b2..36475e393 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -1,1811 +1,1811 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000534 # Number of seconds simulated -sim_ticks 534039500 # Number of ticks simulated -final_tick 534039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000530 # Number of seconds simulated +sim_ticks 530176500 # Number of ticks simulated +final_tick 530176500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 46952087 # Simulator tick rate (ticks/s) -host_mem_usage 215976 # Number of bytes of host memory used -host_seconds 11.37 # Real time elapsed on the host +host_tick_rate 118834220 # Simulator tick rate (ticks/s) +host_mem_usage 236308 # Number of bytes of host memory used +host_seconds 4.46 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 80135 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 83816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 79566 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 82290 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 82935 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 84320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 79631 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 84304 # Number of bytes read from this memory -system.physmem.bytes_read::total 656997 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 418368 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5512 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5388 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5320 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5503 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5449 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5363 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5499 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5488 # Number of bytes written to this memory -system.physmem.bytes_written::total 461890 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10898 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10988 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10833 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10911 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10989 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10862 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10835 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10972 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87288 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6537 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5512 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5388 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5320 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5503 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5449 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5363 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5499 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5488 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50059 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 150054444 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 156947192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 148988979 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 154089726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 155297501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 157890943 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 149110693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 157860982 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1230240460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 783402726 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 10321334 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 10089141 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 9961810 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 10304481 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 10203365 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 10042328 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 10296991 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 10276393 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 864898570 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 783402726 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 160375777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 167036333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 158950789 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 164394207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 165500867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 167933271 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 159407684 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 168137376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2095139030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 78184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 80178 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 79911 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 80308 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 82157 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 80611 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 79164 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 81441 # Number of bytes read from this memory +system.physmem.bytes_read::total 641954 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 404160 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5485 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5400 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5418 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5526 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5422 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5458 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5386 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5538 # Number of bytes written to this memory +system.physmem.bytes_written::total 447793 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10774 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10815 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10863 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11071 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10904 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10870 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10935 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10881 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87113 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6315 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5485 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5400 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5418 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5526 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5422 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5458 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5386 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5538 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49948 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 147467872 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 151228883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 150725277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 151474085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 154961602 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 152045592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 149316313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 153611109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1210830733 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 762312173 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 10345611 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 10185287 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 10219238 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 10422944 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 10226783 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 10294685 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 10158881 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 10445578 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 844611181 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 762312173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 157813483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 161414171 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 160944516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 161897029 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 165188385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 162340277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 159475194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 164056687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2055441914 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 98970 # number of read accesses completed -system.cpu0.num_writes 54697 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22262 # number of replacements -system.cpu0.l1c.tags.tagsinuse 392.444163 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13142 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22657 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.580041 # Average number of references to valid blocks. +system.cpu0.num_reads 99175 # number of read accesses completed +system.cpu0.num_writes 54789 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22440 # number of replacements +system.cpu0.l1c.tags.tagsinuse 392.189512 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13440 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22832 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.588648 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 392.444163 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.766493 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.766493 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 335259 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 335259 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8424 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8424 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1108 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1108 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9532 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9532 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9532 # number of overall hits -system.cpu0.l1c.overall_hits::total 9532 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36392 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36392 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23768 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23768 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60160 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60160 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60160 # number of overall misses -system.cpu0.l1c.overall_misses::total 60160 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 598420373 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 598420373 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 705577272 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 705577272 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1303997645 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1303997645 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1303997645 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1303997645 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44816 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44816 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24876 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24876 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 69692 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 69692 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 69692 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 69692 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.812031 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.812031 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.955459 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.955459 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.863227 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.863227 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.863227 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.863227 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16443.734145 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 16443.734145 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 29686.017839 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 29686.017839 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 21675.492769 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 21675.492769 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 21675.492769 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 21675.492769 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 798798 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 392.189512 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.765995 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.765995 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 392 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 373 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 338141 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 338141 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8693 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8693 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1204 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1204 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9897 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9897 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9897 # number of overall hits +system.cpu0.l1c.overall_hits::total 9897 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36509 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36509 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23927 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23927 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60436 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60436 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60436 # number of overall misses +system.cpu0.l1c.overall_misses::total 60436 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 645236912 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 645236912 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 543361201 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 543361201 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1188598113 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1188598113 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1188598113 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1188598113 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45202 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45202 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25131 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25131 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70333 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70333 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70333 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70333 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807686 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.807686 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.952091 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.952091 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.859284 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.859284 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.859284 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.859284 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 17673.365800 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 17673.365800 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 22709.123626 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 22709.123626 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 19667.054620 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 19667.054620 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 19667.054620 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 19667.054620 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 716464 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 61887 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 58624 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.907363 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.221343 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9766 # number of writebacks -system.cpu0.l1c.writebacks::total 9766 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36392 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36392 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23768 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23768 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60160 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60160 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60160 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60160 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9799 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9799 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5512 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5512 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15311 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15311 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 562029373 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 562029373 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 681810272 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 681810272 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1243839645 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1243839645 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1243839645 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1243839645 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 706647630 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 706647630 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 855364129 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 855364129 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1562011759 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1562011759 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.812031 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.812031 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.955459 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.955459 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.863227 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.863227 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.863227 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.863227 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15443.761623 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15443.761623 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 28686.059912 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 28686.059912 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20675.526014 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20675.526014 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20675.526014 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20675.526014 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 72114.259618 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 72114.259618 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 155182.171444 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155182.171444 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 102018.924891 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 102018.924891 # average overall mshr uncacheable latency +system.cpu0.l1c.writebacks::writebacks 9950 # number of writebacks +system.cpu0.l1c.writebacks::total 9950 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36509 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36509 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23927 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23927 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60436 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60436 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60436 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60436 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9705 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9705 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5489 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5489 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15194 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15194 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 608727912 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 608727912 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 519435201 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 519435201 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1128163113 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1128163113 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1128163113 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1128163113 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 718425919 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 718425919 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 939004763 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 939004763 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1657430682 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1657430682 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807686 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807686 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.952091 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.952091 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859284 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.859284 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859284 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.859284 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 16673.365800 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 16673.365800 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 21709.165420 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 21709.165420 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 18667.071166 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 18667.071166 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 18667.071166 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 18667.071166 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 74026.369809 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74026.369809 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 171070.279286 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 171070.279286 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 109084.551928 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 109084.551928 # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 98379 # number of read accesses completed -system.cpu1.num_writes 54883 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22236 # number of replacements -system.cpu1.l1c.tags.tagsinuse 391.015365 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13378 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22622 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.591371 # Average number of references to valid blocks. +system.cpu1.num_reads 99705 # number of read accesses completed +system.cpu1.num_writes 54823 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22335 # number of replacements +system.cpu1.l1c.tags.tagsinuse 390.697643 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13624 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22725 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.599516 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 391.015365 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.763702 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.763702 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_blocks::cpu1 390.697643 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.763081 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.763081 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 390 # Occupied blocks per task id system.cpu1.l1c.tags.age_task_id_blocks_1024::0 375 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 335372 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 335372 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8546 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8546 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1143 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1143 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9689 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9689 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9689 # number of overall hits -system.cpu1.l1c.overall_hits::total 9689 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36240 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36240 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23835 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23835 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60075 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60075 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60075 # number of overall misses -system.cpu1.l1c.overall_misses::total 60075 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 593535449 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 593535449 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 712426271 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 712426271 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1305961720 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1305961720 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1305961720 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1305961720 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 44786 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 44786 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24978 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24978 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 69764 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 69764 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 69764 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 69764 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.809181 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.809181 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954240 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954240 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.861117 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.861117 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.861117 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.861117 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16377.909741 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 16377.909741 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 29889.921166 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 29889.921166 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 21738.855098 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 21738.855098 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 21738.855098 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 21738.855098 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 803378 # number of cycles access was blocked +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 339221 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 339221 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8840 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8840 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1148 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1148 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9988 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9988 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9988 # number of overall hits +system.cpu1.l1c.overall_hits::total 9988 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36605 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36605 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23987 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23987 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60592 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60592 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60592 # number of overall misses +system.cpu1.l1c.overall_misses::total 60592 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 646842299 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 646842299 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 543658224 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 543658224 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1190500523 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1190500523 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1190500523 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1190500523 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45445 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45445 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 25135 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 25135 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70580 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70580 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70580 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70580 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805479 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.805479 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954327 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954327 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.858487 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.858487 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.858487 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.858487 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 17670.872804 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 17670.872804 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 22664.702714 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 22664.702714 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 19647.816923 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 19647.816923 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 19647.816923 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 19647.816923 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 718948 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 62137 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 59028 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.929140 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.179779 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9779 # number of writebacks -system.cpu1.l1c.writebacks::total 9779 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36240 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36240 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23835 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23835 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60075 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60075 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60075 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60075 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9833 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9833 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5388 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5388 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15221 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15221 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 557295449 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 557295449 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 688592271 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 688592271 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1245887720 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1245887720 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1245887720 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1245887720 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 707451122 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 707451122 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 858171680 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 858171680 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1565622802 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1565622802 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.809181 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.809181 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954240 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954240 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.861117 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.861117 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.861117 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.861117 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15377.909741 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15377.909741 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 28889.963121 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 28889.963121 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20738.871744 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20738.871744 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20738.871744 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20738.871744 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 71946.620767 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71946.620767 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 159274.625093 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159274.625093 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 102859.391761 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 102859.391761 # average overall mshr uncacheable latency +system.cpu1.l1c.writebacks::writebacks 9932 # number of writebacks +system.cpu1.l1c.writebacks::total 9932 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36605 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36605 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23987 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23987 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60592 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60592 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60592 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60592 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9715 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9715 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5400 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5400 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15115 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15115 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 610238299 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 610238299 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 519672224 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 519672224 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1129910523 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1129910523 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1129910523 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1129910523 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 721621903 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 721621903 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 954237303 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 954237303 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1675859206 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1675859206 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805479 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805479 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954327 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954327 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858487 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.858487 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858487 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.858487 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 16670.900123 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 16670.900123 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 21664.744403 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 21664.744403 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 18647.849931 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 18647.849931 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 18647.849931 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 18647.849931 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 74279.145960 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74279.145960 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 176710.611667 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 176710.611667 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 110873.913728 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 110873.913728 # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99126 # number of read accesses completed -system.cpu2.num_writes 55057 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22416 # number of replacements -system.cpu2.l1c.tags.tagsinuse 392.045662 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13448 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22823 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.589230 # Average number of references to valid blocks. +system.cpu2.num_reads 99117 # number of read accesses completed +system.cpu2.num_writes 54908 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22381 # number of replacements +system.cpu2.l1c.tags.tagsinuse 392.253516 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13534 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22797 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.593675 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 392.045662 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.765714 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.765714 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 407 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 394 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 337969 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 337969 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8656 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8656 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1187 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1187 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9843 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9843 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9843 # number of overall hits -system.cpu2.l1c.overall_hits::total 9843 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36613 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36613 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23839 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23839 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60452 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60452 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60452 # number of overall misses -system.cpu2.l1c.overall_misses::total 60452 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 594021809 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 594021809 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 716005587 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 716005587 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1310027396 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1310027396 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1310027396 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1310027396 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45269 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45269 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25026 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25026 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70295 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70295 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70295 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70295 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.808787 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.808787 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.952569 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.952569 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.859976 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.859976 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.859976 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.859976 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16224.341327 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 16224.341327 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 30035.051261 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 30035.051261 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 21670.538543 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 21670.538543 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 21670.538543 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 21670.538543 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 801429 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 392.253516 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.766120 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.766120 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 405 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 338010 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 338010 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8679 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8679 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1137 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1137 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9816 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9816 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9816 # number of overall hits +system.cpu2.l1c.overall_hits::total 9816 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36478 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36478 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 24024 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 24024 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60502 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60502 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60502 # number of overall misses +system.cpu2.l1c.overall_misses::total 60502 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 647459345 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 647459345 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 543523925 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 543523925 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1190983270 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1190983270 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1190983270 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1190983270 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45157 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45157 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25161 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25161 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70318 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70318 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70318 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70318 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.807804 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.807804 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954811 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.954811 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.860406 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.860406 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.860406 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.860406 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 17749.310406 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 17749.310406 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 22624.206002 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 22624.206002 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 19685.023140 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 19685.023140 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 19685.023140 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 19685.023140 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 722959 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 62324 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 59032 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.859075 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.246900 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9798 # number of writebacks -system.cpu2.l1c.writebacks::total 9798 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36613 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36613 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23839 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23839 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60452 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60452 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60452 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60452 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9743 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9743 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5322 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5322 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15065 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15065 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 557410809 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 557410809 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 692167587 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 692167587 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1249578396 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1249578396 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1249578396 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1249578396 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 702012144 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 702012144 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 835893746 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 835893746 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1537905890 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1537905890 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.808787 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.808787 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.952569 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.952569 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859976 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.859976 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859976 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.859976 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15224.395952 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15224.395952 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 29035.093209 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 29035.093209 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20670.588169 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20670.588169 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20670.588169 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20670.588169 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 72052.975880 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 72052.975880 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 157063.838031 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157063.838031 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 102084.692333 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 102084.692333 # average overall mshr uncacheable latency +system.cpu2.l1c.writebacks::writebacks 9774 # number of writebacks +system.cpu2.l1c.writebacks::total 9774 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36478 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36478 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24024 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 24024 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60502 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60502 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60502 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60502 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9767 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9767 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5419 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5419 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15186 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15186 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 610981345 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 610981345 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 519499925 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 519499925 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1130481270 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1130481270 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1130481270 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1130481270 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 722748371 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 722748371 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 934057840 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 934057840 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1656806211 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1656806211 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.807804 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.807804 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954811 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954811 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.860406 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.860406 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.860406 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.860406 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 16749.310406 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 16749.310406 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 21624.206002 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 21624.206002 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 18685.023140 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 18685.023140 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 18685.023140 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 18685.023140 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 73999.014129 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73999.014129 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 172367.196900 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 172367.196900 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 109100.896286 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 109100.896286 # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99267 # number of read accesses completed -system.cpu3.num_writes 54937 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22308 # number of replacements -system.cpu3.l1c.tags.tagsinuse 393.396608 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13642 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22699 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.600996 # Average number of references to valid blocks. +system.cpu3.num_reads 100000 # number of read accesses completed +system.cpu3.num_writes 55255 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22194 # number of replacements +system.cpu3.l1c.tags.tagsinuse 391.395366 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13678 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22603 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.605141 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 393.396608 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.768353 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.768353 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 377 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 336965 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 336965 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8834 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8834 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1126 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1126 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9960 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9960 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9960 # number of overall hits -system.cpu3.l1c.overall_hits::total 9960 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36404 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36404 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23769 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23769 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60173 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60173 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60173 # number of overall misses -system.cpu3.l1c.overall_misses::total 60173 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 595557078 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 595557078 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 707954928 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 707954928 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1303512006 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1303512006 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1303512006 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1303512006 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45238 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45238 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24895 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24895 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70133 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70133 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70133 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70133 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.804722 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.804722 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954770 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.954770 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.857984 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.857984 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.857984 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.857984 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16359.660422 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 16359.660422 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 29784.800707 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 29784.800707 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 21662.739202 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 21662.739202 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 21662.739202 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 21662.739202 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 796210 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 391.395366 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.764444 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.764444 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 403 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 337339 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 337339 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8923 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8923 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1132 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1132 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 10055 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 10055 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 10055 # number of overall hits +system.cpu3.l1c.overall_hits::total 10055 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36521 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36521 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23639 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23639 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60160 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60160 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60160 # number of overall misses +system.cpu3.l1c.overall_misses::total 60160 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 641069966 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 641069966 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 531956623 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 531956623 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1173026589 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1173026589 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1173026589 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1173026589 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45444 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45444 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24771 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24771 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70215 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70215 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70215 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70215 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.803648 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.803648 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954301 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.954301 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.856797 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.856797 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.856797 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.856797 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 17553.461461 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 17553.461461 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 22503.347138 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 22503.347138 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 19498.447291 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 19498.447291 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 19498.447291 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 19498.447291 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 718925 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 61792 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 58812 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.885325 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.224121 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9835 # number of writebacks -system.cpu3.l1c.writebacks::total 9835 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36404 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36404 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23769 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23769 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60173 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60173 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60173 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60173 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9778 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9778 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5503 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5503 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15281 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15281 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 559153078 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 559153078 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 684188928 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 684188928 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1243342006 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1243342006 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1243342006 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1243342006 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 702217176 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 702217176 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 867552200 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 867552200 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1569769376 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1569769376 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.804722 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.804722 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954770 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954770 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.857984 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.857984 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.857984 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.857984 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15359.660422 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15359.660422 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 28784.926922 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 28784.926922 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20662.789058 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20662.789058 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20662.789058 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20662.789058 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 71816.033545 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71816.033545 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 157650.772306 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157650.772306 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 102726.874943 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 102726.874943 # average overall mshr uncacheable latency +system.cpu3.l1c.writebacks::writebacks 9851 # number of writebacks +system.cpu3.l1c.writebacks::total 9851 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36521 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36521 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23639 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23639 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60160 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60160 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60160 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60160 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9973 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9973 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5527 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5527 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15500 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15500 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 604549966 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 604549966 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 508318623 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 508318623 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1112868589 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1112868589 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1112868589 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1112868589 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 738348758 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 738348758 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 962176807 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 962176807 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1700525565 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1700525565 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.803648 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.803648 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954301 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954301 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.856797 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.856797 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.856797 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.856797 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 16553.488842 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 16553.488842 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 21503.389441 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 21503.389441 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 18498.480535 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 18498.480535 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 18498.480535 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 18498.480535 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 74034.769678 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74034.769678 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 174086.630541 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174086.630541 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 109711.326774 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 109711.326774 # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 98613 # number of read accesses completed -system.cpu4.num_writes 54610 # number of write accesses completed -system.cpu4.l1c.tags.replacements 21998 # number of replacements -system.cpu4.l1c.tags.tagsinuse 392.447255 # Cycle average of tags in use +system.cpu4.num_reads 98958 # number of read accesses completed +system.cpu4.num_writes 54718 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22445 # number of replacements +system.cpu4.l1c.tags.tagsinuse 392.205168 # Cycle average of tags in use system.cpu4.l1c.tags.total_refs 13326 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22393 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.595097 # Average number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22839 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.583476 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 392.447255 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.766499 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.766499 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 385 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 335144 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 335144 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8557 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8557 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1170 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1170 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9727 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9727 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9727 # number of overall hits -system.cpu4.l1c.overall_hits::total 9727 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36223 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36223 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23758 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23758 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 59981 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 59981 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 59981 # number of overall misses -system.cpu4.l1c.overall_misses::total 59981 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 587952444 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 587952444 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 716203349 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 716203349 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1304155793 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1304155793 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1304155793 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1304155793 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 44780 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 44780 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24928 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24928 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 69708 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 69708 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 69708 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 69708 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.808910 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.808910 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953065 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.953065 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.860461 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.860461 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.860461 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.860461 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16231.467410 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 16231.467410 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 30145.776118 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 30145.776118 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 21742.815108 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 21742.815108 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 21742.815108 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 21742.815108 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 805297 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 392.205168 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.766026 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.766026 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 383 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 336585 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 336585 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8551 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8551 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1195 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1195 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9746 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9746 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9746 # number of overall hits +system.cpu4.l1c.overall_hits::total 9746 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36430 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36430 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23820 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23820 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60250 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60250 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60250 # number of overall misses +system.cpu4.l1c.overall_misses::total 60250 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 646410865 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 646410865 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 541537295 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 541537295 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1187948160 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1187948160 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1187948160 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1187948160 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44981 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44981 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25015 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25015 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 69996 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 69996 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 69996 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 69996 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.809898 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.809898 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952229 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.952229 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.860763 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.860763 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.860763 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.860763 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 17743.916141 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 17743.916141 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 22734.563182 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 22734.563182 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 19716.981909 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 19716.981909 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 19716.981909 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 19716.981909 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 719943 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 61957 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 58800 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.997676 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.243929 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9749 # number of writebacks -system.cpu4.l1c.writebacks::total 9749 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36223 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36223 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23758 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23758 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 59981 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 59981 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 59981 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 59981 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9847 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9847 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5452 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5452 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15299 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15299 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 551729444 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 551729444 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 692447349 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 692447349 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1244176793 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1244176793 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1244176793 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1244176793 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 708336585 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 708336585 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 860694197 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 860694197 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1569030782 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1569030782 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.808910 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.808910 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953065 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953065 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.860461 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.860461 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.860461 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.860461 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15231.467410 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15231.467410 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 29145.860300 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 29145.860300 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20742.848452 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20742.848452 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20742.848452 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20742.848452 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 71934.252564 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71934.252564 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157867.607667 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157867.607667 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 102557.734623 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 102557.734623 # average overall mshr uncacheable latency +system.cpu4.l1c.writebacks::writebacks 9851 # number of writebacks +system.cpu4.l1c.writebacks::total 9851 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36430 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36430 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23820 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23820 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60250 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60250 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60250 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60250 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9773 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9773 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5424 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5424 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15197 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15197 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 609980865 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 609980865 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 517717295 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 517717295 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1127698160 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1127698160 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1127698160 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1127698160 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 724329762 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 724329762 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 945564873 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 945564873 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1669894635 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1669894635 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.809898 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.809898 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952229 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952229 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.860763 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.860763 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.860763 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.860763 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 16743.916141 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 16743.916141 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 21734.563182 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 21734.563182 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 18716.981909 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 18716.981909 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 18716.981909 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 18716.981909 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 74115.395682 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74115.395682 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 174329.806969 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174329.806969 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 109883.176614 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 109883.176614 # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99530 # number of read accesses completed -system.cpu5.num_writes 55068 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22260 # number of replacements -system.cpu5.l1c.tags.tagsinuse 393.692529 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13670 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22641 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.603772 # Average number of references to valid blocks. +system.cpu5.num_reads 99011 # number of read accesses completed +system.cpu5.num_writes 55007 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22453 # number of replacements +system.cpu5.l1c.tags.tagsinuse 391.576438 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13255 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22854 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.579986 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 393.692529 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.768931 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.768931 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 381 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.744141 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 337364 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 337364 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8908 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8908 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1154 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1154 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 10062 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 10062 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 10062 # number of overall hits -system.cpu5.l1c.overall_hits::total 10062 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36264 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36264 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23895 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23895 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60159 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60159 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60159 # number of overall misses -system.cpu5.l1c.overall_misses::total 60159 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 595565994 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 595565994 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 715910266 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 715910266 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1311476260 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1311476260 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1311476260 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1311476260 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45172 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45172 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25049 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25049 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70221 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70221 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70221 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70221 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.802798 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.802798 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953930 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.953930 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.856710 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.856710 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.856710 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.856710 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16423.064030 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 16423.064030 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 29960.672358 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 29960.672358 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 21800.167224 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 21800.167224 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 21800.167224 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 21800.167224 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 800309 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 391.576438 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.764798 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.764798 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 336606 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 336606 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8524 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8524 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1134 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1134 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9658 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9658 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9658 # number of overall hits +system.cpu5.l1c.overall_hits::total 9658 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36435 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36435 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23892 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23892 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60327 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60327 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60327 # number of overall misses +system.cpu5.l1c.overall_misses::total 60327 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 644721410 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 644721410 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 540612961 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 540612961 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1185334371 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1185334371 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1185334371 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1185334371 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44959 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44959 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25026 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25026 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 69985 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 69985 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 69985 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 69985 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.810405 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.810405 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954687 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.954687 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.861999 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.861999 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.861999 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.861999 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 17695.112117 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 17695.112117 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 22627.363176 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 22627.363176 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 19648.488587 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 19648.488587 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 19648.488587 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 19648.488587 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 717184 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 61932 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 58708 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.922383 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.216120 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9774 # number of writebacks -system.cpu5.l1c.writebacks::total 9774 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36264 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36264 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23895 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23895 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60159 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60159 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60159 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60159 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9698 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9698 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5363 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5363 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15061 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15061 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 559302994 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 559302994 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 692016266 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 692016266 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1251319260 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1251319260 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1251319260 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1251319260 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 697234186 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 697234186 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 847695253 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 847695253 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1544929439 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1544929439 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.802798 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.802798 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953930 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953930 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.856710 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.856710 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.856710 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.856710 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15423.091606 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15423.091606 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 28960.714208 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 28960.714208 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20800.200469 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20800.200469 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20800.200469 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20800.200469 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 71894.636626 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71894.636626 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 158063.630990 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 158063.630990 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 102578.144811 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 102578.144811 # average overall mshr uncacheable latency +system.cpu5.l1c.writebacks::writebacks 9910 # number of writebacks +system.cpu5.l1c.writebacks::total 9910 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36435 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36435 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23892 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23892 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60327 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60327 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60327 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60327 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9763 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9763 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5458 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5458 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15221 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15221 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 608288410 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 608288410 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 516720961 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 516720961 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1125009371 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1125009371 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1125009371 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1125009371 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 723860386 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 723860386 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 946272316 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 946272316 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1670132702 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1670132702 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.810405 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.810405 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954687 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954687 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.861999 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.861999 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.861999 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.861999 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 16695.167010 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 16695.167010 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 21627.363176 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 21627.363176 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 18648.521740 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 18648.521740 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 18648.521740 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 18648.521740 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 74143.233227 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74143.233227 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 173373.454745 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173373.454745 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 109725.556928 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 109725.556928 # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 100001 # number of read accesses completed -system.cpu6.num_writes 54955 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22371 # number of replacements -system.cpu6.l1c.tags.tagsinuse 392.789220 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13659 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22773 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.599789 # Average number of references to valid blocks. +system.cpu6.num_reads 99860 # number of read accesses completed +system.cpu6.num_writes 55212 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22379 # number of replacements +system.cpu6.l1c.tags.tagsinuse 392.641405 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13476 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22769 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.591857 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 392.789220 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.767166 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.767166 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 393 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 338676 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 338676 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8791 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8791 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1193 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1193 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9984 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9984 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9984 # number of overall hits -system.cpu6.l1c.overall_hits::total 9984 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36779 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36779 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23715 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23715 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60494 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60494 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60494 # number of overall misses -system.cpu6.l1c.overall_misses::total 60494 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 595549144 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 595549144 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 708070907 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 708070907 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1303620051 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1303620051 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1303620051 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1303620051 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45570 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45570 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24908 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24908 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70478 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70478 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70478 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70478 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807088 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.807088 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.952104 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.952104 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.858339 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.858339 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.858339 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.858339 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16192.641018 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 16192.641018 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 29857.512418 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 29857.512418 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 21549.576008 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 21549.576008 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 21549.576008 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 21549.576008 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 794028 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 392.641405 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.766878 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.766878 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 390 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 383 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 338111 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 338111 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8761 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8761 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1100 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1100 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9861 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9861 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9861 # number of overall hits +system.cpu6.l1c.overall_hits::total 9861 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36533 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36533 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23935 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23935 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60468 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60468 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60468 # number of overall misses +system.cpu6.l1c.overall_misses::total 60468 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 641137331 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 641137331 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 545446790 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 545446790 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1186584121 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1186584121 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1186584121 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1186584121 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45294 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45294 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25035 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25035 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70329 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70329 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70329 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70329 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806575 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.806575 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.956062 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.956062 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.859788 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.859788 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.859788 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.859788 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 17549.539622 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 17549.539622 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 22788.668895 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 22788.668895 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 19623.339965 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 19623.339965 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 19623.339965 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 19623.339965 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 722832 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 62044 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 59177 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.797821 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.214746 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9773 # number of writebacks -system.cpu6.l1c.writebacks::total 9773 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36779 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36779 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23715 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23715 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60494 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60494 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60494 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60494 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9743 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9743 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5502 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5502 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15245 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15245 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 558770144 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 558770144 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 684356907 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 684356907 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1243127051 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1243127051 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1243127051 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1243127051 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 702205139 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 702205139 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 875087157 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 875087157 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1577292296 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1577292296 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807088 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807088 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.952104 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.952104 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858339 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.858339 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858339 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.858339 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15192.641018 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15192.641018 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 28857.554586 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 28857.554586 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20549.592538 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20549.592538 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20549.592538 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20549.592538 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 72072.784461 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 72072.784461 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 159048.919847 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159048.919847 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 103462.925287 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 103462.925287 # average overall mshr uncacheable latency +system.cpu6.l1c.writebacks::writebacks 9900 # number of writebacks +system.cpu6.l1c.writebacks::total 9900 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36533 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36533 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23935 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23935 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60468 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60468 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60468 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60468 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9853 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9853 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5386 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5386 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15239 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15239 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 604606331 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 604606331 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 521511790 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 521511790 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1126118121 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1126118121 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1126118121 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1126118121 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 730958843 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 730958843 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 936459347 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 936459347 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1667418190 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1667418190 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806575 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806575 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.956062 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.956062 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859788 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.859788 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859788 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.859788 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 16549.594367 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 16549.594367 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 21788.668895 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 21788.668895 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 18623.373040 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 18623.373040 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 18623.373040 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 18623.373040 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 74186.424744 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74186.424744 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 173869.169514 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173869.169514 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 109417.822036 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 109417.822036 # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99732 # number of read accesses completed -system.cpu7.num_writes 55186 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22105 # number of replacements -system.cpu7.l1c.tags.tagsinuse 391.370136 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13595 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22490 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.604491 # Average number of references to valid blocks. +system.cpu7.num_reads 99316 # number of read accesses completed +system.cpu7.num_writes 55530 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22262 # number of replacements +system.cpu7.l1c.tags.tagsinuse 392.242621 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13656 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22650 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.602914 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 391.370136 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.764395 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.764395 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 385 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_blocks::cpu7 392.242621 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.766099 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.766099 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id system.cpu7.l1c.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.751953 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 337196 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 337196 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8779 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8779 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1155 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1155 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9934 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9934 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9934 # number of overall hits -system.cpu7.l1c.overall_hits::total 9934 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36327 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36327 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23913 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23913 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60240 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60240 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60240 # number of overall misses -system.cpu7.l1c.overall_misses::total 60240 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 591115609 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 591115609 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 714870765 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 714870765 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1305986374 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1305986374 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1305986374 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1305986374 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45106 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45106 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25068 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25068 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70174 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70174 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70174 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70174 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805370 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.805370 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953925 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.953925 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.858438 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.858438 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.858438 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.858438 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16272.073361 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 16272.073361 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 29894.649981 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 29894.649981 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 21679.720684 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 21679.720684 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 21679.720684 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 21679.720684 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 800916 # number of cycles access was blocked +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 338652 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 338652 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8912 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8912 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1186 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1186 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 10098 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 10098 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 10098 # number of overall hits +system.cpu7.l1c.overall_hits::total 10098 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36380 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36380 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23998 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23998 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60378 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60378 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60378 # number of overall misses +system.cpu7.l1c.overall_misses::total 60378 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 644409565 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 644409565 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 538142857 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 538142857 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1182552422 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1182552422 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1182552422 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1182552422 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45292 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45292 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25184 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25184 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70476 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70476 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70476 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70476 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.803232 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.803232 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.952907 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.952907 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.856717 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.856717 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.856717 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.856717 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 17713.292056 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 17713.292056 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 22424.487749 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 22424.487749 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 19585.816390 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 19585.816390 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 19585.816390 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 19585.816390 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 716334 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 62109 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 58812 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.895329 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.180065 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9688 # number of writebacks -system.cpu7.l1c.writebacks::total 9688 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36327 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36327 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23913 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23913 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60240 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60240 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60240 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60240 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9808 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9808 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5490 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5490 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15298 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15298 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 554789609 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 554789609 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 690958765 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 690958765 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1245748374 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1245748374 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1245748374 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1245748374 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 704741576 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 704741576 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 868948151 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 868948151 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1573689727 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1573689727 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805370 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805370 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953925 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953925 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858438 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.858438 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858438 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.858438 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15272.100889 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15272.100889 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 28894.691799 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 28894.691799 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20679.753884 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20679.753884 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20679.753884 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20679.753884 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 71853.749592 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71853.749592 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 158278.351730 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 158278.351730 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 102868.984639 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 102868.984639 # average overall mshr uncacheable latency +system.cpu7.l1c.writebacks::writebacks 9846 # number of writebacks +system.cpu7.l1c.writebacks::total 9846 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36380 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36380 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23998 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23998 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60378 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60378 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60378 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60378 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9762 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9762 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5539 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5539 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15301 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15301 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 608029565 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 608029565 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 514144857 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 514144857 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1122174422 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1122174422 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1122174422 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1122174422 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 722808914 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 722808914 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 961004780 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 961004780 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1683813694 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1683813694 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.803232 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.803232 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.952907 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.952907 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.856717 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.856717 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.856717 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.856717 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 16713.292056 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 16713.292056 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 21424.487749 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 21424.487749 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 18585.816390 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 18585.816390 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 18585.816390 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 18585.816390 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 74043.117599 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74043.117599 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 173497.884095 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173497.884095 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 110045.990066 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 110045.990066 # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 13995 # number of replacements -system.l2c.tags.tagsinuse 787.283340 # Cycle average of tags in use -system.l2c.tags.total_refs 163090 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14802 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.018106 # Average number of references to valid blocks. +system.l2c.tags.replacements 13767 # number of replacements +system.l2c.tags.tagsinuse 787.442113 # Cycle average of tags in use +system.l2c.tags.total_refs 164717 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14568 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.306768 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 729.204744 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 7.276243 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 7.685702 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 7.303189 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 7.305571 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.947966 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 7.333904 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 7.314281 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 6.911739 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.712114 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.007106 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.007506 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.007132 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.007134 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.006785 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.007162 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.007143 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006750 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.768831 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 807 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 673 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.788086 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 2092027 # Number of tag accesses -system.l2c.tags.data_accesses 2092027 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 76994 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 76994 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0 283 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 283 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 290 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 275 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 271 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 268 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 273 # number of UpgradeReq hits +system.l2c.tags.occ_blocks::writebacks 730.095360 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 6.568517 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 7.047502 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.052359 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 7.453742 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.826765 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 7.175771 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 7.149899 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 8.072198 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.712984 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.006415 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.006882 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.006887 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.007279 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.006667 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.007008 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.006982 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.007883 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.768986 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 661 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 140 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.782227 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 2101238 # Number of tag accesses +system.l2c.tags.data_accesses 2101238 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 77585 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 77585 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0 280 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 286 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 296 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 265 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 264 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 299 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 295 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu7 273 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2216 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1696 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1826 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1766 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1793 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1691 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1701 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1693 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1794 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 13960 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0 10787 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1 10737 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2 10799 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3 10853 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu4 10789 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu5 10747 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu6 10936 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu7 10812 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 86460 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0 12483 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12563 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12565 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12646 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12480 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12448 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12629 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12606 # number of demand (read+write) hits -system.l2c.demand_hits::total 100420 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12483 # number of overall hits -system.l2c.overall_hits::cpu1 12563 # number of overall hits -system.l2c.overall_hits::cpu2 12565 # number of overall hits -system.l2c.overall_hits::cpu3 12646 # number of overall hits -system.l2c.overall_hits::cpu4 12480 # number of overall hits -system.l2c.overall_hits::cpu5 12448 # number of overall hits -system.l2c.overall_hits::cpu6 12629 # number of overall hits -system.l2c.overall_hits::cpu7 12606 # number of overall hits -system.l2c.overall_hits::total 100420 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0 2004 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 2095 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 2038 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 2061 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 2078 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 2100 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 2074 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 2069 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 16519 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4524 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4568 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4664 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4580 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4684 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4609 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4587 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4667 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 36883 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0 734 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1 790 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2 729 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3 742 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu4 716 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu5 769 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu6 725 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu7 744 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 5949 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0 5258 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5358 # number of demand (read+write) misses +system.l2c.UpgradeReq_hits::total 2258 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1755 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1883 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1739 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1749 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1791 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1796 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1820 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1726 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 14259 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0 10845 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1 10830 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2 10896 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3 10859 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu4 10783 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu5 11038 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu6 10953 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu7 10583 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 86787 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0 12600 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12713 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12635 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12608 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12574 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12834 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12773 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12309 # number of demand (read+write) hits +system.l2c.demand_hits::total 101046 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12600 # number of overall hits +system.l2c.overall_hits::cpu1 12713 # number of overall hits +system.l2c.overall_hits::cpu2 12635 # number of overall hits +system.l2c.overall_hits::cpu3 12608 # number of overall hits +system.l2c.overall_hits::cpu4 12574 # number of overall hits +system.l2c.overall_hits::cpu5 12834 # number of overall hits +system.l2c.overall_hits::cpu6 12773 # number of overall hits +system.l2c.overall_hits::cpu7 12309 # number of overall hits +system.l2c.overall_hits::total 101046 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0 2028 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 2036 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 2114 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 2014 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 2072 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1987 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 2026 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 2019 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 16296 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4674 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4592 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4655 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4541 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4557 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4639 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4724 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4602 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 36984 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0 715 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1 735 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2 738 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3 731 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu4 726 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu5 715 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu6 671 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu7 749 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 5780 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0 5389 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5327 # number of demand (read+write) misses system.l2c.demand_misses::cpu2 5393 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5322 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5400 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5378 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5312 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5411 # number of demand (read+write) misses -system.l2c.demand_misses::total 42832 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5258 # number of overall misses -system.l2c.overall_misses::cpu1 5358 # number of overall misses +system.l2c.demand_misses::cpu3 5272 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5283 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5354 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5395 # 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number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2292 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18554 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6429 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6475 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6394 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6290 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6348 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6435 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6544 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6328 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 51243 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0 11560 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1 11565 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2 11634 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3 11590 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu4 11509 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu5 11753 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu6 11624 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu7 11332 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 92567 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17989 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 18040 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18028 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17880 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17857 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 18188 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 18168 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17660 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 143810 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17989 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 18040 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18028 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17880 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17857 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 18188 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 18168 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17660 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 143810 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.878683 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.876830 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.877178 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.883721 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.886986 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.869204 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.872900 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.880890 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.878301 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.727018 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.709189 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.728026 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.721940 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.717864 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.720901 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.721883 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.727244 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.721738 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0 0.061851 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1 0.063554 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2 0.063435 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3 0.063072 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu4 0.063081 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu5 0.060836 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu6 0.057725 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu7 0.066096 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.062441 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0 0.299572 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.295288 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.299146 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.294855 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.295850 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.294370 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.296951 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.303001 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.297365 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.299572 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.295288 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.299146 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.294855 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.295850 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.294370 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.296951 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.303001 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.297365 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0 16167.395464 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 15850.920923 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 16275.298959 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 15937.187190 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 16721.359073 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 15930.539004 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 16239.620434 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 15983.890540 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 16141.201092 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 32380.805520 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 32450.540287 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 32295.138776 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 32546.587316 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 32900.129032 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 32645.479629 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 32645.615792 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 32500.841156 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 32544.984804 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0 68646.019580 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1 68492.391837 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2 69413.132791 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3 68508.088919 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu4 68445.455923 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu5 68456.530070 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu6 68960.378539 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu7 69186.782377 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 68764.922318 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 37192.389868 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 37423.463300 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 37374.515668 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 37532.903263 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 37784.836078 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 37427.866829 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 37162.243373 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 37635.913100 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 37440.486601 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 37192.389868 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 37423.463300 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 37374.515668 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 37532.903263 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 37784.836078 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 37427.866829 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 37162.243373 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 37635.913100 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 37440.486601 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 15217 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 6432 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 2217 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 5.248290 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 6.863780 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6537 # number of writebacks -system.l2c.writebacks::total 6537 # number of writebacks -system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 5 # number of ReadExReq MSHR hits +system.l2c.writebacks::writebacks 6315 # number of writebacks +system.l2c.writebacks::total 6315 # number of writebacks +system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 6 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 10 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 39 # number of ReadExReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0 4 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1 13 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2 7 # number of ReadSharedReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 8 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 38 # number of ReadExReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0 13 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1 7 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu2 5 # number of ReadSharedReq MSHR hits system.l2c.ReadSharedReq_mshr_hits::cpu3 6 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu4 14 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu5 11 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu6 9 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu7 11 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 75 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 17 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 18 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 21 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 114 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 17 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 18 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 21 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 16 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 114 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 1240 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 1240 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 2003 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 2095 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2038 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2061 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 2078 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2099 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 2074 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 2069 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 16517 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4519 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4564 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4662 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4577 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4680 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4599 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4580 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4663 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 36844 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0 730 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1 777 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2 722 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu3 736 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu4 702 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu5 758 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu6 716 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu7 733 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 5874 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5249 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5341 # 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number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 42525173 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 42051842 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 41416678 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 39402449 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 44058192 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 337322789 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 145853608 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 145649689 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 147175184 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 144801108 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 146292245 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 146287799 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 146230867 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 147390774 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1169681274 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 145853608 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 145649689 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 147175184 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 144801108 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 146292245 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 146287799 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 146230867 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 147390774 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1169681274 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 503077334 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 503572362 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 506294012 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 516868052 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 506181413 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 506175452 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 511232158 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 505608163 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 4059008946 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 292251287 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 290147025 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 292888717 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 297220505 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 290868538 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 292450481 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 288970880 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 297704385 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2342501818 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 795328621 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 793719387 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 799182729 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 814088557 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 797049951 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 798625933 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 800203038 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 803312548 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 6401510764 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.875820 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.880992 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.875430 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.882277 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.884632 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.886402 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.883681 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.883433 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.881612 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.726527 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.713794 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.725039 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.718186 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.734118 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.728843 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.729299 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.721715 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.724662 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.063363 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.067407 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.062630 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.063476 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.061017 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.065821 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.061401 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.063430 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063565 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.295868 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.298030 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.299811 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.295692 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.301007 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.300516 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.295190 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.299495 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.298202 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.295868 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.298030 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.299811 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.295692 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.301007 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.300516 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.295190 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.299495 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.298202 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 51820.502247 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 51833.867780 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 51855.473994 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 51884.746725 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 51804.842637 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 51837.290138 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 51859.671649 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 51753.155631 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 51831.174608 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 52384.680018 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 52396.991893 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 52295.447876 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 52396.372296 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 52463.649145 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 52537.045445 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 52349.646070 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 52328.300236 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 52393.925931 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 58581.380822 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 57851.861004 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 58264.415512 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 58523.644022 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 58044.042735 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 57528.255937 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 58513.831006 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 58347.084584 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 58201.100783 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 53246.480663 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 53190.557386 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 53095.892645 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 53245.171843 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 53191.526570 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 53243.287288 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 53183.021526 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 53145.900111 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 53192.449857 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 53246.480663 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 53190.557386 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 53095.892645 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 53245.171843 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 53191.526570 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 53243.287288 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 53183.021526 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 53145.900111 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 53192.449857 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 51355.455046 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 51346.619343 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 51401.831965 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 51276.397218 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 51338.964862 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 51319.320994 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 51335.275480 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 51301.669657 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 51334.431525 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 53016.913643 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 53236.156088 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 53328.894925 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 53198.964928 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 53109.600294 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 53001.749394 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 53310.127841 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 53104.918200 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 53163.089516 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 51953.584482 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 52015.486302 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 52082.483601 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 51968.753092 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 51969.730583 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 51918.408937 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 52047.761580 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 51948.726678 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 51988.024595 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.878683 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.876830 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.877178 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.883282 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.886558 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.869204 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.872900 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.880454 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.878139 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.726085 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.708571 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.727244 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.721145 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.717549 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.720280 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.721271 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.725980 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.720996 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.060727 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.062949 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.063005 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.062554 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.062125 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.059985 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.057467 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.065743 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.061804 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.298516 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.294678 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.298591 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.294239 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.295122 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.293600 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.296565 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.302322 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.296690 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.298516 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.294678 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.298591 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.294239 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.295122 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.293600 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.296565 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.302322 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.296690 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 19237.777613 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 19269.184185 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 19290.727058 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 19303.659712 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 19276.070014 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 19248.586311 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 19230.378578 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 19251.534192 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19263.681397 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 22354.528063 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 22422.961857 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 22275.815054 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 22547.604718 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 22884.830516 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 22625.916073 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 22633.139407 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 22492.943404 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 22529.055513 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 59120.613960 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 58754.313187 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59471.547067 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 58655.411034 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 58813.765035 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 58747.060993 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 58985.702096 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59138.512752 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 58962.207481 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 27160.820857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 27398.361362 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 27340.736392 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 27523.495153 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 27759.439279 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 27394.718914 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 27140.101522 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 27606.438284 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 27414.190686 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 27160.820857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 27398.361362 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 27340.736392 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 27523.495153 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 27759.439279 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 27394.718914 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 27140.101522 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 27606.438284 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 27414.190686 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 51836.922617 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 51834.520021 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 51837.208150 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 51831.934617 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 51793.861967 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 51846.302571 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 51891.205644 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 51793.501639 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 51833.236869 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 53272.199599 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 53730.930556 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 54048.480716 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 53785.831524 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 53636.094044 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 53581.986259 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 53652.224285 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 53756.660347 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 53682.780686 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 52355.251201 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 52512.033543 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 52626.282695 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 52528.620274 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 52451.299750 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 52468.690165 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 52513.652579 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 52504.088105 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 52495.065513 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 78245 # Transaction distribution -system.membus.trans_dist::ReadResp 84100 # Transaction distribution -system.membus.trans_dist::WriteReq 43522 # Transaction distribution -system.membus.trans_dist::WriteResp 43520 # Transaction distribution -system.membus.trans_dist::WritebackDirty 6537 # Transaction distribution -system.membus.trans_dist::CleanEvict 1268 # Transaction distribution -system.membus.trans_dist::UpgradeReq 61107 # Transaction distribution -system.membus.trans_dist::UpgradeResp 50201 # Transaction distribution -system.membus.trans_dist::ReadExReq 48942 # Transaction distribution -system.membus.trans_dist::ReadExResp 3181 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 5862 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 426485 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 426485 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1118817 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1118817 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 56662 # Total snoops (count) -system.membus.snoop_fanout::samples 253744 # Request fanout histogram +system.membus.trans_dist::ReadReq 78306 # Transaction distribution +system.membus.trans_dist::ReadResp 84006 # Transaction distribution +system.membus.trans_dist::WriteReq 43633 # Transaction distribution +system.membus.trans_dist::WriteResp 43633 # Transaction distribution +system.membus.trans_dist::WritebackDirty 6315 # Transaction distribution +system.membus.trans_dist::CleanEvict 1254 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60980 # Transaction distribution +system.membus.trans_dist::ReadExReq 48711 # Transaction distribution +system.membus.trans_dist::ReadExResp 3097 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 5709 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 375644 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 375644 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1089674 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1089674 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 56426 # Total snoops (count) +system.membus.snoop_fanout::samples 252331 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 253744 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 252331 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 253744 # Request fanout histogram -system.membus.reqLayer0.occupancy 292620525 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 54.8 # Layer utilization (%) -system.membus.respLayer0.occupancy 295409000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 55.3 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 663684 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 282033 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 335738 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 12570 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 5835 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 6735 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 78248 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 369469 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 4 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43523 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43520 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 83531 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 20342 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29636 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29633 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 160854 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 160848 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 291239 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 121995 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122071 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122139 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122334 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122013 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 121723 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122513 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122322 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 977110 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1766349 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1778610 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1781270 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1785072 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1775296 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1771667 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1779976 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1778751 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14216991 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 333737 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 624990 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.150519 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.991140 # Request fanout histogram +system.membus.snoop_fanout::total 252331 # Request fanout histogram +system.membus.reqLayer0.occupancy 290210873 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 54.7 # Layer utilization (%) +system.membus.respLayer0.occupancy 244257000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 46.1 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 663692 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 283641 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 333885 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 12353 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 5692 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 6661 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 78309 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 370176 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43636 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43632 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 83900 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 105566 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29367 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29367 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 161854 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 161852 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 291888 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133128 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 133137 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 133276 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133136 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 132901 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133285 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133385 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 132788 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1065036 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1790740 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1793737 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1783183 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1779785 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1777562 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1801715 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1799686 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1764480 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14290888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 334512 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 624442 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.148246 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.987708 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 174852 27.98% 27.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 256379 41.02% 69.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 133497 21.36% 90.36% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 47307 7.57% 97.93% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 11157 1.79% 99.71% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 1650 0.26% 99.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 145 0.02% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 3 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 174331 27.92% 27.92% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 257461 41.23% 69.15% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 132941 21.29% 90.44% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 47060 7.54% 97.97% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 10899 1.75% 99.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 1610 0.26% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 136 0.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 4 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 624990 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 497290718 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 93.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 100872915 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 18.9 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 100601006 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 18.8 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 101141480 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 18.9 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 100780789 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 18.9 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 100568051 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 18.8 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 100691951 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 18.9 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 101210192 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 19.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 100872512 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 18.9 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 624442 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 496537925 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 93.7 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 101982318 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 19.2 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 102105458 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 19.3 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 101942894 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 19.2 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 101777352 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 19.2 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 101724075 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 19.2 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 101820787 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 19.2 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 102063169 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 19.3 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 101980781 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 19.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 564642e9d..7f5c6bd39 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.128077 # Nu sim_ticks 128076812500 # Number of ticks simulated final_tick 128076812500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 329011 # Simulator instruction rate (inst/s) -host_op_rate 420055 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 598785355 # Simulator tick rate (ticks/s) -host_mem_usage 256952 # Number of bytes of host memory used -host_seconds 213.89 # Real time elapsed on the host +host_inst_rate 887065 # Simulator instruction rate (inst/s) +host_op_rate 1132533 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1614418321 # Simulator tick rate (ticks/s) +host_mem_usage 277452 # Number of bytes of host memory used +host_seconds 79.33 # Real time elapsed on the host sim_insts 70373629 # Number of instructions simulated sim_ops 89847363 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -612,18 +612,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3089 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 214325 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 15790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 34314 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 36910 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53606 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473302 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 526908 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2220672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54706 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 475898 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 530604 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2291072 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18443072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 20663744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 20734144 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 95333 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 274239 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.025051 # Request fanout histogram diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index c506601b8..d6835fc82 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.203116 # Nu sim_ticks 203115876500 # Number of ticks simulated final_tick 203115876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 563415 # Simulator instruction rate (inst/s) -host_op_rate 570710 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 851483432 # Simulator tick rate (ticks/s) -host_mem_usage 239344 # Number of bytes of host memory used -host_seconds 238.54 # Real time elapsed on the host +host_inst_rate 1130669 # Simulator instruction rate (inst/s) +host_op_rate 1145309 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1708768878 # Simulator tick rate (ticks/s) +host_mem_usage 305928 # Number of bytes of host memory used +host_seconds 118.87 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -485,18 +485,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3547 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 209135 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 184923 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 36455 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 36468 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 45499 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558971 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447925 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1006896 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23804608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559024 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447938 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1006962 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23808000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17570752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 41375360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 41378752 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 99021 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 436723 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.008273 # Request fanout histogram diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt index dac1409b7..5cadbdde3 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000043 # Nu sim_ticks 43191 # Number of ticks simulated final_tick 43191 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 247811 # Simulator tick rate (ticks/s) -host_mem_usage 388428 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_tick_rate 428274 # Simulator tick rate (ticks/s) +host_mem_usage 410016 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 57728 # Number of bytes read from this memory diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt index a72f38554..1db6620aa 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000054 # Nu sim_ticks 54211 # Number of ticks simulated final_tick 54211 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 192824 # Simulator tick rate (ticks/s) -host_mem_usage 389940 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host +host_tick_rate 316777 # Simulator tick rate (ticks/s) +host_mem_usage 410608 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54016 # Number of bytes read from this memory diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt index 016399c56..5a3d40466 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000030 # Nu sim_ticks 29561 # Number of ticks simulated final_tick 29561 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 198957 # Simulator tick rate (ticks/s) -host_mem_usage 389156 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_tick_rate 334780 # Simulator tick rate (ticks/s) +host_mem_usage 410240 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 56000 # Number of bytes read from this memory diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt index 122a8ae41..d1da3d54a 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000038 # Nu sim_ticks 37741 # Number of ticks simulated final_tick 37741 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 330031 # Simulator tick rate (ticks/s) -host_mem_usage 387076 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_tick_rate 544029 # Simulator tick rate (ticks/s) +host_mem_usage 408776 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 60992 # Number of bytes read from this memory diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index d7fd446da..9f34f3699 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.230198 # Nu sim_ticks 230197694500 # Number of ticks simulated final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 435347 # Simulator instruction rate (inst/s) -host_op_rate 458966 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 583184688 # Simulator tick rate (ticks/s) -host_mem_usage 252480 # Number of bytes of host memory used -host_seconds 394.73 # Real time elapsed on the host +host_inst_rate 1151849 # Simulator instruction rate (inst/s) +host_op_rate 1214340 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1543000471 # Simulator tick rate (ticks/s) +host_mem_usage 272972 # Number of bytes of host memory used +host_seconds 149.19 # Real time elapsed on the host sim_insts 171842484 # Number of instructions simulated sim_ops 181165371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -596,18 +596,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1448 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 3051 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 689 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7550 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3612 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11162 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 287936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7608 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3618 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11226 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 291648 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 403456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 407168 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 4840 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.033471 # Request fanout histogram |