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authorAndreas Hansson <andreas.hansson@arm.com>2015-05-05 03:22:39 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-05-05 03:22:39 -0400
commit80cd107e51ceb5aac262ec7dd82870e48d345b43 (patch)
tree4bb545ae29522161963a8028f34ca850c98a3403 /tests/quick/se
parent2847d5f5177304236dcdbab112a0369f0bd96aea (diff)
downloadgem5-80cd107e51ceb5aac262ec7dd82870e48d345b43.tar.xz
stats: Update stats to reflect cache changes
Diffstat (limited to 'tests/quick/se')
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt12
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt24
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt12
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt22
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt22
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt12
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt12
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt62
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt22
-rw-r--r--tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt22
-rw-r--r--tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt12
-rw-r--r--tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt62
-rw-r--r--tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt3352
-rw-r--r--tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt3309
-rw-r--r--tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt22
-rw-r--r--tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt12
-rw-r--r--tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt22
-rw-r--r--tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt12
-rw-r--r--tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt62
-rw-r--r--tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt22
20 files changed, 3610 insertions, 3499 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
index 0b52af291..6403398b5 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
@@ -744,17 +744,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 468 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 468 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index 94ce3d081..725976bdf 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu
sim_ticks 17398000 # Number of ticks simulated
final_tick 17398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 32773 # Simulator instruction rate (inst/s)
-host_op_rate 38377 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 124135140 # Simulator tick rate (ticks/s)
-host_mem_usage 303432 # Number of bytes of host memory used
-host_seconds 0.14 # Real time elapsed on the host
+host_inst_rate 57922 # Simulator instruction rate (inst/s)
+host_op_rate 67825 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 219380871 # Simulator tick rate (ticks/s)
+host_mem_usage 310080 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -1162,19 +1162,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5 440 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 440 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index a58641eea..835d1798d 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -1074,17 +1074,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 64 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 503 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.127237 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.127237 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.333570 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 439 87.28% 87.28% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 64 12.72% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 439 87.28% 87.28% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 64 12.72% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 503 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
index 5334b6829..e88fbd103 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
sim_ticks 2695000 # Number of ticks simulated
final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 88081 # Simulator instruction rate (inst/s)
-host_op_rate 103121 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 51657705 # Simulator tick rate (ticks/s)
-host_mem_usage 292672 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 803078 # Simulator instruction rate (inst/s)
+host_op_rate 938405 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 469266934 # Simulator tick rate (ticks/s)
+host_mem_usage 299548 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -347,16 +347,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139
system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 6532 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.704991 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.704991 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 1927 29.50% 29.50% # Request fanout histogram
-system.membus.snoop_fanout::3 4605 70.50% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 1927 29.50% 29.50% # Request fanout histogram
+system.membus.snoop_fanout::1 4605 70.50% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 6532 # Request fanout histogram
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
index cc40f6f8e..d7a1f965a 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
sim_ticks 2695000 # Number of ticks simulated
final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 99386 # Simulator instruction rate (inst/s)
-host_op_rate 116351 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 58281162 # Simulator tick rate (ticks/s)
-host_mem_usage 291652 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 829930 # Simulator instruction rate (inst/s)
+host_op_rate 969708 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 484799424 # Simulator tick rate (ticks/s)
+host_mem_usage 298800 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -228,16 +228,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139
system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 6532 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.704991 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.704991 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 1927 29.50% 29.50% # Request fanout histogram
-system.membus.snoop_fanout::3 4605 70.50% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 1927 29.50% 29.50% # Request fanout histogram
+system.membus.snoop_fanout::1 4605 70.50% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 6532 # Request fanout histogram
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
index 578791a49..eccfa92c7 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -549,17 +549,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 382 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 382 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index ab4491575..66fb99cb1 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -896,17 +896,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 418 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 418 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
index 3bcc97a18..decb816ca 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000006 # Nu
sim_ticks 5615000 # Number of ticks simulated
final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 365210 # Simulator instruction rate (inst/s)
-host_op_rate 661016 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 380445830 # Simulator tick rate (ticks/s)
-host_mem_usage 292780 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
+host_inst_rate 96804 # Simulator instruction rate (inst/s)
+host_op_rate 175298 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 100934348 # Simulator tick rate (ticks/s)
+host_mem_usage 242164 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9748 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -35,33 +35,6 @@ system.physmem.bw_write::total 1266607302 # Wr
system.physmem.bw_total::cpu.inst 9779519145 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2525022262 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12304541407 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 7917 # Transaction distribution
-system.membus.trans_dist::ReadResp 7917 # Transaction distribution
-system.membus.trans_dist::WriteReq 935 # Transaction distribution
-system.membus.trans_dist::WriteResp 935 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13728 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::total 13728 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3976 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::total 3976 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 17704 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 54912 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::total 54912 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 14178 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::total 14178 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 69090 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 8852 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.775418 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.417330 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 1988 22.46% 22.46% # Request fanout histogram
-system.membus.snoop_fanout::3 6864 77.54% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
-system.membus.snoop_fanout::total 8852 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 11 # Number of system calls
@@ -125,5 +98,30 @@ system.cpu.op_class::MemWrite 935 9.59% 100.00% # Cl
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 9748 # Class of executed instruction
+system.membus.trans_dist::ReadReq 7917 # Transaction distribution
+system.membus.trans_dist::ReadResp 7917 # Transaction distribution
+system.membus.trans_dist::WriteReq 935 # Transaction distribution
+system.membus.trans_dist::WriteResp 935 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13728 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::total 13728 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3976 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::total 3976 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 17704 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 54912 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::total 54912 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 14178 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::total 14178 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 69090 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 8852 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.775418 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.417330 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 1988 22.46% 22.46% # Request fanout histogram
+system.membus.snoop_fanout::1 6864 77.54% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 8852 # Request fanout histogram
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
index 2ef89d07d..5185b356a 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu
sim_ticks 28358500 # Number of ticks simulated
final_tick 28358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 312703 # Simulator instruction rate (inst/s)
-host_op_rate 566020 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1645401799 # Simulator tick rate (ticks/s)
-host_mem_usage 307640 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
+host_inst_rate 97635 # Simulator instruction rate (inst/s)
+host_op_rate 176805 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 514168344 # Simulator tick rate (ticks/s)
+host_mem_usage 251928 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9748 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -423,17 +423,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 362 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 362 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
index cffe156e4..5787f53df 100644
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.054141 # Nu
sim_ticks 54141000500 # Number of ticks simulated
final_tick 54141000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1362402 # Simulator instruction rate (inst/s)
-host_op_rate 1369187 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 814125846 # Simulator tick rate (ticks/s)
-host_mem_usage 428768 # Number of bytes of host memory used
-host_seconds 66.50 # Real time elapsed on the host
+host_inst_rate 1892320 # Simulator instruction rate (inst/s)
+host_op_rate 1901744 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1130787212 # Simulator tick rate (ticks/s)
+host_mem_usage 435148 # Number of bytes of host memory used
+host_seconds 47.88 # Real time elapsed on the host
sim_insts 90602408 # Number of instructions simulated
sim_ops 91053639 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736
system.membus.pkt_size::total 540247820 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 135031171 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.798562 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.798562 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 27200400 20.14% 20.14% # Request fanout histogram
-system.membus.snoop_fanout::3 107830771 79.86% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 27200400 20.14% 20.14% # Request fanout histogram
+system.membus.snoop_fanout::1 107830771 79.86% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 135031171 # Request fanout histogram
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
index c88ed3ac4..fd1fa8729 100644
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -589,17 +589,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 1889731 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 1889731 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 1889731 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1889731 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
index 844bb352a..c6a32009b 100644
--- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.168950 # Nu
sim_ticks 168950040000 # Number of ticks simulated
final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1180838 # Simulator instruction rate (inst/s)
-host_op_rate 2079266 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1262766288 # Simulator tick rate (ticks/s)
-host_mem_usage 436624 # Number of bytes of host memory used
-host_seconds 133.79 # Real time elapsed on the host
+host_inst_rate 1204419 # Simulator instruction rate (inst/s)
+host_op_rate 2120788 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1287982979 # Simulator tick rate (ticks/s)
+host_mem_usage 383444 # Number of bytes of host memory used
+host_seconds 131.17 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
sim_ops 278192465 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -35,33 +35,6 @@ system.physmem.bw_write::total 1439319677 # Wr
system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 308475611 # Transaction distribution
-system.membus.trans_dist::ReadResp 308475611 # Transaction distribution
-system.membus.trans_dist::WriteReq 31439752 # Transaction distribution
-system.membus.trans_dist::WriteResp 31439752 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::total 435392328 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::total 244438398 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 679830726 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::total 1741569312 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::total 960419130 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 2701988442 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 339915363 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.640442 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.479871 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 122219199 35.96% 35.96% # Request fanout histogram
-system.membus.snoop_fanout::3 217696164 64.04% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
-system.membus.snoop_fanout::total 339915363 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 444 # Number of system calls
@@ -125,5 +98,30 @@ system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Cl
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 278192465 # Class of executed instruction
+system.membus.trans_dist::ReadReq 308475611 # Transaction distribution
+system.membus.trans_dist::ReadResp 308475611 # Transaction distribution
+system.membus.trans_dist::WriteReq 31439752 # Transaction distribution
+system.membus.trans_dist::WriteResp 31439752 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::total 435392328 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::total 244438398 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 679830726 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::total 1741569312 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::total 960419130 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 2701988442 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 339915363 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.640442 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.479871 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 122219199 35.96% 35.96% # Request fanout histogram
+system.membus.snoop_fanout::1 217696164 64.04% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 339915363 # Request fanout histogram
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
index 1b6566181..c01cc2902 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
@@ -1,1735 +1,1809 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000730 # Number of seconds simulated
-sim_ticks 729906500 # Number of ticks simulated
-final_tick 729906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000790 # Number of seconds simulated
+sim_ticks 789792500 # Number of ticks simulated
+final_tick 789792500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 158517498 # Simulator tick rate (ticks/s)
-host_mem_usage 277860 # Number of bytes of host memory used
-host_seconds 4.60 # Real time elapsed on the host
+host_tick_rate 129975147 # Simulator tick rate (ticks/s)
+host_mem_usage 221936 # Number of bytes of host memory used
+host_seconds 6.08 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0 76606 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 79713 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 76745 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 78087 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 75189 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 77277 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 77630 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 79795 # Number of bytes read from this memory
-system.physmem.bytes_read::total 621042 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 386688 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5350 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5335 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5338 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5543 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5464 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5476 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5444 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5451 # Number of bytes written to this memory
-system.physmem.bytes_written::total 430089 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 10897 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 11106 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 10910 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 10803 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 10929 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 10812 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 10850 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 10810 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 87117 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 6042 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5350 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5335 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5338 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5543 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5464 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5476 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5444 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5451 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 49443 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 104953169 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 109209878 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 105143604 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 106982196 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 103011824 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 105872464 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 106356088 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 109322221 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 850851445 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 529777444 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 7329706 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 7309155 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 7313265 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 7594123 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 7485890 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 7502331 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 7458490 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 7468080 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 589238485 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 529777444 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 112282875 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 116519034 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 112456869 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 114576319 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 110497714 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 113374795 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 113814578 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 116790301 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1440089929 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.num_reads::cpu2 10980 # Number of read requests responded to by this memory
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+system.physmem.num_reads::cpu4 11015 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5 10965 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6 10874 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7 10980 # Number of read requests responded to by this memory
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+system.physmem.num_writes::cpu5 5458 # Number of write requests responded to by this memory
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+system.physmem.num_writes::total 49731 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0 98986759 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1 99622369 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_read::cpu3 96816569 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_write::writebacks 497791509 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0 6854965 # Write bandwidth from this memory (bytes/s)
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+system.physmem.bw_write::total 552980688 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 497791509 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0 105841724 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1 106505190 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2 107167389 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3 103804480 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4 103210653 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5 103034658 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6 107212970 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7 109998512 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1344567086 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.num_reads 99153 # number of read accesses completed
-system.cpu0.num_writes 54942 # number of write accesses completed
-system.cpu0.l1c.tags.replacements 22508 # number of replacements
-system.cpu0.l1c.tags.tagsinuse 393.884164 # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs 13343 # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs 22908 # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs 0.582460 # Average number of references to valid blocks.
+system.cpu0.num_reads 99211 # number of read accesses completed
+system.cpu0.num_writes 54990 # number of write accesses completed
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+system.cpu0.l1c.tags.total_refs 13332 # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs 22858 # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs 0.583253 # Average number of references to valid blocks.
system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0 393.884164 # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0 0.769305 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total 0.769305 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id
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-system.cpu0.l1c.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id
-system.cpu0.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id
-system.cpu0.l1c.tags.tag_accesses 337372 # Number of tag accesses
-system.cpu0.l1c.tags.data_accesses 337372 # Number of data accesses
-system.cpu0.l1c.ReadReq_hits::cpu0 8651 # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total 8651 # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0 1083 # number of WriteReq hits
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-system.cpu0.l1c.overall_hits::cpu0 9734 # number of overall hits
-system.cpu0.l1c.overall_hits::total 9734 # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0 36335 # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total 36335 # number of ReadReq misses
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-system.cpu0.l1c.WriteReq_misses::total 24086 # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0 60421 # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total 60421 # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0 60421 # number of overall misses
-system.cpu0.l1c.overall_misses::total 60421 # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0 1008804376 # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total 1008804376 # number of ReadReq miss cycles
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-system.cpu0.l1c.overall_miss_latency::total 1944271840 # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0 44986 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total 44986 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0 25169 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total 25169 # number of WriteReq accesses(hits+misses)
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-system.cpu0.l1c.overall_accesses::total 70155 # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807696 # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total 0.807696 # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956971 # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total 0.956971 # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0 0.861250 # miss rate for demand accesses
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-system.cpu0.l1c.overall_miss_rate::total 0.861250 # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 27763.984478 # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 27763.984478 # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 38838.639209 # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 38838.639209 # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 32178.743152 # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 32178.743152 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 32178.743152 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 32178.743152 # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs 1068204 # number of cycles access was blocked
+system.cpu0.l1c.tags.occ_blocks::cpu0 393.865816 # Average occupied blocks per requestor
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+system.cpu0.l1c.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id
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+system.cpu0.l1c.tags.data_accesses 337265 # Number of data accesses
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+system.cpu0.l1c.WriteReq_hits::cpu0 1143 # number of WriteReq hits
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+system.cpu0.l1c.ReadReq_accesses::total 44961 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::cpu0 25173 # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::total 25173 # number of WriteReq accesses(hits+misses)
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+system.cpu0.l1c.demand_accesses::total 70134 # number of demand (read+write) accesses
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+system.cpu0.l1c.overall_accesses::total 70134 # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.808857 # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_miss_rate::total 0.808857 # miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954594 # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::total 0.954594 # miss rate for WriteReq accesses
+system.cpu0.l1c.demand_miss_rate::cpu0 0.861166 # miss rate for demand accesses
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+system.cpu0.l1c.overall_miss_rate::total 0.861166 # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 30191.809443 # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_miss_latency::total 30191.809443 # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 41761.436538 # average WriteReq miss latency
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+system.cpu0.l1c.demand_avg_miss_latency::total 34794.987400 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 34794.987400 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::total 34794.987400 # average overall miss latency
+system.cpu0.l1c.blocked_cycles::no_mshrs 1144726 # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs 61717 # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs 61078 # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs 17.308100 # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs 18.742035 # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks 9915 # number of writebacks
-system.cpu0.l1c.writebacks::total 9915 # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36335 # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total 36335 # number of ReadReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::cpu0 24086 # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::total 24086 # number of WriteReq MSHR misses
-system.cpu0.l1c.demand_mshr_misses::cpu0 60421 # number of demand (read+write) MSHR misses
-system.cpu0.l1c.demand_mshr_misses::total 60421 # number of demand (read+write) MSHR misses
-system.cpu0.l1c.overall_mshr_misses::cpu0 60421 # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_misses::total 60421 # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 953224016 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total 953224016 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 898871386 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total 898871386 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1852095402 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::total 1852095402 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1852095402 # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total 1852095402 # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 743740324 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 743740324 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1921383275 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1921383275 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2665123599 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2665123599 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807696 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807696 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956971 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956971 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861250 # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_miss_rate::total 0.861250 # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861250 # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total 0.861250 # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 26234.319967 # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 26234.319967 # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 37319.247115 # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 37319.247115 # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 30653.173599 # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 30653.173599 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 30653.173599 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 30653.173599 # average overall mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu0.l1c.overall_mshr_misses::total 60397 # number of overall MSHR misses
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+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 28664.696401 # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 28664.696401 # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 40239.176862 # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 40239.176862 # average WriteReq mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 33269.805355 # average overall mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::total 33269.805355 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 33269.805355 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::total 33269.805355 # average overall mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 78239.138509 # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78239.138509 # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 392908.833087 # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 392908.833087 # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 189106.368918 # average overall mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 189106.368918 # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.num_reads 100000 # number of read accesses completed
-system.cpu1.num_writes 54938 # number of write accesses completed
-system.cpu1.l1c.tags.replacements 22377 # number of replacements
-system.cpu1.l1c.tags.tagsinuse 394.468790 # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs 13456 # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs 22785 # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs 0.590564 # Average number of references to valid blocks.
+system.cpu1.num_writes 55318 # number of write accesses completed
+system.cpu1.l1c.tags.replacements 22177 # number of replacements
+system.cpu1.l1c.tags.tagsinuse 393.980771 # Cycle average of tags in use
+system.cpu1.l1c.tags.total_refs 13598 # Total number of references to valid blocks.
+system.cpu1.l1c.tags.sampled_refs 22566 # Sample count of references to valid blocks.
+system.cpu1.l1c.tags.avg_refs 0.602588 # Average number of references to valid blocks.
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1 394.468790 # Average occupied blocks per requestor
-system.cpu1.l1c.tags.occ_percent::cpu1 0.770447 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_percent::total 0.770447 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
-system.cpu1.l1c.tags.occ_task_id_percent::1024 0.796875 # Percentage of cache occupancy per task id
-system.cpu1.l1c.tags.tag_accesses 338150 # Number of tag accesses
-system.cpu1.l1c.tags.data_accesses 338150 # Number of data accesses
-system.cpu1.l1c.ReadReq_hits::cpu1 8709 # number of ReadReq hits
-system.cpu1.l1c.ReadReq_hits::total 8709 # number of ReadReq hits
-system.cpu1.l1c.WriteReq_hits::cpu1 1179 # number of WriteReq hits
-system.cpu1.l1c.WriteReq_hits::total 1179 # number of WriteReq hits
-system.cpu1.l1c.demand_hits::cpu1 9888 # number of demand (read+write) hits
-system.cpu1.l1c.demand_hits::total 9888 # number of demand (read+write) hits
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-system.cpu1.l1c.overall_hits::total 9888 # number of overall hits
-system.cpu1.l1c.ReadReq_misses::cpu1 36587 # number of ReadReq misses
-system.cpu1.l1c.ReadReq_misses::total 36587 # number of ReadReq misses
-system.cpu1.l1c.WriteReq_misses::cpu1 23856 # number of WriteReq misses
-system.cpu1.l1c.WriteReq_misses::total 23856 # number of WriteReq misses
-system.cpu1.l1c.demand_misses::cpu1 60443 # number of demand (read+write) misses
-system.cpu1.l1c.demand_misses::total 60443 # number of demand (read+write) misses
-system.cpu1.l1c.overall_misses::cpu1 60443 # number of overall misses
-system.cpu1.l1c.overall_misses::total 60443 # number of overall misses
-system.cpu1.l1c.ReadReq_miss_latency::cpu1 1017715976 # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_latency::total 1017715976 # number of ReadReq miss cycles
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-system.cpu1.l1c.demand_miss_latency::total 1942029580 # number of demand (read+write) miss cycles
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-system.cpu1.l1c.overall_miss_latency::total 1942029580 # number of overall miss cycles
-system.cpu1.l1c.ReadReq_accesses::cpu1 45296 # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_accesses::total 45296 # number of ReadReq accesses(hits+misses)
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-system.cpu1.l1c.WriteReq_accesses::total 25035 # number of WriteReq accesses(hits+misses)
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-system.cpu1.l1c.overall_accesses::total 70331 # number of overall (read+write) accesses
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-system.cpu1.l1c.ReadReq_miss_rate::total 0.807731 # miss rate for ReadReq accesses
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-system.cpu1.l1c.WriteReq_miss_rate::total 0.952906 # miss rate for WriteReq accesses
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-system.cpu1.l1c.demand_miss_rate::total 0.859408 # miss rate for demand accesses
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-system.cpu1.l1c.overall_miss_rate::total 0.859408 # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 27816.327548 # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 27816.327548 # average ReadReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 38745.540074 # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::total 38745.540074 # average WriteReq miss latency
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-system.cpu1.l1c.demand_avg_miss_latency::total 32129.933657 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 32129.933657 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 32129.933657 # average overall miss latency
-system.cpu1.l1c.blocked_cycles::no_mshrs 1075887 # number of cycles access was blocked
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+system.cpu1.l1c.tags.occ_percent::total 0.769494 # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id
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+system.cpu1.l1c.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
+system.cpu1.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id
+system.cpu1.l1c.tags.tag_accesses 338430 # Number of tag accesses
+system.cpu1.l1c.tags.data_accesses 338430 # Number of data accesses
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+system.cpu1.l1c.overall_hits::total 9952 # number of overall hits
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+system.cpu1.l1c.ReadReq_misses::total 36538 # number of ReadReq misses
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+system.cpu1.l1c.WriteReq_misses::total 23930 # number of WriteReq misses
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+system.cpu1.l1c.overall_misses::total 60468 # number of overall misses
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+system.cpu1.l1c.ReadReq_miss_latency::total 1108002821 # number of ReadReq miss cycles
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+system.cpu1.l1c.WriteReq_miss_latency::total 993849096 # number of WriteReq miss cycles
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+system.cpu1.l1c.overall_miss_latency::total 2101851917 # number of overall miss cycles
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+system.cpu1.l1c.ReadReq_accesses::total 45422 # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::cpu1 24998 # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::total 24998 # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.demand_accesses::cpu1 70420 # number of demand (read+write) accesses
+system.cpu1.l1c.demand_accesses::total 70420 # number of demand (read+write) accesses
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+system.cpu1.l1c.overall_accesses::total 70420 # number of overall (read+write) accesses
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+system.cpu1.l1c.ReadReq_miss_rate::total 0.804412 # miss rate for ReadReq accesses
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+system.cpu1.l1c.WriteReq_miss_rate::total 0.957277 # miss rate for WriteReq accesses
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+system.cpu1.l1c.overall_miss_rate::total 0.858677 # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 30324.670781 # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 30324.670781 # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 41531.512578 # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::total 41531.512578 # average WriteReq miss latency
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+system.cpu1.l1c.demand_avg_miss_latency::total 34759.739317 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 34759.739317 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 34759.739317 # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs 1147241 # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs 62059 # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs 61428 # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs 17.336518 # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs 18.676190 # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks 9753 # number of writebacks
-system.cpu1.l1c.writebacks::total 9753 # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36587 # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total 36587 # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23856 # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total 23856 # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1 60443 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total 60443 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1 60443 # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total 60443 # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 961736168 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total 961736168 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 888050076 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total 888050076 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1849786244 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total 1849786244 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1849786244 # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total 1849786244 # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 753708733 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 753708733 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1923800282 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1923800282 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2677509015 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2677509015 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807731 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807731 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.952906 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.952906 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859408 # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_miss_rate::total 0.859408 # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859408 # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total 0.859408 # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 26286.281138 # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 26286.281138 # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37225.439135 # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 37225.439135 # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 30603.812584 # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 30603.812584 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 30603.812584 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 30603.812584 # average overall mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu1.l1c.writebacks::writebacks 9780 # number of writebacks
+system.cpu1.l1c.writebacks::total 9780 # number of writebacks
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+system.cpu1.l1c.ReadReq_mshr_misses::total 36538 # number of ReadReq MSHR misses
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+system.cpu1.l1c.WriteReq_mshr_misses::total 23930 # number of WriteReq MSHR misses
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+system.cpu1.l1c.overall_mshr_misses::total 60468 # number of overall MSHR misses
+system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 10010 # number of ReadReq MSHR uncacheable
+system.cpu1.l1c.ReadReq_mshr_uncacheable::total 10010 # number of ReadReq MSHR uncacheable
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+system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5438 # number of WriteReq MSHR uncacheable
+system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15448 # number of overall MSHR uncacheable misses
+system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15448 # number of overall MSHR uncacheable misses
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+system.cpu1.l1c.WriteReq_mshr_miss_latency::total 957433148 # number of WriteReq MSHR miss cycles
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+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 780874824 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 2141613646 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 2141613646 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2922488470 # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2922488470 # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.804412 # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.804412 # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.957277 # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.957277 # mshr miss rate for WriteReq accesses
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+system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858677 # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_miss_rate::total 0.858677 # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 28796.893289 # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 28796.893289 # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 40009.742917 # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 40009.742917 # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 33234.339403 # average overall mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::total 33234.339403 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 33234.339403 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::total 33234.339403 # average overall mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 78009.472927 # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78009.472927 # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 393823.767194 # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 393823.767194 # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 189182.319394 # average overall mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 189182.319394 # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.num_reads 99515 # number of read accesses completed
-system.cpu2.num_writes 55356 # number of write accesses completed
-system.cpu2.l1c.tags.replacements 22413 # number of replacements
-system.cpu2.l1c.tags.tagsinuse 394.491739 # Cycle average of tags in use
-system.cpu2.l1c.tags.total_refs 13448 # Total number of references to valid blocks.
-system.cpu2.l1c.tags.sampled_refs 22815 # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs 0.589437 # Average number of references to valid blocks.
+system.cpu2.num_reads 99906 # number of read accesses completed
+system.cpu2.num_writes 55186 # number of write accesses completed
+system.cpu2.l1c.tags.replacements 22429 # number of replacements
+system.cpu2.l1c.tags.tagsinuse 394.168243 # Cycle average of tags in use
+system.cpu2.l1c.tags.total_refs 13360 # Total number of references to valid blocks.
+system.cpu2.l1c.tags.sampled_refs 22814 # Sample count of references to valid blocks.
+system.cpu2.l1c.tags.avg_refs 0.585605 # Average number of references to valid blocks.
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.tags.occ_blocks::cpu2 394.491739 # Average occupied blocks per requestor
-system.cpu2.l1c.tags.occ_percent::cpu2 0.770492 # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_percent::total 0.770492 # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
-system.cpu2.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu2.l1c.tags.tag_accesses 338294 # Number of tag accesses
-system.cpu2.l1c.tags.data_accesses 338294 # Number of data accesses
-system.cpu2.l1c.ReadReq_hits::cpu2 8726 # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total 8726 # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2 1175 # number of WriteReq hits
-system.cpu2.l1c.WriteReq_hits::total 1175 # number of WriteReq hits
-system.cpu2.l1c.demand_hits::cpu2 9901 # number of demand (read+write) hits
-system.cpu2.l1c.demand_hits::total 9901 # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits::cpu2 9901 # number of overall hits
-system.cpu2.l1c.overall_hits::total 9901 # number of overall hits
-system.cpu2.l1c.ReadReq_misses::cpu2 36442 # number of ReadReq misses
-system.cpu2.l1c.ReadReq_misses::total 36442 # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses::cpu2 24017 # number of WriteReq misses
-system.cpu2.l1c.WriteReq_misses::total 24017 # number of WriteReq misses
-system.cpu2.l1c.demand_misses::cpu2 60459 # number of demand (read+write) misses
-system.cpu2.l1c.demand_misses::total 60459 # number of demand (read+write) misses
-system.cpu2.l1c.overall_misses::cpu2 60459 # number of overall misses
-system.cpu2.l1c.overall_misses::total 60459 # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency::cpu2 1013968188 # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_latency::total 1013968188 # number of ReadReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::cpu2 926155084 # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::total 926155084 # number of WriteReq miss cycles
-system.cpu2.l1c.demand_miss_latency::cpu2 1940123272 # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_latency::total 1940123272 # number of demand (read+write) miss cycles
-system.cpu2.l1c.overall_miss_latency::cpu2 1940123272 # number of overall miss cycles
-system.cpu2.l1c.overall_miss_latency::total 1940123272 # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2 45168 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_accesses::total 45168 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::cpu2 25192 # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::total 25192 # number of WriteReq accesses(hits+misses)
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-system.cpu2.l1c.demand_accesses::total 70360 # number of demand (read+write) accesses
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-system.cpu2.l1c.overall_accesses::total 70360 # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806810 # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_miss_rate::total 0.806810 # miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953358 # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::total 0.953358 # miss rate for WriteReq accesses
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-system.cpu2.l1c.demand_miss_rate::total 0.859281 # miss rate for demand accesses
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-system.cpu2.l1c.overall_miss_rate::total 0.859281 # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 27824.164096 # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 27824.164096 # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 38562.480077 # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 38562.480077 # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency::cpu2 32089.900131 # average overall miss latency
-system.cpu2.l1c.demand_avg_miss_latency::total 32089.900131 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 32089.900131 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 32089.900131 # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs 1067763 # number of cycles access was blocked
+system.cpu2.l1c.tags.occ_blocks::cpu2 394.168243 # Average occupied blocks per requestor
+system.cpu2.l1c.tags.occ_percent::cpu2 0.769860 # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_percent::total 0.769860 # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_task_id_blocks::1024 385 # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::0 348 # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id
+system.cpu2.l1c.tags.occ_task_id_percent::1024 0.751953 # Percentage of cache occupancy per task id
+system.cpu2.l1c.tags.tag_accesses 338029 # Number of tag accesses
+system.cpu2.l1c.tags.data_accesses 338029 # Number of data accesses
+system.cpu2.l1c.ReadReq_hits::cpu2 8660 # number of ReadReq hits
+system.cpu2.l1c.ReadReq_hits::total 8660 # number of ReadReq hits
+system.cpu2.l1c.WriteReq_hits::cpu2 1124 # number of WriteReq hits
+system.cpu2.l1c.WriteReq_hits::total 1124 # number of WriteReq hits
+system.cpu2.l1c.demand_hits::cpu2 9784 # number of demand (read+write) hits
+system.cpu2.l1c.demand_hits::total 9784 # number of demand (read+write) hits
+system.cpu2.l1c.overall_hits::cpu2 9784 # number of overall hits
+system.cpu2.l1c.overall_hits::total 9784 # number of overall hits
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+system.cpu2.l1c.ReadReq_misses::total 36507 # number of ReadReq misses
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+system.cpu2.l1c.WriteReq_misses::total 24000 # number of WriteReq misses
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+system.cpu2.l1c.demand_misses::total 60507 # number of demand (read+write) misses
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+system.cpu2.l1c.overall_misses::total 60507 # number of overall misses
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+system.cpu2.l1c.ReadReq_miss_latency::total 1106428919 # number of ReadReq miss cycles
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+system.cpu2.l1c.demand_miss_latency::total 2107389897 # number of demand (read+write) miss cycles
+system.cpu2.l1c.overall_miss_latency::cpu2 2107389897 # number of overall miss cycles
+system.cpu2.l1c.overall_miss_latency::total 2107389897 # number of overall miss cycles
+system.cpu2.l1c.ReadReq_accesses::cpu2 45167 # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_accesses::total 45167 # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::cpu2 25124 # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::total 25124 # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.demand_accesses::cpu2 70291 # number of demand (read+write) accesses
+system.cpu2.l1c.demand_accesses::total 70291 # number of demand (read+write) accesses
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+system.cpu2.l1c.overall_accesses::total 70291 # number of overall (read+write) accesses
+system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.808267 # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_miss_rate::total 0.808267 # miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955262 # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::total 0.955262 # miss rate for WriteReq accesses
+system.cpu2.l1c.demand_miss_rate::cpu2 0.860807 # miss rate for demand accesses
+system.cpu2.l1c.demand_miss_rate::total 0.860807 # miss rate for demand accesses
+system.cpu2.l1c.overall_miss_rate::cpu2 0.860807 # miss rate for overall accesses
+system.cpu2.l1c.overall_miss_rate::total 0.860807 # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 30307.308708 # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_miss_latency::total 30307.308708 # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 41706.707417 # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::total 41706.707417 # average WriteReq miss latency
+system.cpu2.l1c.demand_avg_miss_latency::cpu2 34828.861074 # average overall miss latency
+system.cpu2.l1c.demand_avg_miss_latency::total 34828.861074 # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::cpu2 34828.861074 # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::total 34828.861074 # average overall miss latency
+system.cpu2.l1c.blocked_cycles::no_mshrs 1143492 # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs 61601 # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_mshrs 61259 # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs 17.333534 # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs 18.666514 # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks 9861 # number of writebacks
-system.cpu2.l1c.writebacks::total 9861 # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36442 # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total 36442 # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24017 # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total 24017 # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses::cpu2 60459 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.demand_mshr_misses::total 60459 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2 60459 # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total 60459 # number of overall MSHR misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 958233322 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_latency::total 958233322 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 889641050 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total 889641050 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1847874372 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::total 1847874372 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1847874372 # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total 1847874372 # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 744958366 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 744958366 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1919549279 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1919549279 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2664507645 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2664507645 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806810 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806810 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953358 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953358 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859281 # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_miss_rate::total 0.859281 # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859281 # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total 0.859281 # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 26294.751166 # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 26294.751166 # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 37042.138902 # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 37042.138902 # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 30564.090905 # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 30564.090905 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 30564.090905 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 30564.090905 # average overall mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu2.l1c.overall_mshr_misses::total 60507 # number of overall MSHR misses
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+system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9899 # number of ReadReq MSHR uncacheable
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+system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15395 # number of overall MSHR uncacheable misses
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+system.cpu2.l1c.WriteReq_mshr_miss_latency::total 964435030 # number of WriteReq MSHR miss cycles
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+system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2903784014 # number of overall MSHR uncacheable cycles
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+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 28780.860575 # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 28780.860575 # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 40184.792917 # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 40184.792917 # average WriteReq mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 33304.211199 # average overall mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::total 33304.211199 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 33304.211199 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 33304.211199 # average overall mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 78224.602283 # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78224.602283 # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 387452.451965 # average WriteReq mshr uncacheable latency
+system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 387452.451965 # average WriteReq mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 188618.643326 # average overall mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 188618.643326 # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.num_reads 99509 # number of read accesses completed
-system.cpu3.num_writes 55322 # number of write accesses completed
-system.cpu3.l1c.tags.replacements 22357 # number of replacements
-system.cpu3.l1c.tags.tagsinuse 394.352238 # Cycle average of tags in use
-system.cpu3.l1c.tags.total_refs 13564 # Total number of references to valid blocks.
-system.cpu3.l1c.tags.sampled_refs 22743 # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs 0.596403 # Average number of references to valid blocks.
+system.cpu3.num_reads 99687 # number of read accesses completed
+system.cpu3.num_writes 54914 # number of write accesses completed
+system.cpu3.l1c.tags.replacements 22514 # number of replacements
+system.cpu3.l1c.tags.tagsinuse 394.486423 # Cycle average of tags in use
+system.cpu3.l1c.tags.total_refs 13398 # Total number of references to valid blocks.
+system.cpu3.l1c.tags.sampled_refs 22905 # Sample count of references to valid blocks.
+system.cpu3.l1c.tags.avg_refs 0.584938 # Average number of references to valid blocks.
system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.tags.occ_blocks::cpu3 394.352238 # Average occupied blocks per requestor
-system.cpu3.l1c.tags.occ_percent::cpu3 0.770219 # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_percent::total 0.770219 # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::0 354 # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
-system.cpu3.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id
-system.cpu3.l1c.tags.tag_accesses 338647 # Number of tag accesses
-system.cpu3.l1c.tags.data_accesses 338647 # Number of data accesses
-system.cpu3.l1c.ReadReq_hits::cpu3 8763 # number of ReadReq hits
-system.cpu3.l1c.ReadReq_hits::total 8763 # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits::cpu3 1221 # number of WriteReq hits
-system.cpu3.l1c.WriteReq_hits::total 1221 # number of WriteReq hits
-system.cpu3.l1c.demand_hits::cpu3 9984 # number of demand (read+write) hits
-system.cpu3.l1c.demand_hits::total 9984 # number of demand (read+write) hits
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-system.cpu3.l1c.overall_hits::total 9984 # number of overall hits
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-system.cpu3.l1c.ReadReq_misses::total 36641 # number of ReadReq misses
-system.cpu3.l1c.WriteReq_misses::cpu3 23832 # number of WriteReq misses
-system.cpu3.l1c.WriteReq_misses::total 23832 # number of WriteReq misses
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-system.cpu3.l1c.demand_misses::total 60473 # number of demand (read+write) misses
-system.cpu3.l1c.overall_misses::cpu3 60473 # number of overall misses
-system.cpu3.l1c.overall_misses::total 60473 # number of overall misses
-system.cpu3.l1c.ReadReq_miss_latency::cpu3 1024295614 # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_latency::total 1024295614 # number of ReadReq miss cycles
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-system.cpu3.l1c.demand_miss_latency::total 1946360391 # number of demand (read+write) miss cycles
-system.cpu3.l1c.overall_miss_latency::cpu3 1946360391 # number of overall miss cycles
-system.cpu3.l1c.overall_miss_latency::total 1946360391 # number of overall miss cycles
-system.cpu3.l1c.ReadReq_accesses::cpu3 45404 # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_accesses::total 45404 # number of ReadReq accesses(hits+misses)
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-system.cpu3.l1c.WriteReq_accesses::total 25053 # number of WriteReq accesses(hits+misses)
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-system.cpu3.l1c.demand_accesses::total 70457 # number of demand (read+write) accesses
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-system.cpu3.l1c.overall_accesses::total 70457 # number of overall (read+write) accesses
-system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.806999 # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_miss_rate::total 0.806999 # miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.951263 # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::total 0.951263 # miss rate for WriteReq accesses
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-system.cpu3.l1c.demand_miss_rate::total 0.858297 # miss rate for demand accesses
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-system.cpu3.l1c.overall_miss_rate::total 0.858297 # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 27954.903360 # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_miss_latency::total 27954.903360 # average ReadReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 38690.197088 # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::total 38690.197088 # average WriteReq miss latency
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-system.cpu3.l1c.demand_avg_miss_latency::total 32185.609958 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 32185.609958 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 32185.609958 # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs 1061792 # number of cycles access was blocked
+system.cpu3.l1c.tags.occ_blocks::cpu3 394.486423 # Average occupied blocks per requestor
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+system.cpu3.l1c.tags.occ_percent::total 0.770481 # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::0 351 # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id
+system.cpu3.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id
+system.cpu3.l1c.tags.tag_accesses 337490 # Number of tag accesses
+system.cpu3.l1c.tags.data_accesses 337490 # Number of data accesses
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+system.cpu3.l1c.ReadReq_hits::total 8775 # number of ReadReq hits
+system.cpu3.l1c.WriteReq_hits::cpu3 1091 # number of WriteReq hits
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+system.cpu3.l1c.overall_hits::total 9866 # number of overall hits
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+system.cpu3.l1c.ReadReq_misses::total 36393 # number of ReadReq misses
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+system.cpu3.l1c.overall_misses::total 60322 # number of overall misses
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+system.cpu3.l1c.ReadReq_miss_latency::total 1101223942 # number of ReadReq miss cycles
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+system.cpu3.l1c.overall_miss_latency::total 2100864982 # number of overall miss cycles
+system.cpu3.l1c.ReadReq_accesses::cpu3 45168 # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_accesses::total 45168 # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::cpu3 25020 # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::total 25020 # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.demand_accesses::cpu3 70188 # number of demand (read+write) accesses
+system.cpu3.l1c.demand_accesses::total 70188 # number of demand (read+write) accesses
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+system.cpu3.l1c.overall_accesses::total 70188 # number of overall (read+write) accesses
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+system.cpu3.l1c.ReadReq_miss_rate::total 0.805725 # miss rate for ReadReq accesses
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+system.cpu3.l1c.WriteReq_miss_rate::total 0.956395 # miss rate for WriteReq accesses
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+system.cpu3.l1c.overall_miss_rate::total 0.859435 # miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 30259.224082 # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_miss_latency::total 30259.224082 # average ReadReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 41775.295248 # average WriteReq miss latency
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+system.cpu3.l1c.demand_avg_miss_latency::total 34827.508736 # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::cpu3 34827.508736 # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::total 34827.508736 # average overall miss latency
+system.cpu3.l1c.blocked_cycles::no_mshrs 1140042 # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs 61430 # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_mshrs 60968 # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs 17.284584 # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_mshrs 18.699022 # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
-system.cpu3.l1c.writebacks::writebacks 9814 # number of writebacks
-system.cpu3.l1c.writebacks::total 9814 # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36641 # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_misses::total 36641 # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23832 # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::total 23832 # number of WriteReq MSHR misses
-system.cpu3.l1c.demand_mshr_misses::cpu3 60473 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.demand_mshr_misses::total 60473 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.overall_mshr_misses::cpu3 60473 # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_misses::total 60473 # number of overall MSHR misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 968238306 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_latency::total 968238306 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 885855695 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total 885855695 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1854094001 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::total 1854094001 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1854094001 # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total 1854094001 # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 733819505 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 733819505 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1976786114 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1976786114 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2710605619 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2710605619 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.806999 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.806999 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.951263 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.951263 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858297 # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_miss_rate::total 0.858297 # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858297 # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total 0.858297 # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 26424.996752 # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 26424.996752 # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 37170.849908 # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 37170.849908 # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 30659.864750 # average overall mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 30659.864750 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 30659.864750 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 30659.864750 # average overall mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu3.l1c.writebacks::writebacks 9981 # number of writebacks
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+system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5522 # number of WriteReq MSHR uncacheable
+system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15428 # number of overall MSHR uncacheable misses
+system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15428 # number of overall MSHR uncacheable misses
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+system.cpu3.l1c.WriteReq_mshr_miss_latency::total 963227618 # number of WriteReq MSHR miss cycles
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+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 776644993 # number of ReadReq MSHR uncacheable cycles
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+system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2910682159 # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2910682159 # number of overall MSHR uncacheable cycles
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+system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805725 # mshr miss rate for ReadReq accesses
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+system.cpu3.l1c.overall_mshr_miss_rate::total 0.859435 # mshr miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 28732.843349 # average ReadReq mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 28732.843349 # average ReadReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 40253.567554 # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 40253.567554 # average WriteReq mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 33302.973807 # average overall mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::total 33302.973807 # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 33302.973807 # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::total 33302.973807 # average overall mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 78401.473148 # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78401.473148 # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 386460.913799 # average WriteReq mshr uncacheable latency
+system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 386460.913799 # average WriteReq mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 188662.312613 # average overall mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 188662.312613 # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu4.num_reads 99688 # number of read accesses completed
-system.cpu4.num_writes 55538 # number of write accesses completed
-system.cpu4.l1c.tags.replacements 22215 # number of replacements
-system.cpu4.l1c.tags.tagsinuse 391.788113 # Cycle average of tags in use
-system.cpu4.l1c.tags.total_refs 13621 # Total number of references to valid blocks.
-system.cpu4.l1c.tags.sampled_refs 22618 # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs 0.602219 # Average number of references to valid blocks.
+system.cpu4.num_reads 99646 # number of read accesses completed
+system.cpu4.num_writes 55076 # number of write accesses completed
+system.cpu4.l1c.tags.replacements 22475 # number of replacements
+system.cpu4.l1c.tags.tagsinuse 394.666578 # Cycle average of tags in use
+system.cpu4.l1c.tags.total_refs 13432 # Total number of references to valid blocks.
+system.cpu4.l1c.tags.sampled_refs 22873 # Sample count of references to valid blocks.
+system.cpu4.l1c.tags.avg_refs 0.587243 # Average number of references to valid blocks.
system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.tags.occ_blocks::cpu4 391.788113 # Average occupied blocks per requestor
-system.cpu4.l1c.tags.occ_percent::cpu4 0.765211 # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_percent::total 0.765211 # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_task_id_blocks::1024 403 # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::0 365 # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
-system.cpu4.l1c.tags.occ_task_id_percent::1024 0.787109 # Percentage of cache occupancy per task id
-system.cpu4.l1c.tags.tag_accesses 338206 # Number of tag accesses
-system.cpu4.l1c.tags.data_accesses 338206 # Number of data accesses
-system.cpu4.l1c.ReadReq_hits::cpu4 8861 # number of ReadReq hits
-system.cpu4.l1c.ReadReq_hits::total 8861 # number of ReadReq hits
-system.cpu4.l1c.WriteReq_hits::cpu4 1198 # number of WriteReq hits
-system.cpu4.l1c.WriteReq_hits::total 1198 # number of WriteReq hits
-system.cpu4.l1c.demand_hits::cpu4 10059 # number of demand (read+write) hits
-system.cpu4.l1c.demand_hits::total 10059 # number of demand (read+write) hits
-system.cpu4.l1c.overall_hits::cpu4 10059 # number of overall hits
-system.cpu4.l1c.overall_hits::total 10059 # number of overall hits
-system.cpu4.l1c.ReadReq_misses::cpu4 36318 # number of ReadReq misses
-system.cpu4.l1c.ReadReq_misses::total 36318 # number of ReadReq misses
-system.cpu4.l1c.WriteReq_misses::cpu4 24000 # number of WriteReq misses
-system.cpu4.l1c.WriteReq_misses::total 24000 # number of WriteReq misses
-system.cpu4.l1c.demand_misses::cpu4 60318 # number of demand (read+write) misses
-system.cpu4.l1c.demand_misses::total 60318 # number of demand (read+write) misses
-system.cpu4.l1c.overall_misses::cpu4 60318 # number of overall misses
-system.cpu4.l1c.overall_misses::total 60318 # number of overall misses
-system.cpu4.l1c.ReadReq_miss_latency::cpu4 1007698293 # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_latency::total 1007698293 # number of ReadReq miss cycles
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-system.cpu4.l1c.WriteReq_miss_latency::total 930213172 # number of WriteReq miss cycles
-system.cpu4.l1c.demand_miss_latency::cpu4 1937911465 # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_latency::total 1937911465 # number of demand (read+write) miss cycles
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-system.cpu4.l1c.overall_miss_latency::total 1937911465 # number of overall miss cycles
-system.cpu4.l1c.ReadReq_accesses::cpu4 45179 # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_accesses::total 45179 # number of ReadReq accesses(hits+misses)
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-system.cpu4.l1c.WriteReq_accesses::total 25198 # number of WriteReq accesses(hits+misses)
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-system.cpu4.l1c.demand_accesses::total 70377 # number of demand (read+write) accesses
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-system.cpu4.l1c.overall_accesses::total 70377 # number of overall (read+write) accesses
-system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.803869 # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_miss_rate::total 0.803869 # miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952457 # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::total 0.952457 # miss rate for WriteReq accesses
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-system.cpu4.l1c.demand_miss_rate::total 0.857070 # miss rate for demand accesses
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-system.cpu4.l1c.overall_miss_rate::total 0.857070 # miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 27746.524946 # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_miss_latency::total 27746.524946 # average ReadReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 38758.882167 # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::total 38758.882167 # average WriteReq miss latency
-system.cpu4.l1c.demand_avg_miss_latency::cpu4 32128.244720 # average overall miss latency
-system.cpu4.l1c.demand_avg_miss_latency::total 32128.244720 # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::cpu4 32128.244720 # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::total 32128.244720 # average overall miss latency
-system.cpu4.l1c.blocked_cycles::no_mshrs 1066740 # number of cycles access was blocked
+system.cpu4.l1c.tags.occ_blocks::cpu4 394.666578 # Average occupied blocks per requestor
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+system.cpu4.l1c.tags.occ_percent::total 0.770833 # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::0 352 # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
+system.cpu4.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id
+system.cpu4.l1c.tags.tag_accesses 338590 # Number of tag accesses
+system.cpu4.l1c.tags.data_accesses 338590 # Number of data accesses
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+system.cpu4.l1c.ReadReq_hits::total 8683 # number of ReadReq hits
+system.cpu4.l1c.WriteReq_hits::cpu4 1163 # number of WriteReq hits
+system.cpu4.l1c.WriteReq_hits::total 1163 # number of WriteReq hits
+system.cpu4.l1c.demand_hits::cpu4 9846 # number of demand (read+write) hits
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+system.cpu4.l1c.overall_hits::total 9846 # number of overall hits
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+system.cpu4.l1c.ReadReq_misses::total 36657 # number of ReadReq misses
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+system.cpu4.l1c.WriteReq_misses::total 23918 # number of WriteReq misses
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+system.cpu4.l1c.overall_misses::total 60575 # number of overall misses
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+system.cpu4.l1c.ReadReq_miss_latency::total 1108449638 # number of ReadReq miss cycles
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+system.cpu4.l1c.demand_miss_latency::total 2108247247 # number of demand (read+write) miss cycles
+system.cpu4.l1c.overall_miss_latency::cpu4 2108247247 # number of overall miss cycles
+system.cpu4.l1c.overall_miss_latency::total 2108247247 # number of overall miss cycles
+system.cpu4.l1c.ReadReq_accesses::cpu4 45340 # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.ReadReq_accesses::total 45340 # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::cpu4 25081 # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::total 25081 # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.demand_accesses::cpu4 70421 # number of demand (read+write) accesses
+system.cpu4.l1c.demand_accesses::total 70421 # number of demand (read+write) accesses
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+system.cpu4.l1c.overall_accesses::total 70421 # number of overall (read+write) accesses
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+system.cpu4.l1c.ReadReq_miss_rate::total 0.808491 # miss rate for ReadReq accesses
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+system.cpu4.l1c.WriteReq_miss_rate::total 0.953630 # miss rate for WriteReq accesses
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+system.cpu4.l1c.demand_miss_rate::total 0.860184 # miss rate for demand accesses
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+system.cpu4.l1c.overall_miss_rate::total 0.860184 # miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 30238.416619 # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_miss_latency::total 30238.416619 # average ReadReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 41801.053976 # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::total 41801.053976 # average WriteReq miss latency
+system.cpu4.l1c.demand_avg_miss_latency::cpu4 34803.916583 # average overall miss latency
+system.cpu4.l1c.demand_avg_miss_latency::total 34803.916583 # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::cpu4 34803.916583 # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::total 34803.916583 # average overall miss latency
+system.cpu4.l1c.blocked_cycles::no_mshrs 1151337 # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs 61639 # number of cycles access was blocked
+system.cpu4.l1c.blocked::no_mshrs 61602 # number of cycles access was blocked
system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_mshrs 17.306251 # average number of cycles each access was blocked
+system.cpu4.l1c.avg_blocked_cycles::no_mshrs 18.689929 # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
-system.cpu4.l1c.writebacks::writebacks 9826 # number of writebacks
-system.cpu4.l1c.writebacks::total 9826 # number of writebacks
-system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36318 # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_misses::total 36318 # number of ReadReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24000 # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::total 24000 # number of WriteReq MSHR misses
-system.cpu4.l1c.demand_mshr_misses::cpu4 60318 # number of demand (read+write) MSHR misses
-system.cpu4.l1c.demand_mshr_misses::total 60318 # number of demand (read+write) MSHR misses
-system.cpu4.l1c.overall_mshr_misses::cpu4 60318 # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_misses::total 60318 # number of overall MSHR misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 952156937 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_latency::total 952156937 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 893690718 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::total 893690718 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1845847655 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::total 1845847655 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1845847655 # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total 1845847655 # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 748268844 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 748268844 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1945456088 # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1945456088 # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2693724932 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2693724932 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.803869 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.803869 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952457 # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952457 # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857070 # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_miss_rate::total 0.857070 # mshr miss rate for demand accesses
-system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857070 # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_miss_rate::total 0.857070 # mshr miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 26217.218377 # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 26217.218377 # average ReadReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 37237.113250 # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 37237.113250 # average WriteReq mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 30601.937316 # average overall mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 30601.937316 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 30601.937316 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 30601.937316 # average overall mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15342 # number of overall MSHR uncacheable misses
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+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 28711.096435 # average ReadReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 40279.670499 # average WriteReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 40279.670499 # average WriteReq mshr miss latency
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+system.cpu4.l1c.demand_avg_mshr_miss_latency::total 33278.940504 # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 33278.940504 # average overall mshr miss latency
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+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 78189.521739 # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78189.521739 # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 394250.514925 # average WriteReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 394250.514925 # average WriteReq mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 188611.039369 # average overall mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 188611.039369 # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu5.num_reads 98777 # number of read accesses completed
-system.cpu5.num_writes 55102 # number of write accesses completed
-system.cpu5.l1c.tags.replacements 22389 # number of replacements
-system.cpu5.l1c.tags.tagsinuse 394.368473 # Cycle average of tags in use
-system.cpu5.l1c.tags.total_refs 13612 # Total number of references to valid blocks.
-system.cpu5.l1c.tags.sampled_refs 22785 # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs 0.597411 # Average number of references to valid blocks.
+system.cpu5.num_reads 99659 # number of read accesses completed
+system.cpu5.num_writes 54989 # number of write accesses completed
+system.cpu5.l1c.tags.replacements 22353 # number of replacements
+system.cpu5.l1c.tags.tagsinuse 392.762821 # Cycle average of tags in use
+system.cpu5.l1c.tags.total_refs 13360 # Total number of references to valid blocks.
+system.cpu5.l1c.tags.sampled_refs 22726 # Sample count of references to valid blocks.
+system.cpu5.l1c.tags.avg_refs 0.587873 # Average number of references to valid blocks.
system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.tags.occ_blocks::cpu5 394.368473 # Average occupied blocks per requestor
-system.cpu5.l1c.tags.occ_percent::cpu5 0.770251 # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_percent::total 0.770251 # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::0 367 # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id
-system.cpu5.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id
-system.cpu5.l1c.tags.tag_accesses 338353 # Number of tag accesses
-system.cpu5.l1c.tags.data_accesses 338353 # Number of data accesses
-system.cpu5.l1c.ReadReq_hits::cpu5 8788 # number of ReadReq hits
-system.cpu5.l1c.ReadReq_hits::total 8788 # number of ReadReq hits
-system.cpu5.l1c.WriteReq_hits::cpu5 1200 # number of WriteReq hits
-system.cpu5.l1c.WriteReq_hits::total 1200 # number of WriteReq hits
-system.cpu5.l1c.demand_hits::cpu5 9988 # number of demand (read+write) hits
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-system.cpu5.l1c.overall_hits::total 9988 # number of overall hits
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-system.cpu5.l1c.ReadReq_misses::total 36608 # number of ReadReq misses
-system.cpu5.l1c.WriteReq_misses::cpu5 23815 # number of WriteReq misses
-system.cpu5.l1c.WriteReq_misses::total 23815 # number of WriteReq misses
-system.cpu5.l1c.demand_misses::cpu5 60423 # number of demand (read+write) misses
-system.cpu5.l1c.demand_misses::total 60423 # number of demand (read+write) misses
-system.cpu5.l1c.overall_misses::cpu5 60423 # number of overall misses
-system.cpu5.l1c.overall_misses::total 60423 # number of overall misses
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-system.cpu5.l1c.ReadReq_miss_latency::total 1017800983 # number of ReadReq miss cycles
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-system.cpu5.l1c.demand_miss_latency::total 1944398085 # number of demand (read+write) miss cycles
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-system.cpu5.l1c.overall_miss_latency::total 1944398085 # number of overall miss cycles
-system.cpu5.l1c.ReadReq_accesses::cpu5 45396 # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_accesses::total 45396 # number of ReadReq accesses(hits+misses)
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-system.cpu5.l1c.WriteReq_accesses::total 25015 # number of WriteReq accesses(hits+misses)
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-system.cpu5.l1c.overall_accesses::total 70411 # number of overall (read+write) accesses
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-system.cpu5.l1c.ReadReq_miss_rate::total 0.806415 # miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952029 # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::total 0.952029 # miss rate for WriteReq accesses
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-system.cpu5.l1c.demand_miss_rate::total 0.858147 # miss rate for demand accesses
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-system.cpu5.l1c.overall_miss_rate::total 0.858147 # miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 27802.692936 # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_miss_latency::total 27802.692936 # average ReadReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 38908.129414 # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::total 38908.129414 # average WriteReq miss latency
-system.cpu5.l1c.demand_avg_miss_latency::cpu5 32179.767390 # average overall miss latency
-system.cpu5.l1c.demand_avg_miss_latency::total 32179.767390 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 32179.767390 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 32179.767390 # average overall miss latency
-system.cpu5.l1c.blocked_cycles::no_mshrs 1064852 # number of cycles access was blocked
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+system.cpu5.l1c.tags.occ_percent::total 0.767115 # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::0 325 # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::1 48 # Occupied blocks per task id
+system.cpu5.l1c.tags.occ_task_id_percent::1024 0.728516 # Percentage of cache occupancy per task id
+system.cpu5.l1c.tags.tag_accesses 337942 # Number of tag accesses
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+system.cpu5.l1c.ReadReq_hits::total 8666 # number of ReadReq hits
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+system.cpu5.l1c.overall_miss_latency::total 2101079493 # number of overall miss cycles
+system.cpu5.l1c.ReadReq_accesses::cpu5 45307 # number of ReadReq accesses(hits+misses)
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+system.cpu5.l1c.WriteReq_accesses::total 24970 # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.demand_accesses::cpu5 70277 # number of demand (read+write) accesses
+system.cpu5.l1c.demand_accesses::total 70277 # number of demand (read+write) accesses
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+system.cpu5.l1c.overall_accesses::total 70277 # number of overall (read+write) accesses
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+system.cpu5.l1c.ReadReq_miss_rate::total 0.808727 # miss rate for ReadReq accesses
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+system.cpu5.l1c.overall_miss_rate::total 0.860523 # miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 30197.654212 # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_miss_latency::total 30197.654212 # average ReadReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 41730.605228 # average WriteReq miss latency
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+system.cpu5.l1c.demand_avg_miss_latency::total 34742.943249 # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::cpu5 34742.943249 # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::total 34742.943249 # average overall miss latency
+system.cpu5.l1c.blocked_cycles::no_mshrs 1144155 # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs 61539 # number of cycles access was blocked
+system.cpu5.l1c.blocked::no_mshrs 61191 # number of cycles access was blocked
system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs 17.303694 # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_mshrs 18.698093 # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
-system.cpu5.l1c.writebacks::writebacks 9851 # number of writebacks
-system.cpu5.l1c.writebacks::total 9851 # number of writebacks
-system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36608 # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_misses::total 36608 # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23815 # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::total 23815 # number of WriteReq MSHR misses
-system.cpu5.l1c.demand_mshr_misses::cpu5 60423 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.demand_mshr_misses::total 60423 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses::cpu5 60423 # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_misses::total 60423 # number of overall MSHR misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 961777191 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_latency::total 961777191 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 890427492 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::total 890427492 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1852204683 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::total 1852204683 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1852204683 # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total 1852204683 # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 736504009 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 736504009 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1948720715 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1948720715 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2685224724 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2685224724 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806415 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806415 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952029 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952029 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858147 # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_miss_rate::total 0.858147 # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858147 # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_miss_rate::total 0.858147 # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 26272.322744 # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 26272.322744 # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 37389.355112 # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 37389.355112 # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 30653.967579 # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 30653.967579 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 30653.967579 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::total 30653.967579 # average overall mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu5.l1c.overall_mshr_misses::total 60475 # number of overall MSHR misses
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+system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9934 # number of ReadReq MSHR uncacheable
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+system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2919853479 # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2919853479 # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808727 # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808727 # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954505 # mshr miss rate for WriteReq accesses
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+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 28670.663301 # average ReadReq mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 28670.663301 # average ReadReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 40210.004405 # average WriteReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 40210.004405 # average WriteReq mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 33218.470757 # average overall mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::total 33218.470757 # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 33218.470757 # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::total 33218.470757 # average overall mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 78342.751359 # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78342.751359 # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 392233.807143 # average WriteReq mshr uncacheable latency
+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 392233.807143 # average WriteReq mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 189674.774523 # average overall mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 189674.774523 # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu6.num_reads 99339 # number of read accesses completed
-system.cpu6.num_writes 55520 # number of write accesses completed
-system.cpu6.l1c.tags.replacements 22403 # number of replacements
-system.cpu6.l1c.tags.tagsinuse 393.263413 # Cycle average of tags in use
-system.cpu6.l1c.tags.total_refs 13582 # Total number of references to valid blocks.
-system.cpu6.l1c.tags.sampled_refs 22789 # Sample count of references to valid blocks.
-system.cpu6.l1c.tags.avg_refs 0.595989 # Average number of references to valid blocks.
+system.cpu6.num_reads 99691 # number of read accesses completed
+system.cpu6.num_writes 55108 # number of write accesses completed
+system.cpu6.l1c.tags.replacements 22433 # number of replacements
+system.cpu6.l1c.tags.tagsinuse 394.732703 # Cycle average of tags in use
+system.cpu6.l1c.tags.total_refs 13465 # Total number of references to valid blocks.
+system.cpu6.l1c.tags.sampled_refs 22813 # Sample count of references to valid blocks.
+system.cpu6.l1c.tags.avg_refs 0.590234 # Average number of references to valid blocks.
system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.tags.occ_blocks::cpu6 393.263413 # Average occupied blocks per requestor
-system.cpu6.l1c.tags.occ_percent::cpu6 0.768093 # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_percent::total 0.768093 # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::0 355 # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id
-system.cpu6.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id
-system.cpu6.l1c.tags.tag_accesses 338803 # Number of tag accesses
-system.cpu6.l1c.tags.data_accesses 338803 # Number of data accesses
-system.cpu6.l1c.ReadReq_hits::cpu6 8815 # number of ReadReq hits
-system.cpu6.l1c.ReadReq_hits::total 8815 # number of ReadReq hits
-system.cpu6.l1c.WriteReq_hits::cpu6 1164 # number of WriteReq hits
-system.cpu6.l1c.WriteReq_hits::total 1164 # number of WriteReq hits
-system.cpu6.l1c.demand_hits::cpu6 9979 # number of demand (read+write) hits
-system.cpu6.l1c.demand_hits::total 9979 # number of demand (read+write) hits
-system.cpu6.l1c.overall_hits::cpu6 9979 # number of overall hits
-system.cpu6.l1c.overall_hits::total 9979 # number of overall hits
-system.cpu6.l1c.ReadReq_misses::cpu6 36385 # number of ReadReq misses
-system.cpu6.l1c.ReadReq_misses::total 36385 # number of ReadReq misses
-system.cpu6.l1c.WriteReq_misses::cpu6 24126 # number of WriteReq misses
-system.cpu6.l1c.WriteReq_misses::total 24126 # number of WriteReq misses
-system.cpu6.l1c.demand_misses::cpu6 60511 # number of demand (read+write) misses
-system.cpu6.l1c.demand_misses::total 60511 # number of demand (read+write) misses
-system.cpu6.l1c.overall_misses::cpu6 60511 # number of overall misses
-system.cpu6.l1c.overall_misses::total 60511 # number of overall misses
-system.cpu6.l1c.ReadReq_miss_latency::cpu6 1008730718 # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_latency::total 1008730718 # number of ReadReq miss cycles
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-system.cpu6.l1c.demand_miss_latency::total 1945726712 # number of demand (read+write) miss cycles
-system.cpu6.l1c.overall_miss_latency::cpu6 1945726712 # number of overall miss cycles
-system.cpu6.l1c.overall_miss_latency::total 1945726712 # number of overall miss cycles
-system.cpu6.l1c.ReadReq_accesses::cpu6 45200 # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_accesses::total 45200 # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::cpu6 25290 # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::total 25290 # number of WriteReq accesses(hits+misses)
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-system.cpu6.l1c.demand_accesses::total 70490 # number of demand (read+write) accesses
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-system.cpu6.l1c.overall_accesses::total 70490 # number of overall (read+write) accesses
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-system.cpu6.l1c.ReadReq_miss_rate::total 0.804978 # miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953974 # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::total 0.953974 # miss rate for WriteReq accesses
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-system.cpu6.l1c.demand_miss_rate::total 0.858434 # miss rate for demand accesses
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-system.cpu6.l1c.overall_miss_rate::total 0.858434 # miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 27723.807008 # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_miss_latency::total 27723.807008 # average ReadReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 38837.602338 # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::total 38837.602338 # average WriteReq miss latency
-system.cpu6.l1c.demand_avg_miss_latency::cpu6 32154.925749 # average overall miss latency
-system.cpu6.l1c.demand_avg_miss_latency::total 32154.925749 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 32154.925749 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 32154.925749 # average overall miss latency
-system.cpu6.l1c.blocked_cycles::no_mshrs 1063684 # number of cycles access was blocked
+system.cpu6.l1c.tags.occ_blocks::cpu6 394.732703 # Average occupied blocks per requestor
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+system.cpu6.l1c.tags.occ_percent::total 0.770962 # Average percentage of cache occupancy
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+system.cpu6.l1c.tags.age_task_id_blocks_1024::0 337 # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
+system.cpu6.l1c.tags.occ_task_id_percent::1024 0.742188 # Percentage of cache occupancy per task id
+system.cpu6.l1c.tags.tag_accesses 339043 # Number of tag accesses
+system.cpu6.l1c.tags.data_accesses 339043 # Number of data accesses
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+system.cpu6.l1c.ReadReq_hits::total 8806 # number of ReadReq hits
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+system.cpu6.l1c.overall_hits::total 9950 # number of overall hits
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+system.cpu6.l1c.ReadReq_misses::total 36628 # number of ReadReq misses
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+system.cpu6.l1c.overall_misses::total 60572 # number of overall misses
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+system.cpu6.l1c.ReadReq_miss_latency::total 1115774950 # number of ReadReq miss cycles
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+system.cpu6.l1c.overall_miss_latency::total 2110355524 # number of overall miss cycles
+system.cpu6.l1c.ReadReq_accesses::cpu6 45434 # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.ReadReq_accesses::total 45434 # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::cpu6 25088 # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::total 25088 # number of WriteReq accesses(hits+misses)
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+system.cpu6.l1c.demand_accesses::total 70522 # number of demand (read+write) accesses
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+system.cpu6.l1c.overall_accesses::total 70522 # number of overall (read+write) accesses
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+system.cpu6.l1c.ReadReq_miss_rate::total 0.806180 # miss rate for ReadReq accesses
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+system.cpu6.l1c.demand_miss_rate::total 0.858909 # miss rate for demand accesses
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+system.cpu6.l1c.overall_miss_rate::total 0.858909 # miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 30462.349842 # average ReadReq miss latency
+system.cpu6.l1c.ReadReq_avg_miss_latency::total 30462.349842 # average ReadReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 41537.778734 # average WriteReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::total 41537.778734 # average WriteReq miss latency
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+system.cpu6.l1c.demand_avg_miss_latency::total 34840.446477 # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::cpu6 34840.446477 # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::total 34840.446477 # average overall miss latency
+system.cpu6.l1c.blocked_cycles::no_mshrs 1141787 # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_mshrs 61545 # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_mshrs 61213 # number of cycles access was blocked
system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_mshrs 17.283029 # average number of cycles each access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_mshrs 18.652688 # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
-system.cpu6.l1c.writebacks::writebacks 9842 # number of writebacks
-system.cpu6.l1c.writebacks::total 9842 # number of writebacks
-system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36385 # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_misses::total 36385 # number of ReadReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24126 # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::total 24126 # number of WriteReq MSHR misses
-system.cpu6.l1c.demand_mshr_misses::cpu6 60511 # number of demand (read+write) MSHR misses
-system.cpu6.l1c.demand_mshr_misses::total 60511 # number of demand (read+write) MSHR misses
-system.cpu6.l1c.overall_mshr_misses::cpu6 60511 # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_misses::total 60511 # number of overall MSHR misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 953086366 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_latency::total 953086366 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 900293024 # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::total 900293024 # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1853379390 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::total 1853379390 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1853379390 # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::total 1853379390 # number of overall MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 738599910 # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 738599910 # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1965255677 # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1965255677 # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2703855587 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2703855587 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.804978 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.804978 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953974 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953974 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858434 # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_miss_rate::total 0.858434 # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858434 # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_miss_rate::total 0.858434 # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 26194.485805 # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 26194.485805 # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 37316.298765 # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 37316.298765 # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 30628.801210 # average overall mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 30628.801210 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 30628.801210 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 30628.801210 # average overall mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15239 # number of overall MSHR uncacheable misses
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+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 28934.898984 # average ReadReq mshr miss latency
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+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 33315.773790 # average overall mshr miss latency
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+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 78367.968233 # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78367.968233 # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 392388.264085 # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 392388.264085 # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 190652.015224 # average overall mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 190652.015224 # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu7.num_reads 99565 # number of read accesses completed
-system.cpu7.num_writes 55051 # number of write accesses completed
-system.cpu7.l1c.tags.replacements 22600 # number of replacements
-system.cpu7.l1c.tags.tagsinuse 394.642544 # Cycle average of tags in use
-system.cpu7.l1c.tags.total_refs 13380 # Total number of references to valid blocks.
-system.cpu7.l1c.tags.sampled_refs 22986 # Sample count of references to valid blocks.
-system.cpu7.l1c.tags.avg_refs 0.582093 # Average number of references to valid blocks.
+system.cpu7.num_reads 99881 # number of read accesses completed
+system.cpu7.num_writes 55258 # number of write accesses completed
+system.cpu7.l1c.tags.replacements 22490 # number of replacements
+system.cpu7.l1c.tags.tagsinuse 394.773487 # Cycle average of tags in use
+system.cpu7.l1c.tags.total_refs 13394 # Total number of references to valid blocks.
+system.cpu7.l1c.tags.sampled_refs 22887 # Sample count of references to valid blocks.
+system.cpu7.l1c.tags.avg_refs 0.585223 # Average number of references to valid blocks.
system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.tags.occ_blocks::cpu7 394.642544 # Average occupied blocks per requestor
-system.cpu7.l1c.tags.occ_percent::cpu7 0.770786 # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_percent::total 0.770786 # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::0 349 # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id
-system.cpu7.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id
-system.cpu7.l1c.tags.tag_accesses 338392 # Number of tag accesses
-system.cpu7.l1c.tags.data_accesses 338392 # Number of data accesses
-system.cpu7.l1c.ReadReq_hits::cpu7 8664 # number of ReadReq hits
-system.cpu7.l1c.ReadReq_hits::total 8664 # number of ReadReq hits
-system.cpu7.l1c.WriteReq_hits::cpu7 1142 # number of WriteReq hits
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-system.cpu7.l1c.overall_hits::total 9806 # number of overall hits
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-system.cpu7.l1c.WriteReq_misses::total 23923 # number of WriteReq misses
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-system.cpu7.l1c.demand_misses::total 60558 # number of demand (read+write) misses
-system.cpu7.l1c.overall_misses::cpu7 60558 # number of overall misses
-system.cpu7.l1c.overall_misses::total 60558 # number of overall misses
-system.cpu7.l1c.ReadReq_miss_latency::cpu7 1023029462 # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_latency::total 1023029462 # number of ReadReq miss cycles
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-system.cpu7.l1c.overall_miss_latency::total 1952639561 # number of overall miss cycles
-system.cpu7.l1c.ReadReq_accesses::cpu7 45299 # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_accesses::total 45299 # number of ReadReq accesses(hits+misses)
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-system.cpu7.l1c.overall_accesses::total 70364 # number of overall (read+write) accesses
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-system.cpu7.l1c.ReadReq_miss_rate::total 0.808737 # miss rate for ReadReq accesses
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-system.cpu7.l1c.overall_miss_rate::total 0.860639 # miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 27924.920486 # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_miss_latency::total 27924.920486 # average ReadReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 38858.424905 # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::total 38858.424905 # average WriteReq miss latency
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-system.cpu7.l1c.demand_avg_miss_latency::total 32244.122346 # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::cpu7 32244.122346 # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::total 32244.122346 # average overall miss latency
-system.cpu7.l1c.blocked_cycles::no_mshrs 1066072 # number of cycles access was blocked
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+system.cpu7.l1c.tags.occ_percent::total 0.771042 # Average percentage of cache occupancy
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+system.cpu7.l1c.tags.age_task_id_blocks_1024::0 361 # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id
+system.cpu7.l1c.tags.occ_task_id_percent::1024 0.775391 # Percentage of cache occupancy per task id
+system.cpu7.l1c.tags.tag_accesses 338728 # Number of tag accesses
+system.cpu7.l1c.tags.data_accesses 338728 # Number of data accesses
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+system.cpu7.l1c.ReadReq_hits::total 8705 # number of ReadReq hits
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+system.cpu7.l1c.ReadReq_miss_latency::total 1106293724 # number of ReadReq miss cycles
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+system.cpu7.l1c.overall_miss_latency::total 2108866020 # number of overall miss cycles
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+system.cpu7.l1c.ReadReq_accesses::total 45342 # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::cpu7 25097 # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::total 25097 # number of WriteReq accesses(hits+misses)
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+system.cpu7.l1c.demand_accesses::total 70439 # number of demand (read+write) accesses
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+system.cpu7.l1c.overall_accesses::total 70439 # number of overall (read+write) accesses
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+system.cpu7.l1c.overall_miss_rate::total 0.860603 # miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 30196.078391 # average ReadReq miss latency
+system.cpu7.l1c.ReadReq_avg_miss_latency::total 30196.078391 # average ReadReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 41803.456448 # average WriteReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::total 41803.456448 # average WriteReq miss latency
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+system.cpu7.l1c.demand_avg_miss_latency::total 34788.288024 # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::cpu7 34788.288024 # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::total 34788.288024 # average overall miss latency
+system.cpu7.l1c.blocked_cycles::no_mshrs 1141532 # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_mshrs 61535 # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_mshrs 61288 # number of cycles access was blocked
system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_mshrs 17.324645 # average number of cycles each access was blocked
+system.cpu7.l1c.avg_blocked_cycles::no_mshrs 18.625702 # average number of cycles each access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
-system.cpu7.l1c.writebacks::writebacks 9831 # number of writebacks
-system.cpu7.l1c.writebacks::total 9831 # number of writebacks
-system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36635 # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_misses::total 36635 # number of ReadReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23923 # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::total 23923 # number of WriteReq MSHR misses
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-system.cpu7.l1c.demand_mshr_misses::total 60558 # number of demand (read+write) MSHR misses
-system.cpu7.l1c.overall_mshr_misses::cpu7 60558 # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_misses::total 60558 # number of overall MSHR misses
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-system.cpu7.l1c.ReadReq_mshr_miss_latency::total 966974672 # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 893289987 # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::total 893289987 # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1860264659 # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::total 1860264659 # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1860264659 # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::total 1860264659 # number of overall MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 731988929 # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 731988929 # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1960595657 # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1960595657 # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2692584586 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2692584586 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.808737 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.808737 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954438 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954438 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860639 # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_miss_rate::total 0.860639 # mshr miss rate for demand accesses
-system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860639 # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_miss_rate::total 0.860639 # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 26394.832046 # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 26394.832046 # average ReadReq mshr miss latency
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-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 37340.215985 # average WriteReq mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 30718.726824 # average overall mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 30718.726824 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 30718.726824 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::total 30718.726824 # average overall mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
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-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
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-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860603 # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_miss_rate::total 0.860603 # mshr miss rate for overall accesses
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+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 28669.614488 # average ReadReq mshr miss latency
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+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 33264.433289 # average overall mshr miss latency
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+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 189572.944738 # average overall mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 189572.944738 # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.tags.replacements 12974 # number of replacements
-system.l2c.tags.tagsinuse 782.339791 # Cycle average of tags in use
-system.l2c.tags.total_refs 149980 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 13746 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 10.910810 # Average number of references to valid blocks.
+system.l2c.tags.replacements 12865 # number of replacements
+system.l2c.tags.tagsinuse 778.482244 # Cycle average of tags in use
+system.l2c.tags.total_refs 150454 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 13664 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 11.010978 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 728.962494 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0 6.892190 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1 7.186949 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2 6.375204 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3 6.806314 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4 6.399875 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5 6.389081 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6 6.432209 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7 6.895475 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.711877 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0 0.006731 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1 0.007019 # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu3 0.006647 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu4 0.006250 # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu6 0.006281 # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::total 0.764004 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024 772 # Occupied blocks per task id
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-system.l2c.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id
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-system.l2c.ReadReq_hits::cpu2 10626 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3 10750 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu4 10729 # number of ReadReq hits
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-system.l2c.ReadReq_hits::cpu6 10653 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu7 10669 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 85605 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 75955 # number of Writeback hits
-system.l2c.Writeback_hits::total 75955 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0 335 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1 339 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2 335 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3 336 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4 340 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5 357 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6 325 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7 325 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 2692 # number of UpgradeReq hits
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-system.l2c.ReadExReq_hits::cpu3 1952 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu4 1880 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu5 1895 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu6 1918 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu7 1918 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 15383 # number of ReadExReq hits
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-system.l2c.demand_hits::cpu6 12571 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu7 12587 # number of demand (read+write) hits
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-system.l2c.overall_hits::cpu4 12609 # number of overall hits
-system.l2c.overall_hits::cpu5 12579 # number of overall hits
-system.l2c.overall_hits::cpu6 12571 # number of overall hits
-system.l2c.overall_hits::cpu7 12587 # number of overall hits
-system.l2c.overall_hits::total 100988 # number of overall hits
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-system.l2c.ReadReq_misses::cpu6 670 # number of ReadReq misses
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-system.l2c.UpgradeReq_misses::cpu5 1959 # number of UpgradeReq misses
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-system.l2c.ReadExReq_misses::total 35258 # number of ReadExReq misses
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-system.l2c.overall_misses::cpu6 5113 # number of overall misses
-system.l2c.overall_misses::cpu7 5101 # number of overall misses
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-system.l2c.ReadReq_accesses::total 91101 # number of ReadReq accesses(hits+misses)
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-system.l2c.Writeback_accesses::total 75955 # number of Writeback accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu1 2280 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2 2211 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3 2259 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu4 2295 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu5 2316 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu6 2317 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu7 2293 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 18292 # number of UpgradeReq accesses(hits+misses)
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system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 43742.269132 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 43994.444121 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 43681.279217 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 44035.736842 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 44163.151337 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 43823.506608 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 43951.753387 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 43898.066118 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 42778.037476 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 42746.677695 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 42846.831666 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 42760.600389 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 42833.242894 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 42901.308017 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 42779.526710 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 42818.798290 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 42808.113328 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.snoop_filter.tot_requests 123330 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 121282 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.tot_requests 252480 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 249408 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.trans_dist::ReadReq 84079 # Transaction distribution
-system.membus.trans_dist::ReadResp 84076 # Transaction distribution
-system.membus.trans_dist::WriteReq 43401 # Transaction distribution
-system.membus.trans_dist::WriteResp 43399 # Transaction distribution
-system.membus.trans_dist::Writeback 6042 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 58662 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 47800 # Transaction distribution
-system.membus.trans_dist::ReadExReq 50251 # Transaction distribution
-system.membus.trans_dist::ReadExResp 3038 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 420748 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 420748 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1051128 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1051128 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 58073 # Total snoops (count)
-system.membus.snoop_fanout::samples 123330 # Request fanout histogram
+system.membus.trans_dist::ReadReq 84654 # Transaction distribution
+system.membus.trans_dist::ReadResp 84652 # Transaction distribution
+system.membus.trans_dist::WriteReq 43588 # Transaction distribution
+system.membus.trans_dist::WriteResp 43585 # Transaction distribution
+system.membus.trans_dist::Writeback 6143 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 60492 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 49595 # Transaction distribution
+system.membus.trans_dist::ReadExReq 50638 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3207 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 426554 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 426554 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1061863 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1061863 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 58325 # Total snoops (count)
+system.membus.snoop_fanout::samples 252480 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 123330 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 252480 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 123330 # Request fanout histogram
-system.membus.reqLayer0.occupancy 349185814 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 47.8 # Layer utilization (%)
-system.membus.respLayer0.occupancy 311191349 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 42.6 # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests 561297 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 261699 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 297550 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_fanout::total 252480 # Request fanout histogram
+system.membus.reqLayer0.occupancy 472884580 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 59.9 # Layer utilization (%)
+system.membus.respLayer0.occupancy 313892142 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 39.7 # Layer utilization (%)
+system.toL2Bus.snoop_filter.tot_requests 684630 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 383351 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 298207 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 370588 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 370576 # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 43402 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 43399 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 75955 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 29152 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 29150 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 162499 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 162497 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120510 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120652 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120226 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120519 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120569 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120393 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120447 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120346 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 963662 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1766434 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1757944 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1752931 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1758190 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1756878 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1755329 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1752897 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1753790 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 14054393 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 323559 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 561297 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.683086 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 1.176196 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 371695 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 371689 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 43589 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 43585 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 75954 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 29169 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 29167 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 162397 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 162391 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120614 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120783 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120664 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120646 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120853 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120726 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120516 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120736 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 965538 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1756616 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1750933 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1748576 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1754368 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1762730 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1756512 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1757509 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1755676 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 14042920 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 324098 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 684630 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.384232 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 1.250303 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 53942 9.61% 9.61% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 251180 44.75% 54.36% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 141382 25.19% 79.55% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 68926 12.28% 91.83% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 30158 5.37% 97.20% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 11557 2.06% 99.26% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 3492 0.62% 99.88% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 660 0.12% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 176832 25.83% 25.83% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 250927 36.65% 62.48% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 141295 20.64% 83.12% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 69195 10.11% 93.23% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 30377 4.44% 97.66% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 11672 1.70% 99.37% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 3607 0.53% 99.89% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 725 0.11% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 561297 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 720580520 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 98.7 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 100512947 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 13.8 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 100775889 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 13.8 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 100644932 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 13.8 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 100575951 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 13.8 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 100528413 # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization 13.8 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 100450921 # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization 13.8 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 100623449 # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization 13.8 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 100655480 # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization 13.8 # Layer utilization (%)
+system.toL2Bus.snoop_fanout::total 684630 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 782327755 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 99.1 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 100591456 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 12.7 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 100721944 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 12.8 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 100768962 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 12.8 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 100555978 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 12.7 # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy 100847968 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization 12.8 # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy 100723976 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization 12.8 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 100740497 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization 12.8 # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy 100846524 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization 12.8 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
index e072d02ad..ff9b64e46 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
@@ -1,1689 +1,1764 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000473 # Number of seconds simulated
-sim_ticks 473250000 # Number of ticks simulated
-final_tick 473250000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 473398500 # Number of ticks simulated
+final_tick 473398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 101630905 # Simulator tick rate (ticks/s)
-host_mem_usage 277340 # Number of bytes of host memory used
-host_seconds 4.66 # Real time elapsed on the host
+host_tick_rate 74773462 # Simulator tick rate (ticks/s)
+host_mem_usage 221944 # Number of bytes of host memory used
+host_seconds 6.33 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0 80424 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 83171 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 80813 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 86214 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 79490 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 82665 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 85333 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 80902 # Number of bytes read from this memory
-system.physmem.bytes_read::total 659012 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 419392 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5460 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5448 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5355 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5405 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5451 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5481 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5462 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5450 # Number of bytes written to this memory
-system.physmem.bytes_written::total 462904 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 11061 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 10973 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 10946 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 11055 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 10883 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 10908 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 11056 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 10909 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 87791 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 6553 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5460 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5448 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5355 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5405 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5451 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5481 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5462 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5450 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 50065 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 169939778 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 175744321 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 170761754 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 182174326 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 167966191 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 174675119 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 180312731 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 170949815 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1392524036 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 886195457 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 11537242 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 11511886 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 11315372 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 11421025 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 11518225 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 11581616 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 11541469 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 11516112 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 978138405 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 886195457 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 181477021 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 187256207 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 182077126 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 193595351 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 179484416 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 186256735 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 191854200 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 182465927 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2370662441 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bytes_read::cpu1 86349 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2 81279 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3 82686 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4 83314 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5 81031 # Number of bytes read from this memory
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+system.physmem.num_reads::cpu1 11064 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2 10845 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3 10992 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4 10927 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5 11038 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6 10915 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7 10898 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 87697 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 6720 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0 5517 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1 5460 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2 5549 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3 5366 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4 5369 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5 5497 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6 5427 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7 5336 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 50241 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0 180841300 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1 182402352 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2 171692559 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3 174664685 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4 175991263 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5 171168688 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6 175566674 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7 182717098 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1415044619 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 908494640 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0 11654029 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1 11533623 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2 11721626 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3 11335059 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4 11341396 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5 11611782 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6 11463915 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7 11271688 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1000427758 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 908494640 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0 192495329 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1 193935976 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2 183414185 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3 185999744 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4 187332659 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5 182780469 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6 187030588 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7 193988785 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2415472377 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.num_reads 98988 # number of read accesses completed
-system.cpu0.num_writes 54550 # number of write accesses completed
-system.cpu0.l1c.tags.replacements 22171 # number of replacements
-system.cpu0.l1c.tags.tagsinuse 391.248330 # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs 13318 # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs 22569 # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs 0.590101 # Average number of references to valid blocks.
+system.cpu0.num_reads 99308 # number of read accesses completed
+system.cpu0.num_writes 55247 # number of write accesses completed
+system.cpu0.l1c.tags.replacements 22271 # number of replacements
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+system.cpu0.l1c.tags.total_refs 13537 # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs 22673 # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs 0.597054 # Average number of references to valid blocks.
system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0 391.248330 # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0 0.764157 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total 0.764157 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id
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-system.cpu0.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
-system.cpu0.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id
-system.cpu0.l1c.tags.tag_accesses 335805 # Number of tag accesses
-system.cpu0.l1c.tags.data_accesses 335805 # Number of data accesses
-system.cpu0.l1c.ReadReq_hits::cpu0 8501 # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total 8501 # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0 1143 # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total 1143 # number of WriteReq hits
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-system.cpu0.l1c.demand_hits::total 9644 # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0 9644 # number of overall hits
-system.cpu0.l1c.overall_hits::total 9644 # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0 36474 # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total 36474 # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0 23719 # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total 23719 # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0 60193 # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total 60193 # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0 60193 # number of overall misses
-system.cpu0.l1c.overall_misses::total 60193 # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0 587864141 # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total 587864141 # number of ReadReq miss cycles
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-system.cpu0.l1c.overall_miss_latency::total 1240095356 # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0 44975 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total 44975 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0 24862 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total 24862 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses::cpu0 69837 # number of demand (read+write) accesses
-system.cpu0.l1c.demand_accesses::total 69837 # number of demand (read+write) accesses
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-system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.810984 # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total 0.810984 # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954026 # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total 0.954026 # miss rate for WriteReq accesses
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-system.cpu0.l1c.demand_miss_rate::total 0.861907 # miss rate for demand accesses
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-system.cpu0.l1c.overall_miss_rate::total 0.861907 # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16117.347727 # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 16117.347727 # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 27498.259412 # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 27498.259412 # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 20601.986211 # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 20601.986211 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 20601.986211 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 20601.986211 # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs 773904 # number of cycles access was blocked
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+system.cpu0.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id
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+system.cpu0.l1c.tags.tag_accesses 337706 # Number of tag accesses
+system.cpu0.l1c.tags.data_accesses 337706 # Number of data accesses
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+system.cpu0.l1c.ReadReq_hits::total 8778 # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits::cpu0 1202 # number of WriteReq hits
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+system.cpu0.l1c.overall_hits::total 9980 # number of overall hits
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+system.cpu0.l1c.ReadReq_miss_latency::cpu0 585914746 # number of ReadReq miss cycles
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+system.cpu0.l1c.WriteReq_accesses::cpu0 25171 # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::total 25171 # number of WriteReq accesses(hits+misses)
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+system.cpu0.l1c.overall_accesses::total 70261 # number of overall (read+write) accesses
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+system.cpu0.l1c.overall_miss_rate::cpu0 0.857958 # miss rate for overall accesses
+system.cpu0.l1c.overall_miss_rate::total 0.857958 # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16135.568022 # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_miss_latency::total 16135.568022 # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 27617.894113 # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::total 27617.894113 # average WriteReq miss latency
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+system.cpu0.l1c.demand_avg_miss_latency::total 20701.183623 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 20701.183623 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::total 20701.183623 # average overall miss latency
+system.cpu0.l1c.blocked_cycles::no_mshrs 772989 # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs 66096 # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs 66053 # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs 11.708787 # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs 11.702557 # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks 9687 # number of writebacks
-system.cpu0.l1c.writebacks::total 9687 # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36474 # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total 36474 # number of ReadReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23719 # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::total 23719 # number of WriteReq MSHR misses
-system.cpu0.l1c.demand_mshr_misses::cpu0 60193 # number of demand (read+write) MSHR misses
-system.cpu0.l1c.demand_mshr_misses::total 60193 # number of demand (read+write) MSHR misses
-system.cpu0.l1c.overall_mshr_misses::cpu0 60193 # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_misses::total 60193 # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 531003039 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total 531003039 # number of ReadReq MSHR miss cycles
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-system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1146656340 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::total 1146656340 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1146656340 # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total 1146656340 # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 646054384 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 646054384 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 971060215 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 971060215 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1617114599 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1617114599 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.810984 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.810984 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954026 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954026 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861907 # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_miss_rate::total 0.861907 # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861907 # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total 0.861907 # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 14558.398832 # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 14558.398832 # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 25956.123825 # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 25956.123825 # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19049.662585 # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19049.662585 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19049.662585 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19049.662585 # average overall mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu0.l1c.WriteReq_mshr_miss_latency::total 625061532 # number of WriteReq MSHR miss cycles
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+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 26077.914473 # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 26077.914473 # average WriteReq mshr miss latency
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+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19147.483917 # average overall mshr miss latency
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+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 64979.379054 # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64979.379054 # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 175813.110527 # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 175813.110527 # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 104818.597760 # average overall mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 104818.597760 # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.num_reads 99262 # number of read accesses completed
-system.cpu1.num_writes 54743 # number of write accesses completed
-system.cpu1.l1c.tags.replacements 22415 # number of replacements
-system.cpu1.l1c.tags.tagsinuse 391.761420 # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs 13414 # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs 22814 # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs 0.587972 # Average number of references to valid blocks.
+system.cpu1.num_reads 98972 # number of read accesses completed
+system.cpu1.num_writes 54740 # number of write accesses completed
+system.cpu1.l1c.tags.replacements 21894 # number of replacements
+system.cpu1.l1c.tags.tagsinuse 389.013692 # Cycle average of tags in use
+system.cpu1.l1c.tags.total_refs 13227 # Total number of references to valid blocks.
+system.cpu1.l1c.tags.sampled_refs 22299 # Sample count of references to valid blocks.
+system.cpu1.l1c.tags.avg_refs 0.593166 # Average number of references to valid blocks.
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1 391.761420 # Average occupied blocks per requestor
-system.cpu1.l1c.tags.occ_percent::cpu1 0.765159 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_percent::total 0.765159 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
-system.cpu1.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id
-system.cpu1.l1c.tags.tag_accesses 336589 # Number of tag accesses
-system.cpu1.l1c.tags.data_accesses 336589 # Number of data accesses
-system.cpu1.l1c.ReadReq_hits::cpu1 8598 # number of ReadReq hits
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-system.cpu1.l1c.WriteReq_hits::cpu1 1162 # number of WriteReq hits
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-system.cpu1.l1c.overall_hits::total 9760 # number of overall hits
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-system.cpu1.l1c.ReadReq_misses::total 36477 # number of ReadReq misses
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-system.cpu1.l1c.demand_misses::total 60253 # number of demand (read+write) misses
-system.cpu1.l1c.overall_misses::cpu1 60253 # number of overall misses
-system.cpu1.l1c.overall_misses::total 60253 # number of overall misses
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-system.cpu1.l1c.overall_miss_latency::total 1244610600 # number of overall miss cycles
-system.cpu1.l1c.ReadReq_accesses::cpu1 45075 # number of ReadReq accesses(hits+misses)
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-system.cpu1.l1c.overall_accesses::total 70013 # number of overall (read+write) accesses
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-system.cpu1.l1c.overall_miss_rate::total 0.860597 # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16324.281821 # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 16324.281821 # average ReadReq miss latency
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-system.cpu1.l1c.demand_avg_miss_latency::total 20656.408810 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 20656.408810 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 20656.408810 # average overall miss latency
-system.cpu1.l1c.blocked_cycles::no_mshrs 769857 # number of cycles access was blocked
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+system.cpu1.l1c.overall_miss_latency::total 1252908099 # number of overall miss cycles
+system.cpu1.l1c.ReadReq_accesses::cpu1 44712 # number of ReadReq accesses(hits+misses)
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+system.cpu1.l1c.overall_miss_rate::total 0.861267 # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16229.392004 # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 16229.392004 # average ReadReq miss latency
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+system.cpu1.l1c.demand_avg_miss_latency::total 20864.067193 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 20864.067193 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 20864.067193 # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs 781068 # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs 65915 # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs 66159 # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11.679542 # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11.805922 # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks 9826 # number of writebacks
-system.cpu1.l1c.writebacks::total 9826 # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36477 # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total 36477 # number of ReadReq MSHR misses
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-system.cpu1.l1c.WriteReq_mshr_misses::total 23776 # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1 60253 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total 60253 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1 60253 # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total 60253 # number of overall MSHR misses
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-system.cpu1.l1c.ReadReq_mshr_miss_latency::total 538442174 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 612498892 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total 612498892 # number of WriteReq MSHR miss cycles
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-system.cpu1.l1c.demand_mshr_miss_latency::total 1150941066 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1150941066 # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total 1150941066 # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 637533564 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 637533564 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 980538192 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 980538192 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1618071756 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1618071756 # number of overall MSHR uncacheable cycles
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-system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.809251 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953404 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953404 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860597 # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_miss_rate::total 0.860597 # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860597 # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total 0.860597 # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 14761.141925 # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 14761.141925 # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 25761.225269 # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 25761.225269 # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19101.805155 # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19101.805155 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19101.805155 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19101.805155 # average overall mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
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-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 26352.882439 # average WriteReq mshr miss latency
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+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 64762.345491 # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64762.345491 # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 174821.976199 # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174821.976199 # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 103970.909470 # average overall mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 103970.909470 # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.num_reads 99661 # number of read accesses completed
-system.cpu2.num_writes 54617 # number of write accesses completed
-system.cpu2.l1c.tags.replacements 22463 # number of replacements
-system.cpu2.l1c.tags.tagsinuse 392.489979 # Cycle average of tags in use
-system.cpu2.l1c.tags.total_refs 13594 # Total number of references to valid blocks.
-system.cpu2.l1c.tags.sampled_refs 22875 # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs 0.594273 # Average number of references to valid blocks.
+system.cpu2.num_reads 99459 # number of read accesses completed
+system.cpu2.num_writes 55455 # number of write accesses completed
+system.cpu2.l1c.tags.replacements 22538 # number of replacements
+system.cpu2.l1c.tags.tagsinuse 392.681778 # Cycle average of tags in use
+system.cpu2.l1c.tags.total_refs 13552 # Total number of references to valid blocks.
+system.cpu2.l1c.tags.sampled_refs 22938 # Sample count of references to valid blocks.
+system.cpu2.l1c.tags.avg_refs 0.590810 # Average number of references to valid blocks.
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.tags.occ_blocks::cpu2 392.489979 # Average occupied blocks per requestor
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-system.cpu2.l1c.tags.occ_percent::total 0.766582 # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_task_id_blocks::1024 412 # Occupied blocks per task id
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-system.cpu2.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
-system.cpu2.l1c.tags.occ_task_id_percent::1024 0.804688 # Percentage of cache occupancy per task id
-system.cpu2.l1c.tags.tag_accesses 338191 # Number of tag accesses
-system.cpu2.l1c.tags.data_accesses 338191 # Number of data accesses
-system.cpu2.l1c.ReadReq_hits::cpu2 8852 # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total 8852 # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2 1132 # number of WriteReq hits
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-system.cpu2.l1c.overall_hits::total 9984 # number of overall hits
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-system.cpu2.l1c.ReadReq_misses::total 36597 # number of ReadReq misses
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-system.cpu2.l1c.WriteReq_misses::total 23791 # number of WriteReq misses
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-system.cpu2.l1c.demand_misses::total 60388 # number of demand (read+write) misses
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-system.cpu2.l1c.overall_misses::total 60388 # number of overall misses
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-system.cpu2.l1c.overall_miss_latency::total 1242570282 # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2 45449 # number of ReadReq accesses(hits+misses)
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-system.cpu2.l1c.WriteReq_accesses::total 24923 # number of WriteReq accesses(hits+misses)
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-system.cpu2.l1c.ReadReq_miss_rate::total 0.805232 # miss rate for ReadReq accesses
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-system.cpu2.l1c.overall_miss_rate::total 0.858125 # miss rate for overall accesses
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-system.cpu2.l1c.ReadReq_avg_miss_latency::total 16288.451567 # average ReadReq miss latency
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-system.cpu2.l1c.WriteReq_avg_miss_latency::total 27172.536674 # average WriteReq miss latency
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-system.cpu2.l1c.demand_avg_miss_latency::total 20576.443697 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 20576.443697 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 20576.443697 # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs 768951 # number of cycles access was blocked
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+system.cpu2.l1c.WriteReq_accesses::total 25073 # number of WriteReq accesses(hits+misses)
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+system.cpu2.l1c.overall_miss_rate::total 0.859360 # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16261.199973 # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_miss_latency::total 16261.199973 # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27767.096354 # average WriteReq miss latency
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+system.cpu2.l1c.demand_avg_miss_latency::total 20816.387896 # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::cpu2 20816.387896 # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::total 20816.387896 # average overall miss latency
+system.cpu2.l1c.blocked_cycles::no_mshrs 773062 # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs 65985 # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_mshrs 66064 # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs 11.653421 # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs 11.701713 # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks 9852 # number of writebacks
-system.cpu2.l1c.writebacks::total 9852 # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36597 # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total 36597 # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23791 # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total 23791 # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses::cpu2 60388 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.demand_mshr_misses::total 60388 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2 60388 # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total 60388 # number of overall MSHR misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 538960044 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_latency::total 538960044 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 609774472 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total 609774472 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1148734516 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::total 1148734516 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1148734516 # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total 1148734516 # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 638400628 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 638400628 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 959722740 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 959722740 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1598123368 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1598123368 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805232 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805232 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954580 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954580 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858125 # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_miss_rate::total 0.858125 # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858125 # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total 0.858125 # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 14726.891385 # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 14726.891385 # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 25630.468328 # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 25630.468328 # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19022.562695 # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19022.562695 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19022.562695 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19022.562695 # average overall mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
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-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
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+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 26227.665857 # average WriteReq mshr miss latency
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+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 104837.549192 # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu3.num_writes 55095 # number of write accesses completed
-system.cpu3.l1c.tags.replacements 22209 # number of replacements
-system.cpu3.l1c.tags.tagsinuse 391.627346 # Cycle average of tags in use
-system.cpu3.l1c.tags.total_refs 13529 # Total number of references to valid blocks.
-system.cpu3.l1c.tags.sampled_refs 22601 # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs 0.598602 # Average number of references to valid blocks.
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+system.cpu3.l1c.tags.tagsinuse 392.069306 # Cycle average of tags in use
+system.cpu3.l1c.tags.total_refs 13533 # Total number of references to valid blocks.
+system.cpu3.l1c.tags.sampled_refs 22710 # Sample count of references to valid blocks.
+system.cpu3.l1c.tags.avg_refs 0.595905 # Average number of references to valid blocks.
system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu3.l1c.tags.tag_accesses 338542 # Number of tag accesses
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-system.cpu3.l1c.overall_hits::total 9932 # number of overall hits
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-system.cpu3.l1c.demand_misses::total 60493 # number of demand (read+write) misses
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-system.cpu3.l1c.demand_avg_miss_latency::total 20620.193361 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 20620.193361 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 20620.193361 # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs 774947 # number of cycles access was blocked
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+system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16045.324146 # average ReadReq miss latency
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+system.cpu3.l1c.overall_avg_miss_latency::cpu3 20718.293856 # average overall miss latency
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system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs 66468 # number of cycles access was blocked
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system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs 11.658949 # average number of cycles each access was blocked
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system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
-system.cpu3.l1c.writebacks::writebacks 9869 # number of writebacks
-system.cpu3.l1c.writebacks::total 9869 # number of writebacks
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-system.cpu3.l1c.WriteReq_mshr_misses::total 23815 # number of WriteReq MSHR misses
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-system.cpu3.l1c.demand_mshr_misses::total 60493 # number of demand (read+write) MSHR misses
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-system.cpu3.l1c.overall_mshr_misses::total 60493 # number of overall MSHR misses
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-system.cpu3.l1c.ReadReq_mshr_miss_latency::total 538014612 # number of ReadReq MSHR miss cycles
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-system.cpu3.l1c.WriteReq_mshr_miss_latency::total 615289695 # number of WriteReq MSHR miss cycles
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-system.cpu3.l1c.demand_mshr_miss_latency::total 1153304307 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1153304307 # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total 1153304307 # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 640462998 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 640462998 # number of ReadReq MSHR uncacheable cycles
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-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 962755753 # number of WriteReq MSHR uncacheable cycles
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-system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1603218751 # number of overall MSHR uncacheable cycles
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-system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.806801 # mshr miss rate for ReadReq accesses
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-system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953974 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858971 # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_miss_rate::total 0.858971 # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858971 # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total 0.858971 # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 14668.591853 # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 14668.591853 # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 25836.224858 # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 25836.224858 # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19065.086985 # average overall mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19065.086985 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19065.086985 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19065.086985 # average overall mshr miss latency
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-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
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+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 105246.778464 # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu4.num_writes 55186 # number of write accesses completed
-system.cpu4.l1c.tags.replacements 22162 # number of replacements
-system.cpu4.l1c.tags.tagsinuse 390.917230 # Cycle average of tags in use
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-system.cpu4.l1c.tags.sampled_refs 22564 # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs 0.608890 # Average number of references to valid blocks.
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system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu4.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
-system.cpu4.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu4.l1c.tags.tag_accesses 338274 # Number of tag accesses
-system.cpu4.l1c.tags.data_accesses 338274 # Number of data accesses
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-system.cpu4.l1c.ReadReq_hits::total 8951 # number of ReadReq hits
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system.cpu4.l1c.WriteReq_hits::cpu4 1108 # number of WriteReq hits
system.cpu4.l1c.WriteReq_hits::total 1108 # number of WriteReq hits
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-system.cpu4.l1c.overall_miss_rate::total 0.857145 # miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16195.376409 # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_miss_latency::total 16195.376409 # average ReadReq miss latency
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-system.cpu4.l1c.overall_avg_miss_latency::cpu4 20676.392577 # average overall miss latency
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+system.cpu4.l1c.overall_accesses::total 70155 # number of overall (read+write) accesses
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+system.cpu4.l1c.demand_avg_miss_latency::total 20790.207343 # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::cpu4 20790.207343 # average overall miss latency
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+system.cpu4.l1c.blocked_cycles::no_mshrs 777995 # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs 66046 # number of cycles access was blocked
+system.cpu4.l1c.blocked::no_mshrs 66371 # number of cycles access was blocked
system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_mshrs 11.689489 # average number of cycles each access was blocked
+system.cpu4.l1c.avg_blocked_cycles::no_mshrs 11.721912 # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu4.l1c.writebacks::total 9680 # number of writebacks
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-system.cpu4.l1c.ReadReq_mshr_misses::total 36463 # number of ReadReq MSHR misses
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-system.cpu4.l1c.demand_mshr_misses::total 60355 # number of demand (read+write) MSHR misses
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-system.cpu4.l1c.overall_mshr_misses::total 60355 # number of overall MSHR misses
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-system.cpu4.l1c.demand_mshr_miss_latency::total 1154055642 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1154055642 # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total 1154055642 # number of overall MSHR miss cycles
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-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 636776082 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 976656146 # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 976656146 # number of WriteReq MSHR uncacheable cycles
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-system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1613432228 # number of overall MSHR uncacheable cycles
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-system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.802902 # mshr miss rate for ReadReq accesses
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-system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.955680 # mshr miss rate for WriteReq accesses
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-system.cpu4.l1c.demand_mshr_miss_rate::total 0.857145 # mshr miss rate for demand accesses
-system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857145 # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_miss_rate::total 0.857145 # mshr miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 14632.237391 # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 14632.237391 # average ReadReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 25971.888917 # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 25971.888917 # average WriteReq mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19121.127363 # average overall mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19121.127363 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19121.127363 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19121.127363 # average overall mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 26224.258458 # average WriteReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 26224.258458 # average WriteReq mshr miss latency
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+system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19234.896809 # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19234.896809 # average overall mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65094.553692 # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65094.553692 # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 178543.996089 # average WriteReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 178543.996089 # average WriteReq mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 105312.635661 # average overall mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 105312.635661 # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu5.num_reads 98793 # number of read accesses completed
-system.cpu5.num_writes 54966 # number of write accesses completed
-system.cpu5.l1c.tags.replacements 22337 # number of replacements
-system.cpu5.l1c.tags.tagsinuse 392.447401 # Cycle average of tags in use
-system.cpu5.l1c.tags.total_refs 13310 # Total number of references to valid blocks.
-system.cpu5.l1c.tags.sampled_refs 22755 # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs 0.584926 # Average number of references to valid blocks.
+system.cpu5.num_reads 99076 # number of read accesses completed
+system.cpu5.num_writes 54802 # number of write accesses completed
+system.cpu5.l1c.tags.replacements 22210 # number of replacements
+system.cpu5.l1c.tags.tagsinuse 392.101349 # Cycle average of tags in use
+system.cpu5.l1c.tags.total_refs 13412 # Total number of references to valid blocks.
+system.cpu5.l1c.tags.sampled_refs 22600 # Sample count of references to valid blocks.
+system.cpu5.l1c.tags.avg_refs 0.593451 # Average number of references to valid blocks.
system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.tags.occ_blocks::cpu5 392.447401 # Average occupied blocks per requestor
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-system.cpu5.l1c.tags.occ_percent::total 0.766499 # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_task_id_blocks::1024 418 # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::0 408 # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
-system.cpu5.l1c.tags.occ_task_id_percent::1024 0.816406 # Percentage of cache occupancy per task id
-system.cpu5.l1c.tags.tag_accesses 335862 # Number of tag accesses
-system.cpu5.l1c.tags.data_accesses 335862 # Number of data accesses
-system.cpu5.l1c.ReadReq_hits::cpu5 8554 # number of ReadReq hits
-system.cpu5.l1c.ReadReq_hits::total 8554 # number of ReadReq hits
-system.cpu5.l1c.WriteReq_hits::cpu5 1127 # number of WriteReq hits
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-system.cpu5.l1c.demand_hits::total 9681 # number of demand (read+write) hits
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-system.cpu5.l1c.overall_hits::total 9681 # number of overall hits
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-system.cpu5.l1c.ReadReq_misses::total 36144 # number of ReadReq misses
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-system.cpu5.l1c.WriteReq_misses::total 24019 # number of WriteReq misses
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-system.cpu5.l1c.demand_misses::total 60163 # number of demand (read+write) misses
-system.cpu5.l1c.overall_misses::cpu5 60163 # number of overall misses
-system.cpu5.l1c.overall_misses::total 60163 # number of overall misses
-system.cpu5.l1c.ReadReq_miss_latency::cpu5 586243376 # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_latency::total 586243376 # number of ReadReq miss cycles
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-system.cpu5.l1c.overall_miss_latency::total 1250328762 # number of overall miss cycles
-system.cpu5.l1c.ReadReq_accesses::cpu5 44698 # number of ReadReq accesses(hits+misses)
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-system.cpu5.l1c.overall_accesses::total 69844 # number of overall (read+write) accesses
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-system.cpu5.l1c.ReadReq_miss_rate::total 0.808627 # miss rate for ReadReq accesses
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-system.cpu5.l1c.overall_miss_rate::total 0.861391 # miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16219.659584 # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_miss_latency::total 16219.659584 # average ReadReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27648.336151 # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::total 27648.336151 # average WriteReq miss latency
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-system.cpu5.l1c.demand_avg_miss_latency::total 20782.353972 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 20782.353972 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 20782.353972 # average overall miss latency
-system.cpu5.l1c.blocked_cycles::no_mshrs 771700 # number of cycles access was blocked
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+system.cpu5.l1c.tags.occ_percent::total 0.765823 # Average percentage of cache occupancy
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+system.cpu5.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
+system.cpu5.l1c.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id
+system.cpu5.l1c.tags.tag_accesses 335763 # Number of tag accesses
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+system.cpu5.l1c.ReadReq_hits::total 8687 # number of ReadReq hits
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+system.cpu5.l1c.overall_miss_latency::total 1241068455 # number of overall miss cycles
+system.cpu5.l1c.ReadReq_accesses::cpu5 45073 # number of ReadReq accesses(hits+misses)
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+system.cpu5.l1c.WriteReq_accesses::total 24777 # number of WriteReq accesses(hits+misses)
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+system.cpu5.l1c.overall_accesses::total 69850 # number of overall (read+write) accesses
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+system.cpu5.l1c.ReadReq_miss_rate::total 0.807268 # miss rate for ReadReq accesses
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+system.cpu5.l1c.overall_miss_rate::total 0.858626 # miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16138.638872 # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_miss_latency::total 16138.638872 # average ReadReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27718.340794 # average WriteReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::total 27718.340794 # average WriteReq miss latency
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+system.cpu5.l1c.demand_avg_miss_latency::total 20693.096373 # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::cpu5 20693.096373 # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::total 20693.096373 # average overall miss latency
+system.cpu5.l1c.blocked_cycles::no_mshrs 773798 # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs 65809 # number of cycles access was blocked
+system.cpu5.l1c.blocked::no_mshrs 65921 # number of cycles access was blocked
system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs 11.726360 # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_mshrs 11.738262 # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
-system.cpu5.l1c.writebacks::writebacks 9916 # number of writebacks
-system.cpu5.l1c.writebacks::total 9916 # number of writebacks
-system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36144 # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_misses::total 36144 # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24019 # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::total 24019 # number of WriteReq MSHR misses
-system.cpu5.l1c.demand_mshr_misses::cpu5 60163 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.demand_mshr_misses::total 60163 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses::cpu5 60163 # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_misses::total 60163 # number of overall MSHR misses
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-system.cpu5.l1c.ReadReq_mshr_miss_latency::total 529678552 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 626959212 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::total 626959212 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1156637764 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::total 1156637764 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1156637764 # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total 1156637764 # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 632837521 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 632837521 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 970316626 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 970316626 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1603154147 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1603154147 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808627 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808627 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.955182 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.955182 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.861391 # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_miss_rate::total 0.861391 # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.861391 # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_miss_rate::total 0.861391 # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 14654.674413 # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 14654.674413 # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 26102.635913 # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 26102.635913 # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19225.067965 # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19225.067965 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19225.067965 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19225.067965 # average overall mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
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+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 26177.519479 # average WriteReq mshr miss latency
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+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19139.461759 # average overall mshr miss latency
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+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 64886.362849 # average ReadReq mshr uncacheable latency
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+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 176692.307622 # average WriteReq mshr uncacheable latency
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+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 104733.178099 # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu6.num_reads 99383 # number of read accesses completed
-system.cpu6.num_writes 54752 # number of write accesses completed
-system.cpu6.l1c.tags.replacements 22371 # number of replacements
-system.cpu6.l1c.tags.tagsinuse 391.299314 # Cycle average of tags in use
-system.cpu6.l1c.tags.total_refs 13429 # Total number of references to valid blocks.
-system.cpu6.l1c.tags.sampled_refs 22762 # Sample count of references to valid blocks.
-system.cpu6.l1c.tags.avg_refs 0.589975 # Average number of references to valid blocks.
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+system.cpu6.num_writes 55196 # number of write accesses completed
+system.cpu6.l1c.tags.replacements 22166 # number of replacements
+system.cpu6.l1c.tags.tagsinuse 390.500017 # Cycle average of tags in use
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+system.cpu6.l1c.tags.sampled_refs 22571 # Sample count of references to valid blocks.
+system.cpu6.l1c.tags.avg_refs 0.611271 # Average number of references to valid blocks.
system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu6.l1c.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
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-system.cpu6.l1c.tags.tag_accesses 336995 # Number of tag accesses
-system.cpu6.l1c.tags.data_accesses 336995 # Number of data accesses
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-system.cpu6.l1c.ReadReq_hits::total 8731 # number of ReadReq hits
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-system.cpu6.l1c.ReadReq_accesses::cpu6 45276 # number of ReadReq accesses(hits+misses)
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-system.cpu6.l1c.ReadReq_avg_miss_latency::total 16161.213600 # average ReadReq miss latency
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-system.cpu6.l1c.demand_avg_miss_latency::total 20603.039713 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 20603.039713 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 20603.039713 # average overall miss latency
-system.cpu6.l1c.blocked_cycles::no_mshrs 771561 # number of cycles access was blocked
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+system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16203.946313 # average ReadReq miss latency
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+system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28109.785196 # average WriteReq miss latency
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+system.cpu6.l1c.overall_avg_miss_latency::cpu6 20907.660610 # average overall miss latency
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system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_mshrs 66088 # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_mshrs 66360 # number of cycles access was blocked
system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_mshrs 11.674752 # average number of cycles each access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_mshrs 11.740341 # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
-system.cpu6.l1c.writebacks::writebacks 9782 # number of writebacks
-system.cpu6.l1c.writebacks::total 9782 # number of writebacks
-system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36545 # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_misses::total 36545 # number of ReadReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23737 # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::total 23737 # number of WriteReq MSHR misses
-system.cpu6.l1c.demand_mshr_misses::cpu6 60282 # number of demand (read+write) MSHR misses
-system.cpu6.l1c.demand_mshr_misses::total 60282 # number of demand (read+write) MSHR misses
-system.cpu6.l1c.overall_mshr_misses::cpu6 60282 # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_misses::total 60282 # number of overall MSHR misses
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-system.cpu6.l1c.ReadReq_mshr_miss_latency::total 533644023 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 614831387 # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::total 614831387 # number of WriteReq MSHR miss cycles
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-system.cpu6.l1c.demand_mshr_miss_latency::total 1148475410 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1148475410 # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::total 1148475410 # number of overall MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 641180935 # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 641180935 # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 971245186 # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 971245186 # number of WriteReq MSHR uncacheable cycles
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-system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1612426121 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807161 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807161 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.956173 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.956173 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859931 # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_miss_rate::total 0.859931 # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859931 # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_miss_rate::total 0.859931 # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 14602.381256 # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 14602.381256 # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 25901.815183 # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 25901.815183 # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19051.713779 # average overall mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19051.713779 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19051.713779 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19051.713779 # average overall mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 26569.210566 # average WriteReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 26569.210566 # average WriteReq mshr miss latency
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+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19353.150066 # average overall mshr miss latency
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+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 64822.299826 # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64822.299826 # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 179089.477892 # average WriteReq mshr uncacheable latency
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+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 105635.765809 # average overall mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 105635.765809 # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu7.num_reads 99477 # number of read accesses completed
-system.cpu7.num_writes 54915 # number of write accesses completed
-system.cpu7.l1c.tags.replacements 22352 # number of replacements
-system.cpu7.l1c.tags.tagsinuse 391.525005 # Cycle average of tags in use
-system.cpu7.l1c.tags.total_refs 13561 # Total number of references to valid blocks.
-system.cpu7.l1c.tags.sampled_refs 22758 # Sample count of references to valid blocks.
-system.cpu7.l1c.tags.avg_refs 0.595878 # Average number of references to valid blocks.
+system.cpu7.num_reads 99558 # number of read accesses completed
+system.cpu7.num_writes 55171 # number of write accesses completed
+system.cpu7.l1c.tags.replacements 22301 # number of replacements
+system.cpu7.l1c.tags.tagsinuse 392.314330 # Cycle average of tags in use
+system.cpu7.l1c.tags.total_refs 13511 # Total number of references to valid blocks.
+system.cpu7.l1c.tags.sampled_refs 22696 # Sample count of references to valid blocks.
+system.cpu7.l1c.tags.avg_refs 0.595303 # Average number of references to valid blocks.
system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.tags.occ_blocks::cpu7 391.525005 # Average occupied blocks per requestor
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-system.cpu7.l1c.tags.occ_percent::total 0.764697 # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_task_id_blocks::1024 406 # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
-system.cpu7.l1c.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id
-system.cpu7.l1c.tags.tag_accesses 337629 # Number of tag accesses
-system.cpu7.l1c.tags.data_accesses 337629 # Number of data accesses
-system.cpu7.l1c.ReadReq_hits::cpu7 8790 # number of ReadReq hits
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-system.cpu7.l1c.WriteReq_hits::cpu7 1137 # number of WriteReq hits
-system.cpu7.l1c.WriteReq_hits::total 1137 # number of WriteReq hits
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-system.cpu7.l1c.overall_hits::total 9927 # number of overall hits
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-system.cpu7.l1c.WriteReq_misses::total 23844 # number of WriteReq misses
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-system.cpu7.l1c.demand_misses::total 60321 # number of demand (read+write) misses
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-system.cpu7.l1c.overall_misses::total 60321 # number of overall misses
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-system.cpu7.l1c.overall_miss_latency::total 1245041958 # number of overall miss cycles
-system.cpu7.l1c.ReadReq_accesses::cpu7 45267 # number of ReadReq accesses(hits+misses)
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-system.cpu7.l1c.overall_miss_rate::total 0.858686 # miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16276.464896 # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_miss_latency::total 16276.464896 # average ReadReq miss latency
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-system.cpu7.l1c.WriteReq_avg_miss_latency::total 27316.110887 # average WriteReq miss latency
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-system.cpu7.l1c.demand_avg_miss_latency::total 20640.273835 # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::cpu7 20640.273835 # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::total 20640.273835 # average overall miss latency
-system.cpu7.l1c.blocked_cycles::no_mshrs 768557 # number of cycles access was blocked
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+system.cpu7.l1c.tags.occ_percent::total 0.766239 # Average percentage of cache occupancy
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+system.cpu7.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id
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+system.cpu7.l1c.tags.tag_accesses 337937 # Number of tag accesses
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+system.cpu7.l1c.ReadReq_hits::total 8724 # number of ReadReq hits
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+system.cpu7.l1c.overall_misses::total 60474 # number of overall misses
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+system.cpu7.l1c.overall_miss_latency::total 1260670841 # number of overall miss cycles
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+system.cpu7.l1c.overall_miss_rate::total 0.860191 # miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16300.870515 # average ReadReq miss latency
+system.cpu7.l1c.ReadReq_avg_miss_latency::total 16300.870515 # average ReadReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 27799.740986 # average WriteReq miss latency
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+system.cpu7.l1c.overall_avg_miss_latency::cpu7 20846.493386 # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::total 20846.493386 # average overall miss latency
+system.cpu7.l1c.blocked_cycles::no_mshrs 776345 # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_mshrs 65923 # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_mshrs 66228 # number of cycles access was blocked
system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_mshrs 11.658405 # average number of cycles each access was blocked
+system.cpu7.l1c.avg_blocked_cycles::no_mshrs 11.722308 # average number of cycles each access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
-system.cpu7.l1c.writebacks::writebacks 9939 # number of writebacks
-system.cpu7.l1c.writebacks::total 9939 # number of writebacks
-system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36477 # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_misses::total 36477 # number of ReadReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23844 # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::total 23844 # number of WriteReq MSHR misses
-system.cpu7.l1c.demand_mshr_misses::cpu7 60321 # number of demand (read+write) MSHR misses
-system.cpu7.l1c.demand_mshr_misses::total 60321 # number of demand (read+write) MSHR misses
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-system.cpu7.l1c.overall_mshr_misses::total 60321 # number of overall MSHR misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 536729312 # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_miss_latency::total 536729312 # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 614614324 # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::total 614614324 # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1151343636 # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::total 1151343636 # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1151343636 # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::total 1151343636 # number of overall MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 635643033 # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 635643033 # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 965131654 # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 965131654 # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1600774687 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1600774687 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805819 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805819 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954485 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954485 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858686 # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_miss_rate::total 0.858686 # mshr miss rate for demand accesses
-system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858686 # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_miss_rate::total 0.858686 # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 14714.184609 # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 14714.184609 # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 25776.477269 # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 25776.477269 # average WriteReq mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19086.945442 # average overall mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19086.945442 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19086.945442 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19086.945442 # average overall mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
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-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
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+system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5336 # number of WriteReq MSHR uncacheable
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+system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15036 # number of overall MSHR uncacheable misses
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+system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1166699669 # number of overall MSHR miss cycles
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+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 14739.249699 # average ReadReq mshr miss latency
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+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 104740.650173 # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.l2c.tags.tagsinuse 783.697862 # Cycle average of tags in use
-system.l2c.tags.total_refs 151322 # Total number of references to valid blocks.
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-system.l2c.tags.avg_refs 10.346803 # Average number of references to valid blocks.
+system.l2c.tags.replacements 14031 # number of replacements
+system.l2c.tags.tagsinuse 784.967814 # Cycle average of tags in use
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+system.l2c.tags.sampled_refs 14812 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 10.137186 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 724.401984 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0 7.094586 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1 7.546674 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2 7.606935 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3 7.397120 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4 7.288170 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5 7.917650 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6 7.470007 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7 6.974735 # Average occupied blocks per requestor
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-system.l2c.ReadReq_hits::cpu6 10660 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu7 10974 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 86237 # number of ReadReq hits
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-system.l2c.UpgradeReq_hits::cpu2 373 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3 367 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4 376 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5 343 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6 361 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7 335 # number of UpgradeReq hits
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-system.l2c.overall_hits::cpu7 12864 # number of overall hits
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-system.l2c.UpgradeReq_misses::cpu5 2012 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu6 1921 # number of UpgradeReq misses
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-system.l2c.overall_misses::cpu6 5147 # number of overall misses
-system.l2c.overall_misses::cpu7 5089 # number of overall misses
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-system.l2c.ReadReq_accesses::total 92100 # number of ReadReq accesses(hits+misses)
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-system.l2c.Writeback_accesses::total 76857 # number of Writeback accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu1 2360 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2 2279 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3 2302 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu4 2376 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu5 2355 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu6 2282 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu7 2322 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 18591 # number of UpgradeReq accesses(hits+misses)
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-system.l2c.ReadExReq_accesses::total 50850 # number of ReadExReq accesses(hits+misses)
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system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 43210.631824 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 43291.830143 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 43299.964665 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 43348.687155 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 43285.523410 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 43297.255038 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 84510 # Transaction distribution
-system.membus.trans_dist::ReadResp 84504 # Transaction distribution
-system.membus.trans_dist::WriteReq 43512 # Transaction distribution
-system.membus.trans_dist::WriteResp 43509 # Transaction distribution
-system.membus.trans_dist::Writeback 6553 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 58529 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 47554 # Transaction distribution
-system.membus.trans_dist::ReadExReq 49190 # Transaction distribution
-system.membus.trans_dist::ReadExResp 3281 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 421142 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 421142 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1121847 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1121847 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 56880 # Total snoops (count)
-system.membus.snoop_fanout::samples 123632 # Request fanout histogram
+system.membus.trans_dist::ReadReq 84372 # Transaction distribution
+system.membus.trans_dist::ReadResp 84365 # Transaction distribution
+system.membus.trans_dist::WriteReq 43521 # Transaction distribution
+system.membus.trans_dist::WriteResp 43519 # Transaction distribution
+system.membus.trans_dist::Writeback 6720 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 60428 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 49463 # Transaction distribution
+system.membus.trans_dist::ReadExReq 49409 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3325 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 425122 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 425122 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1143411 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1143411 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 57048 # Total snoops (count)
+system.membus.snoop_fanout::samples 253034 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 123632 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 253034 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 123632 # Request fanout histogram
-system.membus.reqLayer0.occupancy 285799779 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 60.4 # Layer utilization (%)
-system.membus.respLayer0.occupancy 306149550 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 64.7 # Layer utilization (%)
-system.toL2Bus.trans_dist::ReadReq 370575 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 370557 # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate 7 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 43514 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 43509 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 76857 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 29562 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 29559 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 161030 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 161024 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120584 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120575 # Packet count per connected master and slave (bytes)
+system.membus.snoop_fanout::total 253034 # Request fanout histogram
+system.membus.reqLayer0.occupancy 288296633 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 60.9 # Layer utilization (%)
+system.membus.respLayer0.occupancy 308136269 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 65.1 # Layer utilization (%)
+system.toL2Bus.trans_dist::ReadReq 369990 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 369967 # Transaction distribution
+system.toL2Bus.trans_dist::ReadRespWithInvalidate 6 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 43524 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 43518 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 76544 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 29606 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 29605 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 161002 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 160999 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120638 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120231 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120590 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120769 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120586 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120766 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120584 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120839 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 965293 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1758906 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1769834 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1777815 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1771618 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1766732 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1791122 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1765164 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1788112 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 14189303 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 320901 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 563826 # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120464 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120699 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120288 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120457 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120419 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 963786 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1770551 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1757664 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1763883 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1765044 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1785450 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1756799 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1766043 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1776312 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 14141746 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 320975 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 687560 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
@@ -1694,29 +1769,29 @@ system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Re
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 563826 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 687560 100.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 563826 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 445759226 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 94.2 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 101149991 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 687560 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 445191055 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 94.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 101323906 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 21.4 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 101191512 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 21.4 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 101359906 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 101013875 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 21.3 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 101243878 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 21.4 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 101648274 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 21.5 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 101307289 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 101066643 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 21.3 # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy 101367492 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 21.4 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 101134998 # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization 21.4 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 101213033 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy 100955896 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization 21.3 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 101182766 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 21.4 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 101242964 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy 101290842 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 21.4 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index 313b6d716..d571b5762 100644
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.048960 # Nu
sim_ticks 48960011500 # Number of ticks simulated
final_tick 48960011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1111911 # Simulator instruction rate (inst/s)
-host_op_rate 1421979 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 767686935 # Simulator tick rate (ticks/s)
-host_mem_usage 303468 # Number of bytes of host memory used
-host_seconds 63.78 # Real time elapsed on the host
+host_inst_rate 1547474 # Simulator instruction rate (inst/s)
+host_op_rate 1979004 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1068409192 # Simulator tick rate (ticks/s)
+host_mem_usage 311136 # Number of bytes of host memory used
+host_seconds 45.83 # Real time elapsed on the host
sim_insts 70913182 # Number of instructions simulated
sim_ops 90688137 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556
system.membus.pkt_size::total 497813832 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 120930619 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.646198 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.646198 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 42785550 35.38% 35.38% # Request fanout histogram
-system.membus.snoop_fanout::3 78145069 64.62% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 42785550 35.38% 35.38% # Request fanout histogram
+system.membus.snoop_fanout::1 78145069 64.62% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 120930619 # Request fanout histogram
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
index 91d42cd77..90d753109 100644
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -597,17 +597,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
system.cpu.toL2Bus.pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 307145 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 307145 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 307145 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 307145 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
index 772df96ed..37a976075 100644
--- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.099596 # Nu
sim_ticks 99596491500 # Number of ticks simulated
final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1304038 # Simulator instruction rate (inst/s)
-host_op_rate 1374666 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 753711187 # Simulator tick rate (ticks/s)
-host_mem_usage 298984 # Number of bytes of host memory used
-host_seconds 132.14 # Real time elapsed on the host
+host_inst_rate 1968226 # Simulator instruction rate (inst/s)
+host_op_rate 2074827 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1137600357 # Simulator tick rate (ticks/s)
+host_mem_usage 306644 # Number of bytes of host memory used
+host_seconds 87.55 # Real time elapsed on the host
sim_insts 172317410 # Number of instructions simulated
sim_ops 181650342 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601
system.membus.pkt_size::total 915226809 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 230024467 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.825391 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.825391 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 40164415 17.46% 17.46% # Request fanout histogram
-system.membus.snoop_fanout::3 189860052 82.54% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 40164415 17.46% 17.46% # Request fanout histogram
+system.membus.snoop_fanout::1 189860052 82.54% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 230024467 # Request fanout histogram
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
index e97c269ba..c495da061 100644
--- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -585,17 +585,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 4856 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 4856 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 4856 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 4856 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
index 7b91ddd8b..b19da3109 100644
--- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.131393 # Nu
sim_ticks 131393279000 # Number of ticks simulated
final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1264426 # Simulator instruction rate (inst/s)
-host_op_rate 2119294 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1257935779 # Simulator tick rate (ticks/s)
-host_mem_usage 324376 # Number of bytes of host memory used
-host_seconds 104.45 # Real time elapsed on the host
+host_inst_rate 851639 # Simulator instruction rate (inst/s)
+host_op_rate 1427424 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 847267215 # Simulator tick rate (ticks/s)
+host_mem_usage 272248 # Number of bytes of host memory used
+host_seconds 155.08 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221363385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -35,33 +35,6 @@ system.physmem.bw_write::total 759720678 # Wr
system.physmem.bw_total::cpu.inst 10563363260 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3122274945 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13685638205 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 230176372 # Transaction distribution
-system.membus.trans_dist::ReadResp 230176372 # Transaction distribution
-system.membus.trans_dist::WriteReq 20515731 # Transaction distribution
-system.membus.trans_dist::WriteResp 20515731 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::total 346988734 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::total 154395472 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 501384206 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::total 1387954936 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::total 410245943 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1798200879 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 250692103 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.692062 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.461641 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 77197736 30.79% 30.79% # Request fanout histogram
-system.membus.snoop_fanout::3 173494367 69.21% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
-system.membus.snoop_fanout::total 250692103 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 400 # Number of system calls
@@ -125,5 +98,30 @@ system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Cl
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 221363385 # Class of executed instruction
+system.membus.trans_dist::ReadReq 230176372 # Transaction distribution
+system.membus.trans_dist::ReadResp 230176372 # Transaction distribution
+system.membus.trans_dist::WriteReq 20515731 # Transaction distribution
+system.membus.trans_dist::WriteResp 20515731 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::total 346988734 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::total 154395472 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 501384206 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::total 1387954936 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::total 410245943 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1798200879 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 250692103 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.692062 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.461641 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 77197736 30.79% 30.79% # Request fanout histogram
+system.membus.snoop_fanout::1 173494367 69.21% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 250692103 # Request fanout histogram
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
index 0e62e6e73..af03b59c5 100644
--- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.250954 # Nu
sim_ticks 250953957500 # Number of ticks simulated
final_tick 250953957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 722726 # Simulator instruction rate (inst/s)
-host_op_rate 1211354 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1373280924 # Simulator tick rate (ticks/s)
-host_mem_usage 338728 # Number of bytes of host memory used
-host_seconds 182.74 # Real time elapsed on the host
+host_inst_rate 582427 # Simulator instruction rate (inst/s)
+host_op_rate 976201 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1106694320 # Simulator tick rate (ticks/s)
+host_mem_usage 282016 # Number of bytes of host memory used
+host_seconds 226.76 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221363385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -446,17 +446,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
system.cpu.toL2Bus.pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 6606 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 6606 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 6606 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 6606 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)