diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:36 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:36 -0400 |
| commit | b63631536d974f31cf99ee280271dc0f7b4c746f (patch) | |
| tree | ff83820d8dd75de8238e4b7ddaf3b91e4cf8374f /tests/quick/se | |
| parent | 646c4a23ca44aab5468c896034288151c89be782 (diff) | |
| download | gem5-b63631536d974f31cf99ee280271dc0f7b4c746f.tar.xz | |
stats: Cumulative stats update
This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.
The main reason for bundling them up is to minimise the changeset
size.
Diffstat (limited to 'tests/quick/se')
25 files changed, 2032 insertions, 2055 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 9728f1e09..dde2aed4b 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu sim_ticks 25046000 # Number of ticks simulated final_tick 25046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25238 # Simulator instruction rate (inst/s) -host_op_rate 25236 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 98905790 # Simulator tick rate (ticks/s) -host_mem_usage 225424 # Number of bytes of host memory used -host_seconds 0.25 # Real time elapsed on the host +host_inst_rate 22373 # Simulator instruction rate (inst/s) +host_op_rate 22372 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 87684145 # Simulator tick rate (ticks/s) +host_mem_usage 225308 # Number of bytes of host memory used +host_seconds 0.29 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 766589475 # In system.physmem.bw_total::cpu.inst 766589475 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 429290106 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1195879582 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 469 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 469 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 469 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 29952 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 29952 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis @@ -195,10 +196,10 @@ system.membus.trans_dist::ReadReq 396 # Tr system.membus.trans_dist::ReadResp 395 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 937 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 937 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29952 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 29952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 937 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 937 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29952 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 29952 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 559000 # Layer occupancy (ticks) @@ -307,15 +308,15 @@ system.cpu.stage3.utilization 2.663047 # Pe system.cpu.stage4.idleCycles 45635 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 8.899447 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 141.294375 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 141.294375 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.068991 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.068991 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 141.294375 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 141.294375 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.068991 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.068991 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits @@ -396,12 +397,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 397 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 603 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 336 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 939 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 19264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 10752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 30016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 939 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 30016 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 235000 # Layer occupancy (ticks) @@ -410,17 +411,17 @@ system.cpu.toL2Bus.respLayer0.occupancy 512750 # La system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 278750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 197.784355 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.343624 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.440731 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 197.784355 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.343624 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.440731 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001722 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006036 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006036 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -535,15 +536,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55479.235880 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.103023 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.103023 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025172 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025172 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 103.103023 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 103.103023 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025172 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025172 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 38483afa5..60f469d0d 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 20671000 # Number of ticks simulated final_tick 20671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25591 # Simulator instruction rate (inst/s) -host_op_rate 25589 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 83008053 # Simulator tick rate (ticks/s) -host_mem_usage 227468 # Number of bytes of host memory used -host_seconds 0.25 # Real time elapsed on the host +host_inst_rate 24570 # Simulator instruction rate (inst/s) +host_op_rate 24568 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79697022 # Simulator tick rate (ticks/s) +host_mem_usage 227340 # Number of bytes of host memory used +host_seconds 0.26 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 969087127 # In system.physmem.bw_total::cpu.inst 969087127 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 538725751 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1507812878 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 488 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 488 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 488 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 488 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 31168 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 69 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 34 # Track reads on a per bank basis @@ -194,10 +195,10 @@ system.membus.trans_dist::ReadReq 415 # Tr system.membus.trans_dist::ReadResp 414 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 975 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 975 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 31168 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 975 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 975 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 31168 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 619500 # Layer occupancy (ticks) @@ -511,12 +512,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 416 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 629 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 348 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 977 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 20096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 31232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 629 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 977 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 31232 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) @@ -525,15 +526,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 531250 # La system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 281250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 159.268512 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1898 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.044586 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 159.268512 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077768 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077768 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 159.268512 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1898 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.044586 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 159.268512 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077768 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077768 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1898 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1898 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1898 # number of demand (read+write) hits @@ -609,17 +610,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 67819.841270 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67819.841270 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 67819.841270 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 218.982908 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.353389 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 59.629519 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 218.982908 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.353389 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 59.629519 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004863 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001820 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006683 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006683 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -734,15 +735,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54395.700637 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62693.965517 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57354.508197 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 106.762654 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2236 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.850575 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 106.762654 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026065 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026065 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 106.762654 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2236 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.850575 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 106.762654 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026065 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026065 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1730 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1730 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index 2ce4c669d..6038d0a3c 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000033 # Nu sim_ticks 32544000 # Number of ticks simulated final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 19861 # Simulator instruction rate (inst/s) -host_op_rate 19860 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 101141711 # Simulator tick rate (ticks/s) -host_mem_usage 224276 # Number of bytes of host memory used -host_seconds 0.32 # Real time elapsed on the host +host_inst_rate 27670 # Simulator instruction rate (inst/s) +host_op_rate 27667 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 140894748 # Simulator tick rate (ticks/s) +host_mem_usage 224272 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory @@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 373 # Tr system.membus.trans_dist::ReadResp 373 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 892 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 892 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 28544 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) @@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 65088 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 127.998991 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.062500 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 127.998991 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062500 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits @@ -175,17 +175,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.497210 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 184.497210 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -300,15 +300,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.762109 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 103.762109 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits @@ -403,12 +403,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 374 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 558 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 336 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 894 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 10752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 28608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 28608 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 07e82d1ad..746096984 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu sim_ticks 11933500 # Number of ticks simulated final_tick 11933500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 492 # Simulator instruction rate (inst/s) -host_op_rate 492 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2461163 # Simulator tick rate (ticks/s) -host_mem_usage 226156 # Number of bytes of host memory used -host_seconds 4.85 # Real time elapsed on the host +host_inst_rate 64 # Simulator instruction rate (inst/s) +host_op_rate 64 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 321705 # Simulator tick rate (ticks/s) +host_mem_usage 226036 # Number of bytes of host memory used +host_seconds 37.09 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1008254075 # In system.physmem.bw_total::cpu.inst 1008254075 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 455859555 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1464113630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 273 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 273 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 273 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 273 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 17472 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 17472 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis @@ -190,10 +191,10 @@ system.membus.trans_dist::ReadReq 249 # Tr system.membus.trans_dist::ReadResp 249 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution system.membus.trans_dist::ReadExResp 24 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 546 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 546 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17472 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 17472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 546 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 546 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17472 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 17472 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 17472 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 344000 # Layer occupancy (ticks) @@ -507,12 +508,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 249 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 249 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 376 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 170 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 546 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 12032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 5440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 17472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 376 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 546 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 17472 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 17472 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 136500 # Layer occupancy (ticks) @@ -521,15 +522,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 318000 # La system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 135500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 91.523450 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 816 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.340426 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 91.523450 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.044689 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.044689 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 91.523450 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 816 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.340426 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 91.523450 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.044689 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.044689 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 816 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 816 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 816 # number of demand (read+write) hits @@ -605,17 +606,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 68062.494681 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68062.494681 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 68062.494681 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 119.912589 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 249 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 91.722261 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.190328 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 119.912589 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 249 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 91.722261 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.190328 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002799 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000860 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003659 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003659 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses @@ -724,15 +725,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54438.829787 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61447.058824 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56620.879121 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 44.879167 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 758 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.917647 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 44.879167 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.010957 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.010957 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 44.879167 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 758 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.917647 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 44.879167 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.010957 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.010957 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 545 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 545 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 034aea3e9..0eefef01d 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 16524000 # Number of ticks simulated final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 252355 # Simulator instruction rate (inst/s) -host_op_rate 251860 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1611932908 # Simulator tick rate (ticks/s) -host_mem_usage 223992 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 70 # Simulator instruction rate (inst/s) +host_op_rate 70 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 446596 # Simulator tick rate (ticks/s) +host_mem_usage 222964 # Number of bytes of host memory used +host_seconds 37.00 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory @@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 218 # Tr system.membus.trans_dist::ReadResp 218 # Transaction distribution system.membus.trans_dist::ReadExReq 27 # Transaction distribution system.membus.trans_dist::ReadExResp 27 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 490 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 490 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15680 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 15680 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 15680 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 245000 # Layer occupancy (ticks) @@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 33048 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 80.050296 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.039087 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 80.050296 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.039087 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits @@ -175,17 +175,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 107.162861 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.168669 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 26.994192 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 107.162861 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.168669 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 26.994192 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002447 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003270 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003270 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses @@ -294,15 +294,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 47.437790 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 47.437790 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits @@ -397,12 +397,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 218 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 326 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 164 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 490 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 10432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 5248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 15680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 326 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 164 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 490 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 15680 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 22dbcae6d..81f115ce9 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000016 # Nu sim_ticks 16494000 # Number of ticks simulated final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31208 # Simulator instruction rate (inst/s) -host_op_rate 38937 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 112083077 # Simulator tick rate (ticks/s) -host_mem_usage 244336 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 32065 # Simulator instruction rate (inst/s) +host_op_rate 40006 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 115159682 # Simulator tick rate (ticks/s) +host_mem_usage 240696 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1051533891 # In system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 393 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 393 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 393 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 393 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 25152 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis @@ -194,10 +195,10 @@ system.membus.trans_dist::ReadReq 352 # Tr system.membus.trans_dist::ReadResp 352 # Transaction distribution system.membus.trans_dist::ReadExReq 41 # Transaction distribution system.membus.trans_dist::ReadExResp 41 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 786 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 786 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 25152 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 25152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 786 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25152 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25152 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 25152 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks) @@ -563,12 +564,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 397 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 582 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 875 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 18624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 27968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 875 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) @@ -577,15 +578,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 485250 # La system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 4 # number of replacements +system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits @@ -661,17 +662,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 64263.745704 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits @@ -795,15 +796,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54591.328413 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 3ccfc050f..ace16d792 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000016 # Nu sim_ticks 16494000 # Number of ticks simulated final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66928 # Simulator instruction rate (inst/s) -host_op_rate 83502 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 240363471 # Simulator tick rate (ticks/s) -host_mem_usage 244336 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 36590 # Simulator instruction rate (inst/s) +host_op_rate 45651 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 131406771 # Simulator tick rate (ticks/s) +host_mem_usage 240696 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1051533891 # In system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 393 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 393 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 393 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 393 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 25152 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis @@ -194,10 +195,10 @@ system.membus.trans_dist::ReadReq 352 # Tr system.membus.trans_dist::ReadResp 352 # Transaction distribution system.membus.trans_dist::ReadExReq 41 # Transaction distribution system.membus.trans_dist::ReadExResp 41 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 786 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 786 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 25152 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 25152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 786 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25152 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25152 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 25152 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks) @@ -518,12 +519,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 397 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 582 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 875 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 18624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 27968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 875 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) @@ -532,15 +533,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 485250 # La system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 4 # number of replacements +system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits @@ -616,17 +617,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 64263.745704 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits @@ -750,15 +751,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54591.328413 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 7a58b161f..13e2763d6 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000026 # Nu sim_ticks 25969000 # Number of ticks simulated final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 220478 # Simulator instruction rate (inst/s) -host_op_rate 273604 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1251201624 # Simulator tick rate (ticks/s) -host_mem_usage 241012 # Number of bytes of host memory used +host_inst_rate 229244 # Simulator instruction rate (inst/s) +host_op_rate 284503 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1301168988 # Simulator tick rate (ticks/s) +host_mem_usage 238660 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5672 # Number of ops (including micro ops) simulated @@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 307 # Tr system.membus.trans_dist::ReadResp 307 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 700 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 22400 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 22400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 22400 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 350000 # Layer occupancy (ticks) @@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 51938 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 114.614391 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055964 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1 # number of replacements +system.cpu.icache.tags.tagsinuse 114.614391 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.055964 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits @@ -185,17 +185,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 50211.618257 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 154.071129 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.889758 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48.181371 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 154.071129 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.889758 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48.181371 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003231 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004702 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004702 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits @@ -313,15 +313,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 83.000387 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1940 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.758865 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020264 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 83.000387 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1940 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.758865 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020264 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits @@ -424,12 +424,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 339 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 482 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 282 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 764 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 24448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 482 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 764 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 24448 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index b2a150376..aeb0e2e25 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu sim_ticks 24587000 # Number of ticks simulated final_tick 24587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 41260 # Simulator instruction rate (inst/s) -host_op_rate 41253 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 174426700 # Simulator tick rate (ticks/s) -host_mem_usage 226212 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 52979 # Simulator instruction rate (inst/s) +host_op_rate 52966 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 223940501 # Simulator tick rate (ticks/s) +host_mem_usage 224928 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 825151503 # In system.physmem.bw_total::cpu.inst 825151503 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 359214219 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1184365722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 455 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 455 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 455 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 29120 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 29120 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 28 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis @@ -195,10 +196,10 @@ system.membus.trans_dist::ReadReq 404 # Tr system.membus.trans_dist::ReadResp 404 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution system.membus.trans_dist::ReadExResp 51 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 910 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 29120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 910 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29120 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 29120 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 29120 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 551500 # Layer occupancy (ticks) @@ -293,15 +294,15 @@ system.cpu.stage3.utilization 2.517539 # Pe system.cpu.stage4.idleCycles 46285 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 2890 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 5.876970 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 150.350232 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 150.350232 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073413 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073413 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 13 # number of replacements +system.cpu.icache.tags.tagsinuse 150.350232 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 150.350232 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073413 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073413 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits @@ -382,12 +383,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 406 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 638 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 914 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 20416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 29248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 638 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 914 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 29248 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 29248 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks) @@ -396,17 +397,17 @@ system.cpu.toL2Bus.respLayer0.occupancy 543000 # La system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 228000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 208.008874 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.043119 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 55.965756 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 208.008874 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.043119 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 55.965756 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004640 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001708 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006348 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006348 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -521,15 +522,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57861.198738 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62804.347826 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59360.439560 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 89.984709 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1638 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.869565 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 89.984709 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021969 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021969 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 89.984709 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1638 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.869565 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 89.984709 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021969 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021969 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1066 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1066 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 6a930873f..f0a85d261 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 21805500 # Number of ticks simulated final_tick 21805500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79844 # Simulator instruction rate (inst/s) -host_op_rate 79828 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 337538221 # Simulator tick rate (ticks/s) -host_mem_usage 228256 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 44396 # Simulator instruction rate (inst/s) +host_op_rate 44386 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 187676879 # Simulator tick rate (ticks/s) +host_mem_usage 228012 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 983238174 # In system.physmem.bw_total::cpu.inst 983238174 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 416775584 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1400013758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 477 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 477 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 477 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 477 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 30528 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 30528 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 30 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis @@ -194,10 +195,10 @@ system.membus.trans_dist::ReadReq 426 # Tr system.membus.trans_dist::ReadResp 426 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution system.membus.trans_dist::ReadExResp 51 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 954 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 954 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 30528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 954 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 954 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 30528 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) @@ -495,12 +496,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 429 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 676 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 284 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 960 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 21632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 30720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 676 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 960 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 30720 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 30720 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) @@ -509,15 +510,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 573500 # La system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 230000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 160.845390 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1531 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.529586 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 160.845390 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078538 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078538 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 17 # number of replacements +system.cpu.icache.tags.tagsinuse 160.845390 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1531 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.529586 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 160.845390 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078538 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1531 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1531 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1531 # number of demand (read+write) hits @@ -593,17 +594,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 70585.798817 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70585.798817 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 70585.798817 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 220.792115 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.133804 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.658310 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 220.792115 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.133804 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.658310 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004978 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006738 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006738 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -718,15 +719,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57459.701493 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64862.676056 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59663.522013 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.308892 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.308892 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022292 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022292 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 91.308892 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 91.308892 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022292 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022292 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index bfb8470a6..d3256ea4d 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000032 # Nu sim_ticks 31633000 # Number of ticks simulated final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 482351 # Simulator instruction rate (inst/s) -host_op_rate 481309 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2613274672 # Simulator tick rate (ticks/s) -host_mem_usage 225064 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 304637 # Simulator instruction rate (inst/s) +host_op_rate 304230 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1653175117 # Simulator tick rate (ticks/s) +host_mem_usage 224940 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory @@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 388 # Tr system.membus.trans_dist::ReadResp 388 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution system.membus.trans_dist::ReadExResp 51 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 878 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 878 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 28096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 878 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 28096 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 28096 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 439000 # Layer occupancy (ticks) @@ -83,15 +83,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 63266 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 132.545353 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 5513 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 303 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.194719 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 132.545353 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.064719 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.064719 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 13 # number of replacements +system.cpu.icache.tags.tagsinuse 132.545353 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 5513 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 303 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.194719 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 132.545353 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.064719 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.064719 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 5513 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5513 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5513 # number of demand (read+write) hits @@ -161,17 +161,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 188.114191 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 388 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.005155 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 133.890657 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 54.223533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 188.114191 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 388 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.005155 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 133.890657 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 54.223533 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004086 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001655 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -286,15 +286,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.492114 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1950 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.130435 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021360 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 87.492114 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1950 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.130435 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021360 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits @@ -389,12 +389,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 390 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 390 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 606 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 882 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 19392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 28224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 606 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 882 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 28224 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 28224 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 50311c18c..9bd3a3844 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000018 # Nu sim_ticks 18469500 # Number of ticks simulated final_tick 18469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54927 # Simulator instruction rate (inst/s) -host_op_rate 54916 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 175080000 # Simulator tick rate (ticks/s) -host_mem_usage 224296 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 100626 # Simulator instruction rate (inst/s) +host_op_rate 100602 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 320728752 # Simulator tick rate (ticks/s) +host_mem_usage 223260 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1195484447 # In system.physmem.bw_total::cpu.inst 1195484447 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 349982403 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1545466851 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 446 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 446 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 446 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 446 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 28544 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 28544 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis @@ -195,10 +196,10 @@ system.membus.trans_dist::ReadReq 399 # Tr system.membus.trans_dist::ReadResp 399 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution system.membus.trans_dist::ReadExResp 47 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 892 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 892 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 28544 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 565000 # Layer occupancy (ticks) @@ -493,12 +494,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 406 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 702 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 204 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 906 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 22464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 6528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 28992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 702 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 906 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 28992 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 28992 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) @@ -507,15 +508,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 590750 # La system.cpu.toL2Bus.respLayer0.utilization 3.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 163000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 167.253035 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1372 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.908832 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 167.253035 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.081667 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.081667 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 167.253035 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1372 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.908832 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 167.253035 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.081667 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.081667 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1372 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1372 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1372 # number of demand (read+write) hits @@ -591,17 +592,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 66831.196581 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66831.196581 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 66831.196581 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 197.401673 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 166.141608 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.260065 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 197.401673 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 166.141608 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.260065 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005070 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006024 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006024 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits @@ -719,15 +720,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54186.231884 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64608.910891 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56546.524664 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 63.117277 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2192 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 21.490196 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 63.117277 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.015409 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.015409 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 63.117277 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2192 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 21.490196 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 63.117277 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.015409 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.015409 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1473 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1473 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 719 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 6e991864c..68c96c714 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 20802500 # Number of ticks simulated final_tick 20802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 39959 # Simulator instruction rate (inst/s) -host_op_rate 39952 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 155990706 # Simulator tick rate (ticks/s) -host_mem_usage 232536 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 86492 # Simulator instruction rate (inst/s) +host_op_rate 86452 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 337526822 # Simulator tick rate (ticks/s) +host_mem_usage 231936 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 889123903 # In system.physmem.bw_total::cpu.inst 889123903 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 412258142 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1301382045 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 423 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 423 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 423 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 27072 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 27072 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 24 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 7 # Track reads on a per bank basis @@ -195,10 +196,10 @@ system.membus.trans_dist::ReadReq 342 # Tr system.membus.trans_dist::ReadResp 342 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution system.membus.trans_dist::ReadExResp 81 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 846 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 846 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 27072 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 27072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 846 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 846 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27072 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 27072 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 502000 # Layer occupancy (ticks) @@ -275,15 +276,15 @@ system.cpu.stage3.utilization 2.343412 # Pe system.cpu.stage4.idleCycles 38449 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 7.587848 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 142.145699 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 142.145699 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.069407 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.069407 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 142.145699 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 142.145699 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.069407 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.069407 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 892 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 892 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 892 # number of demand (read+write) hits @@ -364,12 +365,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 345 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 582 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 270 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 852 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 18624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 27264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 27264 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 27264 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) @@ -378,17 +379,17 @@ system.cpu.toL2Bus.respLayer0.occupancy 489750 # La system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 219500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 168.511029 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.570095 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 26.940934 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 168.511029 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.570095 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 26.940934 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004320 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000822 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005143 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005143 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -506,15 +507,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58848.615917 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59138.059701 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58940.307329 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.821490 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.821490 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020708 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020708 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 84.821490 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 84.821490 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020708 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020708 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index c4b2117ab..b76f909df 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000028 # Nu sim_ticks 27800000 # Number of ticks simulated final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 413138 # Simulator instruction rate (inst/s) -host_op_rate 412367 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2148212772 # Simulator tick rate (ticks/s) -host_mem_usage 231400 # Number of bytes of host memory used +host_inst_rate 441877 # Simulator instruction rate (inst/s) +host_op_rate 441389 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2300957264 # Simulator tick rate (ticks/s) +host_mem_usage 230904 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated @@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 308 # Tr system.membus.trans_dist::ReadResp 308 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution system.membus.trans_dist::ReadExResp 81 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 778 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 778 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 24896 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 24896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 24896 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 389000 # Layer occupancy (ticks) @@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 55600 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 117.043638 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057150 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 117.043638 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057150 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits @@ -143,17 +143,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 142.183999 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 142.183999 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004339 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004339 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -271,15 +271,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.118455 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020048 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 82.118455 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020048 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits @@ -374,12 +374,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 311 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 514 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 270 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 784 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 16448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 25088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 25088 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 7c9257554..cfacb8ad4 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 19639500 # Number of ticks simulated final_tick 19639500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 28578 # Simulator instruction rate (inst/s) -host_op_rate 51768 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 104294046 # Simulator tick rate (ticks/s) -host_mem_usage 245432 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 30549 # Simulator instruction rate (inst/s) +host_op_rate 55338 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 111488682 # Simulator tick rate (ticks/s) +host_mem_usage 243516 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17536 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 892894422 # In system.physmem.bw_total::cpu.inst 892894422 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 462740905 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1355635327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 417 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 417 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 417 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 417 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 26624 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 26624 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 34 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis @@ -195,11 +196,9 @@ system.membus.trans_dist::ReadExReq 77 # Tr system.membus.trans_dist::ReadExResp 77 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 833 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 26624 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) @@ -478,12 +477,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 342 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 341 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 550 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 287 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 837 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 26752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 550 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 837 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 209500 # Layer occupancy (ticks) @@ -492,15 +491,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 463250 # La system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 239750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 130.740950 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1608 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 275 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.847273 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.740950 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063838 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063838 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 130.740950 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1608 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 275 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.847273 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 130.740950 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063838 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063838 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1608 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1608 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1608 # number of demand (read+write) hits @@ -576,17 +575,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 69288.181818 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69288.181818 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 69288.181818 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 163.561658 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 339 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.005900 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.812999 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32.748659 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 163.561658 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 339 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.005900 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.812999 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 32.748659 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003992 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000999 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004992 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004992 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits @@ -704,15 +703,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55924.270073 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61298.951049 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57767.386091 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.722336 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2341 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.370629 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.722336 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020196 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020196 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 82.722336 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2341 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.370629 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 82.722336 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020196 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020196 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1483 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1483 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index f38f31bd7..0aa71b968 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 28358000 # Number of ticks simulated final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90736 # Simulator instruction rate (inst/s) -host_op_rate 164316 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 477859669 # Simulator tick rate (ticks/s) -host_mem_usage 289160 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 186481 # Simulator instruction rate (inst/s) +host_op_rate 337520 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 981039317 # Simulator tick rate (ticks/s) +host_mem_usage 241472 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory @@ -34,11 +34,9 @@ system.membus.trans_dist::ReadExReq 79 # Tr system.membus.trans_dist::ReadExResp 79 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 722 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 23104 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) @@ -69,15 +67,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 56716 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 6637 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 29.109649 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.051538 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 6637 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 29.109649 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.051538 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits @@ -147,17 +145,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 134.034140 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 134.034140 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -272,15 +270,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 80.797237 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019726 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 80.797237 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.019726 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits @@ -375,12 +373,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 283 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 456 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 268 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 724 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 14592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 23168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 23168 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 099eda912..d195e9d48 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu sim_ticks 24404000 # Number of ticks simulated final_tick 24404000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52847 # Simulator instruction rate (inst/s) -host_op_rate 52845 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 101181200 # Simulator tick rate (ticks/s) -host_mem_usage 228064 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host +host_inst_rate 780 # Simulator instruction rate (inst/s) +host_op_rate 780 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1494307 # Simulator tick rate (ticks/s) +host_mem_usage 227936 # Number of bytes of host memory used +host_seconds 16.33 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1636453040 # In system.physmem.bw_total::cpu.inst 1636453040 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 917882314 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2554335355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 974 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 974 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 974 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 974 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 62336 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 62336 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 83 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 153 # Track reads on a per bank basis @@ -205,10 +206,10 @@ system.membus.trans_dist::ReadReq 828 # Tr system.membus.trans_dist::ReadResp 828 # Transaction distribution system.membus.trans_dist::ReadExReq 146 # Transaction distribution system.membus.trans_dist::ReadExResp 146 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 1948 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 1948 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 62336 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 62336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1948 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1948 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62336 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 62336 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 62336 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 1227000 # Layer occupancy (ticks) @@ -452,41 +453,7 @@ system.cpu.iq.FU_type_1::MemWrite 1105 10.23% 100.00% # Ty system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::total 10798 # Type of FU issued -system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type::IntAlu 14327 65.73% 65.75% # Type of FU issued -system.cpu.iq.FU_type::IntMult 2 0.01% 65.76% # Type of FU issued -system.cpu.iq.FU_type::IntDiv 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::FloatAdd 4 0.02% 65.78% # Type of FU issued -system.cpu.iq.FU_type::FloatCmp 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::FloatCvt 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::FloatMult 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::FloatDiv 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::FloatSqrt 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdAdd 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdAlu 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdCmp 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdCvt 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdMisc 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdMult 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdShift 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdSqrt 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::MemRead 5217 23.94% 89.71% # Type of FU issued -system.cpu.iq.FU_type::MemWrite 2242 10.29% 100.00% # Type of FU issued -system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::total 21796 # Type of FU issued +system.cpu.iq.FU_type::total 21796 0.00% 0.00% # Type of FU issued system.cpu.iq.rate 0.446557 # Inst issue rate system.cpu.iq.fu_busy_cnt::0 89 # FU busy when requested system.cpu.iq.fu_busy_cnt::1 86 # FU busy when requested @@ -662,12 +629,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 830 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 830 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1252 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 700 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 1952 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 40064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 22400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 62464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1952 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 62464 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 62464 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 488000 # Layer occupancy (ticks) @@ -676,17 +643,17 @@ system.cpu.toL2Bus.respLayer0.occupancy 1029500 # La system.cpu.toL2Bus.respLayer0.utilization 4.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 566500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) -system.cpu.icache.tags.replacements::0 6 # number of replacements -system.cpu.icache.tags.replacements::1 0 # number of replacements -system.cpu.icache.tags.replacements::total 6 # number of replacements -system.cpu.icache.tags.tagsinuse 309.632563 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4375 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 626 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.988818 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 309.632563 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.151188 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.151188 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements::0 6 # number of replacements +system.cpu.icache.tags.replacements::1 0 # number of replacements +system.cpu.icache.tags.replacements::total 6 # number of replacements +system.cpu.icache.tags.tagsinuse 309.632563 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4375 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 626 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.988818 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 309.632563 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.151188 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.151188 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 4375 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4375 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4375 # number of demand (read+write) hits @@ -762,19 +729,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 75077.070288 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75077.070288 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 75077.070288 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements::0 0 # number of replacements -system.cpu.l2cache.tags.replacements::1 0 # number of replacements -system.cpu.l2cache.tags.replacements::total 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 428.856997 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 828 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 310.126222 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 118.730775 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements::0 0 # number of replacements +system.cpu.l2cache.tags.replacements::1 0 # number of replacements +system.cpu.l2cache.tags.replacements::total 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 428.856997 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 828 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 310.126222 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 118.730775 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009464 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.003623 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.013088 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.013088 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -889,17 +856,17 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61815.705128 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64037.987680 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements::0 0 # number of replacements -system.cpu.dcache.tags.replacements::1 0 # number of replacements -system.cpu.dcache.tags.replacements::total 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 211.884963 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4493 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 350 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.837143 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 211.884963 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.051730 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.051730 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements::0 0 # number of replacements +system.cpu.dcache.tags.replacements::1 0 # number of replacements +system.cpu.dcache.tags.replacements::total 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 211.884963 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4493 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 350 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.837143 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 211.884963 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.051730 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.051730 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 3469 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 3469 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1024 # number of WriteReq hits diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 60e6f3a9f..0c812fe4f 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000027 # Nu sim_ticks 27282000 # Number of ticks simulated final_tick 27282000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50184 # Simulator instruction rate (inst/s) -host_op_rate 50180 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90285398 # Simulator tick rate (ticks/s) -host_mem_usage 232468 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host +host_inst_rate 96636 # Simulator instruction rate (inst/s) +host_op_rate 96628 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 173854426 # Simulator tick rate (ticks/s) +host_mem_usage 231852 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 699068983 # In system.physmem.bw_total::cpu.inst 699068983 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 323729932 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1022798915 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 436 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 436 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 436 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 27904 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 27904 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 97 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 28 # Track reads on a per bank basis @@ -195,10 +196,10 @@ system.membus.trans_dist::ReadReq 351 # Tr system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 85 # Transaction distribution system.membus.trans_dist::ReadExResp 85 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 871 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 871 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 27840 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 27840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 871 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 871 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27840 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 27840 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 27840 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 519000 # Layer occupancy (ticks) @@ -275,15 +276,15 @@ system.cpu.stage3.utilization 5.274443 # Pe system.cpu.stage4.idleCycles 45256 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 17.060387 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 168.400745 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.046823 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 168.400745 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082227 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082227 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 168.400745 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.046823 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 168.400745 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082227 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082227 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits @@ -364,12 +365,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 354 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 600 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 876 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 19136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 27968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 600 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 876 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) @@ -378,17 +379,17 @@ system.cpu.toL2Bus.respLayer0.occupancy 507000 # La system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 223250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 199.371038 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.005714 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.740493 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.630545 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 199.371038 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.005714 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.740493 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.630545 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005119 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006084 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006084 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -503,15 +504,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53302.675585 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57367.753623 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54586.384439 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.106033 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.106033 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.023952 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.023952 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 98.106033 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 98.106033 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.023952 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.023952 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 5128d5dc2..46cdc1496 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000027 # Nu sim_ticks 26524500 # Number of ticks simulated final_tick 26524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52714 # Simulator instruction rate (inst/s) -host_op_rate 52709 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 96835127 # Simulator tick rate (ticks/s) -host_mem_usage 234512 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host +host_inst_rate 95044 # Simulator instruction rate (inst/s) +host_op_rate 95035 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 174603061 # Simulator tick rate (ticks/s) +host_mem_usage 232868 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 808309299 # In system.physmem.bw_total::cpu.inst 808309299 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 354690946 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1163000245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 482 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 482 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 482 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 482 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 30848 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 30848 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 102 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis @@ -194,10 +195,10 @@ system.membus.trans_dist::ReadReq 399 # Tr system.membus.trans_dist::ReadResp 399 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution system.membus.trans_dist::ReadExResp 83 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 964 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 964 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30848 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 30848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 964 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 964 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30848 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 30848 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) @@ -472,12 +473,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 401 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 674 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 968 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 21568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 30976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 674 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 968 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 30976 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 30976 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks) @@ -486,15 +487,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 570000 # La system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 235750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 187.665560 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4873 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 14.459941 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 187.665560 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.091634 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.091634 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 187.665560 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4873 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 14.459941 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 187.665560 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.091634 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.091634 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 4873 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4873 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4873 # number of demand (read+write) hits @@ -570,17 +571,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 66274.480712 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 221.542392 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.054257 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 34.488135 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 221.542392 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.054257 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 34.488135 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005708 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001052 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006761 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006761 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -695,15 +696,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52991.044776 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.809715 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.809715 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024123 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024123 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 98.809715 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 98.809715 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024123 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024123 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index ac8c29d55..45bd7d946 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000041 # Nu sim_ticks 41368000 # Number of ticks simulated final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 479032 # Simulator instruction rate (inst/s) -host_op_rate 478642 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1304958787 # Simulator tick rate (ticks/s) -host_mem_usage 231320 # Number of bytes of host memory used +host_inst_rate 554996 # Simulator instruction rate (inst/s) +host_op_rate 554737 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1512828488 # Simulator tick rate (ticks/s) +host_mem_usage 230824 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated @@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 331 # Tr system.membus.trans_dist::ReadResp 331 # Transaction distribution system.membus.trans_dist::ReadExReq 85 # Transaction distribution system.membus.trans_dist::ReadExResp 85 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 832 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 832 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 26624 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 416000 # Layer occupancy (ticks) @@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 82736 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 153.782734 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.075089 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 153.782734 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.075089 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits @@ -143,17 +143,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52700 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.632038 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 184.632038 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005635 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005635 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -268,15 +268,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 97.994344 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 97.994344 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits @@ -375,12 +375,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 333 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 560 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 836 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 26752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index aa46bcce7..53e641a1b 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000111 # Nu sim_ticks 110804500 # Number of ticks simulated final_tick 110804500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110530 # Simulator instruction rate (inst/s) -host_op_rate 110530 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11745373 # Simulator tick rate (ticks/s) -host_mem_usage 249508 # Number of bytes of host memory used -host_seconds 9.43 # Real time elapsed on the host +host_inst_rate 170931 # Simulator instruction rate (inst/s) +host_op_rate 170931 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18163832 # Simulator tick rate (ticks/s) +host_mem_usage 247816 # Number of bytes of host memory used +host_seconds 6.10 # Real time elapsed on the host sim_insts 1042724 # Number of instructions simulated sim_ops 1042724 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory @@ -57,14 +57,15 @@ system.physmem.bw_total::cpu2.data 11551877 # To system.physmem.bw_total::cpu3.inst 3465563 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3.data 7508720 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 380634361 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 660 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 736 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 660 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 660 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 42176 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 42176 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 76 # Reqs where no action is needed system.physmem.perBankRdReqs::0 115 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis @@ -229,16 +230,421 @@ system.membus.trans_dist::UpgradeReq 287 # Tr system.membus.trans_dist::UpgradeResp 76 # Transaction distribution system.membus.trans_dist::ReadExReq 163 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side 1714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 1714 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side 42176 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 42176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 42176 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 929000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) system.membus.respLayer1.occupancy 6308925 # Layer occupancy (ticks) system.membus.respLayer1.utilization 5.7 # Layer utilization (%) +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 416.979851 # Cycle average of tags in use +system.l2c.tags.total_refs 1443 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 0.800256 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 284.888559 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.382327 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 7.813679 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 0.733163 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 55.504569 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 5.417548 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 2.743977 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.695773 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004347 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000119 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000847 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.006363 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 421 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1443 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits +system.l2c.Writeback_hits::total 1 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits +system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 421 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits +system.l2c.demand_hits::total 1443 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 229 # number of overall hits +system.l2c.overall_hits::cpu0.data 5 # number of overall hits +system.l2c.overall_hits::cpu1.inst 412 # number of overall hits +system.l2c.overall_hits::cpu1.data 11 # number of overall hits +system.l2c.overall_hits::cpu2.inst 349 # number of overall hits +system.l2c.overall_hits::cpu2.data 5 # number of overall hits +system.l2c.overall_hits::cpu3.inst 421 # number of overall hits +system.l2c.overall_hits::cpu3.data 11 # number of overall hits +system.l2c.overall_hits::total 1443 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 16 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 76 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses +system.l2c.ReadReq_misses::total 543 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 18 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 359 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 16 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 76 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses +system.l2c.demand_misses::total 674 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 359 # number of overall misses +system.l2c.overall_misses::cpu0.data 168 # number of overall misses +system.l2c.overall_misses::cpu1.inst 16 # number of overall misses +system.l2c.overall_misses::cpu1.data 13 # number of overall misses +system.l2c.overall_misses::cpu2.inst 76 # number of overall misses +system.l2c.overall_misses::cpu2.data 20 # number of overall misses +system.l2c.overall_misses::cpu3.inst 9 # number of overall misses +system.l2c.overall_misses::cpu3.data 13 # number of overall misses +system.l2c.overall_misses::total 674 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 24362500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 5673000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 1205500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 88750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 5263750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 523750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 570250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.data 88750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 37776250 # number of ReadReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 7324500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 823750 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1067249 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 882250 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10097749 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 24362500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 12997500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 1205500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 912500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 5263750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1590999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 570250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 971000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 47873999 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 24362500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 12997500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 1205500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 912500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 5263750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1590999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 570250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 971000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 47873999 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 428 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 425 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 430 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1986 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 588 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 428 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 425 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 430 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2117 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 588 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 428 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 24 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 425 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 430 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2117 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.610544 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.037383 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.083333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.178824 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.583333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.020930 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.273414 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.962025 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.610544 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.037383 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.541667 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.178824 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.800000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.020930 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.318375 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.610544 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.037383 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.178824 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.020930 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.318375 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 67862.116992 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 76662.162162 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75343.750000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 88750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 69259.868421 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 74821.428571 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 63361.111111 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.data 88750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 69569.521179 # average ReadReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 77920.212766 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68645.833333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82096.076923 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 73520.833333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 77082.053435 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 67862.116992 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 77366.071429 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 75343.750000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 70192.307692 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 69259.868421 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 79549.950000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 63361.111111 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 74692.307692 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 71029.672107 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 67862.116992 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 77366.071429 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 75343.750000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 70192.307692 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 69259.868421 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 79549.950000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 63361.111111 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 74692.307692 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 71029.672107 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.inst 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3.inst 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 14 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.inst 357 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 10 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 73 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.inst 6 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 529 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 22 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 16 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 18 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 76 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 13 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 357 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 10 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 73 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.inst 6 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 660 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 357 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 10 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 73 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.inst 6 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 660 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 19789750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4760500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 695750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 76250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4180000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 436250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 327500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.data 76250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 30342250 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 220022 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 177515 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 180018 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 200020 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 777575 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6148500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 672250 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 907249 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 731250 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8459249 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 19789750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 10909000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 695750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 748500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 4180000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 1343499 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 327500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 807500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 38801499 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 19789750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 10909000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 695750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 748500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 4180000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1343499 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 327500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 807500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 38801499 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.266365 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.962025 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.311762 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.311762 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64331.081081 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69575 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 57357.750473 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 11094.687500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10231.250000 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65409.574468 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56020.833333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69788.384615 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 60937.500000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 64574.419847 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.toL2Bus.throughput 1691772446 # Throughput (bytes/s) system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution @@ -247,24 +653,24 @@ system.toL2Bus.trans_dist::UpgradeReq 290 # Tr system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 393 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 393 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1175 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 586 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 856 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 365 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 850 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 371 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 860 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 352 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 5415 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 37568 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 27392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 27200 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 27520 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 135488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1175 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 586 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 850 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 371 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 860 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5415 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 37568 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 27392 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27200 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27520 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 135488 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 135488 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 51968 # Total snoop data (bytes) system.toL2Bus.reqLayer0.occupancy 1623982 # Layer occupancy (ticks) @@ -548,15 +954,15 @@ system.cpu0.int_regfile_writes 325227 # nu system.cpu0.fp_regfile_reads 192 # number of floating regfile reads system.cpu0.misc_regfile_reads 234817 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.tags.replacements 297 # number of replacements -system.cpu0.icache.tags.tagsinuse 241.148232 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.replacements 297 # number of replacements +system.cpu0.icache.tags.tagsinuse 241.148232 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.148232 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470993 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.470993 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.470993 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 5079 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 5079 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 5079 # number of demand (read+write) hits @@ -632,15 +1038,15 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 46343.965986 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 141.869283 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 155614 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 915.376471 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.replacements 2 # number of replacements +system.cpu0.dcache.tags.tagsinuse 141.869283 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 155614 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 915.376471 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.869283 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277088 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.277088 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.277088 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 78995 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 78995 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 76703 # number of WriteReq hits @@ -1025,15 +1431,15 @@ system.cpu1.int_regfile_writes 148477 # nu system.cpu1.fp_regfile_writes 64 # number of floating regfile writes system.cpu1.misc_regfile_reads 87269 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes -system.cpu1.icache.tags.replacements 318 # number of replacements -system.cpu1.icache.tags.tagsinuse 79.958659 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 25178 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 58.827103 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.replacements 318 # number of replacements +system.cpu1.icache.tags.tagsinuse 79.958659 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 25178 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 58.827103 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 79.958659 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.156169 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.156169 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.156169 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 25178 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 25178 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 25178 # number of demand (read+write) hits @@ -1109,15 +1515,15 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::total 13478.985981 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 24.742100 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 31558 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1088.206897 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 24.742100 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 31558 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1088.206897 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.742100 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.048324 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.048324 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.048324 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 37722 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 37722 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 25226 # number of WriteReq hits @@ -1500,15 +1906,15 @@ system.cpu2.int_regfile_writes 188531 # nu system.cpu2.fp_regfile_writes 64 # number of floating regfile writes system.cpu2.misc_regfile_reads 116514 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes -system.cpu2.icache.tags.replacements 317 # number of replacements -system.cpu2.icache.tags.tagsinuse 82.351710 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 19274 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 45.350588 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.replacements 317 # number of replacements +system.cpu2.icache.tags.tagsinuse 82.351710 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 19274 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 45.350588 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.351710 # Average occupied blocks per requestor system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160843 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.160843 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.160843 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 19274 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 19274 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 19274 # number of demand (read+write) hits @@ -1584,15 +1990,15 @@ system.cpu2.icache.demand_avg_mshr_miss_latency::total 21651.185882 system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::total 21651.185882 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 26.191522 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 42135 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1504.821429 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.replacements 0 # number of replacements +system.cpu2.dcache.tags.tagsinuse 26.191522 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 42135 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1504.821429 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.191522 # Average occupied blocks per requestor system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051155 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.051155 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.051155 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 45549 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 45549 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 35887 # number of WriteReq hits @@ -1975,15 +2381,15 @@ system.cpu3.int_regfile_writes 211087 # nu system.cpu3.fp_regfile_writes 64 # number of floating regfile writes system.cpu3.misc_regfile_reads 133368 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes -system.cpu3.icache.tags.replacements 319 # number of replacements -system.cpu3.icache.tags.tagsinuse 77.348761 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 17724 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 41.218605 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.replacements 319 # number of replacements +system.cpu3.icache.tags.tagsinuse 77.348761 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 17724 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 41.218605 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.348761 # Average occupied blocks per requestor system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151072 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.151072 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.151072 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 17724 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 17724 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 17724 # number of demand (read+write) hits @@ -2059,15 +2465,15 @@ system.cpu3.icache.demand_avg_mshr_miss_latency::total 12138.965116 system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 23.659946 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 47957 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1712.750000 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 23.659946 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 47957 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1712.750000 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.659946 # Average occupied blocks per requestor system.cpu3.dcache.tags.occ_percent::cpu3.data 0.046211 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.046211 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.046211 # Average percentage of cache occupancy system.cpu3.dcache.ReadReq_hits::cpu3.data 50723 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 50723 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 41752 # number of WriteReq hits @@ -2185,410 +2591,5 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9050.591440 system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 416.979851 # Cycle average of tags in use -system.l2c.tags.total_refs 1443 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.800256 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 284.888559 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.382327 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 7.813679 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.733163 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 55.504569 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 5.417548 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2.743977 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.695773 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004347 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000119 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000847 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.006363 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 421 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1443 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits -system.l2c.Writeback_hits::total 1 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 421 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 1443 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 229 # number of overall hits -system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 412 # number of overall hits -system.l2c.overall_hits::cpu1.data 11 # number of overall hits -system.l2c.overall_hits::cpu2.inst 349 # number of overall hits -system.l2c.overall_hits::cpu2.data 5 # number of overall hits -system.l2c.overall_hits::cpu3.inst 421 # number of overall hits -system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 1443 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 16 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 76 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 543 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 359 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 16 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 76 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::total 674 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 359 # number of overall misses -system.l2c.overall_misses::cpu0.data 168 # number of overall misses -system.l2c.overall_misses::cpu1.inst 16 # number of overall misses -system.l2c.overall_misses::cpu1.data 13 # number of overall misses -system.l2c.overall_misses::cpu2.inst 76 # number of overall misses -system.l2c.overall_misses::cpu2.data 20 # number of overall misses -system.l2c.overall_misses::cpu3.inst 9 # number of overall misses -system.l2c.overall_misses::cpu3.data 13 # number of overall misses -system.l2c.overall_misses::total 674 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 24362500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 5673000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 1205500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 88750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 5263750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 523750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 570250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.data 88750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 37776250 # number of ReadReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7324500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 823750 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1067249 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 882250 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10097749 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 24362500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 12997500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 1205500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 912500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 5263750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1590999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 570250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 971000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 47873999 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 24362500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 12997500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 1205500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 912500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 5263750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1590999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 570250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 971000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 47873999 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 428 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 425 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 430 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1986 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 588 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 428 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 425 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 430 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2117 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 588 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 428 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 425 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 430 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2117 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.610544 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.037383 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.178824 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.583333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.020930 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.273414 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.962025 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.610544 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.037383 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.178824 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.800000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.020930 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.318375 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.610544 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.037383 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.178824 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.020930 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.318375 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 67862.116992 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 76662.162162 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75343.750000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 88750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 69259.868421 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 74821.428571 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 63361.111111 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.data 88750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 69569.521179 # average ReadReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 77920.212766 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68645.833333 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82096.076923 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 73520.833333 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 77082.053435 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 67862.116992 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 77366.071429 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 75343.750000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 70192.307692 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 69259.868421 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 79549.950000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 63361.111111 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 74692.307692 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 71029.672107 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 67862.116992 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 77366.071429 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 75343.750000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 70192.307692 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 69259.868421 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 79549.950000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 63361.111111 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 74692.307692 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 71029.672107 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.inst 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3.inst 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 14 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 357 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 10 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 73 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.inst 6 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 529 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 22 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 16 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 18 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 76 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 13 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 357 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 10 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 73 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.inst 6 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 660 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 357 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 10 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 73 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.inst 6 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 660 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 19789750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4760500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 695750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4180000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 436250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 327500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.data 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 30342250 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 220022 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 177515 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 180018 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 200020 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 777575 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6148500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 672250 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 907249 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 731250 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8459249 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 19789750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 10909000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 695750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 748500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 4180000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 1343499 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 327500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 807500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 38801499 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 19789750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 10909000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 695750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 748500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 4180000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 1343499 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 327500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 807500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 38801499 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.266365 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.962025 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.311762 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.311762 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64331.081081 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69575 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 57357.750473 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 11094.687500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10231.250000 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65409.574468 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56020.833333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69788.384615 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 60937.500000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 64574.419847 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 4a2827ac8..8ba84a629 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000263 # Nu sim_ticks 262794500 # Number of ticks simulated final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 146225 # Simulator instruction rate (inst/s) -host_op_rate 146224 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57909206 # Simulator tick rate (ticks/s) -host_mem_usage 244388 # Number of bytes of host memory used -host_seconds 4.54 # Real time elapsed on the host +host_inst_rate 681070 # Simulator instruction rate (inst/s) +host_op_rate 681053 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 269712940 # Simulator tick rate (ticks/s) +host_mem_usage 243700 # Number of bytes of host memory used +host_seconds 0.97 # Real time elapsed on the host sim_insts 663567 # Number of instructions simulated sim_ops 663567 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory @@ -64,16 +64,424 @@ system.membus.trans_dist::UpgradeReq 272 # Tr system.membus.trans_dist::UpgradeResp 77 # Transaction distribution system.membus.trans_dist::ReadExReq 208 # Transaction distribution system.membus.trans_dist::ReadExResp 142 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side 1559 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 1559 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side 36608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 36608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 36608 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 852296 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) system.membus.respLayer1.occupancy 5420500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.1 # Layer utilization (%) +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 349.046072 # Cycle average of tags in use +system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 0.889005 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 231.790437 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 54.207948 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 51.556673 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 6.123914 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1.773020 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.843760 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 1.030292 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.831024 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.003537 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.005326 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits +system.l2c.Writeback_hits::total 1 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits +system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 354 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::total 1220 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 182 # number of overall hits +system.l2c.overall_hits::cpu0.data 5 # number of overall hits +system.l2c.overall_hits::cpu1.inst 300 # number of overall hits +system.l2c.overall_hits::cpu1.data 3 # number of overall hits +system.l2c.overall_hits::cpu2.inst 354 # number of overall hits +system.l2c.overall_hits::cpu2.data 9 # number of overall hits +system.l2c.overall_hits::cpu3.inst 358 # number of overall hits +system.l2c.overall_hits::cpu3.data 9 # number of overall hits +system.l2c.overall_hits::total 1220 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 8 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses +system.l2c.ReadReq_misses::total 450 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 66 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 23 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 16 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses +system.l2c.demand_misses::total 592 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 285 # number of overall misses +system.l2c.overall_misses::cpu0.data 165 # number of overall misses +system.l2c.overall_misses::cpu1.inst 66 # number of overall misses +system.l2c.overall_misses::cpu1.data 23 # number of overall misses +system.l2c.overall_misses::cpu2.inst 12 # number of overall misses +system.l2c.overall_misses::cpu2.data 16 # number of overall misses +system.l2c.overall_misses::cpu3.inst 9 # number of overall misses +system.l2c.overall_misses::cpu3.data 16 # number of overall misses +system.l2c.overall_misses::total 592 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 14927000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 3451500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 3436500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 418500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 597500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 103500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 465000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.data 104500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 23504000 # number of ReadReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5174000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 801000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 747000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 730000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7452000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 14927000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 8625500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 3436500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1219500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 597500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 850500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 465000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 834500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 30956000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 14927000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 8625500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 3436500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1219500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 597500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 850500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 465000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 834500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 30956000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.727273 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.032787 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.181818 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.269461 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.974684 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.884615 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.032787 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.326711 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52375.438596 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52068.181818 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52312.500000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49791.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 51750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 51666.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.data 52250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52231.111111 # average ReadReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52262.626263 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53400 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53357.142857 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52142.857143 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52478.873239 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52068.181818 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 53021.739130 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 49791.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 53156.250000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52290.540541 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52068.181818 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 53021.739130 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 49791.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 53156.250000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52290.540541 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.inst 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.data 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3.inst 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.data 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.data 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.inst 285 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 66 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 59 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.inst 8 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.data 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 15 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 15 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 15 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 14 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 59 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 22 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 15 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.inst 8 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.data 16 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 59 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 22 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 15 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.inst 8 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.data 16 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11414500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 2640000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2368500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 280000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 80000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 40000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 320000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.data 80000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 17223000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 600499 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 763992 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 3084491 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3964000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 577500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5719000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 11414500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 6604000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 2368500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 897500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 80000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 617500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 320000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 640000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 22942000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 11414500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 6604000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 2368500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 897500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 80000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 617500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 320000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 640000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 22942000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090909 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.181818 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.974684 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40053.488372 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40033.266667 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41166.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41250 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40274.647887 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.toL2Bus.throughput 646588875 # Throughput (bytes/s) system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution @@ -82,24 +490,24 @@ system.toL2Bus.trans_dist::UpgradeReq 274 # Tr system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 934 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 580 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 355 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 352 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 734 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 401 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 4820 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 29888 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 10944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 23424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 23424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 23488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 116032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 355 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 734 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 401 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4820 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 116032 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 53888 # Total snoop data (bytes) system.toL2Bus.reqLayer0.occupancy 1473490 # Layer occupancy (ticks) @@ -143,15 +551,15 @@ system.cpu0.num_idle_cycles 0 # Nu system.cpu0.num_busy_cycles 525589 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 212.401822 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 158170 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 338.693790 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.replacements 215 # number of replacements +system.cpu0.icache.tags.tagsinuse 212.401822 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 158170 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 338.693790 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.401822 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.414847 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.414847 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 158170 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 158170 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 158170 # number of demand (read+write) hits @@ -221,15 +629,15 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 36860.813704 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 145.571924 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 73489 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 440.053892 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.replacements 2 # number of replacements +system.cpu0.dcache.tags.tagsinuse 145.571924 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 73489 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 440.053892 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.571924 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.284320 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.284320 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 48827 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 48827 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 24780 # number of WriteReq hits @@ -363,15 +771,15 @@ system.cpu1.num_idle_cycles 69347.869793 # Nu system.cpu1.num_busy_cycles 456240.130207 # Number of busy cycles system.cpu1.not_idle_fraction 0.868057 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.131943 # Percentage of idle cycles -system.cpu1.icache.tags.replacements 280 # number of replacements -system.cpu1.icache.tags.tagsinuse 70.017506 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.replacements 280 # number of replacements +system.cpu1.icache.tags.tagsinuse 70.017506 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017506 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 163138 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 163138 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 163138 # number of demand (read+write) hits @@ -441,15 +849,15 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::total 18601.125683 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 18601.125683 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 27.720196 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 35348 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1178.266667 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 27.720196 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 35348 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1178.266667 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720196 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.054141 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.054141 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.054141 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 41378 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 41378 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 16307 # number of WriteReq hits @@ -581,15 +989,15 @@ system.cpu2.num_idle_cycles 69604.869303 # Nu system.cpu2.num_busy_cycles 455983.130697 # Number of busy cycles system.cpu2.not_idle_fraction 0.867568 # Percentage of non-idle cycles system.cpu2.idle_fraction 0.132432 # Percentage of idle cycles -system.cpu2.icache.tags.replacements 280 # number of replacements -system.cpu2.icache.tags.tagsinuse 67.624969 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.replacements 280 # number of replacements +system.cpu2.icache.tags.tagsinuse 67.624969 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624969 # Average occupied blocks per requestor system.cpu2.icache.tags.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 164533 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 164533 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 164533 # number of demand (read+write) hits @@ -659,15 +1067,15 @@ system.cpu2.icache.demand_avg_mshr_miss_latency::total 12332 system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12332 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::total 12332 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 26.763892 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 36347 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1253.344828 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.replacements 0 # number of replacements +system.cpu2.dcache.tags.tagsinuse 26.763892 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 36347 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1253.344828 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763892 # Average occupied blocks per requestor system.cpu2.dcache.tags.occ_percent::cpu2.data 0.052273 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.052273 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.052273 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 42011 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 42011 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 16865 # number of WriteReq hits @@ -799,15 +1207,15 @@ system.cpu3.num_idle_cycles 69869.868798 # Nu system.cpu3.num_busy_cycles 455718.131202 # Number of busy cycles system.cpu3.not_idle_fraction 0.867063 # Percentage of non-idle cycles system.cpu3.idle_fraction 0.132937 # Percentage of idle cycles -system.cpu3.icache.tags.replacements 281 # number of replacements -system.cpu3.icache.tags.tagsinuse 65.598437 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 176322 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 480.441417 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.replacements 281 # number of replacements +system.cpu3.icache.tags.tagsinuse 65.598437 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 176322 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 480.441417 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.598437 # Average occupied blocks per requestor system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128122 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.128122 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.128122 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 176322 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 176322 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 176322 # number of demand (read+write) hits @@ -877,15 +1285,15 @@ system.cpu3.icache.demand_avg_mshr_miss_latency::total 12023.163488 system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 25.915086 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 15020 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 517.931034 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 25.915086 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 15020 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 517.931034 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.915086 # Average occupied blocks per requestor system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050615 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.050615 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.050615 # Average percentage of cache occupancy system.cpu3.dcache.ReadReq_hits::cpu3.data 39563 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 39563 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 6216 # number of WriteReq hits @@ -995,413 +1403,5 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16184.121528 system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 349.046072 # Cycle average of tags in use -system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.889005 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 231.790437 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 54.207948 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 51.556673 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6.123914 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1.773020 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 0.843760 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 1.030292 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.831024 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.003537 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.005326 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits -system.l2c.Writeback_hits::total 1 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 354 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::total 1220 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 182 # number of overall hits -system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 300 # number of overall hits -system.l2c.overall_hits::cpu1.data 3 # number of overall hits -system.l2c.overall_hits::cpu2.inst 354 # number of overall hits -system.l2c.overall_hits::cpu2.data 9 # number of overall hits -system.l2c.overall_hits::cpu3.inst 358 # number of overall hits -system.l2c.overall_hits::cpu3.data 9 # number of overall hits -system.l2c.overall_hits::total 1220 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 8 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses -system.l2c.ReadReq_misses::total 450 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 66 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 23 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 16 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses -system.l2c.demand_misses::total 592 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 285 # number of overall misses -system.l2c.overall_misses::cpu0.data 165 # number of overall misses -system.l2c.overall_misses::cpu1.inst 66 # number of overall misses -system.l2c.overall_misses::cpu1.data 23 # number of overall misses -system.l2c.overall_misses::cpu2.inst 12 # number of overall misses -system.l2c.overall_misses::cpu2.data 16 # number of overall misses -system.l2c.overall_misses::cpu3.inst 9 # number of overall misses -system.l2c.overall_misses::cpu3.data 16 # number of overall misses -system.l2c.overall_misses::total 592 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 14927000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 3451500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 3436500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 418500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 597500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 103500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 465000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.data 104500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 23504000 # number of ReadReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5174000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 801000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 747000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 730000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7452000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 14927000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 8625500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 3436500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1219500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 597500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 850500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 465000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 834500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 30956000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 14927000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 8625500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 3436500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1219500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 597500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 850500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 465000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 834500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 30956000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.727273 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.032787 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.181818 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.269461 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.974684 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.884615 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.032787 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.326711 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52375.438596 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52068.181818 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52312.500000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49791.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 51750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 51666.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.data 52250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52231.111111 # average ReadReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52262.626263 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53400 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53357.142857 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52142.857143 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52478.873239 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52068.181818 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 53021.739130 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 49791.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 53156.250000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52290.540541 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52068.181818 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 53021.739130 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 49791.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 53156.250000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52290.540541 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.inst 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 285 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 66 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 59 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.inst 8 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.data 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 15 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 15 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 15 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 14 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 59 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 22 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 15 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.inst 8 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.data 16 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 59 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 22 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 15 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.inst 8 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.data 16 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11414500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 2640000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2368500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 280000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 80000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 320000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.data 80000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 17223000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 600499 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 763992 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 3084491 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3964000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 577500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5719000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 11414500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 6604000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 2368500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 897500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 80000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 617500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 320000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 640000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 22942000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 11414500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 6604000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 2368500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 897500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 80000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 617500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 320000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 640000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 22942000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090909 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.181818 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.974684 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40053.488372 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40033.266667 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41166.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41250 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40274.647887 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index 0a30250cf..6f84c5ba1 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000653 # Nu sim_ticks 652606500 # Number of ticks simulated final_tick 652606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 176079756 # Simulator tick rate (ticks/s) -host_mem_usage 355636 # Number of bytes of host memory used -host_seconds 3.71 # Real time elapsed on the host +host_tick_rate 158104978 # Simulator tick rate (ticks/s) +host_mem_usage 355504 # Number of bytes of host memory used +host_seconds 4.13 # Real time elapsed on the host system.physmem.bytes_read::cpu0 80014 # Number of bytes read from this memory system.physmem.bytes_read::cpu1 82049 # Number of bytes read from this memory system.physmem.bytes_read::cpu2 81047 # Number of bytes read from this memory @@ -84,41 +84,41 @@ system.membus.trans_dist::UpgradeReq 57414 # Tr system.membus.trans_dist::UpgradeResp 46744 # Transaction distribution system.membus.trans_dist::ReadExReq 48586 # Transaction distribution system.membus.trans_dist::ReadExResp 3092 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side 417062 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 417062 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side 1086481 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 1086481 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 417062 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 417062 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 1086481 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 1086481 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 1086481 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 286485584 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 43.9 # Layer utilization (%) system.membus.respLayer0.occupancy 311361500 # Layer occupancy (ticks) system.membus.respLayer0.utilization 47.7 # Layer utilization (%) -system.l2c.tags.replacements 13254 # number of replacements -system.l2c.tags.tagsinuse 783.820018 # Cycle average of tags in use -system.l2c.tags.total_refs 149317 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14065 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.616210 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 726.472153 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 7.679894 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 7.566050 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 7.311161 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 6.856177 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 7.195523 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.988954 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 6.739476 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 7.010629 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.709445 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.007500 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.007389 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.007140 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.006695 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.007027 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.006825 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006582 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006846 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.765449 # Average percentage of cache occupancy +system.l2c.tags.replacements 13254 # number of replacements +system.l2c.tags.tagsinuse 783.820018 # Cycle average of tags in use +system.l2c.tags.total_refs 149317 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14065 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.616210 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 726.472153 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 7.679894 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 7.566050 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.311161 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 6.856177 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 7.195523 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 6.988954 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 6.739476 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 7.010629 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.709445 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.007500 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.007389 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.007140 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.006695 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.007027 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.006825 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.006582 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.006846 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.765449 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0 10635 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1 10552 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2 10744 # number of ReadReq hits @@ -690,24 +690,24 @@ system.toL2Bus.trans_dist::UpgradeReq 28719 # Tr system.toL2Bus.trans_dist::UpgradeResp 28718 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 155928 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 155926 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side 118285 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side 118639 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side 118896 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side 119078 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side 118813 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side 118602 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side 118904 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side 119137 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 950354 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side 1731443 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side 1726092 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side 1741657 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side 1748194 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side 1742487 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side 1735937 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side 1741406 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side 1745057 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 13912273 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 118285 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 118639 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 118896 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 119078 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 118813 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 118602 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 118904 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 119137 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 950354 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1731443 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1726092 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1741657 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1748194 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1742487 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1735937 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1741406 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1745057 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 13912273 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 13912273 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 19421888 # Total snoop data (bytes) system.toL2Bus.reqLayer0.occupancy 652560490 # Layer occupancy (ticks) @@ -731,15 +731,15 @@ system.toL2Bus.respLayer7.utilization 24.2 # La system.cpu0.num_reads 98977 # number of read accesses completed system.cpu0.num_writes 53590 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.tags.replacements 21970 # number of replacements -system.cpu0.l1c.tags.tagsinuse 393.709596 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13350 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22370 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.596781 # Average number of references to valid blocks. -system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 393.709596 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.768964 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.768964 # Average percentage of cache occupancy +system.cpu0.l1c.tags.replacements 21970 # number of replacements +system.cpu0.l1c.tags.tagsinuse 393.709596 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13350 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22370 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.596781 # Average number of references to valid blocks. +system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.l1c.tags.occ_blocks::cpu0 393.709596 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.768964 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.768964 # Average percentage of cache occupancy system.cpu0.l1c.ReadReq_hits::cpu0 8685 # number of ReadReq hits system.cpu0.l1c.ReadReq_hits::total 8685 # number of ReadReq hits system.cpu0.l1c.WriteReq_hits::cpu0 1118 # number of WriteReq hits @@ -846,15 +846,15 @@ system.cpu0.l1c.no_allocate_misses 0 # Nu system.cpu1.num_reads 99824 # number of read accesses completed system.cpu1.num_writes 53636 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.tags.replacements 22223 # number of replacements -system.cpu1.l1c.tags.tagsinuse 395.298418 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13436 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22630 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.593725 # Average number of references to valid blocks. -system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 395.298418 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.772067 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.772067 # Average percentage of cache occupancy +system.cpu1.l1c.tags.replacements 22223 # number of replacements +system.cpu1.l1c.tags.tagsinuse 395.298418 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13436 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22630 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.593725 # Average number of references to valid blocks. +system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.l1c.tags.occ_blocks::cpu1 395.298418 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.772067 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.772067 # Average percentage of cache occupancy system.cpu1.l1c.ReadReq_hits::cpu1 8757 # number of ReadReq hits system.cpu1.l1c.ReadReq_hits::total 8757 # number of ReadReq hits system.cpu1.l1c.WriteReq_hits::cpu1 1135 # number of WriteReq hits @@ -961,15 +961,15 @@ system.cpu1.l1c.no_allocate_misses 0 # Nu system.cpu2.num_reads 99336 # number of read accesses completed system.cpu2.num_writes 53403 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.tags.replacements 22214 # number of replacements -system.cpu2.l1c.tags.tagsinuse 394.859577 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13307 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22614 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.588441 # Average number of references to valid blocks. -system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 394.859577 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.771210 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.771210 # Average percentage of cache occupancy +system.cpu2.l1c.tags.replacements 22214 # number of replacements +system.cpu2.l1c.tags.tagsinuse 394.859577 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13307 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22614 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.588441 # Average number of references to valid blocks. +system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.l1c.tags.occ_blocks::cpu2 394.859577 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.771210 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.771210 # Average percentage of cache occupancy system.cpu2.l1c.ReadReq_hits::cpu2 8708 # number of ReadReq hits system.cpu2.l1c.ReadReq_hits::total 8708 # number of ReadReq hits system.cpu2.l1c.WriteReq_hits::cpu2 1070 # number of WriteReq hits @@ -1076,15 +1076,15 @@ system.cpu2.l1c.no_allocate_misses 0 # Nu system.cpu3.num_reads 100000 # number of read accesses completed system.cpu3.num_writes 53536 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.tags.replacements 22464 # number of replacements -system.cpu3.l1c.tags.tagsinuse 397.838914 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13424 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22862 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.587175 # Average number of references to valid blocks. -system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 397.838914 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.777029 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.777029 # Average percentage of cache occupancy +system.cpu3.l1c.tags.replacements 22464 # number of replacements +system.cpu3.l1c.tags.tagsinuse 397.838914 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13424 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22862 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.587175 # Average number of references to valid blocks. +system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.l1c.tags.occ_blocks::cpu3 397.838914 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.777029 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.777029 # Average percentage of cache occupancy system.cpu3.l1c.ReadReq_hits::cpu3 8781 # number of ReadReq hits system.cpu3.l1c.ReadReq_hits::total 8781 # number of ReadReq hits system.cpu3.l1c.WriteReq_hits::cpu3 1109 # number of WriteReq hits @@ -1191,15 +1191,15 @@ system.cpu3.l1c.no_allocate_misses 0 # Nu system.cpu4.num_reads 99830 # number of read accesses completed system.cpu4.num_writes 54064 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.tags.replacements 22082 # number of replacements -system.cpu4.l1c.tags.tagsinuse 393.544066 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13201 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22486 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.587076 # Average number of references to valid blocks. -system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 393.544066 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.768641 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.768641 # Average percentage of cache occupancy +system.cpu4.l1c.tags.replacements 22082 # number of replacements +system.cpu4.l1c.tags.tagsinuse 393.544066 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13201 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22486 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.587076 # Average number of references to valid blocks. +system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu4.l1c.tags.occ_blocks::cpu4 393.544066 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.768641 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.768641 # Average percentage of cache occupancy system.cpu4.l1c.ReadReq_hits::cpu4 8712 # number of ReadReq hits system.cpu4.l1c.ReadReq_hits::total 8712 # number of ReadReq hits system.cpu4.l1c.WriteReq_hits::cpu4 1102 # number of WriteReq hits @@ -1306,15 +1306,15 @@ system.cpu4.l1c.no_allocate_misses 0 # Nu system.cpu5.num_reads 99630 # number of read accesses completed system.cpu5.num_writes 53500 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.tags.replacements 22051 # number of replacements -system.cpu5.l1c.tags.tagsinuse 395.592742 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13484 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22450 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.600624 # Average number of references to valid blocks. -system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 395.592742 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.772642 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.772642 # Average percentage of cache occupancy +system.cpu5.l1c.tags.replacements 22051 # number of replacements +system.cpu5.l1c.tags.tagsinuse 395.592742 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13484 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22450 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.600624 # Average number of references to valid blocks. +system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu5.l1c.tags.occ_blocks::cpu5 395.592742 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.772642 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.772642 # Average percentage of cache occupancy system.cpu5.l1c.ReadReq_hits::cpu5 8824 # number of ReadReq hits system.cpu5.l1c.ReadReq_hits::total 8824 # number of ReadReq hits system.cpu5.l1c.WriteReq_hits::cpu5 1160 # number of WriteReq hits @@ -1421,15 +1421,15 @@ system.cpu5.l1c.no_allocate_misses 0 # Nu system.cpu6.num_reads 99897 # number of read accesses completed system.cpu6.num_writes 53584 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.tags.replacements 22385 # number of replacements -system.cpu6.l1c.tags.tagsinuse 395.582005 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13337 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22793 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.585136 # Average number of references to valid blocks. -system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 395.582005 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.772621 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.772621 # Average percentage of cache occupancy +system.cpu6.l1c.tags.replacements 22385 # number of replacements +system.cpu6.l1c.tags.tagsinuse 395.582005 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13337 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22793 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.585136 # Average number of references to valid blocks. +system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu6.l1c.tags.occ_blocks::cpu6 395.582005 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.772621 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.772621 # Average percentage of cache occupancy system.cpu6.l1c.ReadReq_hits::cpu6 8715 # number of ReadReq hits system.cpu6.l1c.ReadReq_hits::total 8715 # number of ReadReq hits system.cpu6.l1c.WriteReq_hits::cpu6 1094 # number of WriteReq hits @@ -1536,15 +1536,15 @@ system.cpu6.l1c.no_allocate_misses 0 # Nu system.cpu7.num_reads 99207 # number of read accesses completed system.cpu7.num_writes 53401 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.tags.replacements 22143 # number of replacements -system.cpu7.l1c.tags.tagsinuse 394.587693 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13403 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22544 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.594526 # Average number of references to valid blocks. -system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 394.587693 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.770679 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.770679 # Average percentage of cache occupancy +system.cpu7.l1c.tags.replacements 22143 # number of replacements +system.cpu7.l1c.tags.tagsinuse 394.587693 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13403 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22544 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.594526 # Average number of references to valid blocks. +system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu7.l1c.tags.occ_blocks::cpu7 394.587693 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.770679 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.770679 # Average percentage of cache occupancy system.cpu7.l1c.ReadReq_hits::cpu7 8635 # number of ReadReq hits system.cpu7.l1c.ReadReq_hits::total 8635 # number of ReadReq hits system.cpu7.l1c.WriteReq_hits::cpu7 1078 # number of WriteReq hits diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt index ff9167bb3..4e4b75a44 100644 --- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt +++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 29067628326 # Simulator tick rate (ticks/s) -host_mem_usage 231288 # Number of bytes of host memory used -host_seconds 3.44 # Real time elapsed on the host +host_tick_rate 12102739985 # Simulator tick rate (ticks/s) +host_mem_usage 228608 # Number of bytes of host memory used +host_seconds 8.26 # Real time elapsed on the host system.physmem.bytes_read::cpu 213331136 # Number of bytes read from this memory system.physmem.bytes_read::total 213331136 # Number of bytes read from this memory system.physmem.num_reads::cpu 3333299 # Number of read requests responded to by this memory @@ -15,14 +15,15 @@ system.physmem.bw_read::cpu 2133311360 # To system.physmem.bw_read::total 2133311360 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu 2133311360 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2133311360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3333300 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 3333300 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 3333300 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 3333300 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 213331136 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 213331136 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 217600 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 217600 # Track reads on a per bank basis @@ -169,18 +170,15 @@ system.physmem.avgGap 30000.29 # Av system.membus.throughput 2133311360 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3333300 # Transaction distribution system.membus.trans_dist::ReadResp 3333299 # Transaction distribution -system.membus.pkt_count_system.monitor-master 6666599 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 6666599 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.monitor-master 213331136 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 213331136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.monitor-master::system.physmem.port 6666599 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6666599 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.monitor-master::system.physmem.port 213331136 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 213331136 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 213331136 # Total data (bytes) system.membus.reqLayer0.occupancy 6333270000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 6.3 # Layer utilization (%) system.membus.respLayer0.occupancy 17184426300 # Layer occupancy (ticks) system.membus.respLayer0.utilization 17.2 # Layer utilization (%) -system.cpu.numPackets 3333300 # Number of packets generated -system.cpu.numRetries 0 # Number of retries -system.cpu.retryTicks 0 # Time spent waiting due to back-pressure (ticks) system.monitor.readBurstLengthHist::samples 3333300 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets @@ -519,5 +517,8 @@ system.monitor.writeTransHist::17 0 0.00% 100.00% # Hi system.monitor.writeTransHist::18 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::19 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period +system.cpu.numPackets 3333300 # Number of packets generated +system.cpu.numRetries 0 # Number of retries +system.cpu.retryTicks 0 # Time spent waiting due to back-pressure (ticks) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt index 4db87dea6..14b3c1d80 100644 --- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt +++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 14083896029 # Simulator tick rate (ticks/s) -host_mem_usage 231304 # Number of bytes of host memory used -host_seconds 7.10 # Real time elapsed on the host +host_tick_rate 8032030639 # Simulator tick rate (ticks/s) +host_mem_usage 228596 # Number of bytes of host memory used +host_seconds 12.45 # Real time elapsed on the host system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory system.physmem.bytes_read::total 64 # Number of bytes read from this memory system.physmem.bytes_written::cpu 213329152 # Number of bytes written to this memory @@ -26,18 +26,15 @@ system.membus.trans_dist::ReadReq 1 # Tr system.membus.trans_dist::ReadResp 1 # Transaction distribution system.membus.trans_dist::WriteReq 3333268 # Transaction distribution system.membus.trans_dist::WriteResp 3333267 # Transaction distribution -system.membus.pkt_count_system.monitor-master 6666537 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 6666537 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.monitor-master 213329216 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 213329216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.monitor-master::system.physmem.port 6666537 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6666537 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.monitor-master::system.physmem.port 213329216 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 213329216 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 213329216 # Total data (bytes) system.membus.reqLayer0.occupancy 16666342328 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 16.7 # Layer utilization (%) system.membus.respLayer0.occupancy 3333272000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 3.3 # Layer utilization (%) -system.cpu.numPackets 3333269 # Number of packets generated -system.cpu.numRetries 1 # Number of retries -system.cpu.retryTicks 1672 # Time spent waiting due to back-pressure (ticks) system.monitor.readBurstLengthHist::samples 1 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets @@ -376,5 +373,8 @@ system.monitor.writeTransHist::34816-36863 0 0.00% 100.00% # system.monitor.writeTransHist::36864-38911 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::38912-40959 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period +system.cpu.numPackets 3333269 # Number of packets generated +system.cpu.numRetries 1 # Number of retries +system.cpu.retryTicks 1672 # Time spent waiting due to back-pressure (ticks) ---------- End Simulation Statistics ---------- |