diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:12:21 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:12:21 -0400 |
| commit | d52adc4eb68c2733f9af4ac68834583c0a555f9d (patch) | |
| tree | 2ee5c3d271af63a3ef527c54950f57f406a05d90 /tests/quick/se | |
| parent | 88554790c34f6fef4ba6285927fb9742b90ab258 (diff) | |
| download | gem5-d52adc4eb68c2733f9af4ac68834583c0a555f9d.tar.xz | |
Stats: Update stats for cache timings in cycles
This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
Diffstat (limited to 'tests/quick/se')
8 files changed, 4348 insertions, 4348 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index ba49bebdd..062194e2a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 21628500 # Number of ticks simulated final_tick 21628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48865 # Simulator instruction rate (inst/s) -host_op_rate 48859 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 165354272 # Simulator tick rate (ticks/s) -host_mem_usage 218640 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 34038 # Simulator instruction rate (inst/s) +host_op_rate 34033 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 115179622 # Simulator tick rate (ticks/s) +host_mem_usage 212112 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory @@ -270,11 +270,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 56590.517241 system.cpu.dcache.overall_avg_miss_latency::cpu.data 56590.517241 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 56590.517241 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1690000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3380 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 37 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 45675.675676 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 91.351351 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 1d71c4fe2..04aaa0ff5 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 20184000 # Number of ticks simulated final_tick 20184000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50290 # Simulator instruction rate (inst/s) -host_op_rate 50282 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 174536927 # Simulator tick rate (ticks/s) -host_mem_usage 219492 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 91753 # Simulator instruction rate (inst/s) +host_op_rate 91718 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 318298211 # Simulator tick rate (ticks/s) +host_mem_usage 212944 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -160,11 +160,11 @@ system.cpu.icache.demand_avg_miss_latency::total 56098.837209 system.cpu.icache.overall_avg_miss_latency::cpu.inst 56098.837209 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 56098.837209 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 58 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 58 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits @@ -256,11 +256,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 57663.385827 system.cpu.dcache.overall_avg_miss_latency::cpu.data 57663.385827 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 57663.385827 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1194500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2389 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51934.782609 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 103.869565 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 9881f90a7..a6445a723 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18570500 # Number of ticks simulated final_tick 18570500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42410 # Simulator instruction rate (inst/s) -host_op_rate 42404 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 147804999 # Simulator tick rate (ticks/s) -host_mem_usage 221464 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 78205 # Simulator instruction rate (inst/s) +host_op_rate 78177 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 272440141 # Simulator tick rate (ticks/s) +host_mem_usage 214124 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -142,11 +142,11 @@ system.cpu.icache.demand_avg_miss_latency::total 55220 system.cpu.icache.overall_avg_miss_latency::cpu.inst 55220 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 55220 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 109000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 218 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 36333.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 72.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59 # number of ReadReq MSHR hits @@ -238,11 +238,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 55992.711370 system.cpu.dcache.overall_avg_miss_latency::cpu.data 55992.711370 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 55992.711370 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2307000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4614 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51266.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 102.533333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 2a32b08b0..c19d33801 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000015 # Nu sim_ticks 14818500 # Number of ticks simulated final_tick 14818500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71701 # Simulator instruction rate (inst/s) -host_op_rate 71694 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 83350191 # Simulator tick rate (ticks/s) -host_mem_usage 220256 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 95139 # Simulator instruction rate (inst/s) +host_op_rate 95123 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 110579898 # Simulator tick rate (ticks/s) +host_mem_usage 213740 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory @@ -736,11 +736,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 40780.102041 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 38918.400000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44057.746479 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 40780.102041 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 49000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 4083.333333 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8.166667 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index e278da8a8..c5840e3c9 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu sim_ticks 25317500 # Number of ticks simulated final_tick 25317500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 47783 # Simulator instruction rate (inst/s) -host_op_rate 47781 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79779918 # Simulator tick rate (ticks/s) -host_mem_usage 220364 # Number of bytes of host memory used -host_seconds 0.32 # Real time elapsed on the host +host_inst_rate 84248 # Simulator instruction rate (inst/s) +host_op_rate 84237 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 140641450 # Simulator tick rate (ticks/s) +host_mem_usage 214032 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -142,11 +142,11 @@ system.cpu.icache.demand_avg_miss_latency::total 54837.398374 system.cpu.icache.overall_avg_miss_latency::cpu.inst 54837.398374 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 54837.398374 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 65500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 131 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 32750 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 65.500000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits @@ -242,11 +242,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 56182.451253 system.cpu.dcache.overall_avg_miss_latency::cpu.data 56182.451253 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 56182.451253 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4519 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50211.111111 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 100.422222 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 482a9e980..ff9862a27 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,953 +1,953 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000114 # Number of seconds simulated -sim_ticks 113910500 # Number of ticks simulated -final_tick 113910500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000110 # Number of seconds simulated +sim_ticks 109894000 # Number of ticks simulated +final_tick 109894000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141669 # Simulator instruction rate (inst/s) -host_op_rate 141669 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14682125 # Simulator tick rate (ticks/s) -host_mem_usage 244464 # Number of bytes of host memory used -host_seconds 7.76 # Real time elapsed on the host -sim_insts 1099129 # Number of instructions simulated -sim_ops 1099129 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 23168 # Number of bytes read from this memory +host_inst_rate 161995 # Simulator instruction rate (inst/s) +host_op_rate 161994 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16590549 # Simulator tick rate (ticks/s) +host_mem_usage 228988 # Number of bytes of host memory used +host_seconds 6.62 # Real time elapsed on the host +sim_insts 1073027 # Number of instructions simulated +sim_ops 1073027 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5632 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 23168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 29248 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 362 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 42880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 29184 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 84 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 88 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 671 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 203387747 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 94389894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 47194947 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11236892 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 2809223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7303980 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 3371068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7303980 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 376997731 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 203387747 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 47194947 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 2809223 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 3371068 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 256762985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 203387747 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 94389894 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 47194947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11236892 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 2809223 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7303980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 3371068 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7303980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 376997731 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 670 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 209656578 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 97839736 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 51249386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11647588 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 2329518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7570932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 2329518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7570932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 390194187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 209656578 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 51249386 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 2329518 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 2329518 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 265564999 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 209656578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 97839736 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 51249386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11647588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 2329518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7570932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 2329518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7570932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 390194187 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 227822 # number of cpu cycles simulated +system.cpu0.numCycles 219789 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 88179 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 85929 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 1290 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 85894 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 83486 # Number of BTB hits +system.cpu0.BPredUnit.lookups 85747 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 83485 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 1265 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 83551 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 81101 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 517 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.usedRAS 507 # Number of times the RAS was used to get a target. system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 17727 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 523680 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 88179 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 84003 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 172095 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 4009 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 15408 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 17217 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 509162 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 85747 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 81608 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 167267 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3854 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 13783 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1281 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 6036 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 519 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 209087 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.504603 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.209881 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1302 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 6029 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 502 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 202015 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.520417 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.209670 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 36992 17.69% 17.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 85294 40.79% 58.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 585 0.28% 58.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1000 0.48% 59.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 484 0.23% 59.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 81297 38.88% 98.36% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 665 0.32% 98.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 355 0.17% 98.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2415 1.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34748 17.20% 17.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 82895 41.03% 58.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 589 0.29% 58.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 956 0.47% 59.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 519 0.26% 59.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 78871 39.04% 98.30% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 675 0.33% 98.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 356 0.18% 98.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2406 1.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 209087 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.387052 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.298637 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18268 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 16880 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 171017 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 351 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2571 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 520658 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2571 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18993 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2288 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13870 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 170679 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 686 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 517484 # Number of instructions processed by rename -system.cpu0.rename.LSQFullEvents 297 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 353459 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1032335 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 1032335 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 339779 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13680 # Number of HB maps that are undone due to squashing +system.cpu0.fetch.rateDist::total 202015 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.390133 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.316595 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17805 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 15234 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 166234 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 301 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2441 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 506087 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2441 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18480 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 1523 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13039 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 165885 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 647 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 502881 # Number of instructions processed by rename +system.cpu0.rename.LSQFullEvents 252 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 343651 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1003098 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 1003098 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 330631 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13020 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 904 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 933 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4009 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 165974 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 83785 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 81138 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 80830 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 432592 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 951 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 429324 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 270 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11361 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 11323 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 392 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 209087 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.053327 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.097112 # Number of insts issued each cycle +system.cpu0.rename.tempSerializingInsts 932 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 3938 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 161147 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 81377 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 78673 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 78441 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 420405 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 949 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 417702 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 122 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10651 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 9804 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 390 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 202015 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.067678 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.086169 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 36280 17.35% 17.35% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5325 2.55% 19.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 82668 39.54% 59.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 82134 39.28% 98.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1638 0.78% 99.50% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 661 0.32% 99.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 275 0.13% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 94 0.04% 99.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 12 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33785 16.72% 16.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5274 2.61% 19.33% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 80485 39.84% 59.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 79928 39.57% 98.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1527 0.76% 99.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 645 0.32% 99.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 270 0.13% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 14 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 209087 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 202015 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 52 18.77% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 113 40.79% 59.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 112 40.43% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 46 19.74% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 73 31.33% 51.07% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 114 48.93% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 180924 42.14% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 165296 38.50% 80.64% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 83104 19.36% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 176241 42.19% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 160662 38.46% 80.66% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 80799 19.34% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 429324 # Type of FU issued -system.cpu0.iq.rate 1.884471 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 277 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000645 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1068282 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 444960 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 427393 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 417702 # Type of FU issued +system.cpu0.iq.rate 1.900468 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 233 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000558 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1037774 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 432063 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 415867 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 429601 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 417935 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 80458 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 78173 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2495 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 56 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1539 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2242 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 58 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1418 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 20 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2571 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1789 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 88 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 515149 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 291 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 165974 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 83785 # Number of dispatched store instructions +system.cpu0.iew.iewSquashCycles 2441 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1114 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 500579 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 311 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 161147 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 81377 # Number of dispatched store instructions system.cpu0.iew.iewDispNonSpecInsts 838 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 95 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewIQFullEvents 51 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 56 # Number of memory order violations +system.cpu0.iew.memOrderViolationEvents 58 # Number of memory order violations system.cpu0.iew.predictedTakenIncorrect 383 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1113 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1496 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 428216 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 164977 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1108 # Number of squashed instructions skipped in execute +system.cpu0.iew.predictedNotTakenIncorrect 1089 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1472 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 416616 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 160343 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1086 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 81606 # number of nop insts executed -system.cpu0.iew.exec_refs 247935 # number of memory reference insts executed -system.cpu0.iew.exec_branches 85106 # Number of branches executed -system.cpu0.iew.exec_stores 82958 # Number of stores executed -system.cpu0.iew.exec_rate 1.879608 # Inst execution rate -system.cpu0.iew.wb_sent 427739 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 427393 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 253334 # num instructions producing a value -system.cpu0.iew.wb_consumers 255736 # num instructions consuming a value +system.cpu0.iew.exec_nop 79225 # number of nop insts executed +system.cpu0.iew.exec_refs 241004 # number of memory reference insts executed +system.cpu0.iew.exec_branches 82800 # Number of branches executed +system.cpu0.iew.exec_stores 80661 # Number of stores executed +system.cpu0.iew.exec_rate 1.895527 # Inst execution rate +system.cpu0.iew.wb_sent 416200 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 415867 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 246464 # num instructions producing a value +system.cpu0.iew.wb_consumers 248856 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.875995 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.990608 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.892119 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.990388 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 13085 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 12251 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1290 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 206533 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.430701 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.136521 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1265 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 199591 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.446493 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.132962 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 36757 17.80% 17.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 84830 41.07% 58.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2489 1.21% 60.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 701 0.34% 60.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 579 0.28% 60.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 80093 38.78% 99.48% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 561 0.27% 99.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 222 0.11% 99.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 301 0.15% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 34293 17.18% 17.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 82677 41.42% 58.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2432 1.22% 59.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 705 0.35% 60.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 565 0.28% 60.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 77961 39.06% 99.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 418 0.21% 99.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 251 0.13% 99.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 289 0.14% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 206533 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 502020 # Number of instructions committed -system.cpu0.commit.committedOps 502020 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 199591 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 488298 # Number of instructions committed +system.cpu0.commit.committedOps 488298 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 245725 # Number of memory references committed -system.cpu0.commit.loads 163479 # Number of loads committed +system.cpu0.commit.refs 238864 # Number of memory references committed +system.cpu0.commit.loads 158905 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 84133 # Number of branches committed +system.cpu0.commit.branches 81846 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 338110 # Number of committed integer instructions. +system.cpu0.commit.int_insts 328962 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 301 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 289 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 720176 # The number of ROB reads -system.cpu0.rob.rob_writes 1032801 # The number of ROB writes -system.cpu0.timesIdled 336 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 18735 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 421071 # Number of Instructions Simulated -system.cpu0.committedOps 421071 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 421071 # Number of Instructions Simulated -system.cpu0.cpi 0.541054 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.541054 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.848246 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.848246 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 766308 # number of integer regfile reads -system.cpu0.int_regfile_writes 345106 # number of integer regfile writes +system.cpu0.rob.rob_reads 698690 # The number of ROB reads +system.cpu0.rob.rob_writes 1003556 # The number of ROB writes +system.cpu0.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 17774 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 409636 # Number of Instructions Simulated +system.cpu0.committedOps 409636 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 409636 # Number of Instructions Simulated +system.cpu0.cpi 0.536547 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.536547 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.863769 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.863769 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 745424 # number of integer regfile reads +system.cpu0.int_regfile_writes 335847 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 249733 # number of misc regfile reads +system.cpu0.misc_regfile_reads 242810 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.replacements 302 # number of replacements -system.cpu0.icache.tagsinuse 247.706871 # Cycle average of tags in use -system.cpu0.icache.total_refs 5276 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 594 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.882155 # Average number of references to valid blocks. +system.cpu0.icache.replacements 299 # number of replacements +system.cpu0.icache.tagsinuse 247.576197 # Cycle average of tags in use +system.cpu0.icache.total_refs 5285 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 591 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.942470 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 247.706871 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.483802 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.483802 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5276 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5276 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5276 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5276 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5276 # number of overall hits -system.cpu0.icache.overall_hits::total 5276 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 760 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 760 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 760 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 760 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 760 # number of overall misses -system.cpu0.icache.overall_misses::total 760 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 29374500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 29374500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 29374500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 29374500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 29374500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 29374500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6036 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6036 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6036 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6036 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6036 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6036 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125911 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.125911 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125911 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.125911 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125911 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.125911 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38650.657895 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38650.657895 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38650.657895 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38650.657895 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38650.657895 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38650.657895 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 13500 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::cpu0.inst 247.576197 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.483547 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.483547 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5285 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5285 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5285 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5285 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5285 # number of overall hits +system.cpu0.icache.overall_hits::total 5285 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 744 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 744 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 744 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 744 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 744 # number of overall misses +system.cpu0.icache.overall_misses::total 744 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 28183000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 28183000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 28183000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 28183000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 28183000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 28183000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6029 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6029 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6029 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6029 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6029 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6029 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.123404 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.123404 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.123404 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.123404 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.123404 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.123404 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 37880.376344 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 37880.376344 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 37880.376344 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 37880.376344 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 37880.376344 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 37880.376344 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13500 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.500000 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 165 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 165 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 165 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 165 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 595 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 595 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 595 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 595 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 595 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 595 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22317000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 22317000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22317000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 22317000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22317000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 22317000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.098575 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.098575 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.098575 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.098575 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.098575 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.098575 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37507.563025 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37507.563025 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37507.563025 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 37507.563025 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37507.563025 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 37507.563025 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 152 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 152 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 152 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 152 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 152 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 152 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 592 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 592 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 592 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 592 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 592 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 592 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22043000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 22043000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22043000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 22043000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22043000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 22043000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.098192 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.098192 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.098192 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.098192 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.098192 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.098192 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37234.797297 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37234.797297 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37234.797297 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 37234.797297 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37234.797297 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 37234.797297 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 144.389455 # Cycle average of tags in use -system.cpu0.dcache.total_refs 165484 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 144.284283 # Cycle average of tags in use +system.cpu0.dcache.total_refs 160925 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 973.435294 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 946.617647 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 144.389455 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.282011 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.282011 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 83924 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 83924 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 81641 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 81641 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 17 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 17 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 165565 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 165565 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 165565 # number of overall hits -system.cpu0.dcache.overall_hits::total 165565 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 532 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 532 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 563 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 563 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 25 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 25 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1095 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1095 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1095 # number of overall misses -system.cpu0.dcache.overall_misses::total 1095 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16935000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 16935000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 28694494 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 28694494 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 516500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 516500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 45629494 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 45629494 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 45629494 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 45629494 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 84456 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 84456 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 82204 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 82204 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.occ_blocks::cpu0.data 144.284283 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.281805 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.281805 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 81643 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 81643 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 79364 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 79364 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 161007 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 161007 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 161007 # number of overall hits +system.cpu0.dcache.overall_hits::total 161007 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 465 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 465 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 553 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 553 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1018 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1018 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1018 # number of overall misses +system.cpu0.dcache.overall_misses::total 1018 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 14129000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 14129000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26395982 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 26395982 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 370000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 370000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 40524982 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 40524982 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 40524982 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 40524982 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 82108 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 82108 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 79917 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 79917 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 166660 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 166660 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 166660 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 166660 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006299 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006299 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006849 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.006849 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.595238 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.595238 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006570 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006570 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006570 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006570 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31832.706767 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31832.706767 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50967.129663 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50967.129663 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 20660 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 20660 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41670.770776 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 41670.770776 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41670.770776 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 41670.770776 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 112000 # number of cycles access was blocked +system.cpu0.dcache.demand_accesses::cpu0.data 162025 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 162025 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 162025 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 162025 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005663 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.005663 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006920 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006920 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006283 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006283 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006283 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006283 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30384.946237 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 30384.946237 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 47732.336347 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 47732.336347 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 17619.047619 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 17619.047619 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39808.430255 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39808.430255 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39808.430255 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 39808.430255 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 319 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 24 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 6222.222222 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.291667 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 351 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 351 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 394 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 394 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 745 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 745 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 745 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 745 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 181 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 169 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 169 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 25 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 25 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 350 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 350 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5844010 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5844010 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6652500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6652500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 438500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 438500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12496510 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12496510 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12496510 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12496510 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002143 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002143 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002056 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002056 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.595238 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.595238 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002100 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002100 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002100 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002100 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32287.348066 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32287.348066 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39363.905325 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39363.905325 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17540 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17540 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35704.314286 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35704.314286 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35704.314286 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35704.314286 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 276 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 276 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 381 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 381 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 657 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 657 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 657 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 657 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 172 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 172 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5343500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5343500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6330000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6330000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 328000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 328000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11673500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11673500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11673500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11673500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002302 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002302 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002152 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002228 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002228 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002228 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002228 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28272.486772 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28272.486772 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36802.325581 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36802.325581 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 15619.047619 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 15619.047619 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32336.565097 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32336.565097 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32336.565097 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32336.565097 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 191317 # number of cpu cycles simulated +system.cpu1.numCycles 184127 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 53059 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 50011 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 1521 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 46382 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 45427 # Number of BTB hits +system.cpu1.BPredUnit.lookups 48566 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 45425 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 1525 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 41634 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 40784 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 803 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.usedRAS 857 # Number of times the RAS was used to get a target. system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 31318 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 294530 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 53059 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 46230 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 104588 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4407 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 38684 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 6733 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1070 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 21833 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 319 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 185209 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.590257 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.119058 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 32363 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 265611 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 48566 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 41641 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 96301 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4375 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 40077 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.NoActiveThreadStallCycles 6455 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 1055 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 23564 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 345 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 179027 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.483637 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.076927 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 80621 43.53% 43.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 53529 28.90% 72.43% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 6903 3.73% 76.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3276 1.77% 77.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 732 0.40% 78.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 34514 18.64% 96.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1160 0.63% 97.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 883 0.48% 98.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3591 1.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 82726 46.21% 46.21% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 49826 27.83% 74.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7772 4.34% 78.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3158 1.76% 80.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 709 0.40% 80.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 29207 16.31% 96.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1125 0.63% 97.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 886 0.49% 97.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3618 2.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 185209 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.277336 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.539487 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 37437 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 34588 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 97784 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 5856 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2811 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 290465 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2811 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 38251 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18737 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 14962 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 92242 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 11473 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 288015 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 15 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 60 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 201252 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 549512 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 549512 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 185544 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15708 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1231 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1359 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 14237 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 80834 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 37999 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 38862 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 32764 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 237666 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 7151 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 239902 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 128 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12973 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 11962 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 719 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 185209 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.295304 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.311031 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 179027 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.263764 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.442542 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 39330 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 35122 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 88807 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 6541 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2772 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 261671 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2772 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 40116 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 20114 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 14157 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 82544 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 12869 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 259082 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 41 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 180494 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 488461 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 488461 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 165372 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15122 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1240 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1383 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 15783 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 71004 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 32715 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 34344 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 27479 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 212625 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 7991 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 216005 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 69 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12464 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 11017 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 740 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 179027 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.206550 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.298788 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 78322 42.29% 42.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 24974 13.48% 55.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 38132 20.59% 76.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 38761 20.93% 97.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3339 1.80% 99.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1231 0.66% 99.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 341 0.18% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 48 0.03% 99.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 80193 44.79% 44.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 27393 15.30% 60.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 32961 18.41% 78.51% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 33539 18.73% 97.24% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3241 1.81% 99.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1264 0.71% 99.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 324 0.18% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 51 0.03% 99.97% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 185209 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 179027 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 21 6.44% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 95 29.14% 35.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 64.42% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 20 6.78% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 65 22.03% 28.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 71.19% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 116849 48.71% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 85748 35.74% 84.45% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 37305 15.55% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 107139 49.60% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 76812 35.56% 85.16% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 32054 14.84% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 239902 # Type of FU issued -system.cpu1.iq.rate 1.253950 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 326 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001359 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 665467 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 257831 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 237819 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 216005 # Type of FU issued +system.cpu1.iq.rate 1.173131 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 295 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001366 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 611401 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 233118 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 214044 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 240228 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 216300 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 32613 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 27354 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2758 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1567 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2609 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1525 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2811 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 2340 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 107 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 284663 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 401 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 80834 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 37999 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1126 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 105 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2772 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 1710 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 255983 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 380 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 71004 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 32715 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1159 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 52 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 509 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1185 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1694 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 238552 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 79712 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1350 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 484 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1213 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1697 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 214708 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 69981 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1297 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 39846 # number of nop insts executed -system.cpu1.iew.exec_refs 116931 # number of memory reference insts executed -system.cpu1.iew.exec_branches 49232 # Number of branches executed -system.cpu1.iew.exec_stores 37219 # Number of stores executed -system.cpu1.iew.exec_rate 1.246894 # Inst execution rate -system.cpu1.iew.wb_sent 238105 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 237819 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 133762 # num instructions producing a value -system.cpu1.iew.wb_consumers 138617 # num instructions consuming a value +system.cpu1.iew.exec_nop 35367 # number of nop insts executed +system.cpu1.iew.exec_refs 101954 # number of memory reference insts executed +system.cpu1.iew.exec_branches 44806 # Number of branches executed +system.cpu1.iew.exec_stores 31973 # Number of stores executed +system.cpu1.iew.exec_rate 1.166086 # Inst execution rate +system.cpu1.iew.wb_sent 214321 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 214044 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 118861 # num instructions producing a value +system.cpu1.iew.wb_consumers 123754 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.243063 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.964975 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.162480 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.960462 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 14936 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 6432 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1521 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 175666 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.535334 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.989786 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 14492 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 7251 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1525 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 169801 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.422188 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.937267 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 78046 44.43% 44.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 47129 26.83% 71.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6230 3.55% 74.80% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 7351 4.18% 78.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1552 0.88% 79.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 32915 18.74% 98.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 634 0.36% 98.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 995 0.57% 99.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 814 0.46% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 80979 47.69% 47.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 42780 25.19% 72.88% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6215 3.66% 76.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 8147 4.80% 81.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1520 0.90% 82.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 27830 16.39% 98.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 515 0.30% 98.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1002 0.59% 99.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 813 0.48% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 175666 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 269706 # Number of instructions committed -system.cpu1.commit.committedOps 269706 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 169801 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 241489 # Number of instructions committed +system.cpu1.commit.committedOps 241489 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 114508 # Number of memory references committed -system.cpu1.commit.loads 78076 # Number of loads committed -system.cpu1.commit.membars 5720 # Number of memory barriers committed -system.cpu1.commit.branches 48115 # Number of branches committed +system.cpu1.commit.refs 99585 # Number of memory references committed +system.cpu1.commit.loads 68395 # Number of loads committed +system.cpu1.commit.membars 6536 # Number of memory barriers committed +system.cpu1.commit.branches 43685 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 184747 # Number of committed integer instructions. +system.cpu1.commit.int_insts 165393 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 814 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 813 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 458907 # The number of ROB reads -system.cpu1.rob.rob_writes 572109 # The number of ROB writes -system.cpu1.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 6108 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 36503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 225079 # Number of Instructions Simulated -system.cpu1.committedOps 225079 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 225079 # Number of Instructions Simulated -system.cpu1.cpi 0.849999 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.849999 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.176472 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.176472 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 410678 # number of integer regfile reads -system.cpu1.int_regfile_writes 191757 # number of integer regfile writes +system.cpu1.rob.rob_reads 424382 # The number of ROB reads +system.cpu1.rob.rob_writes 514748 # The number of ROB writes +system.cpu1.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 5100 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 35660 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 200479 # Number of Instructions Simulated +system.cpu1.committedOps 200479 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 200479 # Number of Instructions Simulated +system.cpu1.cpi 0.918435 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.918435 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.088808 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.088808 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 365766 # number of integer regfile reads +system.cpu1.int_regfile_writes 171568 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 118640 # number of misc regfile reads +system.cpu1.misc_regfile_reads 103658 # number of misc regfile reads system.cpu1.misc_regfile_writes 646 # number of misc regfile writes -system.cpu1.icache.replacements 322 # number of replacements -system.cpu1.icache.tagsinuse 90.918932 # Cycle average of tags in use -system.cpu1.icache.total_refs 21316 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 436 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 48.889908 # Average number of references to valid blocks. +system.cpu1.icache.replacements 321 # number of replacements +system.cpu1.icache.tagsinuse 92.890627 # Cycle average of tags in use +system.cpu1.icache.total_refs 23041 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 438 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 52.605023 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 90.918932 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.177576 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.177576 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 21316 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 21316 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 21316 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 21316 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 21316 # number of overall hits -system.cpu1.icache.overall_hits::total 21316 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 517 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 517 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 517 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 517 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 517 # number of overall misses -system.cpu1.icache.overall_misses::total 517 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11871000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 11871000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 11871000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 11871000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 11871000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 11871000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 21833 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 21833 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 21833 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 21833 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 21833 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 21833 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023680 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023680 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023680 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023680 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023680 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023680 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22961.315280 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 22961.315280 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22961.315280 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 22961.315280 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22961.315280 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 22961.315280 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 32000 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 92.890627 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.181427 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.181427 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 23041 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 23041 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 23041 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 23041 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 23041 # number of overall hits +system.cpu1.icache.overall_hits::total 23041 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 523 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 523 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 523 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 523 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 523 # number of overall misses +system.cpu1.icache.overall_misses::total 523 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10934000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 10934000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 10934000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 10934000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 10934000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 10934000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 23564 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 23564 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 23564 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 23564 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 23564 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 23564 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022195 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.022195 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022195 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.022195 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022195 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.022195 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20906.309751 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 20906.309751 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20906.309751 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 20906.309751 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20906.309751 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 20906.309751 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 66 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 32000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 66 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 81 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 81 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 81 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 81 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 436 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 436 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 436 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 436 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8857500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8857500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8857500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8857500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8857500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8857500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019970 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019970 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019970 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.019970 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019970 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.019970 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20315.366972 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 20315.366972 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 20315.366972 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 20315.366972 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 20315.366972 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 20315.366972 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 85 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 85 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 85 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 85 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 85 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 438 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 438 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 438 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 438 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 438 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 438 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8718000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8718000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8718000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8718000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8718000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8718000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018588 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.018588 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018588 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.018588 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018588 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.018588 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 19904.109589 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 19904.109589 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19904.109589 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 19904.109589 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19904.109589 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 19904.109589 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 27.526466 # Cycle average of tags in use -system.cpu1.dcache.total_refs 42609 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 27.499718 # Cycle average of tags in use +system.cpu1.dcache.total_refs 37345 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1521.750000 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 1333.750000 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 27.526466 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.053763 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.053763 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 46637 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 46637 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 36226 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 36226 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 82863 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 82863 # 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miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.009473 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003850 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003850 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.787879 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.787879 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007022 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.007022 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007022 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.007022 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 28554.932735 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 28554.932735 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25532.142857 # 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miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004499 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004499 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.753623 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.753623 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007297 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.007297 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007297 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.007297 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 24870.603015 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 24870.603015 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22417.857143 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22417.857143 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 19384.615385 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 19384.615385 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24232.342007 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24232.342007 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24232.342007 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24232.342007 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -956,364 +956,364 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # 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number of SwapReq MSHR misses system.cpu1.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 266 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 266 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3164503 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3164503 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1890000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1890000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 1168500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 1168500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5054503 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 5054503 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5054503 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5054503 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003398 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003398 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002915 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002915 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.787879 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.787879 # 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average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19001.890977 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19001.890977 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19001.890977 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19001.890977 # average overall mshr miss latency +system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2446500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2446500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1653500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1653500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 904000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 904000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4100000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4100000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4100000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4100000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003755 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003755 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003310 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003310 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.753623 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.753623 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003567 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003567 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003567 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003567 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15290.625000 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15290.625000 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16053.398058 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16053.398058 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 17384.615385 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 17384.615385 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15589.353612 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15589.353612 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15589.353612 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15589.353612 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 191010 # number of cpu cycles simulated +system.cpu2.numCycles 183836 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.BPredUnit.lookups 57179 # Number of BP lookups -system.cpu2.BPredUnit.condPredicted 53988 # Number of conditional branches predicted -system.cpu2.BPredUnit.condIncorrect 1553 # Number of conditional branches incorrect -system.cpu2.BPredUnit.BTBLookups 50487 # Number of BTB lookups -system.cpu2.BPredUnit.BTBHits 49441 # Number of BTB hits +system.cpu2.BPredUnit.lookups 53962 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 50907 # Number of conditional branches predicted +system.cpu2.BPredUnit.condIncorrect 1502 # Number of conditional branches incorrect +system.cpu2.BPredUnit.BTBLookups 47302 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 46374 # Number of BTB hits system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.usedRAS 815 # Number of times the RAS was used to get a target. +system.cpu2.BPredUnit.usedRAS 814 # Number of times the RAS was used to get a target. system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.fetch.icacheStallCycles 29527 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 320031 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 57179 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 50256 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 111848 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 4474 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 35937 # Number of cycles fetch has spent blocked +system.cpu2.fetch.icacheStallCycles 29545 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 300535 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 53962 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 47188 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 106111 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 4305 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 35885 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 6751 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1077 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 20539 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 333 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 187993 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.702356 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.156955 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.NoActiveThreadStallCycles 6446 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 1035 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 21240 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 181756 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.653508 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.139245 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 76145 40.50% 40.50% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 56782 30.20% 70.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 6165 3.28% 73.99% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3347 1.78% 75.77% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 731 0.39% 76.16% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 39077 20.79% 96.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1243 0.66% 97.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 913 0.49% 98.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3590 1.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 75645 41.62% 41.62% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 54116 29.77% 71.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 6682 3.68% 75.07% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3224 1.77% 76.84% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 665 0.37% 77.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 35775 19.68% 96.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1232 0.68% 97.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 880 0.48% 98.05% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3537 1.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 187993 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.299351 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.675467 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 35252 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 32290 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 105597 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5255 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2848 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 315625 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2848 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 36036 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 16472 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 14955 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 100655 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 10276 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 313299 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 22 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 57 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 219155 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 602465 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 602465 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 203359 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 15796 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1243 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1365 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 12944 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 89370 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 42679 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 42734 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 37374 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 259618 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 6531 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 261379 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 134 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 13068 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 11786 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 697 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 187993 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.390366 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.314588 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 181756 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.293533 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.634799 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 35633 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 31817 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 99530 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5601 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2729 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 296271 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2729 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 36405 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 17349 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13658 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 94174 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 10995 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 293755 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 37 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 205188 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 562117 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 562117 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 190142 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 15046 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1228 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1359 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 13734 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 82915 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 39246 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 39773 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 34011 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 242760 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 6943 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 245051 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 12414 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11373 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 664 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 181756 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.348242 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.310708 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 73641 39.17% 39.17% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 23139 12.31% 51.48% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 42800 22.77% 74.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 43353 23.06% 97.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3352 1.78% 99.09% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1252 0.67% 99.76% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 341 0.18% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 62 0.03% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 73115 40.23% 40.23% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 24368 13.41% 53.63% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 39333 21.64% 75.27% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 39995 22.00% 97.28% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3268 1.80% 99.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1268 0.70% 99.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 298 0.16% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 187993 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 181756 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 21 6.71% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 82 26.20% 32.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 67.09% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 20 6.83% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 63 21.50% 28.33% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 71.67% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 125670 48.08% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 93767 35.87% 83.95% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 41942 16.05% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 118754 48.46% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 87780 35.82% 84.28% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 38517 15.72% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 261379 # Type of FU issued -system.cpu2.iq.rate 1.368405 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 313 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001197 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 711198 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 279252 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 259224 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 245051 # Type of FU issued +system.cpu2.iq.rate 1.332987 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 293 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001196 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 672224 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 262158 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 243059 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 261692 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 245344 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 37218 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 33799 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2690 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1641 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2624 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1621 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2848 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 1926 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 75 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 309970 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 424 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 89370 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 42679 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1173 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 72 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2729 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 1758 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 40 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 290501 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 383 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 82915 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 39246 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1163 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 35 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 514 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1208 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1722 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 259980 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 88335 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1399 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 513 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1158 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1671 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 243729 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 81914 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1322 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 43821 # number of nop insts executed -system.cpu2.iew.exec_refs 130189 # number of memory reference insts executed -system.cpu2.iew.exec_branches 53302 # Number of branches executed -system.cpu2.iew.exec_stores 41854 # Number of stores executed -system.cpu2.iew.exec_rate 1.361081 # Inst execution rate -system.cpu2.iew.wb_sent 259524 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 259224 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 147020 # num instructions producing a value -system.cpu2.iew.wb_consumers 151915 # num instructions consuming a value +system.cpu2.iew.exec_nop 40798 # number of nop insts executed +system.cpu2.iew.exec_refs 120340 # number of memory reference insts executed +system.cpu2.iew.exec_branches 50195 # Number of branches executed +system.cpu2.iew.exec_stores 38426 # Number of stores executed +system.cpu2.iew.exec_rate 1.325796 # Inst execution rate +system.cpu2.iew.wb_sent 243343 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 243059 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 137174 # num instructions producing a value +system.cpu2.iew.wb_consumers 142058 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.357123 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.967778 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.322151 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.965620 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 15032 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 5834 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1553 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 178395 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.653241 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.030877 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 14265 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 6279 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1502 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 172582 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.600480 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.009191 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 72759 40.79% 40.79% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 51159 28.68% 69.46% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6241 3.50% 72.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6697 3.75% 76.72% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1549 0.87% 77.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 37557 21.05% 98.64% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 629 0.35% 98.99% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 989 0.55% 99.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 815 0.46% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 72897 42.24% 42.24% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 48196 27.93% 70.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6187 3.58% 73.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 7136 4.13% 77.89% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1545 0.90% 78.78% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 34295 19.87% 98.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 518 0.30% 98.95% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 991 0.57% 99.53% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 817 0.47% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 178395 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 294930 # Number of instructions committed -system.cpu2.commit.committedOps 294930 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 172582 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 276214 # Number of instructions committed +system.cpu2.commit.committedOps 276214 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 127718 # Number of memory references committed -system.cpu2.commit.loads 86680 # Number of loads committed -system.cpu2.commit.membars 5119 # Number of memory barriers committed -system.cpu2.commit.branches 52122 # Number of branches committed +system.cpu2.commit.refs 117916 # Number of memory references committed +system.cpu2.commit.loads 80291 # Number of loads committed +system.cpu2.commit.membars 5562 # Number of memory barriers committed +system.cpu2.commit.branches 49152 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 201960 # Number of committed integer instructions. +system.cpu2.commit.int_insts 189186 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 815 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 817 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 486955 # The number of ROB reads -system.cpu2.rob.rob_writes 622786 # The number of ROB writes -system.cpu2.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3017 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 36810 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 246900 # Number of Instructions Simulated -system.cpu2.committedOps 246900 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 246900 # Number of Instructions Simulated -system.cpu2.cpi 0.773633 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.773633 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.292602 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.292602 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 450556 # number of integer regfile reads -system.cpu2.int_regfile_writes 209704 # number of integer regfile writes +system.cpu2.rob.rob_reads 461657 # The number of ROB reads +system.cpu2.rob.rob_writes 583698 # The number of ROB writes +system.cpu2.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 2080 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 35951 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 230713 # Number of Instructions Simulated +system.cpu2.committedOps 230713 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 230713 # Number of Instructions Simulated +system.cpu2.cpi 0.796817 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.796817 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.254994 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.254994 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 420543 # number of integer regfile reads +system.cpu2.int_regfile_writes 196056 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 131893 # number of misc regfile reads +system.cpu2.misc_regfile_reads 121964 # number of misc regfile reads system.cpu2.misc_regfile_writes 646 # number of misc regfile writes -system.cpu2.icache.replacements 322 # number of replacements -system.cpu2.icache.tagsinuse 84.177245 # Cycle average of tags in use -system.cpu2.icache.total_refs 20042 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 438 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 45.757991 # Average number of references to valid blocks. +system.cpu2.icache.replacements 323 # number of replacements +system.cpu2.icache.tagsinuse 86.140818 # Cycle average of tags in use +system.cpu2.icache.total_refs 20746 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 436 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 47.582569 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 84.177245 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.164409 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.164409 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 20042 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 20042 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 20042 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 20042 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 20042 # number of overall hits -system.cpu2.icache.overall_hits::total 20042 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 497 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 497 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 497 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 497 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 497 # number of overall misses -system.cpu2.icache.overall_misses::total 497 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7614500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 7614500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 7614500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 7614500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 7614500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 7614500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 20539 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 20539 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 20539 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 20539 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 20539 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 20539 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024198 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.024198 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024198 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.024198 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024198 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.024198 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15320.925553 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 15320.925553 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15320.925553 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 15320.925553 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15320.925553 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 15320.925553 # average overall miss latency +system.cpu2.icache.occ_blocks::cpu2.inst 86.140818 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.168244 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.168244 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 20746 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 20746 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 20746 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 20746 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 20746 # number of overall hits +system.cpu2.icache.overall_hits::total 20746 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 494 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 494 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 494 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 494 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 494 # number of overall misses +system.cpu2.icache.overall_misses::total 494 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6486500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 6486500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 6486500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 6486500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 6486500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 6486500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 21240 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 21240 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 21240 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 21240 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 21240 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 21240 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.023258 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.023258 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.023258 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.023258 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.023258 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.023258 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13130.566802 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 13130.566802 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13130.566802 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 13130.566802 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13130.566802 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 13130.566802 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1322,106 +1322,106 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan system.cpu2.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 438 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 438 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5672000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 5672000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5672000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 5672000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5672000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 5672000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021325 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021325 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021325 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.021325 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021325 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.021325 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12949.771689 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12949.771689 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12949.771689 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 12949.771689 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12949.771689 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 12949.771689 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 58 # 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Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1686.285714 # Average number of references to valid blocks. +system.cpu2.dcache.tagsinuse 26.073093 # Cycle average of tags in use +system.cpu2.dcache.total_refs 43891 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 1513.482759 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 24.875323 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.048585 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.048585 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 50709 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 50709 # 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number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 141 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 141 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 59 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 59 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 546 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 546 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 546 # number of overall misses +system.cpu2.dcache.overall_misses::total 546 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 9305500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 9305500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2828000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2828000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 998500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 998500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 12133500 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 12133500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 12133500 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 12133500 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 48097 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 48097 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 37554 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 37554 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 85651 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 85651 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 85651 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 85651 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.008420 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.008420 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003755 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.003755 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.830986 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.830986 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.006375 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.006375 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.006375 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.006375 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 22976.543210 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 22976.543210 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20056.737589 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 20056.737589 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 16923.728814 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 16923.728814 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22222.527473 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 22222.527473 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22222.527473 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 22222.527473 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1430,364 +1430,364 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 234 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 234 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 35 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 269 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 269 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 269 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 269 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 155 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 104 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 259 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 259 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2539505 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2539505 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1736500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1736500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 1057000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 1057000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4276005 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 4276005 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4276005 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 4276005 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003033 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003033 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002539 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002539 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.826087 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002813 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.002813 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002813 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.002813 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16383.903226 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 16383.903226 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16697.115385 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16697.115385 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 18543.859649 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 18543.859649 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16509.671815 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16509.671815 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16509.671815 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16509.671815 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 239 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 239 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 273 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 273 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 273 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 273 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 166 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 107 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 59 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 273 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 273 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 273 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 273 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2062000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2062000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1458000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1458000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 880500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 880500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3520000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3520000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3520000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3520000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003451 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003451 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002849 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002849 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.830986 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.830986 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003187 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003187 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003187 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003187 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12421.686747 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 12421.686747 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13626.168224 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13626.168224 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 14923.728814 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 14923.728814 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12893.772894 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12893.772894 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12893.772894 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12893.772894 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 190730 # number of cpu cycles simulated +system.cpu3.numCycles 183564 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.BPredUnit.lookups 50135 # Number of BP lookups -system.cpu3.BPredUnit.condPredicted 46886 # Number of conditional branches predicted -system.cpu3.BPredUnit.condIncorrect 1563 # Number of conditional branches incorrect -system.cpu3.BPredUnit.BTBLookups 43380 # Number of BTB lookups -system.cpu3.BPredUnit.BTBHits 42368 # Number of BTB hits +system.cpu3.BPredUnit.lookups 54292 # Number of BP lookups +system.cpu3.BPredUnit.condPredicted 51137 # Number of conditional branches predicted +system.cpu3.BPredUnit.condIncorrect 1552 # Number of conditional branches incorrect +system.cpu3.BPredUnit.BTBLookups 47375 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 46456 # Number of BTB hits system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.BPredUnit.usedRAS 844 # Number of times the RAS was used to get a target. +system.cpu3.BPredUnit.usedRAS 865 # Number of times the RAS was used to get a target. system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.fetch.icacheStallCycles 33373 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 273510 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 50135 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 43212 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 99693 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 4441 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 43703 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 29332 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 302436 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 54292 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 47321 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 106466 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 4424 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 35508 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 6715 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1058 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 24485 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 321 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 187356 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.459841 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.059659 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 6464 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 1083 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 21183 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 181653 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.664911 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.146175 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 87663 46.79% 46.79% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 51707 27.60% 74.39% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 8154 4.35% 78.74% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3276 1.75% 80.49% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 745 0.40% 80.89% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 30183 16.11% 97.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1182 0.63% 97.63% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 888 0.47% 98.10% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3558 1.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 75187 41.39% 41.39% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 54224 29.85% 71.24% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 6571 3.62% 74.86% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3185 1.75% 76.61% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 729 0.40% 77.01% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 36075 19.86% 96.87% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1175 0.65% 97.52% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 882 0.49% 98.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3625 2.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 187356 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.262858 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.434017 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 40875 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 38262 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 91696 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 6999 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2809 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 269218 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2809 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 41677 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 21676 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 15745 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 84975 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 13759 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 266737 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 40 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 184789 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 501822 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 501822 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 169578 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 15211 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1292 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1426 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 16516 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 73298 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 33720 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 35666 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 28418 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 218299 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 8477 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 222114 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 12726 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 11163 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 773 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 187356 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.185518 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.293170 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 181653 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.295766 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.647578 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 35528 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 31409 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 99893 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 5564 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2795 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 298258 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2795 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 36311 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 17134 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 13439 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 94588 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 10922 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 295479 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 43 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 206753 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 566043 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 566043 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 191392 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 15361 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1256 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1388 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 13950 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 83468 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 39555 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 39943 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 34309 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 244369 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 6827 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 246724 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 64 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 12382 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 11033 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 652 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 181653 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.358216 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.312562 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 85320 45.54% 45.54% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 28690 15.31% 60.85% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 33902 18.09% 78.95% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 34456 18.39% 97.34% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3309 1.77% 99.10% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1236 0.66% 99.76% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 327 0.17% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 54 0.03% 99.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 62 0.03% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 72528 39.93% 39.93% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 24126 13.28% 53.21% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 39707 21.86% 75.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 40305 22.19% 97.25% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3272 1.80% 99.06% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1282 0.71% 99.76% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 320 0.18% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 60 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 187356 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 181653 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 22 7.17% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 75 24.43% 31.60% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 68.40% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 22 7.41% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 65 21.89% 29.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 70.71% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 109540 49.32% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 79567 35.82% 85.14% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 33007 14.86% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 119576 48.47% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 88284 35.78% 84.25% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 38864 15.75% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 222114 # Type of FU issued -system.cpu3.iq.rate 1.164547 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 307 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001382 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 632004 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 239536 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 220090 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 246724 # Type of FU issued +system.cpu3.iq.rate 1.344076 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 297 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001204 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 675462 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 263617 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 244690 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 222421 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 247021 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 28294 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 34138 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2578 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1587 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2601 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1592 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2809 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 1854 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 263586 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 366 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 73298 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 33720 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1219 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 53 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2795 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 1688 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 292203 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 375 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 83468 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 39555 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1173 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 48 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 34 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 509 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1217 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1726 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 220807 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 72290 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1307 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 39 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 498 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1226 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1724 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 245374 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 82515 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1350 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 36810 # number of nop insts executed -system.cpu3.iew.exec_refs 105220 # number of memory reference insts executed -system.cpu3.iew.exec_branches 46242 # Number of branches executed -system.cpu3.iew.exec_stores 32930 # Number of stores executed -system.cpu3.iew.exec_rate 1.157694 # Inst execution rate -system.cpu3.iew.wb_sent 220376 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 220090 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 122048 # num instructions producing a value -system.cpu3.iew.wb_consumers 126919 # num instructions consuming a value +system.cpu3.iew.exec_nop 41007 # number of nop insts executed +system.cpu3.iew.exec_refs 121290 # number of memory reference insts executed +system.cpu3.iew.exec_branches 50490 # Number of branches executed +system.cpu3.iew.exec_stores 38775 # Number of stores executed +system.cpu3.iew.exec_rate 1.336722 # Inst execution rate +system.cpu3.iew.wb_sent 244974 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 244690 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 138171 # num instructions producing a value +system.cpu3.iew.wb_consumers 143054 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.153935 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.961621 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.332996 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.965866 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 14631 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7704 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1563 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 177833 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.399791 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.928963 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 14351 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 6175 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1552 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 172395 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.611613 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.012919 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 86250 48.50% 48.50% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 44177 24.84% 73.34% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6214 3.49% 76.84% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8561 4.81% 81.65% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1535 0.86% 82.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 28697 16.14% 98.65% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 590 0.33% 98.98% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 996 0.56% 99.54% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 813 0.46% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 72191 41.88% 41.88% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 48466 28.11% 69.99% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6229 3.61% 73.60% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 7040 4.08% 77.69% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1522 0.88% 78.57% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 34600 20.07% 98.64% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 541 0.31% 98.95% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 992 0.58% 99.53% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 814 0.47% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 177833 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 248929 # Number of instructions committed -system.cpu3.commit.committedOps 248929 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 172395 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 277834 # Number of instructions committed +system.cpu3.commit.committedOps 277834 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 102853 # Number of memory references committed -system.cpu3.commit.loads 70720 # Number of loads committed -system.cpu3.commit.membars 6986 # Number of memory barriers committed -system.cpu3.commit.branches 45078 # Number of branches committed +system.cpu3.commit.refs 118830 # Number of memory references committed +system.cpu3.commit.loads 80867 # Number of loads committed +system.cpu3.commit.membars 5460 # Number of memory barriers committed +system.cpu3.commit.branches 49386 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 170050 # Number of committed integer instructions. +system.cpu3.commit.int_insts 190336 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 813 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 814 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 439993 # The number of ROB reads -system.cpu3.rob.rob_writes 529937 # The number of ROB writes -system.cpu3.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 3374 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 37090 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 206079 # Number of Instructions Simulated -system.cpu3.committedOps 206079 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 206079 # Number of Instructions Simulated -system.cpu3.cpi 0.925519 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.925519 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.080475 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.080475 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 375615 # number of integer regfile reads -system.cpu3.int_regfile_writes 175714 # number of integer regfile writes +system.cpu3.rob.rob_reads 463179 # The number of ROB reads +system.cpu3.rob.rob_writes 587180 # The number of ROB writes +system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1911 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 36223 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 232199 # Number of Instructions Simulated +system.cpu3.committedOps 232199 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 232199 # Number of Instructions Simulated +system.cpu3.cpi 0.790546 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.790546 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.264948 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.264948 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 423588 # number of integer regfile reads +system.cpu3.int_regfile_writes 197545 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 106918 # number of misc regfile reads +system.cpu3.misc_regfile_reads 122942 # number of misc regfile reads system.cpu3.misc_regfile_writes 646 # number of misc regfile writes -system.cpu3.icache.replacements 323 # number of replacements -system.cpu3.icache.tagsinuse 88.249587 # Cycle average of tags in use -system.cpu3.icache.total_refs 23982 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 439 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 54.628702 # Average number of references to valid blocks. +system.cpu3.icache.replacements 321 # number of replacements +system.cpu3.icache.tagsinuse 83.581511 # Cycle average of tags in use +system.cpu3.icache.total_refs 20679 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 436 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 47.428899 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 88.249587 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.172362 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.172362 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 23982 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 23982 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 23982 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 23982 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 23982 # number of overall hits -system.cpu3.icache.overall_hits::total 23982 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 503 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 503 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 503 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 503 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 503 # number of overall misses -system.cpu3.icache.overall_misses::total 503 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7707000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 7707000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 7707000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 7707000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 7707000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 7707000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 24485 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 24485 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 24485 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 24485 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 24485 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 24485 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020543 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.020543 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020543 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.020543 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020543 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.020543 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15322.067594 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 15322.067594 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15322.067594 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 15322.067594 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15322.067594 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 15322.067594 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 83.581511 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.163245 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.163245 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 20679 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 20679 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 20679 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 20679 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 20679 # number of overall hits +system.cpu3.icache.overall_hits::total 20679 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 504 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 504 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 504 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 504 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 504 # number of overall misses +system.cpu3.icache.overall_misses::total 504 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6381500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6381500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6381500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6381500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6381500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6381500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 21183 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 21183 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 21183 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 21183 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 21183 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 21183 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023793 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.023793 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023793 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.023793 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023793 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.023793 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 12661.706349 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 12661.706349 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 12661.706349 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 12661.706349 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 12661.706349 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 12661.706349 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1796,106 +1796,106 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 64 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 64 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 64 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 64 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 64 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 439 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 439 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 439 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 439 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 439 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 439 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5684000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5684000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5684000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5684000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5684000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5684000 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017929 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.017929 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017929 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.017929 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017929 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.017929 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12947.608200 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12947.608200 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12947.608200 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12947.608200 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12947.608200 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12947.608200 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 68 # 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number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 5023500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5023500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 5023500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5023500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 5023500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020583 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020583 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020583 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.020583 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020583 # 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mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003014 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003014 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 12680.645161 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 12680.645161 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13923.809524 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13923.809524 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 14964.285714 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 14964.285714 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13182.692308 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 13182.692308 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13182.692308 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 13182.692308 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 436.337885 # Cycle average of tags in use -system.l2c.total_refs 1474 # Total number of references to valid blocks. -system.l2c.sampled_refs 537 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.744879 # Average number of references to valid blocks. +system.l2c.tagsinuse 435.526886 # Cycle average of tags in use +system.l2c.total_refs 1471 # Total number of references to valid blocks. +system.l2c.sampled_refs 536 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.744403 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 0.838584 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 294.109117 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 59.534191 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 68.191567 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 5.703860 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 2.346215 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.730565 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 4.110047 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.773739 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 0.836552 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 292.896606 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 59.494044 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 70.004577 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 5.700111 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 3.075204 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 0.772877 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 2.016825 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 0.730090 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.004488 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.004469 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.000908 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.001041 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.001068 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.000087 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.000063 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.006658 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 233 # number of ReadReq hits +system.l2c.occ_percent::cpu2.inst 0.000047 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.000012 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.inst 0.000031 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.006646 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 232 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 350 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 348 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 428 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 427 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 431 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 432 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1474 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1471 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 233 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40720.238095 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 42576.923077 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 41749.253731 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40963.888889 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 43630.952381 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40681.818182 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44175 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42807.692308 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42923.076923 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 42423.076923 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 41641.579732 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 42576.923077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 41749.253731 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 1523ab302..df50fe29d 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,130 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000269 # Number of seconds simulated -sim_ticks 268898000 # Number of ticks simulated -final_tick 268898000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000262 # Number of seconds simulated +sim_ticks 261623500 # Number of ticks simulated +final_tick 261623500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1131883 # Simulator instruction rate (inst/s) -host_op_rate 1131850 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 454173870 # Simulator tick rate (ticks/s) -host_mem_usage 240368 # Number of bytes of host memory used -host_seconds 0.59 # Real time elapsed on the host -sim_insts 670104 # Number of instructions simulated -sim_ops 670104 # Number of ops (including micro ops) simulated +host_inst_rate 776063 # Simulator instruction rate (inst/s) +host_op_rate 776047 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 307506962 # Simulator tick rate (ticks/s) +host_mem_usage 231300 # Number of bytes of host memory used +host_seconds 0.85 # Real time elapsed on the host +sim_insts 660239 # Number of instructions simulated +sim_ops 660239 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 3392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 1408 # Number of bytes read from this memory system.physmem.bytes_read::total 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 3392 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 9 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 53 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 22 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 67832412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 39271397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14042499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5236186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 476017 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 3570127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1904068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3808135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 136140842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 67832412 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14042499 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 476017 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1904068 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 84254996 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 67832412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 39271397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14042499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 5236186 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 476017 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 3570127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1904068 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3808135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 136140842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 69718508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40363347 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 1712384 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3669395 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 2201637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 3914021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 12965196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 5381780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139926268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69718508 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 1712384 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 2201637 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 12965196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86597725 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69718508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40363347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 1712384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3669395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 2201637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 3914021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 12965196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 5381780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 139926268 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 537796 # number of cpu cycles simulated +system.cpu0.numCycles 523247 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 160914 # Number of instructions committed -system.cpu0.committedOps 160914 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 110768 # Number of integer alu accesses +system.cpu0.committedInsts 158010 # Number of instructions committed +system.cpu0.committedOps 158010 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 108832 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 26422 # number of instructions that are conditional controls -system.cpu0.num_int_insts 110768 # number of integer instructions +system.cpu0.num_conditional_control_insts 25938 # number of instructions that are conditional controls +system.cpu0.num_int_insts 108832 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 320462 # number of times the integer registers were read -system.cpu0.num_int_register_writes 112374 # number of times the integer registers were written +system.cpu0.num_int_register_reads 314654 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110438 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 75191 # number of memory refs -system.cpu0.num_load_insts 49787 # Number of load instructions -system.cpu0.num_store_insts 25404 # Number of store instructions +system.cpu0.num_mem_refs 73739 # number of memory refs +system.cpu0.num_load_insts 48819 # Number of load instructions +system.cpu0.num_store_insts 24920 # Number of store instructions system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 537796 # Number of busy cycles +system.cpu0.num_busy_cycles 523247 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.icache.replacements 215 # number of replacements -system.cpu0.icache.tagsinuse 212.263647 # Cycle average of tags in use -system.cpu0.icache.total_refs 160510 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 212.464540 # Cycle average of tags in use +system.cpu0.icache.total_refs 157606 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 343.704497 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 337.486081 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 212.263647 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.414577 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.414577 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 160510 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 160510 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 160510 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 160510 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 160510 # number of overall hits -system.cpu0.icache.overall_hits::total 160510 # number of overall hits +system.cpu0.icache.occ_blocks::cpu0.inst 212.464540 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.414970 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.414970 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 157606 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 157606 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 157606 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 157606 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 157606 # number of overall hits +system.cpu0.icache.overall_hits::total 157606 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18554000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18554000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18554000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18554000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18554000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18554000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 160977 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 160977 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 160977 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 160977 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 160977 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 160977 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002901 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002901 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002901 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002901 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002901 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002901 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39730.192719 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 39730.192719 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39730.192719 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 39730.192719 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39730.192719 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 39730.192719 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18144000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18144000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18144000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18144000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18144000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18144000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 158073 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 158073 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 158073 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 158073 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 158073 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 158073 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002954 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002954 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002954 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002954 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002954 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002954 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38852.248394 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38852.248394 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38852.248394 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38852.248394 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38852.248394 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38852.248394 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -139,44 +139,44 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17153000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17153000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17153000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17153000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17153000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17153000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002901 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002901 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002901 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002901 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002901 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002901 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36730.192719 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36730.192719 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36730.192719 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 36730.192719 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36730.192719 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 36730.192719 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17210000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17210000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17210000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17210000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17210000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17210000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002954 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.002954 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.002954 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36852.248394 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 36852.248394 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 36852.248394 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 145.520681 # Cycle average of tags in use -system.cpu0.dcache.total_refs 74667 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 145.601248 # Cycle average of tags in use +system.cpu0.dcache.total_refs 73215 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 447.107784 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 438.413174 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 145.520681 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.284220 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.284220 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 49615 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 49615 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 25170 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 25170 # number of WriteReq hits +system.cpu0.dcache.occ_blocks::cpu0.data 145.601248 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.284377 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.284377 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 48647 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48647 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 24686 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 24686 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 74785 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 74785 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 74785 # number of overall hits -system.cpu0.dcache.overall_hits::total 74785 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 73333 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 73333 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 73333 # number of overall hits +system.cpu0.dcache.overall_hits::total 73333 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 162 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 162 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses @@ -187,46 +187,46 @@ system.cpu0.dcache.demand_misses::cpu0.data 345 # system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses system.cpu0.dcache.overall_misses::total 345 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5171000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5171000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7310000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7310000 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 522000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 522000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 12481000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 12481000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 12481000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 12481000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 49777 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 49777 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 25353 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 25353 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4649500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4649500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7005000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7005000 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 363500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 363500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11654500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11654500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11654500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11654500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48809 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48809 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24869 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24869 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 75130 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 75130 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 75130 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 75130 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003255 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003255 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007218 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007218 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 73678 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73678 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73678 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73678 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003319 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003319 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007359 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007359 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004592 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004592 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004592 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004592 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31919.753086 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31919.753086 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39945.355191 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 39945.355191 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 20076.923077 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 20076.923077 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36176.811594 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36176.811594 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36176.811594 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36176.811594 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004683 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004683 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004683 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004683 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28700.617284 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28700.617284 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38278.688525 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38278.688525 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13980.769231 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 13980.769231 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33781.159420 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33781.159420 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33781.159420 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33781.159420 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -247,104 +247,104 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 345 system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 345 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4684001 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4684001 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6761000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6761000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 444000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 444000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11445001 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11445001 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11445001 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11445001 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003255 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003255 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007218 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007218 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4325500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4325500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6639000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6639000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 311500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 311500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10964500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10964500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10964500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10964500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003319 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003319 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007359 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007359 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004592 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004592 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004592 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004592 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28913.586420 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28913.586420 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36945.355191 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36945.355191 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17076.923077 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17076.923077 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33173.915942 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33173.915942 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33173.915942 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33173.915942 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004683 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004683 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004683 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004683 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26700.617284 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26700.617284 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36278.688525 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36278.688525 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11980.769231 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11980.769231 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31781.159420 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31781.159420 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31781.159420 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31781.159420 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 537796 # number of cpu cycles simulated +system.cpu1.numCycles 523247 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 159902 # Number of instructions committed -system.cpu1.committedOps 159902 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 114536 # Number of integer alu accesses +system.cpu1.committedInsts 173283 # Number of instructions committed +system.cpu1.committedOps 173283 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 108736 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 26689 # number of instructions that are conditional controls -system.cpu1.num_int_insts 114536 # number of integer instructions +system.cpu1.num_conditional_control_insts 36284 # number of instructions that are conditional controls +system.cpu1.num_int_insts 108736 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 313629 # number of times the integer registers were read -system.cpu1.num_int_register_writes 121810 # number of times the integer registers were written +system.cpu1.num_int_register_reads 252002 # number of times the integer registers were read +system.cpu1.num_int_register_writes 93825 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 64016 # number of memory refs -system.cpu1.num_load_insts 42937 # Number of load instructions -system.cpu1.num_store_insts 21079 # Number of store instructions -system.cpu1.num_idle_cycles 71578.001734 # Number of idle cycles -system.cpu1.num_busy_cycles 466217.998266 # Number of busy cycles -system.cpu1.not_idle_fraction 0.866905 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.133095 # Percentage of idle cycles +system.cpu1.num_mem_refs 48621 # number of memory refs +system.cpu1.num_load_insts 40031 # Number of load instructions +system.cpu1.num_store_insts 8590 # Number of store instructions +system.cpu1.num_idle_cycles 68750.001737 # Number of idle cycles +system.cpu1.num_busy_cycles 454496.998263 # Number of busy cycles +system.cpu1.not_idle_fraction 0.868609 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.131391 # Percentage of idle cycles system.cpu1.icache.replacements 280 # number of replacements -system.cpu1.icache.tagsinuse 69.905818 # Cycle average of tags in use -system.cpu1.icache.total_refs 159569 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 65.593035 # Cycle average of tags in use +system.cpu1.icache.total_refs 172950 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 435.980874 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 472.540984 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 69.905818 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.136535 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.136535 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 159569 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 159569 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 159569 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 159569 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 159569 # number of overall hits -system.cpu1.icache.overall_hits::total 159569 # number of overall hits +system.cpu1.icache.occ_blocks::cpu1.inst 65.593035 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.128111 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.128111 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 172950 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 172950 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 172950 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 172950 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 172950 # number of overall hits +system.cpu1.icache.overall_hits::total 172950 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7984500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7984500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7984500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7984500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7984500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7984500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 159935 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 159935 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 159935 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 159935 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 159935 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 159935 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002288 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002288 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002288 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002288 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002288 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002288 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21815.573770 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 21815.573770 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21815.573770 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 21815.573770 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21815.573770 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 21815.573770 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5373500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5373500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5373500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5373500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5373500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5373500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 173316 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 173316 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 173316 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 173316 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 173316 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 173316 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002112 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002112 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002112 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002112 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002112 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002112 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14681.693989 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14681.693989 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14681.693989 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14681.693989 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14681.693989 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14681.693989 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # 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number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1665500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 549500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 549500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4627500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4627500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4627500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4627500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004422 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004422 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012328 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.012328 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.774648 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.774648 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005810 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.005810 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005810 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.005810 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16734.463277 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16734.463277 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15861.904762 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15861.904762 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 9990.909091 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 9990.909091 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16409.574468 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16409.574468 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16409.574468 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16409.574468 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 537796 # number of cpu cycles simulated +system.cpu2.numCycles 523246 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 177221 # Number of instructions committed -system.cpu2.committedOps 177221 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 109567 # Number of integer alu accesses +system.cpu2.committedInsts 160665 # Number of instructions committed +system.cpu2.committedOps 160665 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 113639 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 37840 # number of instructions that are conditional controls -system.cpu2.num_int_insts 109567 # number of integer instructions +system.cpu2.num_conditional_control_insts 27518 # number of instructions that are conditional controls +system.cpu2.num_int_insts 113639 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 249142 # number of times the integer registers were read -system.cpu2.num_int_register_writes 92045 # number of times the integer registers were written +system.cpu2.num_int_register_reads 306682 # number of times the integer registers were read +system.cpu2.num_int_register_writes 118721 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 47896 # number of memory refs -system.cpu2.num_load_insts 40447 # Number of load instructions -system.cpu2.num_store_insts 7449 # Number of store instructions -system.cpu2.num_idle_cycles 71854.001733 # Number of idle cycles -system.cpu2.num_busy_cycles 465941.998267 # Number of busy cycles -system.cpu2.not_idle_fraction 0.866392 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.133608 # Percentage of idle cycles +system.cpu2.num_mem_refs 62290 # number of memory refs +system.cpu2.num_load_insts 42488 # Number of load instructions +system.cpu2.num_store_insts 19802 # Number of store instructions +system.cpu2.num_idle_cycles 69015.869837 # Number of idle cycles +system.cpu2.num_busy_cycles 454230.130163 # Number of busy cycles +system.cpu2.not_idle_fraction 0.868101 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.131899 # Percentage of idle cycles system.cpu2.icache.replacements 281 # number of replacements -system.cpu2.icache.tagsinuse 67.534984 # Cycle average of tags in use -system.cpu2.icache.total_refs 176887 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 67.731754 # Cycle average of tags in use +system.cpu2.icache.total_refs 160331 # Total number of references to valid blocks. system.cpu2.icache.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 481.980926 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 436.869210 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 67.534984 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.131904 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.131904 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 176887 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 176887 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 176887 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 176887 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 176887 # number of overall hits -system.cpu2.icache.overall_hits::total 176887 # number of overall hits +system.cpu2.icache.occ_blocks::cpu2.inst 67.731754 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.132289 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.132289 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 160331 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 160331 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 160331 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 160331 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 160331 # number of overall hits +system.cpu2.icache.overall_hits::total 160331 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 367 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 367 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 367 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 367 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 367 # number of overall misses system.cpu2.icache.overall_misses::total 367 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5709500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 5709500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 5709500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 5709500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 5709500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 5709500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 177254 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 177254 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 177254 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 177254 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 177254 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 177254 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002070 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002070 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002070 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002070 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002070 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002070 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15557.220708 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 15557.220708 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15557.220708 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 15557.220708 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15557.220708 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 15557.220708 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5321500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 5321500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 5321500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 5321500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 5321500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 5321500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 160698 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 160698 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 160698 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 160698 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 160698 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 160698 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002284 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002284 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002284 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002284 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002284 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002284 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14500 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 14500 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14500 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 14500 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14500 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 14500 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -577,94 +577,94 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 367 system.cpu2.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 367 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4608500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 4608500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4608500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 4608500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4608500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 4608500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002070 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002070 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002070 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002070 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002070 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002070 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12557.220708 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12557.220708 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12557.220708 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 12557.220708 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12557.220708 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 12557.220708 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4587500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 4587500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4587500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 4587500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4587500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 4587500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002284 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002284 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002284 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12500 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12500 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12500 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 12500 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12500 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 12500 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 26.638398 # Cycle average of tags in use -system.cpu2.dcache.total_refs 17171 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 26.833050 # Cycle average of tags in use +system.cpu2.dcache.total_refs 41851 # Total number of references to valid blocks. system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 592.103448 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 1443.137931 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 26.638398 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.052028 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.052028 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 40266 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 40266 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 7273 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 7273 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 18 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 18 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 47539 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 47539 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 47539 # number of overall hits -system.cpu2.dcache.overall_hits::total 47539 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 173 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 173 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 51 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 51 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 278 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 278 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 278 # number of overall misses -system.cpu2.dcache.overall_misses::total 278 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3995000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 3995000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2318000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2318000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 814000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 814000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 6313000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 6313000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 6313000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 6313000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 40439 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 40439 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 7378 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 7378 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 47817 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 47817 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 47817 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 47817 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.004278 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.004278 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.014231 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.014231 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.739130 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.739130 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005814 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.005814 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005814 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.005814 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23092.485549 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 23092.485549 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22076.190476 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 22076.190476 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 15960.784314 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 15960.784314 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22708.633094 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 22708.633094 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22708.633094 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 22708.633094 # average overall miss latency +system.cpu2.dcache.occ_blocks::cpu2.data 26.833050 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.052408 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.052408 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 42328 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42328 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 19626 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 19626 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 61954 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 61954 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 61954 # number of overall hits +system.cpu2.dcache.overall_hits::total 61954 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 152 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 152 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 106 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 106 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 258 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 258 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 258 # number of overall misses +system.cpu2.dcache.overall_misses::total 258 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 1938000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 1938000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2155000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2155000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 612500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 612500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 4093000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 4093000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 4093000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 4093000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 42480 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 42480 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 19732 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 19732 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 62212 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 62212 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 62212 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 62212 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003578 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003578 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.005372 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.005372 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.852941 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.852941 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004147 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004147 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004147 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004147 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12750 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 12750 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20330.188679 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 20330.188679 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10560.344828 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 10560.344828 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15864.341085 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 15864.341085 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15864.341085 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 15864.341085 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -673,114 +673,114 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 173 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 51 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 278 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 278 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 278 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 3476000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 3476000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2003000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2003000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 661000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 661000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 5479000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 5479000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 5479000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 5479000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004278 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004278 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014231 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.014231 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.739130 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.739130 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.005814 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.005814 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.005814 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.005814 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 20092.485549 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 20092.485549 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19076.190476 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19076.190476 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 12960.784314 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 12960.784314 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 19708.633094 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 19708.633094 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 19708.633094 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 19708.633094 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 152 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 258 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 258 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 258 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 258 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1634000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1634000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1943000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1943000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 496500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 496500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3577000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3577000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3577000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3577000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003578 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003578 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.005372 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.005372 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.852941 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.852941 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004147 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004147 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004147 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004147 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10750 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10750 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 18330.188679 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 18330.188679 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8560.344828 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8560.344828 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13864.341085 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13864.341085 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13864.341085 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13864.341085 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 537796 # number of cpu cycles simulated +system.cpu3.numCycles 523246 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 172067 # Number of instructions committed -system.cpu3.committedOps 172067 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 111206 # Number of integer alu accesses +system.cpu3.committedInsts 168281 # Number of instructions committed +system.cpu3.committedOps 168281 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 108796 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 34437 # number of instructions that are conditional controls -system.cpu3.num_int_insts 111206 # number of integer instructions +system.cpu3.num_conditional_control_insts 33752 # number of instructions that are conditional controls +system.cpu3.num_int_insts 108796 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 269314 # number of times the integer registers were read -system.cpu3.num_int_register_writes 101322 # number of times the integer registers were written +system.cpu3.num_int_register_reads 262371 # number of times the integer registers were read +system.cpu3.num_int_register_writes 98980 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 52937 # number of memory refs -system.cpu3.num_load_insts 41268 # Number of load instructions -system.cpu3.num_store_insts 11669 # Number of store instructions -system.cpu3.num_idle_cycles 72130.001732 # Number of idle cycles -system.cpu3.num_busy_cycles 465665.998268 # Number of busy cycles -system.cpu3.not_idle_fraction 0.865879 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.134121 # Percentage of idle cycles +system.cpu3.num_mem_refs 51213 # number of memory refs +system.cpu3.num_load_insts 40064 # Number of load instructions +system.cpu3.num_store_insts 11149 # Number of store instructions +system.cpu3.num_idle_cycles 69253.869381 # Number of idle cycles +system.cpu3.num_busy_cycles 453992.130619 # Number of busy cycles +system.cpu3.not_idle_fraction 0.867646 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.132354 # Percentage of idle cycles system.cpu3.icache.replacements 280 # number of replacements -system.cpu3.icache.tagsinuse 65.345482 # Cycle average of tags in use -system.cpu3.icache.total_refs 171734 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 70.063196 # Cycle average of tags in use +system.cpu3.icache.total_refs 167948 # Total number of references to valid blocks. system.cpu3.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 469.218579 # Average number of references to valid blocks. +system.cpu3.icache.avg_refs 458.874317 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 65.345482 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.127628 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.127628 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 171734 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 171734 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 171734 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 171734 # 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number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 751000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 751000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 5419000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 5419000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 5419000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 5419000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004266 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004266 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.009055 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.009055 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.830986 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.830986 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005316 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.005316 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005316 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.005316 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 22005.681818 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 22005.681818 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14723.809524 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14723.809524 # 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number of ReadReq accesses(hits+misses) @@ -1069,47 +1069,47 @@ system.l2c.ReadReq_accesses::total 1670 # nu system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 27 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 11 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 88 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 87 # 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miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses @@ -1117,54 +1117,54 @@ system.l2c.ReadExReq_miss_rate::cpu3.data 1 # m system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.884615 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.038251 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.640000 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.inst 0.032698 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.021858 # 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Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index e04fdea8a..0a4a4cf1a 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,633 +1,633 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000757 # Number of seconds simulated -sim_ticks 757091500 # Number of ticks simulated -final_tick 757091500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000761 # Number of seconds simulated +sim_ticks 761298000 # Number of ticks simulated +final_tick 761298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 129668365 # Simulator tick rate (ticks/s) -host_mem_usage 347944 # Number of bytes of host memory used -host_seconds 5.84 # Real time elapsed on the host -system.physmem.bytes_read::cpu0 90255 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 89097 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 89397 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 87447 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 92253 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 92127 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 87941 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 90122 # Number of bytes read from this memory -system.physmem.bytes_read::total 718639 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 466688 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5395 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5319 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5314 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5343 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5295 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5581 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5197 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5320 # Number of bytes written to this memory -system.physmem.bytes_written::total 509452 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10977 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11088 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11217 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11361 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 11298 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 11018 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 11057 # Number of read requests responded to by this memory -system.physmem.num_reads::total 89080 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 7292 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5395 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5319 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5314 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5343 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5295 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5581 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5197 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5320 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50056 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 119212803 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 117683265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 118079519 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 115503872 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 121851850 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 121685424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 116156369 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 119037131 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 949210234 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 616422189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 7125955 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 7025571 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 7018967 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 7057271 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 6993871 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 7371632 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 6864428 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 7026892 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 672906775 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 616422189 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 126338758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 124708836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 125098485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 122561144 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 128845721 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 129057056 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 123020797 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 126064023 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1622117010 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 15543 # number of replacements -system.l2c.tagsinuse 804.498263 # Cycle average of tags in use -system.l2c.total_refs 151705 # Total number of references to valid blocks. -system.l2c.sampled_refs 16364 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.270655 # Average number of references to valid blocks. +host_tick_rate 219241825 # Simulator tick rate (ticks/s) +host_mem_usage 341324 # Number of bytes of host memory used +host_seconds 3.47 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 89717 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 92471 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 92156 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 88405 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 90559 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 92920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 90802 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 90403 # Number of bytes read from this memory +system.physmem.bytes_read::total 727433 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 479872 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5444 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5306 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5518 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5318 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5329 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5364 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5370 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5377 # Number of bytes written to this memory +system.physmem.bytes_written::total 522898 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11345 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 11075 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 11201 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11041 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11368 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11335 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11107 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11275 # Number of read requests responded to by this memory +system.physmem.num_reads::total 89747 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 7498 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5444 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5306 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5518 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5318 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5329 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5364 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5370 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5377 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50524 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 117847413 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 121464919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 121051152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 116124041 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 118953419 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 122054701 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 119272611 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 118748506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 955516762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 630333982 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 7150945 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 6969675 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 7248147 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 6985438 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 6999887 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 7045861 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 7053742 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 7062937 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 686850616 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 630333982 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 124998358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 128434595 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 128299299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 123109479 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 125953306 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 129100562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 126326353 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 125811443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1642367378 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 15728 # number of replacements +system.l2c.tagsinuse 804.643799 # Cycle average of tags in use +system.l2c.total_refs 152339 # Total number of references to valid blocks. +system.l2c.sampled_refs 16530 # Sample count of references to valid blocks. +system.l2c.avg_refs 9.215910 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 743.034079 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0 7.652510 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1 7.207345 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2 7.804802 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3 7.584993 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu4 7.883519 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu5 7.822009 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu6 7.314161 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu7 8.194845 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.725619 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0 0.007473 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1 0.007038 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2 0.007622 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3 0.007407 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu4 0.007699 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu5 0.007639 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu6 0.007143 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu7 0.008003 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.785643 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0 10656 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10576 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10855 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10944 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10856 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10997 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10762 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10884 # number of ReadReq hits -system.l2c.ReadReq_hits::total 86530 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 77152 # number of Writeback hits -system.l2c.Writeback_hits::total 77152 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 335 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 345 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 353 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 387 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 361 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 367 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 340 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 332 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2820 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 2056 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 2082 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 2008 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 2098 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 2081 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 2029 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 2020 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 2069 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 16443 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12712 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12658 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12863 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 13042 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12937 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 13026 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12782 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12953 # number of demand (read+write) hits -system.l2c.demand_hits::total 102973 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12712 # number of overall hits -system.l2c.overall_hits::cpu1 12658 # number of overall hits -system.l2c.overall_hits::cpu2 12863 # number of overall hits -system.l2c.overall_hits::cpu3 13042 # number of overall hits -system.l2c.overall_hits::cpu4 12937 # number of overall hits -system.l2c.overall_hits::cpu5 13026 # number of overall hits -system.l2c.overall_hits::cpu6 12782 # number of overall hits -system.l2c.overall_hits::cpu7 12953 # number of overall hits -system.l2c.overall_hits::total 102973 # number of overall hits -system.l2c.ReadReq_misses::cpu0 825 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 783 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 805 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 784 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 818 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 847 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 802 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 828 # number of ReadReq misses -system.l2c.ReadReq_misses::total 6492 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1871 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1835 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1867 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1892 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1828 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1835 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1851 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1876 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 14855 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4261 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4189 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4229 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4314 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4275 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4251 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4117 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4314 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 33950 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5086 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 4972 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5034 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5098 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5093 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5098 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 4919 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5142 # number of demand (read+write) misses -system.l2c.demand_misses::total 40442 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5086 # number of overall misses -system.l2c.overall_misses::cpu1 4972 # number of overall misses -system.l2c.overall_misses::cpu2 5034 # number of overall misses -system.l2c.overall_misses::cpu3 5098 # number of overall misses -system.l2c.overall_misses::cpu4 5093 # number of overall misses -system.l2c.overall_misses::cpu5 5098 # number of overall misses -system.l2c.overall_misses::cpu6 4919 # number of overall misses -system.l2c.overall_misses::cpu7 5142 # number of overall misses -system.l2c.overall_misses::total 40442 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 68189898 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 66156919 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 68642411 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 68279416 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 69618906 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 72771903 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 69510913 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 75078411 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 558248777 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 55439380 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 51556398 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 53772873 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 56810367 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 54586881 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 52940893 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 52708899 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 53996365 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 431812056 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 243093964 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 240130019 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 242345503 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 242765011 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 244393485 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 241342993 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 234214460 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 244073518 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1932358953 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 311283862 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 306286938 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 310987914 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 311044427 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 314012391 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 314114896 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 303725373 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 319151929 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2490607730 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 311283862 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 306286938 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 310987914 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 311044427 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 314012391 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 314114896 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 303725373 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 319151929 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2490607730 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0 11481 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1 11359 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2 11660 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3 11728 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu4 11674 # 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number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2191 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2208 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 17675 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6317 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6271 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6237 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6412 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6356 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6280 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6137 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6383 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50393 # 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number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1828 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 14842 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4339 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4322 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4349 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4270 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4225 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4246 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4116 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4276 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 34143 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5150 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5172 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5190 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5067 # 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number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 53053446 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 55065452 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 53902466 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 431652155 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 247942331 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 244706822 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 247942337 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 243863836 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 241149827 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 241354363 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 234845330 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 242655342 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1944460188 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 315527812 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 317380789 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 320449810 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 311764322 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 312134794 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 313976345 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 308865301 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 314544815 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2514643988 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 315527812 # 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number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11816 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11805 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11792 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 93855 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 77421 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 77421 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2247 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2119 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2235 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2185 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2252 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2188 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2275 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2226 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 17727 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6435 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6412 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6366 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6389 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6253 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6308 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6228 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6331 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50722 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 18261 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 18034 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18176 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17865 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17961 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu5 18124 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17701 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 18095 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 143415 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17798 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17630 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17897 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 18140 # 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number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.071858 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.068932 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.069039 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.066849 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.070070 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.071513 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.069353 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.070697 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.069790 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.848141 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.841743 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.840991 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.830189 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.835085 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.833333 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.844820 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.849638 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.840453 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.674529 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.667996 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.678050 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.672801 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.672593 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.676911 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.670849 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.675858 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.673705 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.285762 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.282019 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.281276 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.281036 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.282474 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.281284 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.277894 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.284167 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.281993 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.285762 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.282019 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.281276 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.281036 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.282474 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.281284 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.277894 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.284167 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.281993 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 82654.421818 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 84491.595147 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 85270.075776 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 87091.091837 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 85108.687042 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 85917.240850 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 86671.961347 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 90674.409420 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 85990.261399 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 29630.881881 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 28096.129700 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 28801.753080 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 30026.621036 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 29861.532276 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 28850.622888 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 28475.904376 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 28782.710554 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29068.465567 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 57050.918564 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 57323.948198 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 57305.628517 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 56273.762401 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 57168.066667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 56773.228182 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 56889.594365 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 56577.078813 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 56917.789485 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 61204.062525 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 61602.360821 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 61777.495828 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 61013.030012 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 61655.682505 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 61615.318949 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 61745.349258 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 62067.664138 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 61584.682508 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 61204.062525 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 61602.360821 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 61777.495828 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 61013.030012 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 61655.682505 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 61615.318949 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 61745.349258 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 62067.664138 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 61584.682508 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 323471 # number of cycles access was blocked +system.l2c.overall_accesses::cpu6 18033 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18123 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 144577 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.068578 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.073137 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.071211 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.069449 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.070208 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.073290 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.073528 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.067927 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.070918 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.847352 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.842850 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.842506 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.830664 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.839254 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.846435 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.828132 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.821204 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.837254 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.674281 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.674049 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.683161 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.668336 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.675676 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.673114 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.660886 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.675407 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.673140 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.282022 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.286792 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.285541 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.283627 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.280998 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.282057 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.276382 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.280141 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.282196 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.282022 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.286792 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.285541 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.283627 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.280998 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.282057 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.276382 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.280141 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.282196 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 83335.981504 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 85498.784706 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 86215.782402 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 85195.089084 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 86356.407543 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 83859.101617 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 85276.464286 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 89749.654182 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 85664.633413 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 28851.082983 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 28838.723964 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 29108.578864 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 29583.996143 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28934.370899 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 28646.569114 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 29227.946921 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 29487.125821 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 29083.152877 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 57142.735884 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 56618.885238 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 57011.344447 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 57110.968618 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 57076.882130 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 56842.760951 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 57056.688533 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 56748.209074 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 56950.478517 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 61267.536311 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 61365.195089 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 61743.701349 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 61528.384054 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 61845.610065 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 61419.472809 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 61971.368579 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 61954.858184 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 61634.941739 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 61267.536311 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 61365.195089 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 61743.701349 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 61528.384054 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 61845.610065 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 61419.472809 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 61971.368579 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 61954.858184 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 61634.941739 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 618 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 94 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 3441.180851 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 6.574468 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 7293 # number of writebacks -system.l2c.writebacks::total 7293 # number of writebacks +system.l2c.writebacks::writebacks 7498 # number of writebacks +system.l2c.writebacks::total 7498 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 1 # number of UpgradeReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 9 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 11 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu0 2 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu0 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 9 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 3 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 31 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 34 # number of ReadExReq MSHR hits system.l2c.demand_mshr_hits::cpu0 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 96 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 19 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 98 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 16 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 96 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 818 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 774 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 794 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 778 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 810 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 838 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 793 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 822 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 6427 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1871 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1835 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1867 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1892 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1828 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1835 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1850 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1876 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 14854 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4256 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4182 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4226 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4311 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4274 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4247 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4111 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4312 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 33919 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5074 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 4956 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5020 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5089 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5084 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5085 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 4904 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5134 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40346 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5074 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 4956 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5020 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5089 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5084 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5085 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 4904 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5134 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40346 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 57681466 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 55801476 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 58516973 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 58678465 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 58920974 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 61933964 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 58878980 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 64759967 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 475172265 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 77326932 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 75430964 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 76820936 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 77936944 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 75295947 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 75638458 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 76288450 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 77210443 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 611949074 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 190865870 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 188480880 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 190796375 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 190236368 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 192397382 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 189567870 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 183778356 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 191626863 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1517749964 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 248547336 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 244282356 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 249313348 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 248914833 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 251318356 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 251501834 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 242657336 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 256386830 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1992922229 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 248547336 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 244282356 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 249313348 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 248914833 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 251318356 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 251501834 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 242657336 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 256386830 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1992922229 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 413458717 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 411792191 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 414319722 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 423127681 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 423239170 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 421136201 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 414540172 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 411527705 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3333141559 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 232000375 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 229604409 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 230860874 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 229140383 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 229719408 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 244869353 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 226374384 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 231941380 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1854510566 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 645459092 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 641396600 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 645180596 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 652268064 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 652958578 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 666005554 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 640914556 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 643469085 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5187652125 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.071248 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.068140 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.068096 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.066337 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.069385 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.070753 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.068575 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.070184 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.069091 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.848141 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.841743 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.840991 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.830189 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.835085 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.833333 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.844363 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.849638 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.840396 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.673738 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.666879 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.677569 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.672333 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.672435 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.676274 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.669871 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.675544 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.673090 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.285088 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.281112 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.280494 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.280540 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.281974 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.280567 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.277046 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.283725 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.281323 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.285088 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.281112 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.280494 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.280540 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.281974 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.280567 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.277046 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.283725 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.281323 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 70515.239609 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 72094.930233 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 73698.958438 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 75422.191517 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 72741.943210 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 73906.878282 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 74248.398487 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 78783.414842 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 73933.758363 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41329.199359 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41106.792371 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41146.725228 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41192.887949 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41190.342998 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41219.868120 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41237 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41156.952559 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41197.594857 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 44846.304041 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 45069.555237 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 45148.219356 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44128.129900 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 45015.765559 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 44635.712267 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44704.051569 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44440.367115 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 44746.306318 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 48984.496650 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 49290.225182 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 49664.013546 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 48912.327176 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 49433.193548 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 49459.554376 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 49481.512235 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 49939.000779 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 49395.782209 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 48984.496650 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 49290.225182 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 49664.013546 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 48912.327176 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 49433.193548 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 49459.554376 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 49481.512235 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 49939.000779 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 49395.782209 # average overall mshr miss latency +system.l2c.overall_mshr_hits::cpu1 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 19 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 98 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 804 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 843 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 831 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 788 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 815 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 856 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 857 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 798 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 6592 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1902 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1786 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1883 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1815 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1889 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1852 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1884 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1828 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 14839 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4334 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4318 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4340 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4265 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4222 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4242 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4116 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4272 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 34109 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5138 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5161 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5171 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5053 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5037 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5098 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 4973 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5070 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40701 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5138 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5161 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5171 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5053 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5037 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5098 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 4973 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5070 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40701 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 57455481 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 61467468 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 61812473 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 57960486 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 60571467 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 61211482 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 62615971 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 61885973 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 484980801 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 78471422 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 73680432 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 77692433 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 74790419 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 77910437 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 76253912 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 77720922 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 75415430 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 611935407 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 195176331 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 192089822 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 194667337 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 191905836 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 189907827 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 189746863 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 184982830 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 190582842 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1529059688 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 252631812 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 253557290 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 256479810 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 249866322 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 250479294 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 250958345 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 247598801 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 252468815 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 2014040489 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 252631812 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 253557290 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 256479810 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 249866322 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 250479294 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 250958345 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 247598801 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 252468815 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 2014040489 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 426624598 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 414248119 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 417125081 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 415481622 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 425535608 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 422832619 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 413879620 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 421948093 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3357675360 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 234914484 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 229533990 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 238126486 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 230756493 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 230060497 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 233129489 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 235046492 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 235339481 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1866907412 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 661539082 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 643782109 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 655251567 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 646238115 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 655596105 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 655962108 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 648926112 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 657287574 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5224582772 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.067986 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.072535 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.070364 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.068665 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.069611 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.072444 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.072596 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.067673 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.070236 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.846462 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.842850 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.842506 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.830664 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.838810 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.846435 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.828132 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.821204 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.837085 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.673504 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.673425 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.681747 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.667554 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.675196 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.672479 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.660886 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.674775 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.672470 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.281365 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.286182 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.284496 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.282844 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.280441 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.281284 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.275772 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.279755 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.281518 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.281365 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.286182 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.284496 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.282844 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.280441 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.281284 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.275772 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.279755 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.281518 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 71462.041045 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 72915.145907 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 74383.240674 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 73553.916244 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 74320.818405 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 71508.740654 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 73064.143524 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 77551.344612 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 73571.116657 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41257.319664 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41254.441209 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41259.921933 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41206.842424 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41244.275807 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41173.818575 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41253.143312 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41255.705689 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41238.318418 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 45033.763498 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 44485.831867 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44854.225115 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44995.506682 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 44980.536949 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 44730.519331 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44942.378523 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44612.088483 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 44828.628456 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 49169.289996 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 49129.488471 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 49599.653839 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 49449.103899 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 49727.872543 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 49226.823264 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 49788.618741 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 49796.610454 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 49483.808481 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 49169.289996 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 49129.488471 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 49599.653839 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 49449.103899 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 49727.872543 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 49226.823264 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 49788.618741 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 49796.610454 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 49483.808481 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -656,114 +656,114 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.num_reads 98965 # number of read accesses completed -system.cpu0.num_writes 53188 # number of write accesses completed +system.cpu0.num_reads 99935 # number of read accesses completed +system.cpu0.num_writes 53927 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.replacements 22322 # number of replacements -system.cpu0.l1c.tagsinuse 389.061969 # Cycle average of tags in use -system.cpu0.l1c.total_refs 13312 # Total number of references to valid blocks. -system.cpu0.l1c.sampled_refs 22723 # Sample count of references to valid blocks. -system.cpu0.l1c.avg_refs 0.585838 # Average number of references to valid blocks. +system.cpu0.l1c.replacements 22552 # number of replacements +system.cpu0.l1c.tagsinuse 390.299440 # Cycle average of tags in use +system.cpu0.l1c.total_refs 13259 # Total number of references to valid blocks. +system.cpu0.l1c.sampled_refs 22978 # Sample count of references to valid blocks. +system.cpu0.l1c.avg_refs 0.577030 # Average number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.occ_blocks::cpu0 389.061969 # Average occupied blocks per requestor -system.cpu0.l1c.occ_percent::cpu0 0.759887 # Average percentage of cache occupancy -system.cpu0.l1c.occ_percent::total 0.759887 # Average percentage of cache occupancy -system.cpu0.l1c.ReadReq_hits::cpu0 8733 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8733 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1107 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1107 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9840 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9840 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9840 # number of overall hits -system.cpu0.l1c.overall_hits::total 9840 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 35619 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 35619 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23007 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23007 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 58626 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 58626 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 58626 # number of overall misses -system.cpu0.l1c.overall_misses::total 58626 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 4549553769 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 4549553769 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 3145624806 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 3145624806 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 7695178575 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 7695178575 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 7695178575 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 7695178575 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44352 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44352 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24114 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24114 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 68466 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 68466 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 68466 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 68466 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.803098 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.803098 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954093 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.954093 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.856279 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.856279 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.856279 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.856279 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 127728.284595 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 127728.284595 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 136724.684053 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 136724.684053 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 131258.802835 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 131258.802835 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 131258.802835 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 131258.802835 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 714656307 # number of cycles access was blocked +system.cpu0.l1c.occ_blocks::cpu0 390.299440 # Average occupied blocks per requestor +system.cpu0.l1c.occ_percent::cpu0 0.762304 # Average percentage of cache occupancy +system.cpu0.l1c.occ_percent::total 0.762304 # Average percentage of cache occupancy +system.cpu0.l1c.ReadReq_hits::cpu0 8650 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8650 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1121 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1121 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9771 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9771 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9771 # number of overall hits +system.cpu0.l1c.overall_hits::total 9771 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36111 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36111 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23070 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23070 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 59181 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 59181 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 59181 # number of overall misses +system.cpu0.l1c.overall_misses::total 59181 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 4619304150 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 4619304150 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 3123415012 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 3123415012 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 7742719162 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 7742719162 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 7742719162 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 7742719162 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44761 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44761 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24191 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24191 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 68952 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 68952 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 68952 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 68952 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.806751 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.806751 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953660 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.953660 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.858293 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.858293 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.858293 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.858293 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 127919.585445 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 127919.585445 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 135388.600433 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 135388.600433 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 130831.164766 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 130831.164766 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 130831.164766 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 130831.164766 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1413270 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 63701 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 64534 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 11218.918180 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 21.899619 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9780 # number of writebacks -system.cpu0.l1c.writebacks::total 9780 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35619 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 35619 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23007 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23007 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 58626 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 58626 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 58626 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 58626 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 4478007425 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 4478007425 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 3099554441 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 3099554441 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 7577561866 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 7577561866 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 7577561866 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 7577561866 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 1380411824 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 1380411824 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 995386324 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 995386324 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2375798148 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2375798148 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.803098 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.803098 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954093 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954093 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.856279 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.856279 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.856279 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.856279 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 125719.627867 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 125719.627867 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 134722.234146 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 134722.234146 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 129252.581892 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 129252.581892 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 129252.581892 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 129252.581892 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9856 # number of writebacks +system.cpu0.l1c.writebacks::total 9856 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36111 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36111 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23070 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23070 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 59181 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 59181 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 59181 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 59181 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 4547088150 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 4547088150 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 3077287012 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 3077287012 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 7624375162 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 7624375162 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 7624375162 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 7624375162 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 1436864073 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 1436864073 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 955697316 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 955697316 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2392561389 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2392561389 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.806751 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.806751 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953660 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953660 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858293 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.858293 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858293 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.858293 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 125919.751599 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 125919.751599 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 133389.120590 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 133389.120590 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 128831.468917 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 128831.468917 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 128831.468917 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 128831.468917 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -771,114 +771,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 97331 # number of read accesses completed -system.cpu1.num_writes 52743 # number of write accesses completed +system.cpu1.num_reads 97805 # number of read accesses completed +system.cpu1.num_writes 52541 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.replacements 21605 # number of replacements -system.cpu1.l1c.tagsinuse 388.260770 # Cycle average of tags in use -system.cpu1.l1c.total_refs 12987 # Total number of references to valid blocks. -system.cpu1.l1c.sampled_refs 21962 # Sample count of references to valid blocks. -system.cpu1.l1c.avg_refs 0.591340 # Average number of references to valid blocks. +system.cpu1.l1c.replacements 21861 # number of replacements +system.cpu1.l1c.tagsinuse 389.546383 # Cycle average of tags in use +system.cpu1.l1c.total_refs 12913 # Total number of references to valid blocks. +system.cpu1.l1c.sampled_refs 22254 # Sample count of references to valid blocks. +system.cpu1.l1c.avg_refs 0.580255 # Average number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.occ_blocks::cpu1 388.260770 # Average occupied blocks per requestor -system.cpu1.l1c.occ_percent::cpu1 0.758322 # Average percentage of cache occupancy -system.cpu1.l1c.occ_percent::total 0.758322 # Average percentage of cache occupancy -system.cpu1.l1c.ReadReq_hits::cpu1 8534 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8534 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1058 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1058 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9592 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9592 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9592 # number of overall hits -system.cpu1.l1c.overall_hits::total 9592 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 35254 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 35254 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 22627 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 22627 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 57881 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 57881 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 57881 # number of overall misses -system.cpu1.l1c.overall_misses::total 57881 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 4617875359 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 4617875359 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 3138675137 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 3138675137 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 7756550496 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 7756550496 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 7756550496 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 7756550496 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 43788 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 43788 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 23685 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 23685 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 67473 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 67473 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 67473 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 67473 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805106 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.805106 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.955330 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.955330 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.857839 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.857839 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.857839 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.857839 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 130988.692319 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 130988.692319 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 138713.710921 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 138713.710921 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 134008.577875 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 134008.577875 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 134008.577875 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 134008.577875 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 723339270 # number of cycles access was blocked +system.cpu1.l1c.occ_blocks::cpu1 389.546383 # Average occupied blocks per requestor +system.cpu1.l1c.occ_percent::cpu1 0.760833 # Average percentage of cache occupancy +system.cpu1.l1c.occ_percent::total 0.760833 # Average percentage of cache occupancy +system.cpu1.l1c.ReadReq_hits::cpu1 8526 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8526 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1045 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1045 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9571 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9571 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9571 # number of overall hits +system.cpu1.l1c.overall_hits::total 9571 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 35398 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 35398 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 22650 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 22650 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 58048 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 58048 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 58048 # number of overall misses +system.cpu1.l1c.overall_misses::total 58048 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 4577570179 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 4577570179 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 3175338798 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 3175338798 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 7752908977 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 7752908977 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 7752908977 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 7752908977 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 43924 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 43924 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 23695 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 23695 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 67619 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 67619 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 67619 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 67619 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805892 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.805892 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.955898 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.955898 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.858457 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.858457 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.858457 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.858457 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 129317.198119 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 129317.198119 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 140191.558411 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 140191.558411 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 133560.311759 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 133560.311759 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 133560.311759 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 133560.311759 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1404233 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 62977 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 62944 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11485.768932 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 22.309243 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9483 # number of writebacks -system.cpu1.l1c.writebacks::total 9483 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35254 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 35254 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22627 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 22627 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 57881 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 57881 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 57881 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 57881 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 4547061522 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 4547061522 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 3093362268 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 3093362268 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 7640423790 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 7640423790 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 7640423790 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 7640423790 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1364091847 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1364091847 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 932992416 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 932992416 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2297084263 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2297084263 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805106 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805106 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.955330 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.955330 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857839 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.857839 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857839 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.857839 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 128980.017076 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 128980.017076 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 136711.109206 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 136711.109206 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 132002.276913 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 132002.276913 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 132002.276913 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 132002.276913 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9603 # number of writebacks +system.cpu1.l1c.writebacks::total 9603 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35398 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 35398 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22650 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 22650 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 58048 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 58048 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 58048 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 58048 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 4506790179 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 4506790179 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 3130040798 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 3130040798 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 7636830977 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 7636830977 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 7636830977 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 7636830977 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1394209419 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1394209419 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 928511940 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 928511940 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2322721359 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2322721359 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805892 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805892 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.955898 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.955898 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858457 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.858457 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858457 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.858457 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 127317.650121 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 127317.650121 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 138191.646711 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 138191.646711 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 131560.621847 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 131560.621847 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 131560.621847 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 131560.621847 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -886,114 +886,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 98360 # number of read accesses completed -system.cpu2.num_writes 53068 # number of write accesses completed +system.cpu2.num_reads 100000 # number of read accesses completed +system.cpu2.num_writes 54114 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.replacements 22096 # number of replacements -system.cpu2.l1c.tagsinuse 389.724593 # Cycle average of tags in use -system.cpu2.l1c.total_refs 13250 # Total number of references to valid blocks. -system.cpu2.l1c.sampled_refs 22502 # Sample count of references to valid blocks. -system.cpu2.l1c.avg_refs 0.588837 # Average number of references to valid blocks. +system.cpu2.l1c.replacements 22990 # number of replacements +system.cpu2.l1c.tagsinuse 392.060782 # Cycle average of tags in use +system.cpu2.l1c.total_refs 13456 # Total number of references to valid blocks. +system.cpu2.l1c.sampled_refs 23401 # Sample count of references to valid blocks. +system.cpu2.l1c.avg_refs 0.575018 # Average number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.occ_blocks::cpu2 389.724593 # Average occupied blocks per requestor -system.cpu2.l1c.occ_percent::cpu2 0.761181 # Average percentage of cache occupancy -system.cpu2.l1c.occ_percent::total 0.761181 # Average percentage of cache occupancy -system.cpu2.l1c.ReadReq_hits::cpu2 8687 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8687 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1121 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1121 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9808 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9808 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9808 # number of overall hits -system.cpu2.l1c.overall_hits::total 9808 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 35624 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 35624 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 22874 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 22874 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 58498 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 58498 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 58498 # number of overall misses -system.cpu2.l1c.overall_misses::total 58498 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 4545456138 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 4545456138 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 3151736803 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 3151736803 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 7697192941 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 7697192941 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 7697192941 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 7697192941 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 44311 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 44311 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 23995 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 23995 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 68306 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 68306 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 68306 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 68306 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.803954 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.803954 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953282 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.953282 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.856411 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.856411 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.856411 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.856411 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 127595.332865 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 127595.332865 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 137786.867317 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 137786.867317 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 131580.446186 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 131580.446186 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 131580.446186 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 131580.446186 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 716129194 # number of cycles access was blocked +system.cpu2.l1c.occ_blocks::cpu2 392.060782 # Average occupied blocks per requestor +system.cpu2.l1c.occ_percent::cpu2 0.765744 # Average percentage of cache occupancy +system.cpu2.l1c.occ_percent::total 0.765744 # Average percentage of cache occupancy +system.cpu2.l1c.ReadReq_hits::cpu2 8750 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8750 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1243 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1243 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9993 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9993 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9993 # number of overall hits +system.cpu2.l1c.overall_hits::total 9993 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36203 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36203 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23173 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23173 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 59376 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 59376 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 59376 # number of overall misses +system.cpu2.l1c.overall_misses::total 59376 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 4641358719 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 4641358719 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 3127191782 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 3127191782 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 7768550501 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 7768550501 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 7768550501 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 7768550501 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44953 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44953 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24416 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24416 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 69369 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 69369 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 69369 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 69369 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805352 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805352 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.949091 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.949091 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.855944 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.855944 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.855944 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.855944 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 128203.704638 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 128203.704638 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 134949.802874 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 134949.802874 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 130836.541717 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 130836.541717 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 130836.541717 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 130836.541717 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1392289 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 63633 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 64514 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 11254.053620 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 21.581192 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9686 # number of writebacks -system.cpu2.l1c.writebacks::total 9686 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35624 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 35624 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22874 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 22874 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 58498 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 58498 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 58498 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 58498 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 4473878832 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 4473878832 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 3105924454 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 3105924454 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 7579803286 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 7579803286 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 7579803286 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 7579803286 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1379555288 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1379555288 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 954692892 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 954692892 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2334248180 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2334248180 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.803954 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.803954 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953282 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953282 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.856411 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.856411 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.856411 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.856411 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 125586.088929 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 125586.088929 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 135784.054123 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 135784.054123 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 129573.716811 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 129573.716811 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 129573.716811 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 129573.716811 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9991 # number of writebacks +system.cpu2.l1c.writebacks::total 9991 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36203 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36203 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23173 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23173 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 59376 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 59376 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 59376 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 59376 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 4568956719 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 4568956719 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 3080855782 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 3080855782 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 7649812501 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 7649812501 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 7649812501 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 7649812501 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1362583834 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1362583834 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 971805765 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 971805765 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2334389599 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2334389599 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805352 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805352 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.949091 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.949091 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.855944 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.855944 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.855944 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.855944 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 126203.815126 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 126203.815126 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 132950.234411 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 132950.234411 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 128836.777503 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 128836.777503 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 128836.777503 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 128836.777503 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -1001,114 +1001,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 100000 # number of read accesses completed -system.cpu3.num_writes 53600 # number of write accesses completed +system.cpu3.num_reads 98308 # number of read accesses completed +system.cpu3.num_writes 52892 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.replacements 22673 # number of replacements -system.cpu3.l1c.tagsinuse 391.747074 # Cycle average of tags in use -system.cpu3.l1c.total_refs 13403 # Total number of references to valid blocks. -system.cpu3.l1c.sampled_refs 23070 # Sample count of references to valid blocks. -system.cpu3.l1c.avg_refs 0.580971 # Average number of references to valid blocks. +system.cpu3.l1c.replacements 21879 # number of replacements +system.cpu3.l1c.tagsinuse 388.243829 # Cycle average of tags in use +system.cpu3.l1c.total_refs 13269 # Total number of references to valid blocks. +system.cpu3.l1c.sampled_refs 22290 # Sample count of references to valid blocks. +system.cpu3.l1c.avg_refs 0.595289 # Average number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.occ_blocks::cpu3 391.747074 # Average occupied blocks per requestor -system.cpu3.l1c.occ_percent::cpu3 0.765131 # Average percentage of cache occupancy -system.cpu3.l1c.occ_percent::total 0.765131 # Average percentage of cache occupancy -system.cpu3.l1c.ReadReq_hits::cpu3 8720 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8720 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1143 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1143 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9863 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9863 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9863 # number of overall hits -system.cpu3.l1c.overall_hits::total 9863 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36203 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36203 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 22978 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 22978 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 59181 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 59181 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 59181 # number of overall misses -system.cpu3.l1c.overall_misses::total 59181 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 4605371729 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 4605371729 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 3121949330 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 3121949330 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 7727321059 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 7727321059 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 7727321059 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 7727321059 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44923 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44923 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24121 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24121 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 69044 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 69044 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 69044 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 69044 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805890 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.805890 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.952614 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.952614 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.857149 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.857149 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.857149 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.857149 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 127209.671270 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 127209.671270 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 135866.887022 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 135866.887022 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 130570.978169 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 130570.978169 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 130570.978169 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 130570.978169 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 721076565 # number of cycles access was blocked +system.cpu3.l1c.occ_blocks::cpu3 388.243829 # Average occupied blocks per requestor +system.cpu3.l1c.occ_percent::cpu3 0.758289 # Average percentage of cache occupancy +system.cpu3.l1c.occ_percent::total 0.758289 # Average percentage of cache occupancy +system.cpu3.l1c.ReadReq_hits::cpu3 8771 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8771 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1066 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1066 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9837 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9837 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9837 # number of overall hits +system.cpu3.l1c.overall_hits::total 9837 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 35672 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 35672 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 22858 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 22858 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 58530 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 58530 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 58530 # number of overall misses +system.cpu3.l1c.overall_misses::total 58530 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 4705192371 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 4705192371 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 3092503889 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 3092503889 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 7797696260 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 7797696260 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 7797696260 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 7797696260 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 44443 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 44443 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 23924 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 23924 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 68367 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 68367 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 68367 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 68367 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.802646 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.802646 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955442 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.955442 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.856115 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.856115 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.856115 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.856115 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 131901.557832 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 131901.557832 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 135291.971695 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 135291.971695 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 133225.632325 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 133225.632325 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 133225.632325 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 133225.632325 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1411864 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 64491 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 63831 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 11181.041773 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 22.118782 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9961 # number of writebacks -system.cpu3.l1c.writebacks::total 9961 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36203 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36203 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22978 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 22978 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 59181 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 59181 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 59181 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 59181 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 4532659362 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 4532659362 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 3075925984 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 3075925984 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 7608585346 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 7608585346 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 7608585346 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 7608585346 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 1393944138 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 1393944138 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 919834390 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 919834390 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2313778528 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2313778528 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805890 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805890 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.952614 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.952614 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.857149 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.857149 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.857149 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.857149 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 125201.208795 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 125201.208795 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 133863.956132 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 133863.956132 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 128564.663422 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 128564.663422 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 128564.663422 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 128564.663422 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9578 # number of writebacks +system.cpu3.l1c.writebacks::total 9578 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35672 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 35672 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22858 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 22858 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 58530 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 58530 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 58530 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 58530 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 4633860371 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 4633860371 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 3046797889 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 3046797889 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 7680658260 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 7680658260 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 7680658260 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 7680658260 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 1383140389 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 1383140389 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 919277948 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 919277948 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2302418337 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2302418337 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.802646 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.802646 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955442 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955442 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.856115 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.856115 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.856115 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.856115 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 129901.894231 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 129901.894231 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 133292.409178 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 133292.409178 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 131226.008201 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 131226.008201 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 131226.008201 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 131226.008201 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -1116,114 +1116,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99186 # number of read accesses completed -system.cpu4.num_writes 53232 # number of write accesses completed +system.cpu4.num_reads 99646 # number of read accesses completed +system.cpu4.num_writes 53184 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.replacements 22556 # number of replacements -system.cpu4.l1c.tagsinuse 391.523203 # Cycle average of tags in use -system.cpu4.l1c.total_refs 13363 # Total number of references to valid blocks. -system.cpu4.l1c.sampled_refs 22976 # Sample count of references to valid blocks. -system.cpu4.l1c.avg_refs 0.581607 # Average number of references to valid blocks. +system.cpu4.l1c.replacements 22486 # number of replacements +system.cpu4.l1c.tagsinuse 389.564427 # Cycle average of tags in use +system.cpu4.l1c.total_refs 13323 # Total number of references to valid blocks. +system.cpu4.l1c.sampled_refs 22871 # Sample count of references to valid blocks. +system.cpu4.l1c.avg_refs 0.582528 # Average number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.occ_blocks::cpu4 391.523203 # Average occupied blocks per requestor -system.cpu4.l1c.occ_percent::cpu4 0.764694 # Average percentage of cache occupancy -system.cpu4.l1c.occ_percent::total 0.764694 # Average percentage of cache occupancy -system.cpu4.l1c.ReadReq_hits::cpu4 8704 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8704 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1177 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1177 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9881 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9881 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9881 # number of overall hits -system.cpu4.l1c.overall_hits::total 9881 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 35925 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 35925 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 22955 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 22955 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 58880 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 58880 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 58880 # number of overall misses -system.cpu4.l1c.overall_misses::total 58880 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 4605243494 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 4605243494 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 3106119837 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 3106119837 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 7711363331 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 7711363331 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 7711363331 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 7711363331 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 44629 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 44629 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24132 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24132 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 68761 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 68761 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 68761 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 68761 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.804970 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.804970 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.951227 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.951227 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.856299 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.856299 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.856299 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.856299 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 128190.493918 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 128190.493918 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 135313.432237 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 135313.432237 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 130967.447877 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 130967.447877 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 130967.447877 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 130967.447877 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 718630789 # number of cycles access was blocked +system.cpu4.l1c.occ_blocks::cpu4 389.564427 # Average occupied blocks per requestor +system.cpu4.l1c.occ_percent::cpu4 0.760868 # Average percentage of cache occupancy +system.cpu4.l1c.occ_percent::total 0.760868 # Average percentage of cache occupancy +system.cpu4.l1c.ReadReq_hits::cpu4 8662 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8662 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1144 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1144 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9806 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9806 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9806 # number of overall hits +system.cpu4.l1c.overall_hits::total 9806 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36129 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36129 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 22914 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 22914 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 59043 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 59043 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 59043 # number of overall misses +system.cpu4.l1c.overall_misses::total 59043 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 4597368029 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 4597368029 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 3131496490 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 3131496490 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 7728864519 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 7728864519 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 7728864519 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 7728864519 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44791 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44791 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24058 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24058 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 68849 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 68849 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 68849 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 68849 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.806613 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.806613 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952448 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.952448 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.857572 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.857572 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.857572 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.857572 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 127248.692989 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 127248.692989 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 136663.022170 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 136663.022170 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 130902.300340 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 130902.300340 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 130902.300340 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 130902.300340 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1409065 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 64157 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 64552 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 11201.128310 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 21.828371 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9838 # number of writebacks -system.cpu4.l1c.writebacks::total 9838 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35925 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 35925 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 22955 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 22955 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 58880 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 58880 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 58880 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 58880 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 4533093127 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 4533093127 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 3060147977 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 3060147977 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 7593241104 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 7593241104 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 7593241104 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 7593241104 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 1402247556 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 1402247556 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 894394941 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 894394941 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2296642497 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2296642497 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.804970 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804970 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.951227 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.951227 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.856299 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.856299 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.856299 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.856299 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 126182.132971 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 126182.132971 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 133310.737399 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 133310.737399 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 128961.295924 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 128961.295924 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 128961.295924 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 128961.295924 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9768 # number of writebacks +system.cpu4.l1c.writebacks::total 9768 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36129 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36129 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 22914 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 22914 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 59043 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 59043 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 59043 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 59043 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 4525124029 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 4525124029 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 3085672490 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 3085672490 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 7610796519 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 7610796519 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 7610796519 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 7610796519 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 1426221714 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 1426221714 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 886330386 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 886330386 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2312552100 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2312552100 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.806613 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.806613 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952448 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952448 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857572 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.857572 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857572 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.857572 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 125249.080489 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 125249.080489 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 134663.196736 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 134663.196736 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 128902.605203 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 128902.605203 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 128902.605203 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 128902.605203 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -1231,114 +1231,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99811 # number of read accesses completed -system.cpu5.num_writes 54122 # number of write accesses completed +system.cpu5.num_reads 99510 # number of read accesses completed +system.cpu5.num_writes 53712 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.replacements 22776 # number of replacements -system.cpu5.l1c.tagsinuse 391.477551 # Cycle average of tags in use -system.cpu5.l1c.total_refs 13322 # Total number of references to valid blocks. -system.cpu5.l1c.sampled_refs 23147 # Sample count of references to valid blocks. -system.cpu5.l1c.avg_refs 0.575539 # Average number of references to valid blocks. +system.cpu5.l1c.replacements 22704 # number of replacements +system.cpu5.l1c.tagsinuse 391.715809 # Cycle average of tags in use +system.cpu5.l1c.total_refs 13238 # Total number of references to valid blocks. +system.cpu5.l1c.sampled_refs 23109 # Sample count of references to valid blocks. +system.cpu5.l1c.avg_refs 0.572850 # Average number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.occ_blocks::cpu5 391.477551 # Average occupied blocks per requestor -system.cpu5.l1c.occ_percent::cpu5 0.764605 # Average percentage of cache occupancy -system.cpu5.l1c.occ_percent::total 0.764605 # Average percentage of cache occupancy -system.cpu5.l1c.ReadReq_hits::cpu5 8701 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8701 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1178 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1178 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9879 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9879 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9879 # number of overall hits -system.cpu5.l1c.overall_hits::total 9879 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36192 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36192 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23103 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23103 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 59295 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 59295 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 59295 # number of overall misses -system.cpu5.l1c.overall_misses::total 59295 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 4578113743 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 4578113743 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 3131851801 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 3131851801 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 7709965544 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 7709965544 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 7709965544 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 7709965544 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44893 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44893 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24281 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24281 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 69174 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 69174 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 69174 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 69174 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806184 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.806184 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.951485 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.951485 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.857186 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.857186 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.857186 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.857186 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 126495.185207 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 126495.185207 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 135560.394797 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 135560.394797 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 130027.245872 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 130027.245872 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 130027.245872 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 130027.245872 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 718707273 # number of cycles access was blocked +system.cpu5.l1c.occ_blocks::cpu5 391.715809 # Average occupied blocks per requestor +system.cpu5.l1c.occ_percent::cpu5 0.765070 # Average percentage of cache occupancy +system.cpu5.l1c.occ_percent::total 0.765070 # Average percentage of cache occupancy +system.cpu5.l1c.ReadReq_hits::cpu5 8676 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8676 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1153 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1153 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9829 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9829 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9829 # number of overall hits +system.cpu5.l1c.overall_hits::total 9829 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36073 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36073 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23060 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23060 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 59133 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 59133 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 59133 # number of overall misses +system.cpu5.l1c.overall_misses::total 59133 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 4612203646 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 4612203646 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 3154708419 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 3154708419 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 7766912065 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 7766912065 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 7766912065 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 7766912065 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44749 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44749 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24213 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24213 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 68962 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 68962 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 68962 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 68962 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806119 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.806119 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952381 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.952381 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.857472 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.857472 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.857472 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.857472 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 127857.501344 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 127857.501344 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 136804.354683 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 136804.354683 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 131346.491215 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 131346.491215 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 131346.491215 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 131346.491215 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1402922 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 64475 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 64326 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 11147.068988 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 21.809564 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 10068 # number of writebacks -system.cpu5.l1c.writebacks::total 10068 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36192 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36192 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23103 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23103 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 59295 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 59295 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 59295 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 59295 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 4505401434 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 4505401434 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 3085574966 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 3085574966 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 7590976400 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 7590976400 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 7590976400 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 7590976400 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 1396623229 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 1396623229 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 970059681 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 970059681 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2366682910 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2366682910 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806184 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806184 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.951485 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.951485 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.857186 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.857186 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.857186 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.857186 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 124486.113893 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 124486.113893 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 133557.328745 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 133557.328745 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 128020.514377 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 128020.514377 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 128020.514377 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 128020.514377 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9873 # number of writebacks +system.cpu5.l1c.writebacks::total 9873 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36073 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36073 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23060 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23060 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 59133 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 59133 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 59133 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 59133 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 4540061646 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 4540061646 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 3108604419 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 3108604419 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 7648666065 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 7648666065 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 7648666065 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 7648666065 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 1397826307 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 1397826307 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 952355893 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 952355893 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2350182200 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2350182200 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806119 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806119 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952381 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952381 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.857472 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.857472 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.857472 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.857472 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 125857.612231 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 125857.612231 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 134805.048526 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 134805.048526 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 129346.829435 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 129346.829435 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 129346.829435 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 129346.829435 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -1346,114 +1346,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 96701 # number of read accesses completed -system.cpu6.num_writes 52167 # number of write accesses completed +system.cpu6.num_reads 99341 # number of read accesses completed +system.cpu6.num_writes 53460 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.replacements 21524 # number of replacements -system.cpu6.l1c.tagsinuse 387.796217 # Cycle average of tags in use -system.cpu6.l1c.total_refs 12859 # Total number of references to valid blocks. -system.cpu6.l1c.sampled_refs 21936 # Sample count of references to valid blocks. -system.cpu6.l1c.avg_refs 0.586205 # Average number of references to valid blocks. +system.cpu6.l1c.replacements 22728 # number of replacements +system.cpu6.l1c.tagsinuse 391.033952 # Cycle average of tags in use +system.cpu6.l1c.total_refs 13418 # Total number of references to valid blocks. +system.cpu6.l1c.sampled_refs 23126 # Sample count of references to valid blocks. +system.cpu6.l1c.avg_refs 0.580213 # Average number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.occ_blocks::cpu6 387.796217 # Average occupied blocks per requestor -system.cpu6.l1c.occ_percent::cpu6 0.757414 # Average percentage of cache occupancy -system.cpu6.l1c.occ_percent::total 0.757414 # Average percentage of cache occupancy -system.cpu6.l1c.ReadReq_hits::cpu6 8329 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8329 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1106 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1106 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9435 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9435 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9435 # number of overall hits -system.cpu6.l1c.overall_hits::total 9435 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 35191 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 35191 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 22544 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 22544 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 57735 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 57735 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 57735 # number of overall misses -system.cpu6.l1c.overall_misses::total 57735 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 4508353371 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 4508353371 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 3154254558 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 3154254558 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 7662607929 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 7662607929 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 7662607929 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 7662607929 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 43520 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 43520 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 23650 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 23650 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 67170 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 67170 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 67170 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 67170 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808617 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.808617 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953235 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.953235 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.859536 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.859536 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.859536 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.859536 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 128110.976414 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 128110.976414 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 139915.478974 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 139915.478974 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 132720.324396 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 132720.324396 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 132720.324396 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 132720.324396 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 719066693 # number of cycles access was blocked +system.cpu6.l1c.occ_blocks::cpu6 391.033952 # Average occupied blocks per requestor +system.cpu6.l1c.occ_percent::cpu6 0.763738 # Average percentage of cache occupancy +system.cpu6.l1c.occ_percent::total 0.763738 # Average percentage of cache occupancy +system.cpu6.l1c.ReadReq_hits::cpu6 8762 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8762 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1095 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1095 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9857 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9857 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9857 # number of overall hits +system.cpu6.l1c.overall_hits::total 9857 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 35979 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 35979 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23081 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23081 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 59060 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 59060 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 59060 # number of overall misses +system.cpu6.l1c.overall_misses::total 59060 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 4670056241 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 4670056241 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 3140122564 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 3140122564 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 7810178805 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 7810178805 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 7810178805 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 7810178805 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 44741 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 44741 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24176 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24176 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 68917 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 68917 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 68917 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 68917 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.804162 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.804162 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954707 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954707 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.856973 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.856973 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.856973 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.856973 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 129799.500848 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 129799.500848 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 136047.942637 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 136047.942637 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 132241.429140 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 132241.429140 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 132241.429140 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 132241.429140 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1402385 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 62816 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 64109 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 11447.190095 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 21.875010 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9499 # number of writebacks -system.cpu6.l1c.writebacks::total 9499 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 35191 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 35191 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 22544 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 22544 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 57735 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 57735 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 57735 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 57735 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 4437636067 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 4437636067 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 3109111203 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 3109111203 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 7546747270 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 7546747270 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 7546747270 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 7546747270 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 1416513847 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 1416513847 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 907986926 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 907986926 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2324500773 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2324500773 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808617 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808617 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953235 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953235 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859536 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.859536 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859536 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.859536 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 126101.448296 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 126101.448296 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 137913.023554 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 137913.023554 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 130713.557980 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 130713.557980 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 130713.557980 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 130713.557980 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9866 # number of writebacks +system.cpu6.l1c.writebacks::total 9866 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 35979 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 35979 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23081 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23081 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 59060 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 59060 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 59060 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 59060 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 4598108241 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 4598108241 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 3093974564 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 3093974564 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 7692082805 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 7692082805 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 7692082805 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 7692082805 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 1335573448 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 1335573448 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 977750934 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 977750934 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2313324382 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2313324382 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.804162 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.804162 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954707 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954707 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.856973 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.856973 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.856973 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.856973 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 127799.778788 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 127799.778788 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 134048.549196 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 134048.549196 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 130241.835506 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 130241.835506 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 130241.835506 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 130241.835506 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -1461,114 +1461,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 98233 # number of read accesses completed -system.cpu7.num_writes 53134 # number of write accesses completed +system.cpu7.num_reads 99191 # number of read accesses completed +system.cpu7.num_writes 53936 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.replacements 22239 # number of replacements -system.cpu7.l1c.tagsinuse 390.077286 # Cycle average of tags in use -system.cpu7.l1c.total_refs 13228 # Total number of references to valid blocks. -system.cpu7.l1c.sampled_refs 22658 # Sample count of references to valid blocks. -system.cpu7.l1c.avg_refs 0.583811 # Average number of references to valid blocks. +system.cpu7.l1c.replacements 22510 # number of replacements +system.cpu7.l1c.tagsinuse 390.052988 # Cycle average of tags in use +system.cpu7.l1c.total_refs 13451 # Total number of references to valid blocks. +system.cpu7.l1c.sampled_refs 22924 # Sample count of references to valid blocks. +system.cpu7.l1c.avg_refs 0.586765 # Average number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.occ_blocks::cpu7 390.077286 # Average occupied blocks per requestor -system.cpu7.l1c.occ_percent::cpu7 0.761870 # Average percentage of cache occupancy -system.cpu7.l1c.occ_percent::total 0.761870 # Average percentage of cache occupancy -system.cpu7.l1c.ReadReq_hits::cpu7 8637 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8637 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1096 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1096 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9733 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9733 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9733 # number of overall hits -system.cpu7.l1c.overall_hits::total 9733 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 35699 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 35699 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 22823 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 22823 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 58522 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 58522 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 58522 # number of overall misses -system.cpu7.l1c.overall_misses::total 58522 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 4580220165 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 4580220165 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 3149286383 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 3149286383 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 7729506548 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 7729506548 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 7729506548 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 7729506548 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44336 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44336 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 23919 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 23919 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 68255 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 68255 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 68255 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 68255 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805192 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.805192 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954179 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.954179 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.857402 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.857402 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.857402 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.857402 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 128301.077481 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 128301.077481 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 137987.397932 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 137987.397932 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 132078.646458 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 132078.646458 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 132078.646458 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 132078.646458 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 716139762 # number of cycles access was blocked +system.cpu7.l1c.occ_blocks::cpu7 390.052988 # Average occupied blocks per requestor +system.cpu7.l1c.occ_percent::cpu7 0.761822 # Average percentage of cache occupancy +system.cpu7.l1c.occ_percent::total 0.761822 # Average percentage of cache occupancy +system.cpu7.l1c.ReadReq_hits::cpu7 8796 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8796 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1169 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1169 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9965 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9965 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9965 # number of overall hits +system.cpu7.l1c.overall_hits::total 9965 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 35920 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 35920 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23167 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23167 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 59087 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 59087 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 59087 # number of overall misses +system.cpu7.l1c.overall_misses::total 59087 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 4583534857 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 4583534857 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 3157115869 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 3157115869 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 7740650726 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 7740650726 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 7740650726 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 7740650726 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 44716 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 44716 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24336 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24336 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 69052 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 69052 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 69052 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 69052 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.803292 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.803292 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.951964 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.951964 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.855688 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.855688 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.855688 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.855688 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 127603.977088 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 127603.977088 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 136276.422023 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 136276.422023 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 131004.294109 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 131004.294109 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 131004.294109 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 131004.294109 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1403287 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 63505 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 64246 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 11276.903582 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 21.842403 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9791 # number of writebacks -system.cpu7.l1c.writebacks::total 9791 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35699 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 35699 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 22823 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 22823 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 58522 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 58522 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 58522 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 58522 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 4508506825 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 4508506825 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 3103586023 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 3103586023 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 7612092848 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 7612092848 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 7612092848 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 7612092848 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 1364395277 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 1364395277 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 924938405 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 924938405 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2289333682 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2289333682 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805192 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805192 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954179 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954179 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857402 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.857402 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857402 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.857402 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 126292.244181 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 126292.244181 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 135985.016124 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 135985.016124 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 130072.329175 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 130072.329175 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 130072.329175 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 130072.329175 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9883 # number of writebacks +system.cpu7.l1c.writebacks::total 9883 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35920 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 35920 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23167 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23167 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 59087 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 59087 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 59087 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 59087 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 4511708857 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 4511708857 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 3110789869 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 3110789869 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 7622498726 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 7622498726 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 7622498726 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 7622498726 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 1423430289 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 1423430289 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 942416285 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 942416285 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2365846574 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2365846574 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.803292 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.803292 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.951964 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.951964 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.855688 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.855688 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.855688 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.855688 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 125604.366843 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 125604.366843 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 134276.767341 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 134276.767341 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 129004.666441 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 129004.666441 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 129004.666441 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 129004.666441 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency |