diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
| commit | f2e2410a505ef48516f121ce1b2232ba7aa389af (patch) | |
| tree | dbe4c8482b37e854302410318fc474f507310724 /tests/quick/se | |
| parent | 184c6d7ebd7faa0869f294526a54a239a216b7c8 (diff) | |
| download | gem5-f2e2410a505ef48516f121ce1b2232ba7aa389af.tar.xz | |
stats: Get all stats updated to reflect current behaviour
Line everything up again.
Diffstat (limited to 'tests/quick/se')
34 files changed, 10511 insertions, 9418 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index e5561895a..112157b30 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000041 # Nu sim_ticks 41083000 # Number of ticks simulated final_tick 41083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 217103 # Simulator instruction rate (inst/s) -host_op_rate 217013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1389706699 # Simulator tick rate (ticks/s) -host_mem_usage 253264 # Number of bytes of host memory used +host_inst_rate 202272 # Simulator instruction rate (inst/s) +host_op_rate 202193 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1294825774 # Simulator tick rate (ticks/s) +host_mem_usage 252636 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host sim_insts 6413 # Number of instructions simulated sim_ops 6413 # Number of ops (including micro ops) simulated @@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 3 3.30% 84.62% # By system.physmem.bytesPerActivate::896-1023 8 8.79% 93.41% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 6 6.59% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 91 # Bytes accessed per row activation -system.physmem.totQLat 6580250 # Total ticks spent queuing -system.physmem.totMemAccLat 16555250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 6584250 # Total ticks spent queuing +system.physmem.totMemAccLat 16559250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2660000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12368.89 # Average queueing delay per DRAM burst +system.physmem.avgQLat 12376.41 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31118.89 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31126.41 # Average memory access latency per DRAM burst system.physmem.avgRdBW 828.76 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 828.76 # Average system read bandwidth in MiByte/s @@ -247,9 +247,9 @@ system.physmem_1.preEnergy 208725 # En system.physmem_1.readEnergy 1842120 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4022490 # Energy for active background per rank (pJ) +system.physmem_1.actBackEnergy 4023060 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 174720 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 14292750 # Energy for active power-down per rank (pJ) +system.physmem_1.actPowerDownEnergy 14292180 # Energy for active power-down per rank (pJ) system.physmem_1.prePowerDownEnergy 178080 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_1.totalEnergy 24213345 # Total energy per rank (pJ) @@ -262,19 +262,19 @@ system.physmem_1.memoryStateTime::PRE_PDN 464250 # T system.physmem_1.memoryStateTime::ACT 7679500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 31350750 # Time in different power states system.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2003 # Number of BP lookups -system.cpu.branchPred.condPredicted 1238 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1605 # Number of BTB lookups +system.cpu.branchPred.lookups 2002 # Number of BP lookups +system.cpu.branchPred.condPredicted 1237 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 378 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1602 # Number of BTB lookups system.cpu.branchPred.BTBHits 377 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 23.489097 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 235 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 23.533084 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 234 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 335 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 322 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 113 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 333 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 14 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 319 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 114 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -292,10 +292,10 @@ system.cpu.dtb.data_hits 2249 # DT system.cpu.dtb.data_misses 14 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 2263 # DTB accesses -system.cpu.itb.fetch_hits 2686 # ITB hits +system.cpu.itb.fetch_hits 2685 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2703 # ITB accesses +system.cpu.itb.fetch_accesses 2702 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -315,7 +315,7 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6413 # Number of instructions committed system.cpu.committedOps 6413 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1095 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1093 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 12.812412 # CPI: cycles per instruction system.cpu.ipc 0.078049 # IPC: instructions per cycle @@ -358,18 +358,18 @@ system.cpu.op_class_0::FloatMemWrite 7 0.11% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 6413 # Class of committed instruction -system.cpu.tickCycles 12644 # Number of cycles that the object actually ticked -system.cpu.idleCycles 69522 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 12637 # Number of cycles that the object actually ticked +system.cpu.idleCycles 69529 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.984752 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.987673 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1990 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.775148 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.984752 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025387 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025387 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.987673 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025388 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025388 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id @@ -395,12 +395,12 @@ system.cpu.dcache.overall_misses::cpu.data 221 # system.cpu.dcache.overall_misses::total 221 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 8545500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 8545500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10429000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10429000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18974500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18974500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18974500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18974500 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10428500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10428500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18974000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18974000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18974000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18974000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1346 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1346 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -419,12 +419,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.099955 system.cpu.dcache.overall_miss_rate::total 0.099955 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89015.625000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 89015.625000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83432 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 83432 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 85857.466063 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 85857.466063 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83428 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 83428 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 85855.203620 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 85855.203620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 85855.203620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 85855.203620 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,12 +447,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 169 system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8449500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 8449500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6089500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6089500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14539000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14539000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14539000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14539000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6089000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6089000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14538500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14538500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14538500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14538500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071322 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071322 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -463,65 +463,65 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076436 system.cpu.dcache.overall_mshr_miss_rate::total 0.076436 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88015.625000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88015.625000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83417.808219 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83417.808219 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83410.958904 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83410.958904 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86026.627219 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 86026.627219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86026.627219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 86026.627219 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 175.153182 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2322 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 175.158440 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2321 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 364 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.379121 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.376374 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 175.153182 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085524 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085524 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 175.158440 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085527 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085527 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 271 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.177734 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 5736 # Number of tag accesses -system.cpu.icache.tags.data_accesses 5736 # Number of data accesses +system.cpu.icache.tags.tag_accesses 5734 # Number of tag accesses +system.cpu.icache.tags.data_accesses 5734 # Number of data accesses system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 2322 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2322 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2322 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2322 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2322 # number of overall hits -system.cpu.icache.overall_hits::total 2322 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 2321 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2321 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2321 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2321 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2321 # number of overall hits +system.cpu.icache.overall_hits::total 2321 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30317500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30317500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30317500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30317500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30317500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30317500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2686 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2686 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2686 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2686 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2686 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2686 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.135517 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.135517 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.135517 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.135517 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.135517 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.135517 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83289.835165 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 83289.835165 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 83289.835165 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 83289.835165 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 83289.835165 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 83289.835165 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30321500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30321500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30321500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30321500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30321500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30321500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2685 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2685 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2685 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2685 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2685 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2685 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.135568 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.135568 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.135568 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.135568 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.135568 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.135568 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83300.824176 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 83300.824176 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 83300.824176 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 83300.824176 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 83300.824176 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 83300.824176 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -534,33 +534,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 364 system.cpu.icache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 364 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29953500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 29953500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29953500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 29953500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29953500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 29953500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135517 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.135517 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.135517 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82289.835165 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82289.835165 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29957500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 29957500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29957500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 29957500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29957500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 29957500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135568 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135568 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135568 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.135568 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135568 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.135568 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82300.824176 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82300.824176 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82300.824176 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 82300.824176 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82300.824176 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 82300.824176 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 279.180738 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 279.188916 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 532 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.001880 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.152793 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 104.027945 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.158050 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 104.030866 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005345 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.003175 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.008520 # Average percentage of cache occupancy @@ -589,18 +589,18 @@ system.cpu.l2cache.demand_misses::total 532 # nu system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses system.cpu.l2cache.overall_misses::total 532 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5980000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5980000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29396000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 29396000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5979500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5979500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29400000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 29400000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8304000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 8304000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 29396000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 14284000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 43680000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 29396000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 14284000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 43680000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 29400000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 14283500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 43683500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 29400000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 14283500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 43683500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 364 # number of ReadCleanReq accesses(hits+misses) @@ -625,18 +625,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.998124 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997253 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.998124 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81917.808219 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81917.808219 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80980.716253 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80980.716253 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81910.958904 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81910.958904 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80991.735537 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80991.735537 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86500 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80980.716253 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84520.710059 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82105.263158 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80980.716253 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84520.710059 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82105.263158 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80991.735537 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84517.751479 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82111.842105 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80991.735537 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84517.751479 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82111.842105 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -655,18 +655,18 @@ system.cpu.l2cache.demand_mshr_misses::total 532 system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 532 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5250000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5250000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25766000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25766000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5249500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5249500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25770000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25770000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7344000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7344000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25766000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12594000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 38360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25766000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12594000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 38360000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25770000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12593500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 38363500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25770000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12593500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 38363500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for ReadCleanReq accesses @@ -679,18 +679,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.998124 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998124 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71917.808219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71917.808219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70980.716253 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70980.716253 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71910.958904 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71910.958904 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70991.735537 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70991.735537 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76500 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70991.735537 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74517.751479 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72111.842105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70991.735537 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74517.751479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72111.842105 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -755,7 +755,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 532 # Request fanout histogram -system.membus.reqLayer0.occupancy 607500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 607000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) system.membus.respLayer1.occupancy 2825000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 6.9 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 3af1cbc4b..c57cc4c2c 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,47 +4,47 @@ sim_seconds 0.000024 # Nu sim_ticks 23776000 # Number of ticks simulated final_tick 23776000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 4743 # Simulator instruction rate (inst/s) -host_op_rate 4743 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17659718 # Simulator tick rate (ticks/s) -host_mem_usage 236044 # Number of bytes of host memory used -host_seconds 1.35 # Real time elapsed on the host +host_inst_rate 135386 # Simulator instruction rate (inst/s) +host_op_rate 135348 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 503875461 # Simulator tick rate (ticks/s) +host_mem_usage 253920 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 6385 # Number of instructions simulated sim_ops 6385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 19904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory -system.physmem.bytes_read::total 31040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 30976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19904 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 311 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory -system.physmem.num_reads::total 485 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 839838493 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 484 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 837146703 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 465679677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1305518170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 839838493 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 839838493 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 839838493 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 1302826380 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 837146703 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 837146703 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 837146703 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 465679677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1305518170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 485 # Number of read requests accepted +system.physmem.bw_total::total 1302826380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 484 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 485 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 484 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 31040 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 30976 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 31040 # Total read bytes from the system interface side +system.physmem.bytesReadSys 30976 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 69 # Per bank write bursts system.physmem.perBankRdBursts::1 32 # Per bank write bursts -system.physmem.perBankRdBursts::2 33 # Per bank write bursts +system.physmem.perBankRdBursts::2 32 # Per bank write bursts system.physmem.perBankRdBursts::3 47 # Per bank write bursts system.physmem.perBankRdBursts::4 42 # Per bank write bursts system.physmem.perBankRdBursts::5 20 # Per bank write bursts @@ -83,7 +83,7 @@ system.physmem.readPktSize::2 0 # Re system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 485 # Read request sizes (log2) +system.physmem.readPktSize::6 484 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -92,7 +92,7 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 141 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 140 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see @@ -188,9 +188,9 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 89 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.044944 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 230.274346 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 313.082327 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 347.325843 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 230.027877 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 312.328054 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 21 23.60% 23.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 22 24.72% 48.31% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 15 16.85% 65.17% # Bytes accessed per row activation @@ -201,101 +201,101 @@ system.physmem.bytesPerActivate::768-895 2 2.25% 87.64% # By system.physmem.bytesPerActivate::896-1023 1 1.12% 88.76% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 11.24% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation -system.physmem.totQLat 8008750 # Total ticks spent queuing -system.physmem.totMemAccLat 17102500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2425000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16512.89 # Average queueing delay per DRAM burst +system.physmem.totQLat 8020750 # Total ticks spent queuing +system.physmem.totMemAccLat 17095750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2420000 # Total ticks spent in databus transfers +system.physmem.avgQLat 16571.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35262.89 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1305.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 35321.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1302.83 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1305.52 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1302.83 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.20 # Data bus utilization in percentage -system.physmem.busUtilRead 10.20 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.18 # Data bus utilization in percentage +system.physmem.busUtilRead 10.18 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 395 # Number of row buffer hits during reads +system.physmem.readRowHits 394 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.40 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 48208.25 # Average gap between requests -system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined +system.physmem.avgGap 48307.85 # Average gap between requests +system.physmem.pageHitRate 81.40 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 242760 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 125235 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1763580 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 1756440 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3004470 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 7623750 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 132480 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actBackEnergy 3000480 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 47040 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 7630020 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 131040 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 14783715 # Total energy per rank (pJ) -system.physmem_0.averagePower 621.784975 # Core power per rank (mW) -system.physmem_0.totalIdleTime 16958250 # Total Idle time Per DRAM Rank +system.physmem_0.totalEnergy 14776935 # Total energy per rank (pJ) +system.physmem_0.averagePower 621.499816 # Core power per rank (mW) +system.physmem_0.totalIdleTime 16971750 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 344500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5899500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 16711500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 340500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5886000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 16729000 # Time in different power states system.physmem_1.actEnergy 399840 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 212520 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1699320 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2978250 # Energy for active background per rank (pJ) +system.physmem_1.actBackEnergy 2975400 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 130080 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 7628310 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 68160 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actPowerDownEnergy 7630590 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 68640 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 14960400 # Total energy per rank (pJ) -system.physmem_1.averagePower 629.216130 # Core power per rank (mW) -system.physmem_1.totalIdleTime 16769000 # Total Idle time Per DRAM Rank +system.physmem_1.totalEnergy 14960310 # Total energy per rank (pJ) +system.physmem_1.averagePower 629.212344 # Core power per rank (mW) +system.physmem_1.totalIdleTime 16765250 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 214000 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 178500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 5875500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 16728000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 5879250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 16724250 # Time in different power states system.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2854 # Number of BP lookups -system.cpu.branchPred.condPredicted 1681 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2203 # Number of BTB lookups -system.cpu.branchPred.BTBHits 713 # Number of BTB hits +system.cpu.branchPred.lookups 2851 # Number of BP lookups +system.cpu.branchPred.condPredicted 1679 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 484 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2196 # Number of BTB lookups +system.cpu.branchPred.BTBHits 719 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.364957 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 441 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 32.741348 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 42 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 462 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 461 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 25 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 437 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 436 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 123 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2252 # DTB read hits +system.cpu.dtb.read_hits 2241 # DTB read hits system.cpu.dtb.read_misses 48 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2300 # DTB read accesses -system.cpu.dtb.write_hits 1038 # DTB write hits +system.cpu.dtb.read_accesses 2289 # DTB read accesses +system.cpu.dtb.write_hits 1046 # DTB write hits system.cpu.dtb.write_misses 28 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1066 # DTB write accesses -system.cpu.dtb.data_hits 3290 # DTB hits +system.cpu.dtb.write_accesses 1074 # DTB write accesses +system.cpu.dtb.data_hits 3287 # DTB hits system.cpu.dtb.data_misses 76 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3366 # DTB accesses -system.cpu.itb.fetch_hits 2295 # ITB hits +system.cpu.dtb.data_accesses 3363 # DTB accesses +system.cpu.itb.fetch_hits 2298 # ITB hits system.cpu.itb.fetch_misses 27 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2322 # ITB accesses +system.cpu.itb.fetch_accesses 2325 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -313,240 +313,240 @@ system.cpu.pwrStateResidencyTicks::ON 23776000 # Cu system.cpu.numCycles 47553 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8498 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16559 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2854 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5759 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1046 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 8497 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16552 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2851 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1186 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 5772 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1050 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 656 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2295 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 335 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15458 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.071225 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.458645 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2298 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15472 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.069804 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.455665 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 12472 80.68% 80.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 297 1.92% 82.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 230 1.49% 84.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 258 1.67% 85.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 292 1.89% 87.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 234 1.51% 89.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 282 1.82% 90.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 146 0.94% 91.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1247 8.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12480 80.66% 80.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 299 1.93% 82.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 231 1.49% 84.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 265 1.71% 85.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 295 1.91% 87.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 231 1.49% 89.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 280 1.81% 91.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 147 0.95% 91.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1244 8.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15458 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.060017 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.348222 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8341 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4008 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2446 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 214 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 449 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 226 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 15472 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.059954 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.348075 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8344 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4012 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2454 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 211 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 451 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 754 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15004 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 14992 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 221 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 449 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8500 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1841 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 451 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8504 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1836 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 655 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2476 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1537 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14448 # Number of instructions processed by rename +system.cpu.rename.RunCycles 2480 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1546 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14425 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1471 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 10929 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17896 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17887 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1479 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 10912 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17882 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17873 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4577 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6352 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6335 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 28 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 585 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2834 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1292 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 18 # Number of conflicting loads. +system.cpu.rename.skidInsts 586 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2823 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1299 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 17 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 13054 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 13035 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10776 # Number of instructions issued +system.cpu.iq.iqInstsIssued 10770 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6695 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3669 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 6676 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3655 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15458 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.697115 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.442161 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15472 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.696096 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.440906 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11418 73.86% 73.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1297 8.39% 82.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 916 5.93% 88.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 681 4.41% 92.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 517 3.34% 95.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 347 2.24% 98.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 200 1.29% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.36% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 27 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11426 73.85% 73.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1307 8.45% 82.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 919 5.94% 88.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 676 4.37% 92.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 515 3.33% 95.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 346 2.24% 98.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 202 1.31% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 53 0.34% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 28 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15458 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15472 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 21 14.89% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 83 58.87% 73.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 36 25.53% 99.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 1 0.71% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 21 14.79% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 83 58.45% 73.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 37 26.06% 99.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 1 0.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7185 66.68% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2474 22.96% 89.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1104 10.24% 99.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7179 66.66% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2465 22.89% 89.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1113 10.33% 99.93% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 1 0.01% 99.94% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 7 0.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10776 # Type of FU issued -system.cpu.iq.rate 0.226610 # Inst issue rate -system.cpu.iq.fu_busy_cnt 141 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013085 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 37147 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19787 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9745 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10770 # Type of FU issued +system.cpu.iq.rate 0.226484 # Inst issue rate +system.cpu.iq.fu_busy_cnt 142 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013185 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 37150 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19749 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9744 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10904 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10899 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 119 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1649 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1638 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 23 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 427 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 434 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 78 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 449 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1429 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 451 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1424 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 338 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13165 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 13146 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2834 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1292 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2823 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1299 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 331 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 23 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 497 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10290 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2300 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 486 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 389 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 499 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10283 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2289 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 487 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 84 # number of nop insts executed -system.cpu.iew.exec_refs 3376 # number of memory reference insts executed -system.cpu.iew.exec_branches 1642 # Number of branches executed -system.cpu.iew.exec_stores 1076 # Number of stores executed -system.cpu.iew.exec_rate 0.216390 # Inst execution rate -system.cpu.iew.wb_sent 9948 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9755 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5155 # num instructions producing a value +system.cpu.iew.exec_refs 3373 # number of memory reference insts executed +system.cpu.iew.exec_branches 1639 # Number of branches executed +system.cpu.iew.exec_stores 1084 # Number of stores executed +system.cpu.iew.exec_rate 0.216243 # Inst execution rate +system.cpu.iew.wb_sent 9942 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9754 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5150 # num instructions producing a value system.cpu.iew.wb_consumers 7025 # num instructions consuming a value -system.cpu.iew.wb_rate 0.205140 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.733808 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 6712 # The number of squashed insts skipped by commit +system.cpu.iew.wb_rate 0.205118 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.733096 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 6693 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 408 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14221 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.450179 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.361050 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 410 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14238 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.449642 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.359190 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11794 82.93% 82.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1158 8.14% 91.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 469 3.30% 94.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 205 1.44% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 133 0.94% 96.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 85 0.60% 97.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 97 0.68% 98.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 88 0.62% 98.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 192 1.35% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11808 82.93% 82.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1161 8.15% 91.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 469 3.29% 94.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 204 1.43% 95.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 134 0.94% 96.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 86 0.60% 97.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 97 0.68% 98.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 89 0.63% 98.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 190 1.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14221 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14238 # Number of insts commited each cycle system.cpu.commit.committedInsts 6402 # Number of instructions committed system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -596,48 +596,48 @@ system.cpu.commit.op_class_0::FloatMemWrite 7 0.11% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 6402 # Class of committed instruction -system.cpu.commit.bw_lim_events 192 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 190 # number cycles where commit BW limit reached system.cpu.rob.rob_reads 26792 # The number of ROB reads -system.cpu.rob.rob_writes 27482 # The number of ROB writes +system.cpu.rob.rob_writes 27441 # The number of ROB writes system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32095 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 32081 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6385 # Number of Instructions Simulated system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated system.cpu.cpi 7.447612 # CPI: Cycles Per Instruction system.cpu.cpi_total 7.447612 # CPI: Total CPI of All Threads system.cpu.ipc 0.134271 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.134271 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12923 # number of integer regfile reads -system.cpu.int_regfile_writes 7437 # number of integer regfile writes +system.cpu.int_regfile_reads 13028 # number of integer regfile reads +system.cpu.int_regfile_writes 7426 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 110.182603 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2402 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 110.199847 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2391 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.884393 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.820809 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 110.182603 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026900 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026900 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 110.199847 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026904 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026904 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 6051 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 6051 # Number of data accesses +system.cpu.dcache.tags.tag_accesses 6029 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 6029 # Number of data accesses system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1894 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1894 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 1883 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1883 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 508 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 508 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2402 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2402 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2402 # number of overall hits -system.cpu.dcache.overall_hits::total 2402 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2391 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2391 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2391 # number of overall hits +system.cpu.dcache.overall_hits::total 2391 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 180 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 180 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 357 # number of WriteReq misses @@ -646,43 +646,43 @@ system.cpu.dcache.demand_misses::cpu.data 537 # n system.cpu.dcache.demand_misses::total 537 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 537 # number of overall misses system.cpu.dcache.overall_misses::total 537 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13953000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13953000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31158482 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31158482 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45111482 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45111482 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45111482 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45111482 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2074 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2074 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13954000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13954000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31258982 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31258982 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45212982 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45212982 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45212982 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45212982 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2063 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2063 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2939 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2939 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2939 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2939 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086789 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.086789 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2928 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2928 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2928 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2928 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087252 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.087252 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.182715 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.182715 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.182715 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.182715 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77516.666667 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 77516.666667 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87278.661064 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 87278.661064 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 84006.484171 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 84006.484171 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 84006.484171 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 84006.484171 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3098 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.183402 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.183402 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.183402 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.183402 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77522.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 77522.222222 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87560.173669 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 87560.173669 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 84195.497207 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 84195.497207 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 84195.497207 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 84195.497207 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3108 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 37 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.729730 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits @@ -700,137 +700,137 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 173 system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9401500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9401500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7013500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7013500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16415000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16415000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16415000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16415000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048698 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048698 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9402500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9402500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7030000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7030000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16432500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16432500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16432500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16432500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048958 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048958 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058864 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.058864 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058864 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.058864 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93084.158416 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93084.158416 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97409.722222 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97409.722222 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94884.393064 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 94884.393064 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94884.393064 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 94884.393064 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059085 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059085 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059085 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.059085 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93094.059406 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93094.059406 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97638.888889 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97638.888889 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94985.549133 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 94985.549133 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94985.549133 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 94985.549133 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 160.538154 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1837 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 313 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.869010 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 160.011089 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1840 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 312 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.897436 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 160.538154 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078388 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078388 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 313 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 160.011089 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078130 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078130 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 312 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.152832 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4903 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4903 # Number of data accesses +system.cpu.icache.tags.age_task_id_blocks_1024::1 186 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.152344 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4908 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4908 # Number of data accesses system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1837 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1837 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1837 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1837 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1837 # number of overall hits -system.cpu.icache.overall_hits::total 1837 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 1840 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1840 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1840 # 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miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996795 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997942 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.997938 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996795 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997942 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95868.055556 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95868.055556 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82665.064103 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82665.064103 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82665.064103 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86464.948454 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82665.064103 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86464.948454 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997938 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96097.222222 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96097.222222 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82680.064309 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82680.064309 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91509.900990 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91509.900990 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82680.064309 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93419.075145 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86518.595041 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82680.064309 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93419.075145 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86518.595041 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -906,119 +906,119 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 312 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 312 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 311 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 311 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 101 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 101 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 311 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 485 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 484 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6182500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6182500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22671500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22671500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8231500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8231500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22671500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14414000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 37085500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22671500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14414000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 37085500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 484 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6199000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6199000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22603500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22603500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8232500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8232500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22603500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14431500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 37035000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22603500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14431500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 37035000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996805 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996795 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997938 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85868.055556 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85868.055556 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72665.064103 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72665.064103 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72665.064103 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76464.948454 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72665.064103 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76464.948454 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997938 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86097.222222 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86097.222222 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72680.064309 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72680.064309 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81509.900990 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81509.900990 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72680.064309 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83419.075145 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76518.595041 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72680.064309 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83419.075145 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76518.595041 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 413 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 313 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 312 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 626 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 624 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 972 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 970 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 31104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 31040 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 486 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002058 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.045361 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 485 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002062 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.045408 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 485 99.79% 99.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 484 99.79% 99.79% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 486 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 243000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 485 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 242500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 469500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 468000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 484 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 413 # Transaction distribution +system.membus.trans_dist::ReadResp 412 # Transaction distribution system.membus.trans_dist::ReadExReq 72 # Transaction distribution system.membus.trans_dist::ReadExResp 72 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 413 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 970 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 970 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 31040 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 412 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 968 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 968 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30976 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30976 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 485 # Request fanout histogram +system.membus.snoop_fanout::samples 484 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 485 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 484 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 485 # Request fanout histogram -system.membus.reqLayer0.occupancy 595000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 484 # Request fanout histogram +system.membus.reqLayer0.occupancy 593000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2572250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2566000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 10.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index 70a6e8611..effdd0b8b 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000112 # Nu sim_ticks 112490 # Number of ticks simulated final_tick 112490 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 109209 # Simulator instruction rate (inst/s) -host_op_rate 109187 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1917933 # Simulator tick rate (ticks/s) -host_mem_usage 416076 # Number of bytes of host memory used +host_inst_rate 109524 # Simulator instruction rate (inst/s) +host_op_rate 109501 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1923375 # Simulator tick rate (ticks/s) +host_mem_usage 415960 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated @@ -414,13 +414,35 @@ system.ruby.miss_latency_hist_seqr::stdev 35.333412 system.ruby.miss_latency_hist_seqr | 876 50.61% 50.61% | 798 46.10% 96.71% | 40 2.31% 99.02% | 5 0.29% 99.31% | 6 0.35% 99.65% | 6 0.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1731 system.ruby.Directory.incomplete_times_seqr 1730 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.015352 # Average number of messages in buffer +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.997813 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.030740 # Average number of messages in buffer +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.743091 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015388 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999387 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.030740 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999396 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 6732 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1731 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8463 # Number of cache demand accesses +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.015352 # Average number of messages in buffer +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.984319 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.075242 # Average number of messages in buffer +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999991 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.061480 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999947 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.015388 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.995333 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.015352 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.986612 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.015388 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.996053 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.092150 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.743802 # Average number of cycles messages are stalled in this MB system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 7.685128 system.ruby.network.routers0.msg_count.Control::2 1731 @@ -431,6 +453,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 13848 system.ruby.network.routers0.msg_bytes.Data::2 124344 system.ruby.network.routers0.msg_bytes.Response_Data::4 124632 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13816 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.030740 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.743268 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.015352 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.995609 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.015388 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998755 # Average number of cycles messages are stalled in this MB system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 7.685128 system.ruby.network.routers1.msg_count.Control::2 1731 @@ -441,6 +469,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 13848 system.ruby.network.routers1.msg_bytes.Data::2 124344 system.ruby.network.routers1.msg_bytes.Response_Data::4 124632 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13816 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.030740 # Average number of messages in buffer +system.ruby.network.int_link_buffers02.avg_stall_time 7.743695 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015352 # Average number of messages in buffer +system.ruby.network.int_link_buffers08.avg_stall_time 2.993386 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.015388 # Average number of messages in buffer +system.ruby.network.int_link_buffers09.avg_stall_time 2.998107 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.015352 # Average number of messages in buffer +system.ruby.network.int_link_buffers13.avg_stall_time 4.988888 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.015388 # Average number of messages in buffer +system.ruby.network.int_link_buffers14.avg_stall_time 4.996755 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.030740 # Average number of messages in buffer +system.ruby.network.int_link_buffers17.avg_stall_time 9.743428 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.015352 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.991146 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.015388 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.997440 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.030740 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.743571 # Average number of cycles messages are stalled in this MB system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 7.685128 system.ruby.network.routers2.msg_count.Control::2 1731 diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 4822d2cee..680b47747 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 32719500 # Number of ticks simulated -final_tick 32719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 32617500 # Number of ticks simulated +final_tick 32617500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128948 # Simulator instruction rate (inst/s) -host_op_rate 150916 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 915725978 # Simulator tick rate (ticks/s) -host_mem_usage 269308 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 159604 # Simulator instruction rate (inst/s) +host_op_rate 186772 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1129633158 # Simulator tick rate (ticks/s) +host_mem_usage 268376 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 19456 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory -system.physmem.bytes_read::total 26944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 304 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory -system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 596586134 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 226898333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 823484466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 596586134 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 596586134 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 596586134 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 226898333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 823484466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 421 # Number of read requests accepted +system.physmem.num_reads::total 420 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 596489614 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 227607879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 824097494 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 596489614 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 596489614 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 596489614 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 227607879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 824097494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 420 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 420 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 26880 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side +system.physmem.bytesReadSys 26880 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -46,7 +46,7 @@ system.physmem.perBankRdBursts::0 91 # Pe system.physmem.perBankRdBursts::1 52 # Per bank write bursts system.physmem.perBankRdBursts::2 20 # Per bank write bursts system.physmem.perBankRdBursts::3 43 # Per bank write bursts -system.physmem.perBankRdBursts::4 22 # Per bank write bursts +system.physmem.perBankRdBursts::4 21 # Per bank write bursts system.physmem.perBankRdBursts::5 41 # Per bank write bursts system.physmem.perBankRdBursts::6 36 # Per bank write bursts system.physmem.perBankRdBursts::7 12 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 32621500 # Total gap between requests +system.physmem.totGap 32519500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 421 # Read request sizes (log2) +system.physmem.readPktSize::6 420 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,7 +91,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 70 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -188,95 +188,95 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 70 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 374.857143 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 257.842659 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 316.227871 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12 17.14% 17.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 20 28.57% 45.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 373.942857 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 254.068407 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 318.910277 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13 18.57% 18.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 27.14% 45.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 11 15.71% 61.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 9 12.86% 74.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 2.86% 77.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 4.29% 81.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 5.71% 87.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 11.43% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.29% 77.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 2.86% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5 7.14% 87.14% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 2 2.86% 90.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 7 10.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 70 # Bytes accessed per row activation -system.physmem.totQLat 5175000 # Total ticks spent queuing -system.physmem.totMemAccLat 13068750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12292.16 # Average queueing delay per DRAM burst +system.physmem.totQLat 5148000 # Total ticks spent queuing +system.physmem.totMemAccLat 13023000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12257.14 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31042.16 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 823.48 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31007.14 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 824.10 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 823.48 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 824.10 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.43 # Data bus utilization in percentage -system.physmem.busUtilRead 6.43 # Data bus utilization in percentage for reads +system.physmem.busUtil 6.44 # Data bus utilization in percentage +system.physmem.busUtilRead 6.44 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 347 # Number of row buffer hits during reads +system.physmem.readRowHits 346 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.42 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.38 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 77485.75 # Average gap between requests -system.physmem.pageHitRate 82.42 # Row buffer hit rate, read and write combined +system.physmem.avgGap 77427.38 # Average gap between requests +system.physmem.pageHitRate 82.38 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 349860 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 174570 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2263380 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 2256240 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4410090 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 4399260 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 59520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 10437840 # Energy for active power-down per rank (pJ) +system.physmem_0.actPowerDownEnergy 10401930 # Energy for active power-down per rank (pJ) system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 20155260 # Total energy per rank (pJ) -system.physmem_0.averagePower 615.992054 # Core power per rank (mW) -system.physmem_0.totalIdleTime 22842000 # Total Idle time Per DRAM Rank +system.physmem_0.totalEnergy 20101380 # Total energy per rank (pJ) +system.physmem_0.averagePower 616.275926 # Core power per rank (mW) +system.physmem_0.totalIdleTime 22764750 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 30000 # Time in different power states system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8749750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 22896000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8725000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 22818750 # Time in different power states system.physmem_1.actEnergy 178500 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 91080 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 742560 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1743060 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 96480 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 12022440 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 876000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 1740780 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 96960 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 12060060 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 806400 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 18208680 # Total energy per rank (pJ) -system.physmem_1.averagePower 556.500000 # Core power per rank (mW) -system.physmem_1.totalIdleTime 28380000 # Total Idle time Per DRAM Rank +system.physmem_1.totalEnergy 18174900 # Total energy per rank (pJ) +system.physmem_1.averagePower 557.213152 # Core power per rank (mW) +system.physmem_1.totalIdleTime 28278000 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 141000 # Time in different power states system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 2280750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 2099750 # Time in different power states system.physmem_1.memoryStateTime::ACT 2887500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 26370250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 1968 # Number of BP lookups -system.cpu.branchPred.condPredicted 1177 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1659 # Number of BTB lookups -system.cpu.branchPred.BTBHits 322 # Number of BTB hits +system.physmem_1.memoryStateTime::ACT_PDN 26449250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 1965 # Number of BP lookups +system.cpu.branchPred.condPredicted 1175 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 349 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1668 # Number of BTB lookups +system.cpu.branchPred.BTBHits 324 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 19.409283 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 221 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 19.424460 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 220 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 135 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 137 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 8 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 127 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectMisses 129 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -306,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -336,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -366,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -397,16 +397,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 32719500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 65439 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 32617500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 65235 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4605 # Number of instructions committed system.cpu.committedOps 5391 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1193 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1187 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 14.210423 # CPI: cycles per instruction -system.cpu.ipc 0.070371 # IPC: instructions per cycle +system.cpu.cpi 14.166124 # CPI: cycles per instruction +system.cpu.ipc 0.070591 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction @@ -446,25 +446,25 @@ system.cpu.op_class_0::FloatMemWrite 16 0.30% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 5391 # Class of committed instruction -system.cpu.tickCycles 10731 # Number of cycles that the object actually ticked -system.cpu.idleCycles 54708 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 10712 # Number of cycles that the object actually ticked +system.cpu.idleCycles 54523 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.904844 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.828759 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.904844 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021217 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021217 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.828759 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021198 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021198 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4334 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4334 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits @@ -567,59 +567,59 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72253.424658 system.cpu.dcache.demand_avg_mshr_miss_latency::total 72253.424658 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72253.424658 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 72253.424658 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 162.619345 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1965 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.102484 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 162.068358 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1966 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.124611 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 162.619345 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.079404 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.079404 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 162.068358 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.079135 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.079135 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 317 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4896 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4896 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1965 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1965 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1965 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1965 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1965 # number of overall hits -system.cpu.icache.overall_hits::total 1965 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses -system.cpu.icache.overall_misses::total 322 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26079500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26079500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26079500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26079500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26079500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26079500 # number of overall miss cycles +system.cpu.icache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.154785 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4895 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4895 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1966 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1966 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1966 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1966 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1966 # number of overall hits +system.cpu.icache.overall_hits::total 1966 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses +system.cpu.icache.overall_misses::total 321 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25981000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25981000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25981000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25981000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25981000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25981000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2287 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2287 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2287 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 2287 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 2287 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 2287 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.140796 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.140796 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.140796 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.140796 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.140796 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.140796 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80992.236025 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 80992.236025 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 80992.236025 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 80992.236025 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 80992.236025 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 80992.236025 # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.140359 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.140359 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.140359 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.140359 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.140359 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.140359 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80937.694704 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 80937.694704 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 80937.694704 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 80937.694704 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 80937.694704 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 80937.694704 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -628,49 +628,49 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 4 # number of writebacks system.cpu.icache.writebacks::total 4 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25757500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25757500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25757500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25757500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25757500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25757500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140796 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.140796 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.140796 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79992.236025 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79992.236025 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79992.236025 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 79992.236025 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79992.236025 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 79992.236025 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 321 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 321 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 321 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 321 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25660000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25660000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25660000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25660000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25660000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25660000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140359 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.140359 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.140359 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79937.694704 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79937.694704 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79937.694704 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79937.694704 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79937.694704 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79937.694704 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 224.400944 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 223.784324 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.099762 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 420 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.100000 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 155.496620 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 68.904325 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004745 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002103 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006848 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.947993 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 68.836332 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004729 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002101 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006829 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 420 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4189 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4189 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012817 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4180 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4180 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits @@ -685,66 +685,66 @@ system.cpu.l2cache.overall_hits::cpu.data 22 # n system.cpu.l2cache.overall_hits::total 39 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 305 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 305 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 304 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 304 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 81 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 81 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 304 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 124 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses +system.cpu.l2cache.demand_misses::total 428 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 304 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses -system.cpu.l2cache.overall_misses::total 429 # number of overall misses +system.cpu.l2cache.overall_misses::total 428 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3423500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3423500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25079000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 25079000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 24983000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 24983000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6647000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 6647000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 25079000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 24983000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 10070500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35149500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 25079000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 35053500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 24983000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 10070500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35149500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35053500 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 322 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 321 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 321 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 322 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 321 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 322 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 467 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 321 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 468 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 467 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947205 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947205 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947040 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947040 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.786408 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.786408 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947205 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947040 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.916488 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947040 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.916488 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79616.279070 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79616.279070 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82226.229508 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82226.229508 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82180.921053 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82180.921053 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82061.728395 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82061.728395 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82226.229508 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82180.921053 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81213.709677 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81933.566434 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82226.229508 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81900.700935 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82180.921053 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81213.709677 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81933.566434 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81900.700935 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -759,120 +759,120 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 8 system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 305 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 305 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 304 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 304 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 73 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 73 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2993500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2993500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22029000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22029000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 21943000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 21943000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5321000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5321000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22029000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21943000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8314500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30343500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22029000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30257500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21943000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8314500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30343500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30257500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947205 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947040 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69616.279070 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69616.279070 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72226.229508 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72226.229508 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72180.921053 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72180.921053 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72890.410959 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72890.410959 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72226.229508 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72180.921053 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71676.724138 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72074.821853 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72226.229508 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72041.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72180.921053 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71676.724138 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72074.821853 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 472 # Total number of requests made to the snoop filter. +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72041.666667 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 50 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 321 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 648 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 940 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 938 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20800 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.100427 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.300891 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 467 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.100642 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.301177 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 421 89.96% 89.96% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 47 10.04% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 420 89.94% 89.94% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 47 10.06% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 467 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 239500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 481500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 421 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 420 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 378 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 377 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 378 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26944 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 377 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 421 # Request fanout histogram +system.membus.snoop_fanout::samples 420 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 420 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 421 # Request fanout histogram -system.membus.reqLayer0.occupancy 489500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 420 # Request fanout histogram +system.membus.reqLayer0.occupancy 489000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2238250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2233000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 6.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 5d8a28b22..bd3252a40 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18422500 # Number of ticks simulated -final_tick 18422500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000019 # Number of seconds simulated +sim_ticks 18517500 # Number of ticks simulated +final_tick 18517500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76941 # Simulator instruction rate (inst/s) -host_op_rate 90095 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 308579581 # Simulator tick rate (ticks/s) -host_mem_usage 270584 # Number of bytes of host memory used +host_inst_rate 74881 # Simulator instruction rate (inst/s) +host_op_rate 87684 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 301872470 # Simulator tick rate (ticks/s) +host_mem_usage 270416 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory -system.physmem.bytes_read::total 25408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory -system.physmem.num_reads::total 397 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 958827521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 420355543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1379183064 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 958827521 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 958827521 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 958827521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 420355543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1379183064 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 397 # Number of read requests accepted +system.physmem.num_reads::total 396 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 950452275 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 418199001 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1368651276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 950452275 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 950452275 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 950452275 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 418199001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1368651276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 396 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 25344 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side +system.physmem.bytesReadSys 25344 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -51,7 +51,7 @@ system.physmem.perBankRdBursts::5 32 # Pe system.physmem.perBankRdBursts::6 35 # Per bank write bursts system.physmem.perBankRdBursts::7 10 # Per bank write bursts system.physmem.perBankRdBursts::8 4 # Per bank write bursts -system.physmem.perBankRdBursts::9 9 # Per bank write bursts +system.physmem.perBankRdBursts::9 8 # Per bank write bursts system.physmem.perBankRdBursts::10 28 # Per bank write bursts system.physmem.perBankRdBursts::11 42 # Per bank write bursts system.physmem.perBankRdBursts::12 10 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18337000 # Total gap between requests +system.physmem.totGap 18432000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 397 # Read request sizes (log2) +system.physmem.readPktSize::6 396 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,10 +91,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 204 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -188,95 +188,95 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 407.864407 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 273.934367 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 344.219630 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 10 16.95% 16.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 28.81% 45.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 13.56% 59.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 11.86% 71.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 406.779661 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 269.610222 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 346.645206 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 11 18.64% 18.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16 27.12% 45.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7 11.86% 57.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 13.56% 71.19% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 1 1.69% 72.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.39% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 5.08% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 5.08% 86.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8 13.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 5.08% 77.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.39% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.39% 84.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 15.25% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation -system.physmem.totQLat 5196750 # Total ticks spent queuing -system.physmem.totMemAccLat 12640500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13090.05 # Average queueing delay per DRAM burst +system.physmem.totQLat 5212000 # Total ticks spent queuing +system.physmem.totMemAccLat 12637000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13161.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31840.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1379.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31911.62 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1368.65 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1379.18 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1368.65 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.77 # Data bus utilization in percentage -system.physmem.busUtilRead 10.77 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.69 # Data bus utilization in percentage +system.physmem.busUtilRead 10.69 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.90 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.87 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 330 # Number of row buffer hits during reads +system.physmem.readRowHits 329 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.08 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 46188.92 # Average gap between requests -system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined +system.physmem.avgGap 46545.45 # Average gap between requests +system.physmem.pageHitRate 83.08 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 314160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 151800 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2084880 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3077430 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 36000 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5255970 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 20640 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actBackEnergy 3085980 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 37920 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 5290170 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 19200 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 12170160 # Total energy per rank (pJ) -system.physmem_0.averagePower 660.613923 # Core power per rank (mW) -system.physmem_0.totalIdleTime 11420000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states +system.physmem_0.totalEnergy 12213390 # Total energy per rank (pJ) +system.physmem_0.averagePower 659.559336 # Core power per rank (mW) +system.physmem_0.totalIdleTime 11496500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 29500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 53500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 6303750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 11521750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 49250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 6316250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 11602500 # Time in different power states system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 72105 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 749700 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 742560 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1466040 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 65760 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 6124080 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 616800 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 1457490 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 66240 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 6092730 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 686400 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 10487985 # Total energy per rank (pJ) -system.physmem_1.averagePower 569.303026 # Core power per rank (mW) -system.physmem_1.totalIdleTime 14986000 # Total Idle time Per DRAM Rank +system.physmem_1.totalEnergy 10511025 # Total energy per rank (pJ) +system.physmem_1.averagePower 567.626569 # Core power per rank (mW) +system.physmem_1.totalIdleTime 15098500 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 116000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1605250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2751250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 13430000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2844 # Number of BP lookups -system.cpu.branchPred.condPredicted 1749 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2408 # Number of BTB lookups -system.cpu.branchPred.BTBHits 867 # Number of BTB hits +system.physmem_1.memoryStateTime::PRE_PDN 1787250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2733750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 13360500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2820 # Number of BP lookups +system.cpu.branchPred.condPredicted 1728 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 468 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2384 # Number of BTB lookups +system.cpu.branchPred.BTBHits 844 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 36.004983 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 35.402685 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 322 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 266 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 260 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 253 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectMisses 247 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 64 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -306,7 +306,7 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -336,7 +336,7 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 0 # DTB hits system.cpu.checker.dtb.misses 0 # DTB misses system.cpu.checker.dtb.accesses 0 # DTB accesses -system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -366,7 +366,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.checker.itb.walker.walks 0 # Table walker walks requested system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -397,11 +397,11 @@ system.cpu.checker.itb.hits 0 # DT system.cpu.checker.itb.misses 0 # DTB misses system.cpu.checker.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.checker.pwrStateResidencyTicks::ON 18422500 # Cumulative time (in ticks) in various power states +system.cpu.checker.pwrStateResidencyTicks::ON 18517500 # Cumulative time (in ticks) in various power states system.cpu.checker.numCycles 5391 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -431,7 +431,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -461,7 +461,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -491,7 +491,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -521,245 +521,245 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.pwrStateResidencyTicks::ON 18422500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 36846 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 18517500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 37036 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7661 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12314 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2844 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1194 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5108 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 977 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 7733 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12373 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2820 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 5113 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 985 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 260 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1962 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13535 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.094422 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.458272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1982 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 291 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13616 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.093052 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.461769 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10839 80.08% 80.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 264 1.95% 82.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 185 1.37% 83.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 204 1.51% 84.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 283 2.09% 87.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 398 2.94% 89.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 139 1.03% 90.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 173 1.28% 92.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1050 7.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10916 80.17% 80.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 271 1.99% 82.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 182 1.34% 83.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 206 1.51% 85.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 259 1.90% 86.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 398 2.92% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 138 1.01% 90.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 192 1.41% 92.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1054 7.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13535 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.077186 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.334202 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6279 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4644 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2146 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 334 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 431 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 13616 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.076142 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.334080 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6341 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4657 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2138 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 142 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 338 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 909 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12150 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12250 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 334 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6511 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 826 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 338 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6573 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 835 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2470 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2033 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1361 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11433 # Number of instructions processed by rename +system.cpu.rename.RunCycles 2036 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1364 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11552 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 178 # Number of times rename has blocked due to IQ full +system.cpu.rename.IQFullEvents 181 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 144 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1169 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11641 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 52345 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12355 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1170 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 11673 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 53030 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12530 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6147 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6179 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 40 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 446 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2197 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1543 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 442 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2293 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1619 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 33 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10169 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10296 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8096 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 37 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4835 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12334 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8207 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 43 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4962 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 12830 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13535 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.598153 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.329974 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13616 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.602747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.340306 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10320 76.25% 76.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1163 8.59% 84.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 763 5.64% 90.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 482 3.56% 94.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 344 2.54% 96.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 273 2.02% 98.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 120 0.89% 99.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 60 0.44% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10392 76.32% 76.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1145 8.41% 84.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 762 5.60% 90.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 485 3.56% 93.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 356 2.61% 96.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 278 2.04% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 127 0.93% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 61 0.45% 99.93% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13535 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13616 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 6.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 66 44.00% 50.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 62 41.33% 91.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 91.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 13 8.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 5.42% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 83 50.00% 55.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 61 36.75% 92.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 92.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 13 7.83% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5023 62.04% 62.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1876 23.17% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1154 14.25% 99.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 33 0.41% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5024 61.22% 61.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1962 23.91% 85.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1178 14.35% 99.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 33 0.40% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8096 # Type of FU issued -system.cpu.iq.rate 0.219725 # Inst issue rate -system.cpu.iq.fu_busy_cnt 150 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018528 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29820 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14935 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7404 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8207 # Type of FU issued +system.cpu.iq.rate 0.221595 # Inst issue rate +system.cpu.iq.fu_busy_cnt 166 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.020227 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30145 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15189 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7438 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 94 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8200 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8327 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 46 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 24 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1170 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1266 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 605 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 681 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 334 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 696 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10222 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 131 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2197 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1543 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 707 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10349 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 128 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2293 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1619 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 32 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 94 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 356 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7806 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1768 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 290 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 93 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 267 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 360 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7885 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1840 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 322 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 9 # number of nop insts executed -system.cpu.iew.exec_refs 2921 # number of memory reference insts executed -system.cpu.iew.exec_branches 1491 # Number of branches executed -system.cpu.iew.exec_stores 1153 # Number of stores executed -system.cpu.iew.exec_rate 0.211855 # Inst execution rate -system.cpu.iew.wb_sent 7533 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7436 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3503 # num instructions producing a value -system.cpu.iew.wb_consumers 6835 # num instructions consuming a value -system.cpu.iew.wb_rate 0.201813 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.512509 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4843 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 3007 # number of memory reference insts executed +system.cpu.iew.exec_branches 1490 # Number of branches executed +system.cpu.iew.exec_stores 1167 # Number of stores executed +system.cpu.iew.exec_rate 0.212901 # Inst execution rate +system.cpu.iew.wb_sent 7581 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7470 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3518 # num instructions producing a value +system.cpu.iew.wb_consumers 6872 # num instructions consuming a value +system.cpu.iew.wb_rate 0.201696 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.511932 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4970 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 310 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12682 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.424066 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.266213 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 314 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12743 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.422036 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.264076 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10636 83.87% 83.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 879 6.93% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 416 3.28% 94.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 218 1.72% 95.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 111 0.88% 96.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10698 83.95% 83.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 879 6.90% 90.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 416 3.26% 94.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 216 1.70% 95.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 111 0.87% 96.68% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 220 1.73% 98.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 54 0.43% 98.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 55 0.43% 98.84% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 39 0.31% 99.14% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 109 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12682 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12743 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -810,120 +810,120 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22637 # The number of ROB reads -system.cpu.rob.rob_writes 21308 # The number of ROB writes -system.cpu.timesIdled 191 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 23311 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22825 # The number of ROB reads +system.cpu.rob.rob_writes 21580 # The number of ROB writes +system.cpu.timesIdled 193 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 23420 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.023955 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.023955 # CPI: Total CPI of All Threads -system.cpu.ipc 0.124627 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.124627 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7656 # number of integer regfile reads -system.cpu.int_regfile_writes 4268 # number of integer regfile writes +system.cpu.cpi 8.065331 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.065331 # CPI: Total CPI of All Threads +system.cpu.ipc 0.123987 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.123987 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7779 # number of integer regfile reads +system.cpu.int_regfile_writes 4297 # number of integer regfile writes system.cpu.fp_regfile_reads 32 # number of floating regfile reads -system.cpu.cc_regfile_reads 27780 # number of cc regfile reads -system.cpu.cc_regfile_writes 3273 # number of cc regfile writes -system.cpu.misc_regfile_reads 2974 # number of misc regfile reads +system.cpu.cc_regfile_reads 28140 # number of cc regfile reads +system.cpu.cc_regfile_writes 3276 # number of cc regfile writes +system.cpu.misc_regfile_reads 3029 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 88.014551 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2093 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.889702 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2158 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.238095 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.680272 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 88.014551 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021488 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021488 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 87.889702 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021457 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021457 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5335 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5335 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1475 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1475 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5471 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5471 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 1540 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2072 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2072 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2072 # number of overall hits -system.cpu.dcache.overall_hits::total 2072 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 183 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 183 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2137 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2137 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2137 # number of overall hits +system.cpu.dcache.overall_hits::total 2137 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 499 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses -system.cpu.dcache.overall_misses::total 499 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11345000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11345000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24463500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24463500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses +system.cpu.dcache.overall_misses::total 502 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11381500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11381500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24478000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24478000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 156000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 156000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35808500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35808500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35808500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35808500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1658 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1658 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 35859500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35859500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35859500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35859500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1726 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1726 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2571 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2571 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2571 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2571 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110374 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.110374 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2639 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2639 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2639 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2639 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.107764 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.107764 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.194088 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.194088 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.194088 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.194088 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61994.535519 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61994.535519 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77416.139241 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77416.139241 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.190224 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.190224 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.190224 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.190224 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61190.860215 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61190.860215 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77462.025316 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77462.025316 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71760.521042 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71760.521042 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71760.521042 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71760.521042 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71433.266932 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71433.266932 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71433.266932 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71433.266932 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 159 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 352 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 352 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 352 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -932,140 +932,140 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7355500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7355500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7338000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7338000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3668000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3668000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11023500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11023500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11023500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11023500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063329 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063329 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11006000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11006000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11006000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11006000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.060834 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.060834 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057176 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057176 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057176 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.057176 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70052.380952 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70052.380952 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055703 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.055703 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055703 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.055703 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69885.714286 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69885.714286 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87333.333333 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87333.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74989.795918 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74989.795918 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74989.795918 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74989.795918 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74870.748299 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74870.748299 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74870.748299 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74870.748299 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 149.507349 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.363946 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 148.671994 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1587 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.416382 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 149.507349 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073002 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073002 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 148.671994 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.072594 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.072594 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4218 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4218 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits -system.cpu.icache.overall_hits::total 1577 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 385 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 385 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 385 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 385 # number of overall misses -system.cpu.icache.overall_misses::total 385 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28997500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28997500 # 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number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1982 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1982 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1982 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1982 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199294 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.199294 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.199294 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.199294 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.199294 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.199294 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75097.468354 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75097.468354 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75097.468354 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75097.468354 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75097.468354 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75097.468354 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 422 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 98.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 105.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 440 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.938776 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.938776 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.938567 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.938567 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.809524 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.809524 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938776 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938567 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.913832 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.913636 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938567 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.913832 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.913636 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85785.714286 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85785.714286 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82728.260870 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82728.260870 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81894.117647 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81894.117647 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82728.260870 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83181.102362 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82870.967742 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82728.260870 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83181.102362 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82870.967742 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82878.181818 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82878.181818 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81688.235294 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81688.235294 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82878.181818 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83043.307087 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82930.348259 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82878.181818 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83043.307087 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82930.348259 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1154,120 +1154,120 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 6 system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 276 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 276 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 275 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 275 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 79 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 79 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 396 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3183000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3183000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20073000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20073000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5729500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5729500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20073000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8912500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28985500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20073000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8912500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28985500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20041500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20041500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5712000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5712000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20041500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8895000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28936500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20041500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8895000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28936500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938776 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938567 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75785.714286 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75785.714286 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72728.260870 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72728.260870 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72525.316456 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72525.316456 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72728.260870 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73657.024793 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73011.335013 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72728.260870 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73657.024793 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73011.335013 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter. +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72878.181818 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72878.181818 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72303.797468 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72303.797468 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72878.181818 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73512.396694 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73071.969697 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72878.181818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73512.396694 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73071.969697 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 442 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 294 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 884 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 882 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28288 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.099773 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.300038 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.100000 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.300341 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 397 90.02% 90.02% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 44 9.98% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 396 90.00% 90.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 44 10.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 223000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 441000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 439500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 397 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 396 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 355 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 354 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution system.membus.trans_dist::ReadExResp 42 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 355 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 354 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 792 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 792 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25344 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 397 # Request fanout histogram +system.membus.snoop_fanout::samples 396 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 396 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 397 # Request fanout histogram -system.membus.reqLayer0.occupancy 486500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 396 # Request fanout histogram +system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2098750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 2091500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 307f14079..bc5d2d1fc 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 20302000 # Number of ticks simulated final_tick 20302000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 10367 # Simulator instruction rate (inst/s) -host_op_rate 12141 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45828431 # Simulator tick rate (ticks/s) -host_mem_usage 248616 # Number of bytes of host memory used -host_seconds 0.44 # Real time elapsed on the host +host_inst_rate 93691 # Simulator instruction rate (inst/s) +host_op_rate 109699 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 414022055 # Simulator tick rate (ticks/s) +host_mem_usage 265936 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -205,12 +205,12 @@ system.physmem.bytesPerActivate::768-895 2 3.23% 77.42% # By system.physmem.bytesPerActivate::896-1023 4 6.45% 83.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 16.13% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 6124000 # Total ticks spent queuing -system.physmem.totMemAccLat 14467750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 6135000 # Total ticks spent queuing +system.physmem.totMemAccLat 14478750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13761.80 # Average queueing delay per DRAM burst +system.physmem.avgQLat 13786.52 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32511.80 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 32536.52 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1402.82 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1402.82 # Average system read bandwidth in MiByte/s @@ -232,28 +232,28 @@ system.physmem_0.preEnergy 170775 # En system.physmem_0.readEnergy 2334780 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3561360 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 3562500 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 28800 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5661240 # Energy for active power-down per rank (pJ) +system.physmem_0.actPowerDownEnergy 5660100 # Energy for active power-down per rank (pJ) system.physmem_0.prePowerDownEnergy 960 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_0.totalEnergy 13337055 # Total energy per rank (pJ) system.physmem_0.averagePower 656.916882 # Core power per rank (mW) -system.physmem_0.totalIdleTime 12272000 # Total Idle time Per DRAM Rank +system.physmem_0.totalIdleTime 12261000 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 19000 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 2500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7340250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12420250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7351250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 12409250 # Time in different power states system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 64515 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 842520 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1479720 # Energy for active background per rank (pJ) +system.physmem_1.actBackEnergy 1478010 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 68640 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 7413420 # Energy for active power-down per rank (pJ) +system.physmem_1.actPowerDownEnergy 7415130 # Energy for active power-down per rank (pJ) system.physmem_1.prePowerDownEnergy 238560 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_1.totalEnergy 11500875 # Total energy per rank (pJ) @@ -267,12 +267,12 @@ system.physmem_1.memoryStateTime::ACT 2792000 # Ti system.physmem_1.memoryStateTime::ACT_PDN 16259500 # Time in different power states system.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 2438 # Number of BP lookups -system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 522 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups -system.cpu.branchPred.BTBHits 449 # Number of BTB hits +system.cpu.branchPred.condPredicted 1441 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 523 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 913 # Number of BTB lookups +system.cpu.branchPred.BTBHits 446 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 49.071038 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 48.849945 # BTB Hit Percentage system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups. @@ -405,80 +405,80 @@ system.cpu.pwrStateResidencyTicks::ON 20302000 # Cu system.cpu.numCycles 40605 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6160 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11461 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 6162 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11460 # Number of instructions fetch has processed system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 8317 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1087 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.predictedBranches 745 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 8314 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1089 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 286 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 447 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3903 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 179 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.856236 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.206395 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 466 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3900 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 180 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15914 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.856227 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.206589 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9529 59.87% 59.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2505 15.74% 75.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 521 3.27% 78.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3360 21.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9531 59.89% 59.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2501 15.72% 75.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 521 3.27% 78.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3361 21.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15915 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 15914 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.060042 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.282256 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5815 # Number of cycles decode is idle +system.cpu.fetch.rate 0.282231 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5816 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 4410 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5174 # Number of cycles decode is running +system.cpu.decode.RunCycles 5171 # Number of cycles decode is running system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 384 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 374 # Number of times decode resolved a branch +system.cpu.decode.SquashCycles 385 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 538 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 10174 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 10171 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 1674 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 384 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6926 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 385 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6927 # Number of cycles rename is idle system.cpu.rename.BlockCycles 1165 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2515 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4185 # Number of cycles rename is running +system.cpu.rename.RunCycles 4182 # Number of cycles rename is running system.cpu.rename.UnblockCycles 740 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 9093 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 464 # Number of squashed instructions processed by rename +system.cpu.rename.RenamedInsts 9091 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 462 # Number of squashed instructions processed by rename system.cpu.rename.ROBFullEvents 25 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 631 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9451 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 41117 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedOperands 9449 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 41113 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 9997 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3957 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3955 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 29 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 332 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1821 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1286 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1287 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 8508 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7222 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 185 # Number of squashed instructions issued +system.cpu.iq.iqInstsIssued 7227 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 183 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 3168 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8232 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 8218 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.453786 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.844098 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15914 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.454128 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.844358 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11657 73.25% 73.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1985 12.47% 85.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11653 73.22% 73.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1987 12.49% 85.71% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 1624 10.20% 95.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 607 3.81% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 608 3.82% 99.74% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 42 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle @@ -487,147 +487,147 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15914 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 415 28.86% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 468 32.55% 61.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 414 28.79% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 469 32.61% 61.40% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 538 37.41% 98.82% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.82% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 17 1.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4533 62.77% 62.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1600 22.15% 85.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1065 14.75% 99.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4537 62.78% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1601 22.15% 85.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1065 14.74% 99.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 16 0.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7222 # Type of FU issued -system.cpu.iq.rate 0.177860 # Inst issue rate +system.cpu.iq.FU_type_0::total 7227 # Type of FU issued +system.cpu.iq.rate 0.177983 # Inst issue rate system.cpu.iq.fu_busy_cnt 1438 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.199114 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31933 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_rate 0.198976 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31940 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 11705 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6615 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 6623 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 49 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8627 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8632 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 33 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 12 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 794 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 348 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 349 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 384 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 385 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 345 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 8559 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1821 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1286 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1287 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 60 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 318 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6815 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1418 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 407 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 320 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 6823 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1419 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 13 # number of nop insts executed -system.cpu.iew.exec_refs 2442 # number of memory reference insts executed -system.cpu.iew.exec_branches 1297 # Number of branches executed +system.cpu.iew.exec_refs 2443 # number of memory reference insts executed +system.cpu.iew.exec_branches 1299 # Number of branches executed system.cpu.iew.exec_stores 1024 # Number of stores executed -system.cpu.iew.exec_rate 0.167836 # Inst execution rate -system.cpu.iew.wb_sent 6675 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6631 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2981 # num instructions producing a value -system.cpu.iew.wb_consumers 5426 # num instructions consuming a value -system.cpu.iew.wb_rate 0.163305 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549392 # average fanout of values written-back +system.cpu.iew.exec_rate 0.168033 # Inst execution rate +system.cpu.iew.wb_sent 6684 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6639 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2983 # num instructions producing a value +system.cpu.iew.wb_consumers 5430 # num instructions consuming a value +system.cpu.iew.wb_rate 0.163502 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.549355 # average fanout of values written-back system.cpu.commit.commitSquashedInsts 2701 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 363 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 15348 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.350404 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.989339 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 364 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 15346 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.350450 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.989791 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 12680 82.62% 82.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1404 9.15% 91.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 12681 82.63% 82.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1400 9.12% 91.76% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 606 3.95% 95.71% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 298 1.94% 97.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 164 1.07% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 165 1.08% 98.72% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 80 0.52% 99.24% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 44 0.29% 99.53% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 28 0.18% 99.71% # Number of insts commited each cycle @@ -635,7 +635,7 @@ system.cpu.commit.committed_per_cycle::8 44 0.29% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 15348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 15346 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -686,33 +686,33 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 23226 # The number of ROB reads -system.cpu.rob.rob_writes 16730 # The number of ROB writes -system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24690 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23224 # The number of ROB reads +system.cpu.rob.rob_writes 16731 # The number of ROB writes +system.cpu.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 24691 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated system.cpu.cpi 8.842552 # CPI: Cycles Per Instruction system.cpu.cpi_total 8.842552 # CPI: Total CPI of All Threads system.cpu.ipc 0.113090 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.113090 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6765 # number of integer regfile reads -system.cpu.int_regfile_writes 3787 # number of integer regfile writes +system.cpu.int_regfile_reads 6850 # number of integer regfile reads +system.cpu.int_regfile_writes 3795 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 24202 # number of cc regfile reads -system.cpu.cc_regfile_writes 2924 # number of cc regfile writes -system.cpu.misc_regfile_reads 2558 # number of misc regfile reads +system.cpu.cc_regfile_reads 24229 # number of cc regfile reads +system.cpu.cc_regfile_writes 2927 # number of cc regfile writes +system.cpu.misc_regfile_reads 2559 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.060908 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1926 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 84.085192 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1923 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.468531 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.447552 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.060908 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164181 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164181 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.085192 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164229 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164229 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id @@ -720,38 +720,38 @@ system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 system.cpu.dcache.tags.tag_accesses 4715 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4715 # Number of data accesses system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1184 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1184 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 1181 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1181 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1906 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1906 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1906 # number of overall hits -system.cpu.dcache.overall_hits::total 1906 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 1903 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1903 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1903 # number of overall hits +system.cpu.dcache.overall_hits::total 1903 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses -system.cpu.dcache.overall_misses::total 358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12046500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12046500 # number of ReadReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 361 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 361 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 361 # number of overall misses +system.cpu.dcache.overall_misses::total 361 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12060000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12060000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 8016500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 8016500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 139000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 139000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20063000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20063000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20063000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20063000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20076500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20076500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20076500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20076500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1351 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1351 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -764,26 +764,26 @@ system.cpu.dcache.demand_accesses::cpu.data 2264 # system.cpu.dcache.demand_accesses::total 2264 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2264 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2264 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123612 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.123612 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.125833 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.125833 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.158127 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.158127 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.158127 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.158127 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72134.730539 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72134.730539 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.159452 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.159452 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.159452 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.159452 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70941.176471 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70941.176471 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41971.204188 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 41971.204188 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56041.899441 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56041.899441 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56041.899441 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56041.899441 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55613.573407 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55613.573407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55613.573407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55613.573407 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 853 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -792,16 +792,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets 47.388889 # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 1 # number of writebacks system.cpu.dcache.writebacks::total 1 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 214 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 214 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 214 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 217 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 217 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 217 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 217 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -810,14 +810,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 144 system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7999500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7999500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7989500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7989500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2594500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2594500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10594000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10594000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10594000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10594000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10584000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10584000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10584000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10584000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076240 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076240 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses @@ -826,67 +826,67 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063604 system.cpu.dcache.demand_mshr_miss_rate::total 0.063604 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063604 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.063604 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77665.048544 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77665.048544 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77567.961165 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77567.961165 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63280.487805 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63280.487805 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73569.444444 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73569.444444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73569.444444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73569.444444 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73500 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 44 # number of replacements -system.cpu.icache.tags.tagsinuse 137.464664 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3536 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 137.523624 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3532 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.826087 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.812709 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 137.464664 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.268486 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.268486 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 137.523624 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.268601 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.268601 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 255 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 8101 # Number of tag accesses -system.cpu.icache.tags.data_accesses 8101 # Number of data accesses +system.cpu.icache.tags.tag_accesses 8095 # Number of tag accesses +system.cpu.icache.tags.data_accesses 8095 # Number of data accesses system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 3536 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3536 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3536 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3536 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3536 # number of overall hits -system.cpu.icache.overall_hits::total 3536 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses -system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25043490 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25043490 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25043490 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25043490 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25043490 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25043490 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3901 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3901 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3901 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093566 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.093566 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.093566 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.093566 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.093566 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.093566 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68612.301370 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68612.301370 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68612.301370 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68612.301370 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68612.301370 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68612.301370 # average overall miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 3532 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3532 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3532 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3532 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3532 # number of overall hits +system.cpu.icache.overall_hits::total 3532 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses +system.cpu.icache.overall_misses::total 366 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25091490 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25091490 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25091490 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25091490 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25091490 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25091490 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3898 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3898 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3898 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3898 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3898 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3898 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093894 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.093894 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.093894 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.093894 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.093894 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.093894 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68555.983607 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68555.983607 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68555.983607 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68555.983607 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68555.983607 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68555.983607 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 9833 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 47 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 97 # number of cycles access was blocked @@ -895,36 +895,36 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 101.371134 system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 44 # number of writebacks system.cpu.icache.writebacks::total 44 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 66 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 66 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 66 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 299 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 299 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 299 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22004990 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22004990 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22004990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22004990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22004990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22004990 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076647 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.076647 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.076647 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73595.284281 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73595.284281 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73595.284281 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73595.284281 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73595.284281 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73595.284281 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22025990 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22025990 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22025990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22025990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22025990 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22025990 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076706 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.076706 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.076706 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73665.518395 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73665.518395 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73665.518395 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73665.518395 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73665.518395 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73665.518395 # average overall mshr miss latency system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified @@ -934,16 +934,16 @@ system.cpu.l2cache.prefetcher.pfRemovedFull 0 # system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 17.355508 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 17.362749 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 41 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.073171 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9.226998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.128510 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000563 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 9.237342 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.125407 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000564 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000496 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.001059 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.001060 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1022 13 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id @@ -981,16 +981,16 @@ system.cpu.l2cache.overall_misses::cpu.data 133 # system.cpu.l2cache.overall_misses::total 424 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2460000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2460000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21645500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 21645500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7838000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7838000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21645500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10298000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31943500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21645500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10298000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31943500 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21666500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 21666500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7828000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7828000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21666500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10288000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31954500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21666500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10288000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31954500 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) @@ -1019,16 +1019,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.923611 system.cpu.l2cache.overall_miss_rate::total 0.957111 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82000 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74383.161512 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74383.161512 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76097.087379 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76097.087379 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74383.161512 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77428.571429 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75338.443396 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74383.161512 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77428.571429 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75338.443396 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74455.326460 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74455.326460 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76000 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76000 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74455.326460 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77353.383459 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75364.386792 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74455.326460 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77353.383459 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75364.386792 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1064,17 +1064,17 @@ system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1766 system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1766926 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2280000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2280000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19843000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19843000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6922500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6922500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19843000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9202500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29045500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19843000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9202500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19864000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19864000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6912500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6912500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19864000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9192500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29056500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19864000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9192500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1766926 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30812426 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30823426 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses @@ -1094,17 +1094,17 @@ system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33338.226415 # average HardPFReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68424.137931 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68424.137931 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70637.755102 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70637.755102 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68424.137931 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71894.531250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69486.842105 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68424.137931 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71894.531250 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68496.551724 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68496.551724 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70535.714286 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70535.714286 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68496.551724 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71816.406250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69513.157895 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68496.551724 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71816.406250 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65419.163482 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65442.518047 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -1173,7 +1173,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 445 # Request fanout histogram system.membus.reqLayer0.occupancy 554444 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 2338000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2338250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 11.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 888fdd0d2..00c469890 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu sim_ticks 24405000 # Number of ticks simulated final_tick 24405000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38911 # Simulator instruction rate (inst/s) -host_op_rate 38904 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 189891987 # Simulator tick rate (ticks/s) -host_mem_usage 234100 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 119579 # Simulator instruction rate (inst/s) +host_op_rate 119550 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 583509526 # Simulator tick rate (ticks/s) +host_mem_usage 251420 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 4999 # Number of instructions simulated sim_ops 4999 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 4 3.51% 93.86% # By system.physmem.bytesPerActivate::896-1023 3 2.63% 96.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 4 3.51% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 114 # Bytes accessed per row activation -system.physmem.totQLat 7577250 # Total ticks spent queuing -system.physmem.totMemAccLat 16371000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 7589250 # Total ticks spent queuing +system.physmem.totMemAccLat 16383000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16156.18 # Average queueing delay per DRAM burst +system.physmem.avgQLat 16181.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34906.18 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 34931.77 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1229.91 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1229.91 # Average system read bandwidth in MiByte/s @@ -228,9 +228,9 @@ system.physmem_0.preEnergy 98670 # En system.physmem_0.readEnergy 756840 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1602840 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 1603980 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 46560 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 8339100 # Energy for active power-down per rank (pJ) +system.physmem_0.actPowerDownEnergy 8337960 # Energy for active power-down per rank (pJ) system.physmem_0.prePowerDownEnergy 952800 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_0.totalEnergy 13833510 # Total energy per rank (pJ) @@ -247,29 +247,29 @@ system.physmem_1.preEnergy 333960 # En system.physmem_1.readEnergy 2591820 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4214580 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 89760 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 6593190 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 180480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 4208310 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 89280 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 6602310 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 178560 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 16490310 # Total energy per rank (pJ) -system.physmem_1.averagePower 675.693915 # Core power per rank (mW) +system.physmem_1.totalEnergy 16490760 # Total energy per rank (pJ) +system.physmem_1.averagePower 675.712354 # Core power per rank (mW) system.physmem_1.totalIdleTime 14889250 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 122500 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 470250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 464250 # Time in different power states system.physmem_1.memoryStateTime::ACT 8563750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 14468500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 14474500 # Time in different power states system.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2188 # Number of BP lookups -system.cpu.branchPred.condPredicted 1456 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 424 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1784 # Number of BTB lookups -system.cpu.branchPred.BTBHits 587 # Number of BTB hits +system.cpu.branchPred.lookups 2177 # Number of BP lookups +system.cpu.branchPred.condPredicted 1448 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 422 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1779 # Number of BTB lookups +system.cpu.branchPred.BTBHits 589 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.903587 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 252 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 33.108488 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 251 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 270 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 2 # Number of indirect target hits. @@ -299,91 +299,91 @@ system.cpu.pwrStateResidencyTicks::ON 24405000 # Cu system.cpu.numCycles 48811 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 9088 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13001 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2188 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 841 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5447 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 868 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 9085 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12947 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2177 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 842 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 5440 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 864 # Number of cycles fetch has spent squashing system.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2050 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15174 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.856795 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.144946 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2046 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 261 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15162 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.853911 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.140587 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11814 77.86% 77.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1507 9.93% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 111 0.73% 88.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 162 1.07% 89.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 279 1.84% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 100 0.66% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 140 0.92% 93.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 158 1.04% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 903 5.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11809 77.89% 77.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1506 9.93% 87.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 111 0.73% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 164 1.08% 89.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 279 1.84% 91.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 101 0.67% 92.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 136 0.90% 93.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 158 1.04% 94.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 898 5.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15174 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.044826 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.266354 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8420 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3450 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2768 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 142 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 394 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 183 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 15162 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.044601 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.265248 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8416 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3447 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2766 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 141 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 392 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 589 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 40 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12000 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 11962 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 160 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 394 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8571 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 620 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 392 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8568 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 617 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 1023 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2740 # Number of cycles rename is running +system.cpu.rename.RunCycles 2736 # Number of cycles rename is running system.cpu.rename.UnblockCycles 1826 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11562 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 11523 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 193 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 1606 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 6927 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13556 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13323 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 6897 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13509 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13276 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3292 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3635 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3605 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 13 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 323 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2468 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2464 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9014 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8995 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8118 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4025 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2012 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8108 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4006 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1995 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15174 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.534994 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.265800 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15162 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.534758 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.264874 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11850 78.09% 78.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1336 8.80% 86.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 728 4.80% 91.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 453 2.99% 94.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 341 2.25% 96.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 284 1.87% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 110 0.72% 99.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 53 0.35% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11839 78.08% 78.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1338 8.82% 86.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 727 4.79% 91.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 451 2.97% 94.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 343 2.26% 96.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 283 1.87% 98.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 110 0.73% 99.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 52 0.34% 99.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15174 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15162 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 6 3.33% 3.33% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available @@ -423,58 +423,58 @@ system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4775 58.82% 58.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2273 28.00% 86.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1063 13.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4767 58.79% 58.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2271 28.01% 86.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1063 13.11% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8118 # Type of FU issued -system.cpu.iq.rate 0.166315 # Inst issue rate +system.cpu.iq.FU_type_0::total 8108 # Type of FU issued +system.cpu.iq.rate 0.166110 # Inst issue rate system.cpu.iq.fu_busy_cnt 180 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022173 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31605 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 13057 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7337 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.022200 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31574 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 13019 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7329 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8296 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8286 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1333 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1329 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 257 # Number of stores squashed @@ -483,45 +483,45 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 394 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 490 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 392 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 487 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 74 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10621 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 10600 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 154 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2468 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2464 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 75 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 338 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 439 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7790 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 328 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 335 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 436 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7776 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2123 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 332 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1596 # number of nop insts executed -system.cpu.iew.exec_refs 3178 # number of memory reference insts executed -system.cpu.iew.exec_branches 1363 # Number of branches executed +system.cpu.iew.exec_nop 1594 # number of nop insts executed +system.cpu.iew.exec_refs 3172 # number of memory reference insts executed +system.cpu.iew.exec_branches 1361 # Number of branches executed system.cpu.iew.exec_stores 1049 # Number of stores executed -system.cpu.iew.exec_rate 0.159595 # Inst execution rate -system.cpu.iew.wb_sent 7432 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7339 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2867 # num instructions producing a value -system.cpu.iew.wb_consumers 4274 # num instructions consuming a value -system.cpu.iew.wb_rate 0.150355 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.670800 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4982 # The number of squashed insts skipped by commit +system.cpu.iew.exec_rate 0.159308 # Inst execution rate +system.cpu.iew.wb_sent 7424 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7331 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2863 # num instructions producing a value +system.cpu.iew.wb_consumers 4269 # num instructions consuming a value +system.cpu.iew.wb_rate 0.150192 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.670649 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4961 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 384 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14293 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.394599 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.198950 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 382 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14286 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.394792 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.199270 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 12101 84.66% 84.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 885 6.19% 90.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 521 3.65% 94.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 12095 84.66% 84.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 883 6.18% 90.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 522 3.65% 94.50% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 254 1.78% 96.28% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 160 1.12% 97.40% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 166 1.16% 98.56% # Number of insts commited each cycle @@ -531,7 +531,7 @@ system.cpu.commit.committed_per_cycle::8 102 0.71% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14293 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14286 # Number of insts commited each cycle system.cpu.commit.committedInsts 5640 # Number of instructions committed system.cpu.commit.committedOps 5640 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -582,46 +582,46 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5640 # Class of committed instruction system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 24800 # The number of ROB reads -system.cpu.rob.rob_writes 22133 # The number of ROB writes +system.cpu.rob.rob_reads 24772 # The number of ROB reads +system.cpu.rob.rob_writes 22085 # The number of ROB writes system.cpu.timesIdled 264 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 33637 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 33649 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4999 # Number of Instructions Simulated system.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated system.cpu.cpi 9.764153 # CPI: Cycles Per Instruction system.cpu.cpi_total 9.764153 # CPI: Total CPI of All Threads system.cpu.ipc 0.102415 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.102415 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10560 # number of integer regfile reads -system.cpu.int_regfile_writes 5141 # number of integer regfile writes +system.cpu.int_regfile_reads 10585 # number of integer regfile reads +system.cpu.int_regfile_writes 5135 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 161 # number of misc regfile reads system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.114159 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 91.124976 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2389 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.107143 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.064286 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.114159 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022245 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022245 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 91.124976 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022247 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022247 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5952 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5952 # Number of data accesses +system.cpu.dcache.tags.tag_accesses 5940 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5940 # Number of data accesses system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1838 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1838 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 557 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 557 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits -system.cpu.dcache.overall_hits::total 2395 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2389 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2389 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2389 # number of overall hits +system.cpu.dcache.overall_hits::total 2389 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 344 # number of WriteReq misses @@ -638,22 +638,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 46928999 system.cpu.dcache.demand_miss_latency::total 46928999 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 46928999 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 46928999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2005 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1999 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1999 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2906 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2906 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2906 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2906 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083292 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.083292 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2900 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2900 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2900 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2900 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083542 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.083542 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381798 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.381798 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.175843 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.175843 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.175843 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.175843 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.176207 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.176207 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.176207 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.176207 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76104.790419 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 76104.790419 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99475.287791 # average WriteReq miss latency @@ -692,14 +692,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13010499 system.cpu.dcache.demand_mshr_miss_latency::total 13010499 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13010499 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 13010499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044888 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044888 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048176 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048176 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048176 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048176 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048276 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048276 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048276 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048276 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89938.888889 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89938.888889 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98319.980000 # average WriteReq mshr miss latency @@ -710,57 +710,57 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 92932.135714 system.cpu.dcache.overall_avg_mshr_miss_latency::total 92932.135714 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 160.115290 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1613 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 160.153151 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1609 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 332 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.858434 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.846386 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 160.115290 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078181 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078181 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 160.153151 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078200 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078200 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 315 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.153809 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4432 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4432 # Number of data accesses +system.cpu.icache.tags.tag_accesses 4424 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4424 # Number of data accesses system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1613 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1613 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1613 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1613 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1613 # number of overall hits -system.cpu.icache.overall_hits::total 1613 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 1609 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1609 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1609 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1609 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1609 # number of overall hits +system.cpu.icache.overall_hits::total 1609 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses system.cpu.icache.overall_misses::total 437 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 35529000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 35529000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 35529000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 35529000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 35529000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 35529000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2050 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2050 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2050 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2050 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2050 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2050 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213171 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.213171 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.213171 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.213171 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.213171 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.213171 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81302.059497 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 81302.059497 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 81302.059497 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 81302.059497 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 81302.059497 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 81302.059497 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 35547000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 35547000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 35547000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 35547000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 35547000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 35547000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2046 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2046 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2046 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2046 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2046 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2046 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213587 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.213587 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.213587 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.213587 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.213587 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.213587 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81343.249428 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 81343.249428 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 81343.249428 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 81343.249428 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 81343.249428 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 81343.249428 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -781,36 +781,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 332 system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28112000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28112000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28112000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28112000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28112000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28112000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161951 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.161951 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.161951 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84674.698795 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84674.698795 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84674.698795 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 84674.698795 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84674.698795 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 84674.698795 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28124000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 28124000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28124000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 28124000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28124000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 28124000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.162268 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.162268 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.162268 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.162268 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162268 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.162268 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84710.843373 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84710.843373 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84710.843373 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 84710.843373 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84710.843373 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 84710.843373 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 253.317649 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 253.368786 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 469 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.042644 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 162.143256 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 91.174392 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004948 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002782 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007731 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 162.183576 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 91.185210 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004949 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002783 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007732 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 469 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id @@ -840,16 +840,16 @@ system.cpu.l2cache.overall_misses::cpu.data 140 # system.cpu.l2cache.overall_misses::total 469 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4840000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4840000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27581000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 27581000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27593000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 27593000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7956500 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 7956500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27581000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27593000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 12796500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 40377500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27581000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 40389500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27593000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 12796500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 40377500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 40389500 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) @@ -878,16 +878,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1 system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96800 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96800 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83832.826748 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83832.826748 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83869.300912 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83869.300912 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88405.555556 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88405.555556 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83832.826748 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83869.300912 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86092.750533 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83832.826748 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86118.336887 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83869.300912 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86092.750533 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86118.336887 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -908,16 +908,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 140 system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4340000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4340000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24291000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24291000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24303000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24303000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7056500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7056500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24291000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24303000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11396500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 35687500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24291000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 35699500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24303000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11396500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 35687500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 35699500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for ReadCleanReq accesses @@ -932,16 +932,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86800 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86800 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73832.826748 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73832.826748 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73869.300912 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73869.300912 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78405.555556 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78405.555556 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73832.826748 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73869.300912 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76092.750533 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73832.826748 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76118.336887 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73869.300912 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76092.750533 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76118.336887 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index b83fdc852..4dafeb8f4 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000106 # Nu sim_ticks 106125 # Number of ticks simulated final_tick 106125 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 110492 # Simulator instruction rate (inst/s) -host_op_rate 110472 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2077956 # Simulator tick rate (ticks/s) -host_mem_usage 415232 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 95829 # Simulator instruction rate (inst/s) +host_op_rate 95814 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1802278 # Simulator tick rate (ticks/s) +host_mem_usage 414992 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -401,13 +401,35 @@ system.ruby.miss_latency_hist_seqr::stdev 37.614530 system.ruby.miss_latency_hist_seqr | 577 39.20% 39.20% | 834 56.66% 95.86% | 40 2.72% 98.57% | 8 0.54% 99.12% | 8 0.54% 99.66% | 5 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1472 system.ruby.Directory.incomplete_times_seqr 1471 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.013833 # Average number of messages in buffer +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.997663 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.027703 # Average number of messages in buffer +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.765826 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.013870 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999350 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.027703 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999359 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 6206 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1472 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7678 # Number of cache demand accesses +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.013833 # Average number of messages in buffer +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.983246 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.072357 # Average number of messages in buffer +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999991 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.055406 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999943 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.013870 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.995053 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.013833 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.985696 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.013870 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.995816 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.083033 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.766579 # Average number of cycles messages are stalled in this MB system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 6.925795 system.ruby.network.routers0.msg_count.Control::2 1472 @@ -418,6 +440,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 11776 system.ruby.network.routers0.msg_bytes.Data::2 105696 system.ruby.network.routers0.msg_bytes.Response_Data::4 105984 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11744 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.027703 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.766014 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.013833 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.995307 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.013870 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998681 # Average number of cycles messages are stalled in this MB system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 6.925795 system.ruby.network.routers1.msg_count.Control::2 1472 @@ -428,6 +456,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 11776 system.ruby.network.routers1.msg_bytes.Data::2 105696 system.ruby.network.routers1.msg_bytes.Response_Data::4 105984 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11744 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.027703 # Average number of messages in buffer +system.ruby.network.int_link_buffers02.avg_stall_time 7.766466 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.013833 # Average number of messages in buffer +system.ruby.network.int_link_buffers08.avg_stall_time 2.992933 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.013870 # Average number of messages in buffer +system.ruby.network.int_link_buffers09.avg_stall_time 2.997993 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.013833 # Average number of messages in buffer +system.ruby.network.int_link_buffers13.avg_stall_time 4.988127 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.013870 # Average number of messages in buffer +system.ruby.network.int_link_buffers14.avg_stall_time 4.996561 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.027703 # Average number of messages in buffer +system.ruby.network.int_link_buffers17.avg_stall_time 9.766184 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.013833 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.990540 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.013870 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.997286 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.027703 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.766334 # Average number of cycles messages are stalled in this MB system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 6.925795 system.ruby.network.routers2.msg_count.Control::2 1472 diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 1c774fd71..f6ed1582b 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21268000 # Number of ticks simulated -final_tick 21268000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21189000 # Number of ticks simulated +final_tick 21189000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49400 # Simulator instruction rate (inst/s) -host_op_rate 49392 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 181337178 # Simulator tick rate (ticks/s) -host_mem_usage 231948 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 143245 # Simulator instruction rate (inst/s) +host_op_rate 143198 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 523712790 # Simulator tick rate (ticks/s) +host_mem_usage 249592 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 6400 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 21824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 6528 # Number of bytes read from this memory system.physmem.bytes_read::total 28352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21952 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 100 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 21824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21824 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 341 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 102 # Number of read requests responded to by this memory system.physmem.num_reads::total 443 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1032160993 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 300921572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1333082565 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1032160993 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1032160993 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1032160993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 300921572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1333082565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 1029968380 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 308084383 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1338052763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1029968380 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1029968380 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1029968380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 308084383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1338052763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 444 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 445 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28480 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 28416 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28480 # Total read bytes from the system interface side +system.physmem.bytesReadSys 28416 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -47,7 +47,7 @@ system.physmem.perBankRdBursts::1 42 # Pe system.physmem.perBankRdBursts::2 55 # Per bank write bursts system.physmem.perBankRdBursts::3 58 # Per bank write bursts system.physmem.perBankRdBursts::4 53 # Per bank write bursts -system.physmem.perBankRdBursts::5 62 # Per bank write bursts +system.physmem.perBankRdBursts::5 61 # Per bank write bursts system.physmem.perBankRdBursts::6 52 # Per bank write bursts system.physmem.perBankRdBursts::7 10 # Per bank write bursts system.physmem.perBankRdBursts::8 9 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21217500 # Total gap between requests +system.physmem.totGap 21128500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 445 # Read request sizes (log2) +system.physmem.readPktSize::6 444 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -92,9 +92,9 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 44 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -187,93 +187,93 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 75 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 351.573333 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.062906 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 340.509998 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23 30.67% 30.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18 24.00% 54.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11 14.67% 69.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2 2.67% 72.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.00% 76.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4 5.33% 81.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.67% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 4.00% 88.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 12.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 75 # Bytes accessed per row activation -system.physmem.totQLat 5980000 # Total ticks spent queuing -system.physmem.totMemAccLat 14323750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13438.20 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 348.631579 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 212.894378 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 337.912685 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24 31.58% 31.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17 22.37% 53.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 12 15.79% 69.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2 2.63% 72.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 3.95% 76.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4 5.26% 81.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.63% 84.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 11.84% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation +system.physmem.totQLat 5920000 # Total ticks spent queuing +system.physmem.totMemAccLat 14245000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13333.33 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32188.20 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1339.10 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32083.33 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1341.07 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1339.10 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1341.07 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.46 # Data bus utilization in percentage -system.physmem.busUtilRead 10.46 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.48 # Data bus utilization in percentage +system.physmem.busUtilRead 10.48 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 360 # Number of row buffer hits during reads +system.physmem.readRowHits 358 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.90 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.63 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47679.78 # Average gap between requests -system.physmem.pageHitRate 80.90 # Row buffer hit rate, read and write combined +system.physmem.avgGap 47586.71 # Average gap between requests +system.physmem.pageHitRate 80.63 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 528360 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 254265 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2877420 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 2870280 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3922170 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 3925590 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 28320 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5666370 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 64320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actPowerDownEnergy 5657820 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 38400 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 14570505 # Total energy per rank (pJ) -system.physmem_0.averagePower 685.066353 # Core power per rank (mW) -system.physmem_0.totalIdleTime 12593250 # Total Idle time Per DRAM Rank +system.physmem_0.totalEnergy 14532315 # Total energy per rank (pJ) +system.physmem_0.averagePower 685.810052 # Core power per rank (mW) +system.physmem_0.totalIdleTime 12505250 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 17500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 167250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8137250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12426000 # Time in different power states -system.physmem_1.actEnergy 78540 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 30360 # Energy for precharge commands per rank (pJ) +system.physmem_0.memoryStateTime::PRE_PDN 100250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8146250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 12405000 # Time in different power states +system.physmem_1.actEnergy 85680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 34155 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 299880 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 747840 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1408800 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 6431880 # Energy for active power-down per rank (pJ) +system.physmem_1.actBackEnergy 759810 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1412160 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 6380010 # Energy for active power-down per rank (pJ) system.physmem_1.prePowerDownEnergy 712320 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 10938900 # Total energy per rank (pJ) -system.physmem_1.averagePower 514.317955 # Core power per rank (mW) -system.physmem_1.totalIdleTime 13775500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3585000 # Time in different power states +system.physmem_1.totalEnergy 10913295 # Total energy per rank (pJ) +system.physmem_1.averagePower 515.021000 # Core power per rank (mW) +system.physmem_1.totalIdleTime 13660000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3594000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 1854750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1201500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 14106750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2411 # Number of BP lookups -system.cpu.branchPred.condPredicted 1982 # Number of conditional branches predicted +system.physmem_1.memoryStateTime::ACT 1229000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 13991250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2458 # Number of BP lookups +system.cpu.branchPred.condPredicted 2033 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 409 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2056 # Number of BTB lookups -system.cpu.branchPred.BTBHits 693 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2104 # Number of BTB lookups +system.cpu.branchPred.BTBHits 724 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 33.706226 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 227 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 35 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 130 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 19 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 111 # Number of indirect misses. +system.cpu.branchPred.BTBHitPct 34.410646 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 228 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 36 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 135 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 18 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 117 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 37 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -295,244 +295,244 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 21268000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 42537 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 21189000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 42379 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7674 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13369 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2411 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 939 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4149 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 849 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 7639 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13455 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2458 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 970 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4277 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 847 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1861 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 290 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12420 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.076409 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.475819 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1865 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12512 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.075368 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.471061 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10086 81.21% 81.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 166 1.34% 82.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 214 1.72% 84.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 147 1.18% 85.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 241 1.94% 87.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 150 1.21% 88.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 280 2.25% 90.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 148 1.19% 92.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 988 7.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10164 81.23% 81.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 163 1.30% 82.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 210 1.68% 84.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 146 1.17% 85.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 247 1.97% 87.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 148 1.18% 88.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 304 2.43% 90.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 158 1.26% 92.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 972 7.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12420 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.056680 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.314291 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7247 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2821 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1946 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 12512 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.058000 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.317492 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7217 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2933 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1957 # Number of cycles decode is running system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 276 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 324 # Number of times decode resolved a branch +system.cpu.decode.SquashCycles 275 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 791 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 149 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11479 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 451 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 276 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7415 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 800 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 463 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1897 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1569 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11042 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full +system.cpu.decode.DecodedInsts 11520 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 456 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 275 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7386 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 930 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 461 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1904 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1556 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11074 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 22 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1522 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9711 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17897 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17871 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1496 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9775 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17991 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17965 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4713 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4777 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 381 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1937 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1590 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 402 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1923 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10171 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8808 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4442 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3474 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12420 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.709179 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.511732 # Number of insts issued each cycle +system.cpu.memDep0.conflictingStores 32 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10204 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 65 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8807 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 41 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4477 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3567 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12512 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.703884 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.500750 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9305 74.92% 74.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 969 7.80% 82.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 656 5.28% 88.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 462 3.72% 91.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 429 3.45% 95.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 293 2.36% 97.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 212 1.71% 99.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 64 0.52% 99.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 30 0.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9387 75.02% 75.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 964 7.70% 82.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 667 5.33% 88.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 467 3.73% 91.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 439 3.51% 95.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 290 2.32% 97.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 213 1.70% 99.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 56 0.45% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 29 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12420 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12512 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 12 6.06% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 88 44.44% 50.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 87 43.94% 94.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 94.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 11 5.56% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 12 6.22% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 87 45.08% 51.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 83 43.01% 94.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 94.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 11 5.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5530 62.78% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1811 20.56% 83.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1439 16.34% 99.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5542 62.93% 62.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1815 20.61% 83.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1422 16.15% 99.70% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 2 0.02% 99.73% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 24 0.27% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8808 # Type of FU issued -system.cpu.iq.rate 0.207067 # Inst issue rate -system.cpu.iq.fu_busy_cnt 198 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022480 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30220 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14647 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8115 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8807 # Type of FU issued +system.cpu.iq.rate 0.207815 # Inst issue rate +system.cpu.iq.fu_busy_cnt 193 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021914 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30293 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14716 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8133 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 67 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8967 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8961 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 39 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 84 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 976 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 544 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 962 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 524 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 276 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 722 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 71 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10234 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1937 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1590 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 275 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 818 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 73 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10269 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 43 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1923 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 53 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 60 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly +system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 71 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 256 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 324 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8463 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1703 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 345 # Number of squashed instructions skipped in execute +system.cpu.iew.branchMispredicts 327 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8488 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1719 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 319 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3080 # number of memory reference insts executed -system.cpu.iew.exec_branches 1358 # Number of branches executed -system.cpu.iew.exec_stores 1377 # Number of stores executed -system.cpu.iew.exec_rate 0.198956 # Inst execution rate -system.cpu.iew.wb_sent 8242 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8142 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4448 # num instructions producing a value -system.cpu.iew.wb_consumers 7158 # num instructions consuming a value -system.cpu.iew.wb_rate 0.191410 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.621403 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4444 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 3083 # number of memory reference insts executed +system.cpu.iew.exec_branches 1364 # Number of branches executed +system.cpu.iew.exec_stores 1364 # Number of stores executed +system.cpu.iew.exec_rate 0.200288 # Inst execution rate +system.cpu.iew.wb_sent 8262 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8160 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4466 # num instructions producing a value +system.cpu.iew.wb_consumers 7207 # num instructions consuming a value +system.cpu.iew.wb_rate 0.192548 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.619675 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4479 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 270 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11718 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.494282 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.358473 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11808 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.490515 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.351526 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9553 81.52% 81.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 850 7.25% 88.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 527 4.50% 93.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 215 1.83% 95.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 176 1.50% 96.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 112 0.96% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 126 1.08% 98.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 49 0.42% 99.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 110 0.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9643 81.66% 81.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 845 7.16% 88.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 531 4.50% 93.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 215 1.82% 95.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 177 1.50% 96.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 110 0.93% 97.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 132 1.12% 98.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 50 0.42% 99.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 105 0.89% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11718 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11808 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -582,310 +582,310 @@ system.cpu.commit.op_class_0::FloatMemWrite 19 0.33% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5792 # Class of committed instruction -system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 21844 # The number of ROB reads -system.cpu.rob.rob_writes 21175 # The number of ROB writes -system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30117 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 105 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 21974 # The number of ROB reads +system.cpu.rob.rob_writes 21247 # The number of ROB writes +system.cpu.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29867 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.344095 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.344095 # CPI: Total CPI of All Threads -system.cpu.ipc 0.136164 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.136164 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13368 # number of integer regfile reads -system.cpu.int_regfile_writes 7153 # number of integer regfile writes +system.cpu.cpi 7.316816 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.316816 # CPI: Total CPI of All Threads +system.cpu.ipc 0.136671 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.136671 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13468 # number of integer regfile reads +system.cpu.int_regfile_writes 7187 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 64.389343 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2206 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 21.627451 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 66.953799 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2204 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 104 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 21.192308 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 64.389343 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.015720 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.015720 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5390 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5390 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1485 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1485 # number of ReadReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 66.953799 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.016346 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.016346 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 104 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 80 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.025391 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5386 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5386 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 1483 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1483 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 721 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 721 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2206 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2206 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2206 # number of overall hits -system.cpu.dcache.overall_hits::total 2206 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2204 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2204 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2204 # number of overall hits +system.cpu.dcache.overall_hits::total 2204 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 112 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 112 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 325 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 325 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 438 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 438 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 438 # number of overall misses -system.cpu.dcache.overall_misses::total 438 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8211000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8211000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 32489496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 32489496 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 40700496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 40700496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 40700496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 40700496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1598 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1598 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses +system.cpu.dcache.overall_misses::total 437 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8129500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8129500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 32497996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 32497996 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 40627496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 40627496 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 40627496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 40627496 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1595 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1595 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2644 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2644 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2644 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2644 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070713 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070713 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2641 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2641 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2641 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2641 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070219 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070219 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.310707 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.310707 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.165658 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.165658 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.165658 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.165658 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72663.716814 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72663.716814 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99967.680000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 99967.680000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 92923.506849 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 92923.506849 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 92923.506849 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 92923.506849 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 612 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.165468 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.165468 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.165468 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.165468 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72584.821429 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72584.821429 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99993.833846 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 99993.833846 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 92969.098398 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 92969.098398 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 92969.098398 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 92969.098398 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 749 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 102 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.222222 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 278 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 278 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 334 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 334 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 334 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 334 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 57 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 57 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 332 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 332 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 332 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 332 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 58 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 58 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 104 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 104 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 104 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 104 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4669500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4669500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4693998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4693998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9363498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9363498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9363498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9363498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035670 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035670 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 105 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 105 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 105 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 105 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4818000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4818000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4694498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4694498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9512498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9512498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9512498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9512498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036364 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036364 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.039334 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.039334 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.039334 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.039334 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81921.052632 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81921.052632 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99872.297872 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99872.297872 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90033.634615 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 90033.634615 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90033.634615 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 90033.634615 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.039758 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.039758 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.039758 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.039758 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83068.965517 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83068.965517 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99882.936170 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99882.936170 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90595.219048 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 90595.219048 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90595.219048 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 90595.219048 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 168.912200 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1425 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 168.700112 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1435 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.083095 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.111748 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 168.912200 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082477 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082477 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 168.700112 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082373 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082373 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4071 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4071 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1425 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1425 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1425 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1425 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1425 # number of overall hits -system.cpu.icache.overall_hits::total 1425 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 436 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 436 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 436 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 436 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 436 # number of overall misses -system.cpu.icache.overall_misses::total 436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 33901500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 33901500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 33901500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 33901500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 33901500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 33901500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1861 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1861 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1861 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1861 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1861 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1861 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234283 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.234283 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.234283 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.234283 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.234283 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.234283 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77755.733945 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77755.733945 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77755.733945 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77755.733945 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77755.733945 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77755.733945 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 567 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 4079 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4079 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1435 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1435 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1435 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1435 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1435 # number of overall hits +system.cpu.icache.overall_hits::total 1435 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 430 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 430 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 430 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 430 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 430 # number of overall misses +system.cpu.icache.overall_misses::total 430 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 33426000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 33426000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 33426000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 33426000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 33426000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 33426000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1865 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1865 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1865 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1865 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1865 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1865 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230563 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.230563 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.230563 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.230563 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.230563 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.230563 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77734.883721 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77734.883721 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77734.883721 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77734.883721 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77734.883721 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77734.883721 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 569 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 113.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 113.800000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 86 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 86 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 86 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 80 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 80 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 80 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28298000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28298000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28298000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28298000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28298000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28298000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188071 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188071 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188071 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.188071 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188071 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.188071 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80851.428571 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80851.428571 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80851.428571 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 63.518527 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005118 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001938 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007056 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 166.990617 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 65.219974 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005096 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001990 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007087 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 443 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013519 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4075 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4075 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 6 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 6 # number of ReadCleanReq hits +system.cpu.l2cache.tags.tag_accesses 4083 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4083 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 8 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 8 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits +system.cpu.l2cache.demand_hits::total 10 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 2 # number of overall hits -system.cpu.l2cache.overall_hits::total 8 # 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number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 342 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 103 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 445 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 342 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 103 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4150500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4150500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24128000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24128000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4159000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4159000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24128000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8309500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32437500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24128000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8309500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32437500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.982857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.964912 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.964912 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980769 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.982379 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980769 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.982379 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88297.872340 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88297.872340 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70566.860465 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70566.860465 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73327.272727 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73327.272727 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70566.860465 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80225.490196 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72775.784753 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70566.860465 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80225.490196 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72775.784753 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 454 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 8 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.977143 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.977143 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.965517 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.977143 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.978022 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.977143 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.978022 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88308.510638 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88308.510638 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70549.707602 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70549.707602 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74267.857143 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74267.857143 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70549.707602 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.757282 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72893.258427 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70549.707602 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.757282 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72893.258427 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 455 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 10 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 350 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 57 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 58 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 206 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 905 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 209 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 908 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28992 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 454 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.017621 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.131715 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 455 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.021978 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.146773 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 446 98.24% 98.24% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 8 1.76% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 445 97.80% 97.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 10 2.20% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 454 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 227000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 455 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 227500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 523500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 156000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 444 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 396 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution system.membus.trans_dist::ReadExResp 47 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 398 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 397 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 887 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28352 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 445 # Request fanout histogram +system.membus.snoop_fanout::samples 444 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 445 # Request fanout histogram +system.membus.snoop_fanout::total 444 # Request fanout histogram system.membus.reqLayer0.occupancy 553000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2325250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 10.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2325750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt index 6dc71361b..7c3cea8ee 100644 --- a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000014 # Nu sim_ticks 14435000 # Number of ticks simulated final_tick 14435000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 13240 # Simulator instruction rate (inst/s) -host_op_rate 13237 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 119615611 # Simulator tick rate (ticks/s) -host_mem_usage 232036 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 136295 # Simulator instruction rate (inst/s) +host_op_rate 136181 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1229999304 # Simulator tick rate (ticks/s) +host_mem_usage 249560 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 1597 # Number of instructions simulated sim_ops 1597 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -261,16 +261,16 @@ system.pwrStateResidencyTicks::UNDEFINED 14435000 # Cu system.cpu.branchPred.lookups 995 # Number of BP lookups system.cpu.branchPred.condPredicted 543 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 229 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 945 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 944 # Number of BTB lookups system.cpu.branchPred.BTBHits 100 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 10.582011 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 10.593220 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 204 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 202 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 11 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 193 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 64 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectMisses 191 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses diff --git a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt index 25d8ca24a..4e1344fa0 100644 --- a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000008 # Nu sim_ticks 7939500 # Number of ticks simulated final_tick 7939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 22942 # Simulator instruction rate (inst/s) -host_op_rate 22935 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 114711600 # Simulator tick rate (ticks/s) -host_mem_usage 232976 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 81718 # Simulator instruction rate (inst/s) +host_op_rate 81674 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 408398393 # Simulator tick rate (ticks/s) +host_mem_usage 251348 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 1587 # Number of instructions simulated sim_ops 1587 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -258,18 +258,18 @@ system.physmem_1.memoryStateTime::PRE_PDN 0 # T system.physmem_1.memoryStateTime::ACT 0 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 1252 # Number of BP lookups -system.cpu.branchPred.condPredicted 681 # Number of conditional branches predicted +system.cpu.branchPred.lookups 1255 # Number of BP lookups +system.cpu.branchPred.condPredicted 684 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 259 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1186 # Number of BTB lookups -system.cpu.branchPred.BTBHits 300 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1188 # Number of BTB lookups +system.cpu.branchPred.BTBHits 302 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 25.295110 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 25.420875 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 253 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 25 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 228 # Number of indirect misses. +system.cpu.branchPred.indirectLookups 254 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 24 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 230 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 67 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -296,9 +296,9 @@ system.cpu.numCycles 15880 # nu system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 3023 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 4970 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1252 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 325 # Number of branches that fetch has predicted taken +system.cpu.fetch.Insts 4974 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1255 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 326 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 964 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 540 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs @@ -307,71 +307,71 @@ system.cpu.fetch.IcacheWaitRetryStallCycles 1 # system.cpu.fetch.CacheLines 803 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 191 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 4447 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.117607 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.502607 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.118507 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.504003 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 3513 79.00% 79.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 134 3.01% 82.01% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 87 1.96% 83.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 91 2.05% 86.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 45 1.01% 87.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 71 1.60% 88.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 65 1.46% 90.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 64 1.44% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90 2.02% 85.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 45 1.01% 87.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 71 1.60% 88.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 65 1.46% 90.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 65 1.46% 91.52% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 377 8.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 4447 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.078841 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.312972 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 3140 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 349 # Number of cycles decode is blocked +system.cpu.fetch.branchRate 0.079030 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.313224 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 3139 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 350 # Number of cycles decode is blocked system.cpu.decode.RunCycles 756 # Number of cycles decode is running system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 185 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 187 # Number of times decode resolved a branch +system.cpu.decode.BranchResolved 287 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 86 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3862 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 3866 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 255 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 185 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 3239 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 107 # Number of cycles rename is blocking +system.cpu.rename.IdleCycles 3237 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 108 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 243 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 672 # Number of cycles rename is running +system.cpu.rename.RunCycles 673 # Number of cycles rename is running system.cpu.rename.UnblockCycles 1 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3496 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 3508 # Number of instructions processed by rename system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full -system.cpu.rename.RenamedOperands 2449 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4481 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4481 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 2456 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4500 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4500 # Number of integer rename lookups system.cpu.rename.CommittedMaps 1077 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1372 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 1379 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 16 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 16 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 82 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 548 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 470 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 547 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 471 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 3003 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 3013 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 17 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2694 # Number of instructions issued +system.cpu.iq.iqInstsIssued 2703 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1432 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 769 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 1442 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 770 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 4447 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.605802 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.426720 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.607826 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.430977 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 3524 79.24% 79.24% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 251 5.64% 84.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185 4.16% 89.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 180 4.05% 93.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 147 3.31% 96.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 65 1.46% 97.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 57 1.28% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 182 4.09% 88.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 180 4.05% 93.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 148 3.33% 96.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 66 1.48% 97.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 58 1.30% 99.15% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 26 0.58% 99.73% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle @@ -417,73 +417,73 @@ system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 9 0.33% 0.33% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1755 65.14% 65.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.04% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 512 19.01% 84.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 417 15.48% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1765 65.30% 65.63% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.04% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 511 18.90% 84.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 417 15.43% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2694 # Type of FU issued -system.cpu.iq.rate 0.169647 # Inst issue rate +system.cpu.iq.FU_type_0::total 2703 # Type of FU issued +system.cpu.iq.rate 0.170214 # Inst issue rate system.cpu.iq.fu_busy_cnt 70 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025984 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 9926 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4453 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2310 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.025897 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 9944 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4473 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2318 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2755 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 2764 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 14 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 259 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 258 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 1 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 191 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 192 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 185 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 106 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 107 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3020 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 3030 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 66 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 548 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 470 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 547 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 471 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 17 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall @@ -491,41 +491,41 @@ system.cpu.iew.memOrderViolationEvents 1 # Nu system.cpu.iew.predictedTakenIncorrect 12 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 187 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 199 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2452 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 472 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 242 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2459 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 471 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 244 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 847 # number of memory reference insts executed -system.cpu.iew.exec_branches 563 # Number of branches executed +system.cpu.iew.exec_refs 846 # number of memory reference insts executed +system.cpu.iew.exec_branches 566 # Number of branches executed system.cpu.iew.exec_stores 375 # Number of stores executed -system.cpu.iew.exec_rate 0.154408 # Inst execution rate -system.cpu.iew.wb_sent 2361 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2310 # cumulative count of insts written-back -system.cpu.iew.wb_producers 793 # num instructions producing a value -system.cpu.iew.wb_consumers 1130 # num instructions consuming a value -system.cpu.iew.wb_rate 0.145466 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.701770 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 1436 # The number of squashed insts skipped by commit +system.cpu.iew.exec_rate 0.154849 # Inst execution rate +system.cpu.iew.wb_sent 2369 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2318 # cumulative count of insts written-back +system.cpu.iew.wb_producers 798 # num instructions producing a value +system.cpu.iew.wb_consumers 1140 # num instructions consuming a value +system.cpu.iew.wb_rate 0.145970 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.700000 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 1446 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 174 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 4156 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.381858 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.174026 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 4155 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.381949 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.175996 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 3562 85.71% 85.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 208 5.00% 90.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 146 3.51% 94.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 85 2.05% 96.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 60 1.44% 97.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34 0.82% 98.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 3563 85.75% 85.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 208 5.01% 90.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 142 3.42% 94.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86 2.07% 96.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 60 1.44% 97.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 35 0.84% 98.53% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 26 0.63% 99.16% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 14 0.34% 99.49% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 21 0.51% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 4156 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 4155 # Number of insts commited each cycle system.cpu.commit.committedInsts 1587 # Number of instructions committed system.cpu.commit.committedOps 1587 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -576,8 +576,8 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1587 # Class of committed instruction system.cpu.commit.bw_lim_events 21 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 7041 # The number of ROB reads -system.cpu.rob.rob_writes 6340 # The number of ROB writes +system.cpu.rob.rob_reads 7050 # The number of ROB reads +system.cpu.rob.rob_writes 6361 # The number of ROB writes system.cpu.timesIdled 96 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 11433 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1587 # Number of Instructions Simulated @@ -586,14 +586,14 @@ system.cpu.cpi 10.006301 # CP system.cpu.cpi_total 10.006301 # CPI: Total CPI of All Threads system.cpu.ipc 0.099937 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.099937 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3068 # number of integer regfile reads -system.cpu.int_regfile_writes 1663 # number of integer regfile writes +system.cpu.int_regfile_reads 3116 # number of integer regfile reads +system.cpu.int_regfile_writes 1668 # number of integer regfile writes system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 24.179106 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 626 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 625 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 33 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 18.969697 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 18.939394 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 24.179106 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.005903 # Average percentage of cache occupancy @@ -601,17 +601,17 @@ system.cpu.dcache.tags.occ_percent::total 0.005903 # A system.cpu.dcache.tags.occ_task_id_blocks::1024 33 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.008057 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1497 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1497 # Number of data accesses +system.cpu.dcache.tags.tag_accesses 1495 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1495 # Number of data accesses system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 432 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 432 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 431 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 431 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 194 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 194 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 626 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 626 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 626 # number of overall hits -system.cpu.dcache.overall_hits::total 626 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 625 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 625 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 625 # number of overall hits +system.cpu.dcache.overall_hits::total 625 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 21 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 21 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses @@ -628,22 +628,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7406500 system.cpu.dcache.demand_miss_latency::total 7406500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 7406500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 7406500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 453 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 453 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 452 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 452 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 279 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 732 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 732 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 732 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 732 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.046358 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.046358 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 731 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 731 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 731 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 731 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.046460 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.046460 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.304659 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.304659 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.144809 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.144809 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.144809 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.144809 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.145007 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.145007 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.145007 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.145007 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62142.857143 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 62142.857143 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71782.352941 # average WriteReq miss latency @@ -682,14 +682,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2572500 system.cpu.dcache.demand_mshr_miss_latency::total 2572500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2572500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 2572500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035320 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035320 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035398 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035398 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.064516 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.064516 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046448 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.046448 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046448 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.046448 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046512 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.046512 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046512 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.046512 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71312.500000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71312.500000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79527.777778 # average WriteReq mshr miss latency diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt index e859af8d4..d3136e926 100644 --- a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 27947 # Number of ticks simulated final_tick 27947 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 19868 # Simulator instruction rate (inst/s) -host_op_rate 19863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 349695 # Simulator tick rate (ticks/s) -host_mem_usage 390760 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 89967 # Simulator instruction rate (inst/s) +host_op_rate 89916 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1582597 # Simulator tick rate (ticks/s) +host_mem_usage 409032 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 1587 # Number of instructions simulated sim_ops 1587 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -397,13 +397,35 @@ system.ruby.miss_latency_hist_seqr::stdev 27.345330 system.ruby.miss_latency_hist_seqr | 0 0.00% 0.00% | 202 46.12% 46.12% | 224 51.14% 97.26% | 2 0.46% 97.72% | 2 0.46% 98.17% | 7 1.60% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 1 0.23% 100.00% system.ruby.miss_latency_hist_seqr::total 438 system.ruby.Directory.incomplete_times_seqr 437 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.015529 # Average number of messages in buffer +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.986546 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.031201 # Average number of messages in buffer +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.686704 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015672 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.997531 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.031201 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.997567 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 1727 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 438 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 2165 # Number of cache demand accesses +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.015529 # Average number of messages in buffer +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.904322 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.077501 # Average number of messages in buffer +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999964 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.062402 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999785 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.015672 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.981215 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.015529 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.918205 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.015672 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.984113 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.093316 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.689566 # Average number of cycles messages are stalled in this MB system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 7.800479 system.ruby.network.routers0.msg_count.Control::2 438 @@ -414,6 +436,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 3504 system.ruby.network.routers0.msg_bytes.Data::2 31248 system.ruby.network.routers0.msg_bytes.Response_Data::4 31536 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 3472 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.031201 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.687419 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.015529 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.973021 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.015672 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.994991 # Average number of cycles messages are stalled in this MB system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 7.800479 system.ruby.network.routers1.msg_count.Control::2 438 @@ -424,6 +452,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 3504 system.ruby.network.routers1.msg_bytes.Data::2 31248 system.ruby.network.routers1.msg_bytes.Response_Data::4 31536 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 3472 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.031201 # Average number of messages in buffer +system.ruby.network.int_link_buffers02.avg_stall_time 7.689137 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015529 # Average number of messages in buffer +system.ruby.network.int_link_buffers08.avg_stall_time 2.959425 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.015672 # Average number of messages in buffer +system.ruby.network.int_link_buffers09.avg_stall_time 2.992379 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.015529 # Average number of messages in buffer +system.ruby.network.int_link_buffers13.avg_stall_time 4.932017 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.015672 # Average number of messages in buffer +system.ruby.network.int_link_buffers14.avg_stall_time 4.986940 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.031201 # Average number of messages in buffer +system.ruby.network.int_link_buffers17.avg_stall_time 9.688064 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.015529 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.945756 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.015672 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.989695 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.031201 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.688636 # Average number of cycles messages are stalled in this MB system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 7.800479 system.ruby.network.routers2.msg_count.Control::2 438 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index c1f6ae8aa..90c8ea4fc 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000087 # Nu sim_ticks 86746 # Number of ticks simulated final_tick 86746 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 115505 # Simulator instruction rate (inst/s) -host_op_rate 115448 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1879120 # Simulator tick rate (ticks/s) -host_mem_usage 414144 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 122857 # Simulator instruction rate (inst/s) +host_op_rate 122829 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1999767 # Simulator tick rate (ticks/s) +host_mem_usage 415460 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -381,13 +381,35 @@ system.ruby.miss_latency_hist_seqr::stdev 35.397665 system.ruby.miss_latency_hist_seqr | 610 47.32% 47.32% | 633 49.11% 96.43% | 36 2.79% 99.22% | 1 0.08% 99.30% | 6 0.47% 99.77% | 2 0.16% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1289 system.ruby.Directory.incomplete_times_seqr 1288 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.014813 # Average number of messages in buffer +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.995735 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029672 # Average number of messages in buffer +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.745697 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.014859 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999205 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029672 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999216 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.014813 # Average number of messages in buffer +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.969659 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.077916 # Average number of messages in buffer +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999988 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.059345 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999931 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.014859 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.993948 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.014813 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.974063 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.014859 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.994882 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.088925 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.746619 # Average number of cycles messages are stalled in this MB system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 7.418209 system.ruby.network.routers0.msg_count.Control::2 1289 @@ -398,6 +420,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 10312 system.ruby.network.routers0.msg_bytes.Data::2 92520 system.ruby.network.routers0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10280 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.029672 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.745928 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.014813 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.991446 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.014859 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998386 # Average number of cycles messages are stalled in this MB system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 7.418209 system.ruby.network.routers1.msg_count.Control::2 1289 @@ -408,6 +436,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 10312 system.ruby.network.routers1.msg_bytes.Data::2 92520 system.ruby.network.routers1.msg_bytes.Response_Data::4 92808 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10280 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.029672 # Average number of messages in buffer +system.ruby.network.int_link_buffers02.avg_stall_time 7.746481 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.014813 # Average number of messages in buffer +system.ruby.network.int_link_buffers08.avg_stall_time 2.987135 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.014859 # Average number of messages in buffer +system.ruby.network.int_link_buffers09.avg_stall_time 2.997545 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.014813 # Average number of messages in buffer +system.ruby.network.int_link_buffers13.avg_stall_time 4.978443 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.014859 # Average number of messages in buffer +system.ruby.network.int_link_buffers14.avg_stall_time 4.995792 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.029672 # Average number of messages in buffer +system.ruby.network.int_link_buffers17.avg_stall_time 9.746135 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.014813 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.982801 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014859 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.996680 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.029672 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.746320 # Average number of cycles messages are stalled in this MB system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 7.418209 system.ruby.network.routers2.msg_count.Control::2 1289 diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index ff0e9261d..136389a07 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,55 +1,55 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 22466500 # Number of ticks simulated -final_tick 22466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000023 # Number of seconds simulated +sim_ticks 22516500 # Number of ticks simulated +final_tick 22516500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24766 # Simulator instruction rate (inst/s) -host_op_rate 44863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 103395613 # Simulator tick rate (ticks/s) -host_mem_usage 253532 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 69174 # Simulator instruction rate (inst/s) +host_op_rate 125309 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 289442861 # Simulator tick rate (ticks/s) +host_mem_usage 271352 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory -system.physmem.bytes_read::total 26752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory +system.physmem.bytes_read::total 26688 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory -system.physmem.num_reads::total 418 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 789085972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 401664701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1190750673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 789085972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 789085972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 789085972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 401664701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1190750673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 418 # Number of read requests accepted +system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory +system.physmem.num_reads::total 417 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 787333733 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 397930407 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1185264140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 787333733 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 787333733 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 787333733 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 397930407 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1185264140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 417 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 418 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26752 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 26688 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26752 # Total read bytes from the system interface side +system.physmem.bytesReadSys 26688 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 32 # Per bank write bursts +system.physmem.perBankRdBursts::0 31 # Per bank write bursts system.physmem.perBankRdBursts::1 1 # Per bank write bursts system.physmem.perBankRdBursts::2 5 # Per bank write bursts system.physmem.perBankRdBursts::3 8 # Per bank write bursts -system.physmem.perBankRdBursts::4 50 # Per bank write bursts +system.physmem.perBankRdBursts::4 51 # Per bank write bursts system.physmem.perBankRdBursts::5 44 # Per bank write bursts system.physmem.perBankRdBursts::6 21 # Per bank write bursts -system.physmem.perBankRdBursts::7 37 # Per bank write bursts +system.physmem.perBankRdBursts::7 36 # Per bank write bursts system.physmem.perBankRdBursts::8 24 # Per bank write bursts system.physmem.perBankRdBursts::9 71 # Per bank write bursts system.physmem.perBankRdBursts::10 64 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22337000 # Total gap between requests +system.physmem.totGap 22387500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 418 # Read request sizes (log2) +system.physmem.readPktSize::6 417 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -92,9 +92,9 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -187,336 +187,336 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 95 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 246.568421 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 159.892164 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 259.040400 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 37 38.95% 38.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 23 24.21% 63.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16 16.84% 80.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 6.32% 86.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 2.11% 88.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 3.16% 91.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.11% 93.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 2.11% 95.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4 4.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 95 # Bytes accessed per row activation -system.physmem.totQLat 6799250 # Total ticks spent queuing -system.physmem.totMemAccLat 14636750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2090000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16266.15 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 98 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 239.673469 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 154.283411 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 255.721287 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 41 41.84% 41.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22 22.45% 64.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16 16.33% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 7.14% 87.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1 1.02% 88.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 3.06% 91.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.04% 93.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 2.04% 95.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4 4.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 98 # Bytes accessed per row activation +system.physmem.totQLat 6651000 # Total ticks spent queuing +system.physmem.totMemAccLat 14469750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15949.64 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35016.15 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1190.75 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 34699.64 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1185.26 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1190.75 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1185.26 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.30 # Data bus utilization in percentage -system.physmem.busUtilRead 9.30 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.26 # Data bus utilization in percentage +system.physmem.busUtilRead 9.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.67 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 310 # Number of row buffer hits during reads +system.physmem.readRowHits 307 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.16 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.62 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 53437.80 # Average gap between requests -system.physmem.pageHitRate 74.16 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 285600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125235 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1413720 # Energy for read commands per rank (pJ) +system.physmem.avgGap 53687.05 # Average gap between requests +system.physmem.pageHitRate 73.62 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 307020 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 140415 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1406580 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2399130 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 30240 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 7645980 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 138240 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actBackEnergy 2488050 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 28320 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 7581570 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 138720 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 13267425 # Total energy per rank (pJ) -system.physmem_0.averagePower 590.516301 # Core power per rank (mW) -system.physmem_0.totalIdleTime 17035500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states +system.physmem_0.totalEnergy 13319955 # Total energy per rank (pJ) +system.physmem_0.averagePower 591.537915 # Core power per rank (mW) +system.physmem_0.totalIdleTime 16888750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 17500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 359250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 4794250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 16769500 # Time in different power states -system.physmem_1.actEnergy 485520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 235290 # Energy for precharge commands per rank (pJ) +system.physmem_0.memoryStateTime::PRE_PDN 361000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 4997500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 16620500 # Time in different power states +system.physmem_1.actEnergy 478380 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 231495 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1570800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2962290 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 82560 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 7183140 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 2961150 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 80160 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 7211640 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 13750320 # Total energy per rank (pJ) -system.physmem_1.averagePower 612.009347 # Core power per rank (mW) -system.physmem_1.totalIdleTime 14672000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 109000 # Time in different power states +system.physmem_1.totalEnergy 13762905 # Total energy per rank (pJ) +system.physmem_1.averagePower 611.209282 # Core power per rank (mW) +system.physmem_1.totalIdleTime 15691750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 103000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 3500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 6091750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 15742250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 3488 # Number of BP lookups -system.cpu.branchPred.condPredicted 3488 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 571 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2960 # Number of BTB lookups +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 6065500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 15828000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 3542 # Number of BP lookups +system.cpu.branchPred.condPredicted 3542 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 576 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 3006 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 360 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 94 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2960 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 483 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2477 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 410 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 386 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 97 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3006 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 514 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2492 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 416 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22466500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 44934 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 22516500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 45034 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12177 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15717 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3488 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 843 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 10477 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 12047 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16169 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3542 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 900 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 10333 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1321 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 78 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1414 # Number of stall cycles due to pending traps +system.cpu.fetch.MiscStallCycles 74 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1582 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 15 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 2026 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 276 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 24836 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.141770 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.668775 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 2077 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 274 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 24737 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.175931 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.701309 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20599 82.94% 82.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 175 0.70% 83.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 165 0.66% 84.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 225 0.91% 85.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 209 0.84% 86.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 222 0.89% 86.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 269 1.08% 88.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 159 0.64% 88.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2813 11.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20389 82.42% 82.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 178 0.72% 83.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 168 0.68% 83.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 246 0.99% 84.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 215 0.87% 85.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 220 0.89% 86.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 262 1.06% 87.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 167 0.68% 88.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2892 11.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 24836 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.077625 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.349780 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12221 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8128 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3370 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 457 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 24737 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.078652 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.359040 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12032 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8141 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3437 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 467 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 660 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 26405 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 26977 # Number of instructions handled by decode system.cpu.rename.SquashCycles 660 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 12481 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1971 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1213 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3524 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4987 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 24875 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 82 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 4849 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 27762 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 60616 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 34638 # Number of integer rename lookups +system.cpu.rename.IdleCycles 12302 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2135 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1085 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3589 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4966 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 25351 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 77 # Number of times rename has blocked due to IQ full +system.cpu.rename.SQFullEvents 4831 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 28444 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 61768 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 35524 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16699 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1436 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2622 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1598 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21775 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 18112 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 144 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12051 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16553 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 24836 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.729264 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.710701 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 17381 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 24 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 1430 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2685 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1593 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 22118 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 18234 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 157 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12393 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 17118 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 24737 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.737114 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.712019 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19689 79.28% 79.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1202 4.84% 84.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 867 3.49% 87.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 575 2.32% 89.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 814 3.28% 93.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 575 2.32% 95.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 614 2.47% 97.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 364 1.47% 99.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 136 0.55% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19548 79.02% 79.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1204 4.87% 83.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 865 3.50% 87.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 579 2.34% 89.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 831 3.36% 93.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 615 2.49% 95.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 628 2.54% 98.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 340 1.37% 99.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127 0.51% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 24836 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 24737 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 223 79.93% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 41 14.70% 94.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 15 5.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 218 79.85% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 40 14.65% 94.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 15 5.49% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14478 79.94% 79.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.03% 79.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2258 12.47% 92.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1357 7.49% 99.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14605 80.10% 80.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.03% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2269 12.44% 92.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1341 7.35% 99.98% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.98% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 4 0.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 18112 # Type of FU issued -system.cpu.iq.rate 0.403080 # Inst issue rate -system.cpu.iq.fu_busy_cnt 279 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015404 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 61475 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 33854 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16418 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 18234 # Type of FU issued +system.cpu.iq.rate 0.404894 # Inst issue rate +system.cpu.iq.fu_busy_cnt 273 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014972 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 61627 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 34538 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16576 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18385 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18501 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 199 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1569 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1632 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 663 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 658 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 660 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1482 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 1518 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 153 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21798 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 34 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2622 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1598 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 22140 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 9 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2685 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1593 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 152 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 680 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 798 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 17038 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2047 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1074 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 127 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 676 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 803 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 17166 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2051 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1068 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3306 # number of memory reference insts executed -system.cpu.iew.exec_branches 1731 # Number of branches executed -system.cpu.iew.exec_stores 1259 # Number of stores executed -system.cpu.iew.exec_rate 0.379178 # Inst execution rate -system.cpu.iew.wb_sent 16737 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16422 # cumulative count of insts written-back -system.cpu.iew.wb_producers 11018 # num instructions producing a value -system.cpu.iew.wb_consumers 17146 # num instructions consuming a value -system.cpu.iew.wb_rate 0.365469 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.642599 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 12050 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 3303 # number of memory reference insts executed +system.cpu.iew.exec_branches 1740 # Number of branches executed +system.cpu.iew.exec_stores 1252 # Number of stores executed +system.cpu.iew.exec_rate 0.381179 # Inst execution rate +system.cpu.iew.wb_sent 16892 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16580 # cumulative count of insts written-back +system.cpu.iew.wb_producers 11141 # num instructions producing a value +system.cpu.iew.wb_consumers 17351 # num instructions consuming a value +system.cpu.iew.wb_rate 0.368166 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.642096 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 12392 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 648 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 22793 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.427631 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.307612 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 22646 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.430407 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.314219 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19537 85.71% 85.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1003 4.40% 90.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 565 2.48% 92.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 727 3.19% 95.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 384 1.68% 97.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 133 0.58% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 124 0.54% 98.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 72 0.32% 98.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 248 1.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19391 85.63% 85.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1011 4.46% 90.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 560 2.47% 92.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 726 3.21% 95.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 383 1.69% 97.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 128 0.57% 98.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 118 0.52% 98.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 74 0.33% 98.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 255 1.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 22793 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 22646 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -566,283 +566,283 @@ system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 9747 # Class of committed instruction -system.cpu.commit.bw_lim_events 248 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 44342 # The number of ROB reads -system.cpu.rob.rob_writes 45672 # The number of ROB writes -system.cpu.timesIdled 156 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20098 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 255 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 44530 # The number of ROB reads +system.cpu.rob.rob_writes 46401 # The number of ROB writes +system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20297 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.352045 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.352045 # CPI: Total CPI of All Threads -system.cpu.ipc 0.119731 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.119731 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 21663 # number of integer regfile reads -system.cpu.int_regfile_writes 13219 # number of integer regfile writes +system.cpu.cpi 8.370632 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.370632 # CPI: Total CPI of All Threads +system.cpu.ipc 0.119465 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.119465 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 21947 # number of integer regfile reads +system.cpu.int_regfile_writes 13377 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8286 # number of cc regfile reads -system.cpu.cc_regfile_writes 5066 # number of cc regfile writes -system.cpu.misc_regfile_reads 7640 # number of misc regfile reads +system.cpu.cc_regfile_reads 8355 # number of cc regfile reads +system.cpu.cc_regfile_writes 5130 # number of cc regfile writes +system.cpu.misc_regfile_reads 7644 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.537314 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2520 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.872340 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 81.908470 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2549 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 18.207143 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.537314 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019907 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019907 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5567 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5567 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1661 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1661 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 859 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2520 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2520 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2520 # number of overall hits -system.cpu.dcache.overall_hits::total 2520 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 193 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 193 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 193 # number of overall misses -system.cpu.dcache.overall_misses::total 193 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10224000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10224000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7069500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7069500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17293500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17293500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17293500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17293500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1778 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1778 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 81.908470 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.019997 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.019997 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5608 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5608 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 1687 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1687 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 862 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2549 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2549 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2549 # number of overall hits +system.cpu.dcache.overall_hits::total 2549 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 112 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 112 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 185 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 185 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 185 # number of overall misses +system.cpu.dcache.overall_misses::total 185 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9812000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9812000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6772000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6772000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16584000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16584000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16584000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16584000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1799 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1799 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065804 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.065804 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.071139 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.071139 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.071139 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.071139 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87384.615385 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 87384.615385 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93019.736842 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 93019.736842 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 89603.626943 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 89603.626943 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 89603.626943 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 89603.626943 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2734 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2734 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2734 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2734 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062257 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.062257 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078075 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.078075 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.067666 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.067666 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.067666 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.067666 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87607.142857 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 87607.142857 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 92767.123288 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 92767.123288 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 89643.243243 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 89643.243243 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 89643.243243 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 89643.243243 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 29 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 52 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 52 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 52 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 52 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6446000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6446000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6993500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6993500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13439500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13439500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13439500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13439500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036558 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036558 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051972 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051972 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051972 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051972 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 99169.230769 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 99169.230769 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 92019.736842 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92019.736842 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 95315.602837 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 95315.602837 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 95315.602837 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 95315.602837 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 45 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 45 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 45 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 67 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 67 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6419000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6419000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6699000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6699000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13118000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13118000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13118000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13118000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.037243 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.037243 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.078075 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.078075 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051207 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051207 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051207 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051207 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 95805.970149 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 95805.970149 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91767.123288 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91767.123288 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 93700 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 93700 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 93700 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 93700 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 130.259615 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1641 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 130.523512 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1695 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.902878 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.097122 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.259615 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063603 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063603 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 130.523512 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063732 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063732 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 278 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.135742 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4330 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4330 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1641 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1641 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1641 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1641 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1641 # number of overall hits -system.cpu.icache.overall_hits::total 1641 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 385 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 385 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 385 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 385 # number of overall misses -system.cpu.icache.overall_misses::total 385 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30145000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30145000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30145000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30145000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30145000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30145000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2026 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2026 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2026 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2026 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2026 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2026 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.190030 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.190030 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.190030 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.190030 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.190030 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.190030 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78298.701299 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 78298.701299 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 78298.701299 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 78298.701299 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 78298.701299 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 78298.701299 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 171 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 4432 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4432 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1695 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1695 # 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number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30098500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30098500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30098500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2077 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2077 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2077 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2077 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2077 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2077 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183919 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.183919 # 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average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 277 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 277 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 67 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 67 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 418 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 418 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6119500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6119500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20006500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20006500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5698000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5698000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20006500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11817500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 31824000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20006500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11817500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 31824000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5859500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5859500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20109500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20109500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5647500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5647500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20109500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11507000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 31616500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20109500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11507000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31616500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for ReadCleanReq accesses @@ -905,91 +905,91 @@ system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997613 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997613 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80519.736842 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80519.736842 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72225.631769 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72225.631769 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87661.538462 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87661.538462 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72225.631769 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83812.056738 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76133.971292 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72225.631769 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83812.056738 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76133.971292 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 419 # Total number of requests made to the snoop filter. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80267.123288 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80267.123288 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72597.472924 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72597.472924 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 84291.044776 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84291.044776 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72597.472924 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82192.857143 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75818.944844 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72597.472924 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82192.857143 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75818.944844 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 343 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 76 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 76 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 278 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 67 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 556 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 838 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 26816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 419 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002387 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.048853 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002392 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.048912 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 418 99.76% 99.76% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 417 99.76% 99.76% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 419 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 209500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 417000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 342 # Transaction distribution -system.membus.trans_dist::ReadExReq 76 # Transaction distribution -system.membus.trans_dist::ReadExResp 76 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 342 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 836 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 836 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 344 # Transaction distribution +system.membus.trans_dist::ReadExReq 73 # Transaction distribution +system.membus.trans_dist::ReadExResp 73 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 344 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 834 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 834 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 834 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 418 # Request fanout histogram +system.membus.snoop_fanout::samples 417 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 418 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 418 # Request fanout histogram -system.membus.reqLayer0.occupancy 506000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2231250 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 417 # Request fanout histogram +system.membus.reqLayer0.occupancy 504000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2226500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 9.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index c59c92e77..87a90ab33 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000092 # Nu sim_ticks 91859 # Number of ticks simulated final_tick 91859 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 91408 # Simulator instruction rate (inst/s) -host_op_rate 165563 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1559913 # Simulator tick rate (ticks/s) -host_mem_usage 432272 # Number of bytes of host memory used +host_inst_rate 94122 # Simulator instruction rate (inst/s) +host_op_rate 170479 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1606243 # Simulator tick rate (ticks/s) +host_mem_usage 432368 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated @@ -388,13 +388,35 @@ system.ruby.miss_latency_hist_seqr::stdev 33.880423 system.ruby.miss_latency_hist_seqr | 751 54.54% 54.54% | 589 42.77% 97.31% | 26 1.89% 99.20% | 4 0.29% 99.49% | 3 0.22% 99.71% | 4 0.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1377 system.ruby.Directory.incomplete_times_seqr 1376 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.014947 # Average number of messages in buffer +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.996691 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029937 # Average number of messages in buffer +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.743740 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.014990 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999249 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029937 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999260 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.014947 # Average number of messages in buffer +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.976377 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.096364 # Average number of messages in buffer +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999989 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.059874 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999935 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.014990 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.994285 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.014947 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.979817 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.014990 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.995167 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.089723 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.744611 # Average number of cycles messages are stalled in this MB system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 7.484297 system.ruby.network.routers0.msg_count.Control::2 1377 @@ -405,6 +427,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 11016 system.ruby.network.routers0.msg_bytes.Data::2 98856 system.ruby.network.routers0.msg_bytes.Response_Data::4 99144 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10984 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.029937 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.743958 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.014947 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.993359 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.014990 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998476 # Average number of cycles messages are stalled in this MB system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 7.484297 system.ruby.network.routers1.msg_count.Control::2 1377 @@ -415,6 +443,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 11016 system.ruby.network.routers1.msg_bytes.Data::2 98856 system.ruby.network.routers1.msg_bytes.Response_Data::4 99144 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10984 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.029937 # Average number of messages in buffer +system.ruby.network.int_link_buffers02.avg_stall_time 7.744481 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.014947 # Average number of messages in buffer +system.ruby.network.int_link_buffers08.avg_stall_time 2.990007 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.014990 # Average number of messages in buffer +system.ruby.network.int_link_buffers09.avg_stall_time 2.997681 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.014947 # Average number of messages in buffer +system.ruby.network.int_link_buffers13.avg_stall_time 4.983235 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.014990 # Average number of messages in buffer +system.ruby.network.int_link_buffers14.avg_stall_time 4.996027 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.029937 # Average number of messages in buffer +system.ruby.network.int_link_buffers17.avg_stall_time 9.744154 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.014947 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.986632 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014990 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.996865 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.029937 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.744328 # Average number of cycles messages are stalled in this MB system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 7.484297 system.ruby.network.routers2.msg_count.Control::2 1377 diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt index 9b1a7b7c9..255fcdbff 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000027 # Number of seconds simulated -sim_ticks 26661500 # Number of ticks simulated -final_tick 26661500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000026 # Number of seconds simulated +sim_ticks 25563000 # Number of ticks simulated +final_tick 25563000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 29979 # Simulator instruction rate (inst/s) -host_op_rate 29977 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62584510 # Simulator tick rate (ticks/s) -host_mem_usage 237004 # Number of bytes of host memory used -host_seconds 0.43 # Real time elapsed on the host -sim_insts 12770 # Number of instructions simulated -sim_ops 12770 # Number of ops (including micro ops) simulated +host_inst_rate 149418 # Simulator instruction rate (inst/s) +host_op_rate 149401 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 290951659 # Simulator tick rate (ticks/s) +host_mem_usage 254508 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +sim_insts 13125 # Number of instructions simulated +sim_ops 13125 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 21888 # Number of bytes read from this memory -system.physmem.bytes_read::total 61888 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 40000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 40000 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 625 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 342 # Number of read requests responded to by this memory -system.physmem.num_reads::total 967 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1500290681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 820959061 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2321249742 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1500290681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1500290681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1500290681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 820959061 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2321249742 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 968 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 25563000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11200 # Number of bytes read from this memory +system.physmem.bytes_read::total 31488 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 20288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 20288 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 175 # Number of read requests responded to by this memory +system.physmem.num_reads::total 492 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 793647068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 438133239 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1231780307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 793647068 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 793647068 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 793647068 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 438133239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1231780307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 492 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 968 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 492 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61952 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 31488 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61952 # Total read bytes from the system interface side +system.physmem.bytesReadSys 31488 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 84 # Per bank write bursts -system.physmem.perBankRdBursts::1 150 # Per bank write bursts -system.physmem.perBankRdBursts::2 77 # Per bank write bursts -system.physmem.perBankRdBursts::3 58 # Per bank write bursts -system.physmem.perBankRdBursts::4 90 # Per bank write bursts -system.physmem.perBankRdBursts::5 45 # Per bank write bursts -system.physmem.perBankRdBursts::6 33 # Per bank write bursts -system.physmem.perBankRdBursts::7 50 # Per bank write bursts -system.physmem.perBankRdBursts::8 42 # Per bank write bursts -system.physmem.perBankRdBursts::9 38 # Per bank write bursts -system.physmem.perBankRdBursts::10 28 # Per bank write bursts -system.physmem.perBankRdBursts::11 34 # Per bank write bursts -system.physmem.perBankRdBursts::12 15 # Per bank write bursts -system.physmem.perBankRdBursts::13 120 # Per bank write bursts -system.physmem.perBankRdBursts::14 67 # Per bank write bursts -system.physmem.perBankRdBursts::15 37 # Per bank write bursts +system.physmem.perBankRdBursts::0 14 # Per bank write bursts +system.physmem.perBankRdBursts::1 155 # Per bank write bursts +system.physmem.perBankRdBursts::2 30 # Per bank write bursts +system.physmem.perBankRdBursts::3 55 # Per bank write bursts +system.physmem.perBankRdBursts::4 70 # Per bank write bursts +system.physmem.perBankRdBursts::5 0 # Per bank write bursts +system.physmem.perBankRdBursts::6 6 # Per bank write bursts +system.physmem.perBankRdBursts::7 3 # Per bank write bursts +system.physmem.perBankRdBursts::8 43 # Per bank write bursts +system.physmem.perBankRdBursts::9 15 # Per bank write bursts +system.physmem.perBankRdBursts::10 26 # Per bank write bursts +system.physmem.perBankRdBursts::11 0 # Per bank write bursts +system.physmem.perBankRdBursts::12 0 # Per bank write bursts +system.physmem.perBankRdBursts::13 2 # Per bank write bursts +system.physmem.perBankRdBursts::14 44 # Per bank write bursts +system.physmem.perBankRdBursts::15 29 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26630500 # Total gap between requests +system.physmem.totGap 25412500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 968 # Read request sizes (log2) +system.physmem.readPktSize::6 492 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,12 +91,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 332 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -187,115 +187,115 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 202 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 289.584158 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.299588 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 295.891915 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 69 34.16% 34.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 55 27.23% 61.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 20 9.90% 71.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 16 7.92% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 9 4.46% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7 3.47% 87.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9 4.46% 91.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 1.49% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 14 6.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 202 # Bytes accessed per row activation -system.physmem.totQLat 15941250 # Total ticks spent queuing -system.physmem.totMemAccLat 34091250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4840000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16468.23 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 105 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 284.647619 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 175.785516 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 296.753264 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 38 36.19% 36.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 31 29.52% 65.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6 5.71% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 9 8.57% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 2.86% 82.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4 3.81% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5 4.76% 91.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 2.86% 94.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 5.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 105 # Bytes accessed per row activation +system.physmem.totQLat 8936250 # Total ticks spent queuing +system.physmem.totMemAccLat 18161250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2460000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18163.11 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35218.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2323.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 36913.11 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1231.78 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2323.65 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1231.78 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 18.15 # Data bus utilization in percentage -system.physmem.busUtilRead 18.15 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.62 # Data bus utilization in percentage +system.physmem.busUtilRead 9.62 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.46 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.77 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 755 # Number of row buffer hits during reads +system.physmem.readRowHits 382 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.00 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.64 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 27510.85 # Average gap between requests -system.physmem.pageHitRate 78.00 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 849660 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 436425 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4191180 # Energy for read commands per rank (pJ) +system.physmem.avgGap 51651.42 # Average gap between requests +system.physmem.pageHitRate 77.64 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 564060 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 288420 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2377620 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6126930 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5973030 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actBackEnergy 4052700 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 52800 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 7250970 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 244800 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 19470105 # Total energy per rank (pJ) -system.physmem_0.averagePower 730.243038 # Core power per rank (mW) -system.physmem_0.totalIdleTime 12953500 # Total Idle time Per DRAM Rank +system.physmem_0.totalEnergy 16675290 # Total energy per rank (pJ) +system.physmem_0.averagePower 652.302186 # Core power per rank (mW) +system.physmem_0.totalIdleTime 16451750 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 12735000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 13102250 # Time in different power states -system.physmem_1.actEnergy 671160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 330165 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2720340 # Energy for read commands per rank (pJ) +system.physmem_0.memoryStateTime::PRE_PDN 637500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8201250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 15903750 # Time in different power states +system.physmem_1.actEnergy 221340 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 110055 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1135260 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4611870 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 162240 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 6909540 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 373920 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 2074800 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 239040 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 8714160 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 492000 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 17623155 # Total energy per rank (pJ) -system.physmem_1.averagePower 660.971589 # Core power per rank (mW) -system.physmem_1.totalIdleTime 16131250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 312000 # Time in different power states +system.physmem_1.totalEnergy 14830575 # Total energy per rank (pJ) +system.physmem_1.averagePower 580.140824 # Core power per rank (mW) +system.physmem_1.totalIdleTime 20195750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 443500 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 973000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9438250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 15158250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 4864 # Number of BP lookups -system.cpu.branchPred.condPredicted 2895 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 795 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 3714 # Number of BTB lookups -system.cpu.branchPred.BTBHits 1183 # Number of BTB hits +system.physmem_1.memoryStateTime::PRE_PDN 1279500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 3943500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 19116500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 25563000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 5883 # Number of BP lookups +system.cpu.branchPred.condPredicted 3464 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1044 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 4417 # Number of BTB lookups +system.cpu.branchPred.BTBHits 1219 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.852450 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 710 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 762 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 147 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 615 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 133 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 27.597917 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 791 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 1012 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 40 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 972 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 246 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4131 # DTB read hits -system.cpu.dtb.read_misses 76 # DTB read misses +system.cpu.dtb.read_hits 4167 # DTB read hits +system.cpu.dtb.read_misses 88 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4207 # DTB read accesses -system.cpu.dtb.write_hits 2011 # DTB write hits -system.cpu.dtb.write_misses 48 # DTB write misses +system.cpu.dtb.read_accesses 4255 # DTB read accesses +system.cpu.dtb.write_hits 2106 # DTB write hits +system.cpu.dtb.write_misses 58 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2059 # DTB write accesses -system.cpu.dtb.data_hits 6142 # DTB hits -system.cpu.dtb.data_misses 124 # DTB misses +system.cpu.dtb.write_accesses 2164 # DTB write accesses +system.cpu.dtb.data_hits 6273 # DTB hits +system.cpu.dtb.data_misses 146 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6266 # DTB accesses -system.cpu.itb.fetch_hits 3836 # ITB hits -system.cpu.itb.fetch_misses 50 # ITB misses +system.cpu.dtb.data_accesses 6419 # DTB accesses +system.cpu.itb.fetch_hits 4394 # ITB hits +system.cpu.itb.fetch_misses 52 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 3886 # ITB accesses +system.cpu.itb.fetch_accesses 4446 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -308,878 +308,872 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload0.num_syscalls 17 # Number of system calls -system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 26661500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 53324 # number of cpu cycles simulated +system.cpu.workload0.num_syscalls 18 # Number of system calls +system.cpu.workload1.num_syscalls 18 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 25563000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 51127 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 748 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 27869 # Number of instructions fetch has processed -system.cpu.fetch.Branches 4864 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2040 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9408 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 875 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 344 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 3836 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 566 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 26305 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.059456 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.449327 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 960 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 33549 # Number of instructions fetch has processed +system.cpu.fetch.Branches 5883 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2050 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9426 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1118 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 4394 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 660 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 17609 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.905219 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.084149 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21280 80.90% 80.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 504 1.92% 82.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 391 1.49% 84.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 446 1.70% 86.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 478 1.82% 87.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 367 1.40% 89.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 469 1.78% 90.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 276 1.05% 92.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2094 7.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11843 67.26% 67.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 481 2.73% 69.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 427 2.42% 72.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 478 2.71% 75.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 423 2.40% 77.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 397 2.25% 79.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 518 2.94% 82.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 341 1.94% 84.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2701 15.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 26305 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.091216 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.522635 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36539 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 10373 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3958 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 496 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 725 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 405 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 151 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 24588 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 377 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 725 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 36883 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3499 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1435 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4115 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5434 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 23584 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 222 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 329 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4703 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 17574 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 29532 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 29514 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 17609 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.115066 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.656189 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 18146 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 10408 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5085 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 609 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 960 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1283 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 29203 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 227 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 960 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18571 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3611 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1447 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 5248 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5371 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 27754 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 18 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 466 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 832 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4294 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 20868 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 34818 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 34800 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 9154 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8420 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 57 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1617 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1925 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1093 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2578 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1286 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 15 # Number of conflicting loads. -system.cpu.memDep1.conflictingStores 4 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21800 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 19298 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9080 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4750 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 26305 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.733625 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.450843 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 9408 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 11460 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 54 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 1221 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2635 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1335 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. +system.cpu.memDep1.insertedLoads 2668 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1295 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 8 # Number of conflicting loads. +system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 25217 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21059 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12140 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 6785 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 17609 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.195923 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.068924 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 18975 72.13% 72.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 2364 8.99% 81.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1624 6.17% 87.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1293 4.92% 92.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1059 4.03% 96.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 566 2.15% 98.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 282 1.07% 99.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 87 0.33% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 55 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11762 66.80% 66.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1075 6.10% 72.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1081 6.14% 79.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 919 5.22% 84.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 899 5.11% 89.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 701 3.98% 93.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 574 3.26% 96.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 264 1.50% 98.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 334 1.90% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 26305 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 17609 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 29 9.60% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 193 63.91% 73.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77 25.50% 99.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 3 0.99% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 153 31.03% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 227 46.04% 77.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 109 22.11% 99.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 4 0.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5886 66.05% 66.07% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2014 22.60% 88.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 999 11.21% 99.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 1 0.01% 99.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 7 0.08% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7042 67.16% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2285 21.79% 88.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1146 10.93% 99.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 1 0.01% 99.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 7 0.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8912 # Type of FU issued +system.cpu.iq.FU_type_0::total 10486 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 6849 65.94% 65.96% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMultAcc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMisc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2410 23.20% 89.20% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1114 10.73% 99.92% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7119 67.33% 67.35% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.36% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMultAcc 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMisc 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2310 21.85% 89.23% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1131 10.70% 99.92% # Type of FU issued system.cpu.iq.FU_type_1::FloatMemRead 1 0.01% 99.93% # Type of FU issued system.cpu.iq.FU_type_1::FloatMemWrite 7 0.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 10386 # Type of FU issued -system.cpu.iq.FU_type::total 19298 0.00% 0.00% # Type of FU issued -system.cpu.iq.rate 0.361901 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 154 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 148 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 302 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.007980 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.007669 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.015649 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 65211 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 30942 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 17509 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 43 # Number of floating instruction queue reads +system.cpu.iq.FU_type_1::total 10573 # Type of FU issued +system.cpu.iq.FU_type::total 21059 0.00% 0.00% # Type of FU issued +system.cpu.iq.rate 0.411896 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 245 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 248 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 493 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.011634 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.011776 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.023410 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 60282 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 37413 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19074 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 19573 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 39 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 21524 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 24 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 740 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1418 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 228 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 450 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 290 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 97 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.cacheBlocked 58 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 83 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1393 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 14 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 421 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1434 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 13 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 405 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 234 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 57 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 725 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1992 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 420 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21985 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 174 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 4503 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2379 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 21 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 390 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 134 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 638 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 772 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 18590 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 1946 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2264 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4210 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 708 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 960 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2021 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 347 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 25404 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 199 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 5303 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2630 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 49 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 341 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 167 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 860 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1027 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 19999 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2117 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2148 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4265 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1060 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 63 # number of nop insts executed -system.cpu.iew.exec_nop::1 71 # number of nop insts executed -system.cpu.iew.exec_nop::total 134 # number of nop insts executed -system.cpu.iew.exec_refs::0 2943 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3338 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6281 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1393 # Number of branches executed -system.cpu.iew.exec_branches::1 1580 # Number of branches executed -system.cpu.iew.exec_branches::total 2973 # Number of branches executed -system.cpu.iew.exec_stores::0 997 # Number of stores executed -system.cpu.iew.exec_stores::1 1074 # Number of stores executed -system.cpu.iew.exec_stores::total 2071 # Number of stores executed -system.cpu.iew.exec_rate 0.348624 # Inst execution rate -system.cpu.iew.wb_sent::0 8287 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9496 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 17783 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 8202 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9327 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 17529 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 4343 # num instructions producing a value -system.cpu.iew.wb_producers::1 4920 # num instructions producing a value -system.cpu.iew.wb_producers::total 9263 # num instructions producing a value -system.cpu.iew.wb_consumers::0 5887 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6620 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 12507 # num instructions consuming a value -system.cpu.iew.wb_rate::0 0.153814 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.174912 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.328726 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.737727 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.743202 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.740625 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 9130 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 646 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 26287 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.487085 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.404867 # Number of insts commited each cycle +system.cpu.iew.exec_nop::0 69 # number of nop insts executed +system.cpu.iew.exec_nop::1 69 # number of nop insts executed +system.cpu.iew.exec_nop::total 138 # number of nop insts executed +system.cpu.iew.exec_refs::0 3217 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3234 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6451 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1607 # Number of branches executed +system.cpu.iew.exec_branches::1 1627 # Number of branches executed +system.cpu.iew.exec_branches::total 3234 # Number of branches executed +system.cpu.iew.exec_stores::0 1100 # Number of stores executed +system.cpu.iew.exec_stores::1 1086 # Number of stores executed +system.cpu.iew.exec_stores::total 2186 # Number of stores executed +system.cpu.iew.exec_rate 0.391163 # Inst execution rate +system.cpu.iew.wb_sent::0 9679 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9769 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 19448 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9504 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9590 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 19094 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 4946 # num instructions producing a value +system.cpu.iew.wb_producers::1 5011 # num instructions producing a value +system.cpu.iew.wb_producers::total 9957 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6500 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6565 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 13065 # num instructions consuming a value +system.cpu.iew.wb_rate::0 0.185890 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.187572 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.373462 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.760923 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.763290 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.762113 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 12156 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 36 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 887 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 17042 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.772151 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.826014 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21303 81.04% 81.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2500 9.51% 90.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 926 3.52% 94.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 402 1.53% 95.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 249 0.95% 96.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 154 0.59% 97.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 214 0.81% 97.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 116 0.44% 98.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 423 1.61% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 13049 76.57% 76.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1202 7.05% 83.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 934 5.48% 89.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 454 2.66% 91.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 336 1.97% 93.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 195 1.14% 94.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 209 1.23% 96.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 150 0.88% 96.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 513 3.01% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 26287 # Number of insts commited each cycle -system.cpu.commit.committedInsts::0 6402 # Number of instructions committed -system.cpu.commit.committedInsts::1 6402 # Number of instructions committed -system.cpu.commit.committedInsts::total 12804 # Number of instructions committed -system.cpu.commit.committedOps::0 6402 # Number of ops (including micro ops) committed -system.cpu.commit.committedOps::1 6402 # Number of ops (including micro ops) committed -system.cpu.commit.committedOps::total 12804 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 17042 # Number of insts commited each cycle +system.cpu.commit.committedInsts::0 6547 # Number of instructions committed +system.cpu.commit.committedInsts::1 6612 # Number of instructions committed +system.cpu.commit.committedInsts::total 13159 # Number of instructions committed +system.cpu.commit.committedOps::0 6547 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps::1 6612 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps::total 13159 # Number of ops (including micro ops) committed system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed -system.cpu.commit.refs::0 2050 # Number of memory references committed -system.cpu.commit.refs::1 2050 # Number of memory references committed -system.cpu.commit.refs::total 4100 # Number of memory references committed -system.cpu.commit.loads::0 1185 # Number of loads committed -system.cpu.commit.loads::1 1185 # Number of loads committed -system.cpu.commit.loads::total 2370 # Number of loads committed +system.cpu.commit.refs::0 2102 # Number of memory references committed +system.cpu.commit.refs::1 2124 # Number of memory references committed +system.cpu.commit.refs::total 4226 # Number of memory references committed +system.cpu.commit.loads::0 1217 # Number of loads committed +system.cpu.commit.loads::1 1234 # Number of loads committed +system.cpu.commit.loads::total 2451 # Number of loads committed system.cpu.commit.membars::0 0 # Number of memory barriers committed system.cpu.commit.membars::1 0 # Number of memory barriers committed system.cpu.commit.membars::total 0 # Number of memory barriers committed -system.cpu.commit.branches::0 1056 # Number of branches committed -system.cpu.commit.branches::1 1056 # Number of branches committed -system.cpu.commit.branches::total 2112 # Number of branches committed +system.cpu.commit.branches::0 1082 # Number of branches committed +system.cpu.commit.branches::1 1095 # Number of branches committed +system.cpu.commit.branches::total 2177 # Number of branches committed system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions. system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions. system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions. -system.cpu.commit.int_insts::0 6319 # Number of committed integer instructions. -system.cpu.commit.int_insts::1 6319 # Number of committed integer instructions. -system.cpu.commit.int_insts::total 12638 # Number of committed integer instructions. -system.cpu.commit.function_calls::0 127 # Number of function calls committed. -system.cpu.commit.function_calls::1 127 # Number of function calls committed. -system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 4330 67.64% 67.93% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 1 0.02% 67.95% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 1184 18.49% 86.47% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 858 13.40% 99.88% # Class of committed instruction +system.cpu.commit.int_insts::0 6462 # Number of committed integer instructions. +system.cpu.commit.int_insts::1 6526 # Number of committed integer instructions. +system.cpu.commit.int_insts::total 12988 # Number of committed integer instructions. +system.cpu.commit.function_calls::0 132 # Number of function calls committed. +system.cpu.commit.function_calls::1 133 # Number of function calls committed. +system.cpu.commit.function_calls::total 265 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 19 0.29% 0.29% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 4423 67.56% 67.85% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 1 0.02% 67.86% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.86% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.89% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1216 18.57% 86.47% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 878 13.41% 99.88% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.89% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 6402 # Class of committed instruction -system.cpu.commit.op_class_1::No_OpClass 19 0.30% 0.30% # Class of committed instruction -system.cpu.commit.op_class_1::IntAlu 4330 67.64% 67.93% # Class of committed instruction -system.cpu.commit.op_class_1::IntMult 1 0.02% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::FloatMultAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::FloatMisc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::MemRead 1184 18.49% 86.47% # Class of committed instruction -system.cpu.commit.op_class_1::MemWrite 858 13.40% 99.88% # Class of committed instruction +system.cpu.commit.op_class_0::total 6547 # Class of committed instruction +system.cpu.commit.op_class_1::No_OpClass 19 0.29% 0.29% # Class of committed instruction +system.cpu.commit.op_class_1::IntAlu 4466 67.54% 67.83% # Class of committed instruction +system.cpu.commit.op_class_1::IntMult 1 0.02% 67.85% # Class of committed instruction +system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.85% # Class of committed instruction +system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::FloatMultAcc 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::FloatMisc 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_1::MemRead 1233 18.65% 86.52% # Class of committed instruction +system.cpu.commit.op_class_1::MemWrite 883 13.35% 99.88% # Class of committed instruction system.cpu.commit.op_class_1::FloatMemRead 1 0.02% 99.89% # Class of committed instruction system.cpu.commit.op_class_1::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_1::total 6402 # Class of committed instruction -system.cpu.commit.op_class::total 12804 0.00% 0.00% # Class of committed instruction -system.cpu.commit.bw_lim_events 423 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 113065 # The number of ROB reads -system.cpu.rob.rob_writes 45570 # The number of ROB writes -system.cpu.timesIdled 413 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27019 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts::0 6385 # Number of Instructions Simulated -system.cpu.committedInsts::1 6385 # Number of Instructions Simulated -system.cpu.committedInsts::total 12770 # Number of Instructions Simulated -system.cpu.committedOps::0 6385 # Number of Ops (including micro ops) Simulated -system.cpu.committedOps::1 6385 # Number of Ops (including micro ops) Simulated -system.cpu.committedOps::total 12770 # Number of Ops (including micro ops) Simulated -system.cpu.cpi::0 8.351449 # CPI: Cycles Per Instruction -system.cpu.cpi::1 8.351449 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.175724 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.119740 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.119740 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.239479 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 23483 # number of integer regfile reads -system.cpu.int_regfile_writes 13138 # number of integer regfile writes +system.cpu.commit.op_class_1::total 6612 # Class of committed instruction +system.cpu.commit.op_class::total 13159 0.00% 0.00% # Class of committed instruction +system.cpu.commit.bw_lim_events 513 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 93105 # The number of ROB reads +system.cpu.rob.rob_writes 52882 # The number of ROB writes +system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 33518 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts::0 6530 # Number of Instructions Simulated +system.cpu.committedInsts::1 6595 # Number of Instructions Simulated +system.cpu.committedInsts::total 13125 # Number of Instructions Simulated +system.cpu.committedOps::0 6530 # Number of Ops (including micro ops) Simulated +system.cpu.committedOps::1 6595 # Number of Ops (including micro ops) Simulated +system.cpu.committedOps::total 13125 # Number of Ops (including micro ops) Simulated +system.cpu.cpi::0 7.829556 # CPI: Cycles Per Instruction +system.cpu.cpi::1 7.752388 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.895390 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.127721 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.128993 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.256714 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 25576 # number of integer regfile reads +system.cpu.int_regfile_writes 14448 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 25563000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements::0 0 # number of replacements system.cpu.dcache.tags.replacements::1 0 # number of replacements system.cpu.dcache.tags.replacements::total 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 216.020896 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4237 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 342 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.388889 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 108.945725 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4625 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 175 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 26.428571 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 216.020896 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.052739 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.052739 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.083496 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 10870 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 10870 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 3225 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3225 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1012 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1012 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4237 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4237 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4237 # number of overall hits -system.cpu.dcache.overall_hits::total 4237 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 309 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 309 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 718 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 718 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1027 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1027 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1027 # number of overall misses -system.cpu.dcache.overall_misses::total 1027 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24016000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24016000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 51330451 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 51330451 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 75346451 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 75346451 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 75346451 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 75346451 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3534 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3534 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5264 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5264 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5264 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5264 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087436 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.087436 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.195099 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.195099 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.195099 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.195099 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77721.682848 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 77721.682848 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71490.878830 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 71490.878830 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73365.580331 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73365.580331 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73365.580331 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73365.580331 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5997 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 108 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.527778 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 110 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 110 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 574 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 574 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 684 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 684 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 684 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 684 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 199 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 199 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 144 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 144 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 343 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 343 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 343 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 343 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17847000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17847000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12459487 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12459487 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30306487 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 30306487 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30306487 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 30306487 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.056310 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.056310 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065160 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.065160 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065160 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.065160 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89683.417085 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89683.417085 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86524.215278 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86524.215278 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88357.104956 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 88357.104956 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88357.104956 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 88357.104956 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements::0 7 # number of replacements +system.cpu.dcache.tags.occ_blocks::cpu.data 108.945725 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026598 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026598 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 175 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.042725 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 11523 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 11523 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 25563000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 3561 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3561 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1064 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1064 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 4625 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4625 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4625 # number of overall hits +system.cpu.dcache.overall_hits::total 4625 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 338 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 338 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 711 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 711 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1049 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1049 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1049 # number of overall misses +system.cpu.dcache.overall_misses::total 1049 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29216500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29216500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 54293993 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 54293993 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83510493 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83510493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83510493 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83510493 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3899 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3899 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1775 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1775 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 5674 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5674 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5674 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5674 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086689 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.086689 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.400563 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.400563 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.184878 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.184878 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.184878 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.184878 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 86439.349112 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 86439.349112 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76362.859353 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76362.859353 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 79609.621544 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 79609.621544 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 79609.621544 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 79609.621544 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1769 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 155 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 17 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 104.058824 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 155 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 236 # 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Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 628 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.676752 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements::total 1 # number of replacements +system.cpu.icache.tags.tagsinuse 159.243131 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3483 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 317 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.987382 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 318.054191 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.155300 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.155300 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 621 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 383 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.303223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 8292 # Number of tag accesses -system.cpu.icache.tags.data_accesses 8292 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 2937 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2937 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2937 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2937 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2937 # number of overall hits -system.cpu.icache.overall_hits::total 2937 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 895 # 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number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3832 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3832 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3832 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3832 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3832 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.233559 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.233559 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.233559 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.233559 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.233559 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.233559 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81346.363128 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 81346.363128 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 81346.363128 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 81346.363128 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 81346.363128 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 81346.363128 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3504 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 159.243131 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077755 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077755 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 316 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 192 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.154297 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 9105 # Number of tag accesses +system.cpu.icache.tags.data_accesses 9105 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 25563000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 3483 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3483 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3483 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3483 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3483 # number of overall hits +system.cpu.icache.overall_hits::total 3483 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 911 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 911 # 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number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 4394 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4394 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 4394 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4394 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.207328 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.207328 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.207328 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.207328 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.207328 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.207328 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80937.430296 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 80937.430296 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 80937.430296 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 80937.430296 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 80937.430296 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 80937.430296 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 136 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 58 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 60.413793 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 136 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 7 # number of writebacks -system.cpu.icache.writebacks::total 7 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 267 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 267 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 267 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 267 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 267 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 267 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 628 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 628 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 628 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 628 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 628 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 628 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54756996 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 54756996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54756996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 54756996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54756996 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 54756996 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163883 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.163883 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.163883 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 87192.668790 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 87192.668790 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 87192.668790 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 87192.668790 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 87192.668790 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 87192.668790 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states +system.cpu.icache.writebacks::writebacks 1 # number of writebacks +system.cpu.icache.writebacks::total 1 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 594 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 594 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 594 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 594 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 594 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 594 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 317 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 317 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 317 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 317 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 317 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27574500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27574500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27574500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27574500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27574500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27574500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.072144 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.072144 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.072144 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.072144 # 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mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.996910 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.996910 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74886.206897 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74886.206897 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76043.200000 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76043.200000 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78262.626263 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78262.626263 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76043.200000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76835.276968 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76323.863636 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76043.200000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76835.276968 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76323.863636 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 978 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74082.191781 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74082.191781 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75481.072555 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75481.072555 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89127.450980 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 89127.450980 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75481.072555 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82851.428571 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78102.642276 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75481.072555 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82851.428571 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78102.642276 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 493 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 825 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 145 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 145 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 628 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 198 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1263 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 685 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1948 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 62528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 25563000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 419 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 317 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 102 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 635 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 985 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20352 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 971 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002060 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.045361 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 492 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 969 99.79% 99.79% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2 0.21% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 971 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 496000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 942000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 513000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 968 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 492 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 247500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 475500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 262500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 492 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 822 # Transaction distribution -system.membus.trans_dist::ReadExReq 145 # Transaction distribution -system.membus.trans_dist::ReadExResp 145 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 823 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1935 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1935 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 61888 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 61888 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 25563000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 419 # Transaction distribution +system.membus.trans_dist::ReadExReq 73 # Transaction distribution +system.membus.trans_dist::ReadExResp 73 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 419 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 984 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 984 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 31488 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 968 # Request fanout histogram +system.membus.snoop_fanout::samples 492 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 968 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 968 # Request fanout histogram -system.membus.reqLayer0.occupancy 1179500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 4.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 5127250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.2 # Layer utilization (%) +system.membus.snoop_fanout::total 492 # Request fanout histogram +system.membus.reqLayer0.occupancy 588500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2626750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt index b23a2b88f..cdfe6dd6a 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000167 # Number of seconds simulated -sim_ticks 167328500 # Number of ticks simulated -final_tick 167328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 167318000 # Number of ticks simulated +final_tick 167318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54302 # Simulator instruction rate (inst/s) -host_op_rate 54316 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79708249 # Simulator tick rate (ticks/s) -host_mem_usage 244184 # Number of bytes of host memory used -host_seconds 2.10 # Real time elapsed on the host +host_inst_rate 259842 # Simulator instruction rate (inst/s) +host_op_rate 259907 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 381385356 # Simulator tick rate (ticks/s) +host_mem_usage 261864 # Number of bytes of host memory used +host_seconds 0.44 # Real time elapsed on the host sim_insts 113991 # Number of instructions simulated sim_ops 114022 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 52672 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 17088 # Number of bytes read from this memory system.physmem.bytes_read::total 69760 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 52672 # Nu system.physmem.num_reads::cpu.inst 823 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 267 # Number of read requests responded to by this memory system.physmem.num_reads::total 1090 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 314782001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 102122472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 416904472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314782001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314782001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314782001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 102122472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 416904472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314801755 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 102128880 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 416930635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314801755 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314801755 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314801755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 102128880 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 416930635 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1090 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 1090 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 166995000 # Total gap between requests +system.physmem.totGap 166987000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -201,15 +201,15 @@ system.physmem.bytesPerActivate::768-895 10 4.83% 90.82% # By system.physmem.bytesPerActivate::896-1023 1 0.48% 91.30% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 18 8.70% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 207 # Bytes accessed per row activation -system.physmem.totQLat 15434500 # Total ticks spent queuing -system.physmem.totMemAccLat 35872000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 15449500 # Total ticks spent queuing +system.physmem.totMemAccLat 35887000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 5450000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14160.09 # Average queueing delay per DRAM burst +system.physmem.avgQLat 14173.85 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32910.09 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 416.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32923.85 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 416.93 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 416.90 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 416.93 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.26 # Data bus utilization in percentage @@ -221,59 +221,59 @@ system.physmem.readRowHits 874 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 153206.42 # Average gap between requests +system.physmem.avgGap 153199.08 # Average gap between requests system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 763980 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 387090 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 3619980 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 9305250 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 493440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 55143510 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 7150560 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actBackEnergy 9302400 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 492960 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 55152630 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 7141920 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 2565480 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 92951370 # Total energy per rank (pJ) -system.physmem_0.averagePower 555.501490 # Core power per rank (mW) -system.physmem_0.totalIdleTime 145131750 # Total Idle time Per DRAM Rank +system.physmem_0.totalEnergy 92948520 # Total energy per rank (pJ) +system.physmem_0.averagePower 555.517657 # Core power per rank (mW) +system.physmem_0.totalIdleTime 145123750 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 654000 # Time in different power states system.physmem_0.memoryStateTime::REF 5732000 # Time in different power states system.physmem_0.memoryStateTime::SREF 6087000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 18616750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 18593750 # Time in different power states system.physmem_0.memoryStateTime::ACT 15316500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 120922250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 120934750 # Time in different power states system.physmem_1.actEnergy 778260 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 398475 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 4162620 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 9798300 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 485280 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 44769510 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 12438720 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 4465980 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 90204585 # Total energy per rank (pJ) -system.physmem_1.averagePower 539.085991 # Core power per rank (mW) -system.physmem_1.totalIdleTime 144266000 # Total Idle time Per DRAM Rank +system.physmem_1.actBackEnergy 9796590 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 484800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 44771220 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 12438240 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 4464180 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 90201825 # Total energy per rank (pJ) +system.physmem_1.averagePower 539.101715 # Core power per rank (mW) +system.physmem_1.totalIdleTime 144258000 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 729500 # Time in different power states system.physmem_1.memoryStateTime::REF 5472000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 14006250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 32390000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 13998250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 32388000 # Time in different power states system.physmem_1.memoryStateTime::ACT 16564250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 98166500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 31621 # Number of BP lookups -system.cpu.branchPred.condPredicted 20020 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2186 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 28229 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15507 # Number of BTB hits +system.physmem_1.memoryStateTime::ACT_PDN 98166000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 31578 # Number of BP lookups +system.cpu.branchPred.condPredicted 20002 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2179 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 27728 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15512 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 54.932870 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 55.943451 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 5663 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 3671 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1992 # Number of indirect misses. +system.cpu.branchPred.indirectLookups 5649 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 3670 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1979 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 1067 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -295,16 +295,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 43 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 167328500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 334657 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 167318000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 334636 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 113991 # Number of instructions committed system.cpu.committedOps 114022 # Number of ops (including micro ops) committed -system.cpu.discardedOps 5904 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 5891 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 2.935819 # CPI: cycles per instruction -system.cpu.ipc 0.340620 # IPC: instructions per cycle +system.cpu.cpi 2.935635 # CPI: cycles per instruction +system.cpu.ipc 0.340642 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 43 0.04% 0.04% # Class of committed instruction system.cpu.op_class_0::IntAlu 70180 61.55% 61.59% # Class of committed instruction system.cpu.op_class_0::IntMult 105 0.09% 61.68% # Class of committed instruction @@ -344,38 +344,38 @@ system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 114022 # Class of committed instruction -system.cpu.tickCycles 171660 # Number of cycles that the object actually ticked -system.cpu.idleCycles 162997 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 171594 # Number of cycles that the object actually ticked +system.cpu.idleCycles 163042 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 215.204481 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 44066 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 215.201598 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 44063 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 268 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 164.425373 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 164.414179 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 215.204481 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.052540 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.052540 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 215.201598 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052539 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052539 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 268 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 203 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.065430 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 89318 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 89318 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 24534 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 24534 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 89312 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 89312 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 24531 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 24531 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19526 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19526 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 4 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 4 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44060 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44060 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44060 # number of overall hits -system.cpu.dcache.overall_hits::total 44060 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 44057 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44057 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44057 # number of overall hits +system.cpu.dcache.overall_hits::total 44057 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 75 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 75 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 384 # number of WriteReq misses @@ -384,42 +384,42 @@ system.cpu.dcache.demand_misses::cpu.data 459 # n system.cpu.dcache.demand_misses::total 459 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 459 # number of overall misses system.cpu.dcache.overall_misses::total 459 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8632000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8632000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8632500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8632500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 30737000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 30737000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39369000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39369000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39369000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39369000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24609 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24609 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 39369500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39369500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39369500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39369500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24606 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24606 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19910 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19910 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 2 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 4 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 4 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 44519 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 44519 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 44519 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 44519 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 44516 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 44516 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 44516 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 44516 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003048 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003048 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019287 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.019287 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010310 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010310 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010310 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010310 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115093.333333 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 115093.333333 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.010311 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010311 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010311 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010311 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115100 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 115100 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80044.270833 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 80044.270833 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 85771.241830 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 85771.241830 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 85771.241830 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 85771.241830 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 85772.331155 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 85772.331155 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 85772.331155 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 85772.331155 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -442,14 +442,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 268 system.cpu.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 268 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7963000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7963000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7963500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7963500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15953500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 15953500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23916500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23916500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23916500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23916500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23917000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23917000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23917000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23917000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002804 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002804 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009995 # mshr miss rate for WriteReq accesses @@ -458,68 +458,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006020 system.cpu.dcache.demand_mshr_miss_rate::total 0.006020 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006020 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006020 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115405.797101 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115405.797101 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115413.043478 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115413.043478 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80168.341709 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80168.341709 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89240.671642 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 89240.671642 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89240.671642 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 89240.671642 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89242.537313 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 89242.537313 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89242.537313 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 89242.537313 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 18 # number of replacements -system.cpu.icache.tags.tagsinuse 401.761519 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 49677 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 401.741743 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 49660 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 823 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 60.360875 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 60.340219 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 401.761519 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.196173 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.196173 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 401.741743 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.196163 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.196163 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 805 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 240 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.393066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 101823 # Number of tag accesses -system.cpu.icache.tags.data_accesses 101823 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 49677 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 49677 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 49677 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 49677 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 49677 # number of overall hits -system.cpu.icache.overall_hits::total 49677 # number of overall hits +system.cpu.icache.tags.tag_accesses 101789 # Number of tag accesses +system.cpu.icache.tags.data_accesses 101789 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 49660 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 49660 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 49660 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 49660 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 49660 # number of overall hits +system.cpu.icache.overall_hits::total 49660 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 823 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 823 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 823 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 823 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 823 # number of overall misses system.cpu.icache.overall_misses::total 823 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 69966000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 69966000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 69966000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 69966000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 69966000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 69966000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 50500 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 50500 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 50500 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 50500 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 50500 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 50500 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016297 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016297 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016297 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016297 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016297 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016297 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85013.365735 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 85013.365735 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 85013.365735 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 85013.365735 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 85013.365735 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 85013.365735 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 69983000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 69983000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 69983000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 69983000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 69983000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 69983000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 50483 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 50483 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 50483 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 50483 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 50483 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 50483 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016303 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016303 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016303 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016303 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016303 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016303 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85034.021871 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 85034.021871 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 85034.021871 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 85034.021871 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 85034.021871 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 85034.021871 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -534,36 +534,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 823 system.cpu.icache.demand_mshr_misses::total 823 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 823 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69143000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 69143000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69143000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 69143000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69143000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 69143000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016297 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016297 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016297 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84013.365735 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84013.365735 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84013.365735 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 84013.365735 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84013.365735 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 84013.365735 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69160000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 69160000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69160000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 69160000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69160000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 69160000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016303 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016303 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016303 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84034.021871 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84034.021871 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84034.021871 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 84034.021871 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84034.021871 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 84034.021871 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 622.728504 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 622.705265 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 19 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1090 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.017431 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 407.968080 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 214.760424 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 407.947689 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 214.757576 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.012450 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006554 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.019004 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.019003 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 1090 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 585 # Occupied blocks per task id @@ -571,7 +571,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 454 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.033264 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 9962 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 9962 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 18 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 18 # number of WritebackClean hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits @@ -594,16 +594,16 @@ system.cpu.l2cache.overall_misses::cpu.data 267 # system.cpu.l2cache.overall_misses::total 1090 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15654000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 15654000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 67908500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 67908500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7847000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7847000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 67908500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 23501000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 91409500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 67908500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 23501000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 91409500 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 67925500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 67925500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7847500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7847500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 67925500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 23501500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 91427000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 67925500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 23501500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 91427000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 18 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 18 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 199 # number of ReadExReq accesses(hits+misses) @@ -632,16 +632,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.996269 system.cpu.l2cache.overall_miss_rate::total 0.999083 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78663.316583 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78663.316583 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82513.365735 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82513.365735 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115397.058824 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115397.058824 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82513.365735 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88018.726592 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83861.926606 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82513.365735 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88018.726592 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83861.926606 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82534.021871 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82534.021871 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115404.411765 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115404.411765 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82534.021871 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88020.599251 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83877.981651 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82534.021871 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88020.599251 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83877.981651 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -662,16 +662,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 267 system.cpu.l2cache.overall_mshr_misses::total 1090 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13664000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13664000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 59678500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 59678500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7167000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7167000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59678500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20831000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 80509500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59678500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20831000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 80509500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 59695500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 59695500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7167500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7167500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59695500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20831500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 80527000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59695500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20831500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 80527000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -686,23 +686,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996269 system.cpu.l2cache.overall_mshr_miss_rate::total 0.999083 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68663.316583 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68663.316583 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72513.365735 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72513.365735 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105397.058824 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105397.058824 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72513.365735 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78018.726592 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73861.926606 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72513.365735 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78018.726592 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73861.926606 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72534.021871 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72534.021871 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105404.411765 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105404.411765 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72534.021871 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78020.599251 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73877.981651 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72534.021871 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78020.599251 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73877.981651 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1109 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 19 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 892 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 18 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 199 # Transaction distribution @@ -740,7 +740,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 891 # Transaction distribution system.membus.trans_dist::ReadExReq 199 # Transaction distribution system.membus.trans_dist::ReadExResp 199 # Transaction distribution @@ -761,7 +761,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 1090 # Request fanout histogram -system.membus.reqLayer0.occupancy 1226500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1229000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) system.membus.respLayer1.occupancy 5789000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.5 # Layer utilization (%) diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt index 8b3036b08..0712c8493 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000796 # Nu sim_ticks 796036 # Number of ticks simulated final_tick 796036 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 51863 # Simulator instruction rate (inst/s) -host_op_rate 51862 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 623875 # Simulator tick rate (ticks/s) -host_mem_usage 411084 # Number of bytes of host memory used -host_seconds 1.28 # Real time elapsed on the host +host_inst_rate 163786 # Simulator instruction rate (inst/s) +host_op_rate 163781 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1970174 # Simulator tick rate (ticks/s) +host_mem_usage 428500 # Number of bytes of host memory used +host_seconds 0.40 # Real time elapsed on the host sim_insts 66173 # Number of instructions simulated sim_ops 66173 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -401,13 +401,35 @@ system.ruby.miss_latency_hist_seqr::stdev 31.144722 system.ruby.miss_latency_hist_seqr | 10486 74.63% 74.63% | 3313 23.58% 98.21% | 168 1.20% 99.41% | 27 0.19% 99.60% | 26 0.19% 99.79% | 19 0.14% 99.92% | 1 0.01% 99.93% | 1 0.01% 99.94% | 0 0.00% 99.94% | 9 0.06% 100.00% system.ruby.miss_latency_hist_seqr::total 14050 system.ruby.Directory.incomplete_times_seqr 14049 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.017645 # Average number of messages in buffer +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.999377 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.035295 # Average number of messages in buffer +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.715164 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.017650 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999913 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.035295 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999915 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 76386 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 14050 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 90436 # Number of cache demand accesses +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.017645 # Average number of messages in buffer +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.995586 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.113609 # Average number of messages in buffer +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999999 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.070590 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999992 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.017650 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.999340 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.017645 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.996224 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.017650 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.999442 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.105874 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.715264 # Average number of cycles messages are stalled in this MB system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 8.823722 system.ruby.network.routers0.msg_count.Control::2 14050 @@ -418,6 +440,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 112400 system.ruby.network.routers0.msg_bytes.Data::2 1011312 system.ruby.network.routers0.msg_bytes.Response_Data::4 1011600 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 112368 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.035295 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.715189 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.017645 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.998751 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.017650 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.999824 # Average number of cycles messages are stalled in this MB system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 8.823722 system.ruby.network.routers1.msg_count.Control::2 14050 @@ -428,6 +456,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 112400 system.ruby.network.routers1.msg_bytes.Data::2 1011312 system.ruby.network.routers1.msg_bytes.Response_Data::4 1011600 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 112368 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.035295 # Average number of messages in buffer +system.ruby.network.int_link_buffers02.avg_stall_time 7.715249 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.017645 # Average number of messages in buffer +system.ruby.network.int_link_buffers08.avg_stall_time 2.998123 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.017650 # Average number of messages in buffer +system.ruby.network.int_link_buffers09.avg_stall_time 2.999732 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.017645 # Average number of messages in buffer +system.ruby.network.int_link_buffers13.avg_stall_time 4.996859 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.017650 # Average number of messages in buffer +system.ruby.network.int_link_buffers14.avg_stall_time 4.999541 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.035295 # Average number of messages in buffer +system.ruby.network.int_link_buffers17.avg_stall_time 9.715212 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.017645 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.997493 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.017650 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.999638 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.035295 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.715232 # Average number of cycles messages are stalled in this MB system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 8.823722 system.ruby.network.routers2.msg_count.Control::2 14050 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt index c2cf1b21c..042307b53 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000339 # Number of seconds simulated -sim_ticks 339160000 # Number of ticks simulated -final_tick 339160000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 339173000 # Number of ticks simulated +final_tick 339173000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25032 # Simulator instruction rate (inst/s) -host_op_rate 25032 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28360795 # Simulator tick rate (ticks/s) -host_mem_usage 244952 # Number of bytes of host memory used -host_seconds 11.96 # Real time elapsed on the host +host_inst_rate 215547 # Simulator instruction rate (inst/s) +host_op_rate 215545 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 244214530 # Simulator tick rate (ticks/s) +host_mem_usage 263004 # Number of bytes of host memory used +host_seconds 1.39 # Real time elapsed on the host sim_insts 299354 # Number of instructions simulated sim_ops 299354 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 74688 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 20352 # Number of bytes read from this memory system.physmem.bytes_read::total 95040 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 74688 # Nu system.physmem.num_reads::cpu.inst 1167 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 318 # Number of read requests responded to by this memory system.physmem.num_reads::total 1485 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 220214648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 60007076 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 280221724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 220214648 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 220214648 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 220214648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 60007076 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 280221724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 220206207 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 60004776 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 280210984 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 220206207 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 220206207 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 220206207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 60004776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 280210984 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1485 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 1485 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 338943500 # Total gap between requests +system.physmem.totGap 338956500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -189,27 +189,27 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 285 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 327.859649 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 221.469651 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 221.082687 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 283.652997 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 67 23.51% 23.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 73 25.61% 49.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 39 13.68% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 33 11.58% 74.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 28 9.82% 84.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 15 5.26% 89.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 68 23.86% 23.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 71 24.91% 48.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 38 13.33% 62.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 36 12.63% 74.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 28 9.82% 84.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 14 4.91% 89.47% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 7 2.46% 91.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 2 0.70% 92.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 21 7.37% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 285 # Bytes accessed per row activation -system.physmem.totQLat 19805250 # Total ticks spent queuing -system.physmem.totMemAccLat 47649000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 20061750 # Total ticks spent queuing +system.physmem.totMemAccLat 47905500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 7425000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13336.87 # Average queueing delay per DRAM burst +system.physmem.avgQLat 13509.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32086.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 280.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32259.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 280.21 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 280.22 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 280.21 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.19 # Data bus utilization in percentage @@ -221,58 +221,58 @@ system.physmem.readRowHits 1195 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 228244.78 # Average gap between requests +system.physmem.avgGap 228253.54 # Average gap between requests system.physmem.pageHitRate 80.47 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 1106700 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 576840 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 6368880 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16006740 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 700320 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 122840700 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 12504960 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actBackEnergy 16018710 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 699840 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 123298980 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 12114720 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 619740.000000 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 187769040 # Total energy per rank (pJ) -system.physmem_0.averagePower 553.629673 # Core power per rank (mW) -system.physmem_0.totalIdleTime 301401000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 546000 # Time in different power states +system.physmem_0.totalEnergy 187848570 # Total energy per rank (pJ) +system.physmem_0.averagePower 553.841711 # Core power per rank (mW) +system.physmem_0.totalIdleTime 301380500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 552000 # Time in different power states system.physmem_0.memoryStateTime::REF 11446000 # Time in different power states system.physmem_0.memoryStateTime::SREF 280750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 32576500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 24926250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 269384500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 31555500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 24953750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 270385000 # Time in different power states system.physmem_1.actEnergy 963900 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 504735 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 4234020 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 12901950 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 3644640 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 106370550 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 25587360 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 12906510 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3648480 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 105703080 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 26147040 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 905640.000000 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 182156955 # Total energy per rank (pJ) -system.physmem_1.averagePower 537.082660 # Core power per rank (mW) -system.physmem_1.totalIdleTime 301148500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 8278250 # Time in different power states +system.physmem_1.totalEnergy 182057565 # Total energy per rank (pJ) +system.physmem_1.averagePower 536.767851 # Core power per rank (mW) +system.physmem_1.totalIdleTime 301140750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 8284250 # Time in different power states system.physmem_1.memoryStateTime::REF 11446000 # Time in different power states system.physmem_1.memoryStateTime::SREF 1471750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 66617000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 18107500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 233239500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 80709 # Number of BP lookups -system.cpu.branchPred.condPredicted 51944 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5835 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 64346 # Number of BTB lookups -system.cpu.branchPred.BTBHits 38294 # Number of BTB hits +system.physmem_1.memoryStateTime::PRE_PDN 68075000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 18122250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 231773750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 80662 # Number of BP lookups +system.cpu.branchPred.condPredicted 51937 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5790 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 60622 # Number of BTB lookups +system.cpu.branchPred.BTBHits 38260 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 59.512635 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 63.112401 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 13164 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 7506 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 13147 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 7489 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 5658 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 3210 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -295,16 +295,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 162 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 339160000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 678320 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 339173000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 678346 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 299354 # Number of instructions committed system.cpu.committedOps 299354 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13959 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13899 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 2.265946 # CPI: cycles per instruction -system.cpu.ipc 0.441317 # IPC: instructions per cycle +system.cpu.cpi 2.266033 # CPI: cycles per instruction +system.cpu.ipc 0.441300 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 162 0.05% 0.05% # Class of committed instruction system.cpu.op_class_0::IntAlu 179913 60.10% 60.15% # Class of committed instruction system.cpu.op_class_0::IntMult 466 0.16% 60.31% # Class of committed instruction @@ -344,34 +344,34 @@ system.cpu.op_class_0::FloatMemWrite 147 0.05% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 299354 # Class of committed instruction -system.cpu.tickCycles 449536 # Number of cycles that the object actually ticked -system.cpu.idleCycles 228784 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 449143 # Number of cycles that the object actually ticked +system.cpu.idleCycles 229203 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 254.196505 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 119907 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 254.242270 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 119892 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 320 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 374.709375 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 374.662500 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 254.196505 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.062060 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.062060 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 254.242270 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.062071 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.062071 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 320 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.078125 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 241156 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 241156 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 71754 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 71754 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 241126 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 241126 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 71739 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 71739 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 48153 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 48153 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 119907 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 119907 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 119907 # number of overall hits -system.cpu.dcache.overall_hits::total 119907 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 119892 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 119892 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 119892 # number of overall hits +system.cpu.dcache.overall_hits::total 119892 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 118 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 393 # number of WriteReq misses @@ -380,22 +380,22 @@ system.cpu.dcache.demand_misses::cpu.data 511 # n system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses system.cpu.dcache.overall_misses::total 511 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10963000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10963000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10980000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10980000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 31520500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 31520500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 42483500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 42483500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 42483500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 42483500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 71872 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 71872 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 42500500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 42500500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 42500500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 42500500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 71857 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 71857 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 48546 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 48546 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 120418 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 120418 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 120418 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 120418 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 120403 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 120403 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 120403 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 120403 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001642 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.001642 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008095 # miss rate for WriteReq accesses @@ -404,14 +404,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004244 system.cpu.dcache.demand_miss_rate::total 0.004244 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004244 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004244 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 92906.779661 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 92906.779661 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 93050.847458 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 93050.847458 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80204.834606 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 80204.834606 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 83137.964775 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 83137.964775 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 83137.964775 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 83137.964775 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 83171.232877 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 83171.232877 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 83171.232877 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 83171.232877 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -432,84 +432,84 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 320 system.cpu.dcache.demand_mshr_misses::total 320 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 320 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 320 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10845000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10845000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10862000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10862000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16122000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 16122000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26967000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26967000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26967000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26967000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26984000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26984000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26984000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26984000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001642 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001642 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004161 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004161 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002657 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002657 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002657 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002657 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91906.779661 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91906.779661 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002658 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002658 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002658 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002658 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92050.847458 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92050.847458 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79811.881188 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79811.881188 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84271.875000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84271.875000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84271.875000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84271.875000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84325 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84325 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84325 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84325 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 80 # number of replacements -system.cpu.icache.tags.tagsinuse 640.869470 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 135081 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 641.197715 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 134928 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 1178 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 114.669779 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 114.539898 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 640.869470 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.312925 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.312925 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 641.197715 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.313085 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.313085 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1098 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 846 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.536133 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 273696 # Number of tag accesses -system.cpu.icache.tags.data_accesses 273696 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 135081 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 135081 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 135081 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 135081 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 135081 # number of overall hits -system.cpu.icache.overall_hits::total 135081 # number of overall hits +system.cpu.icache.tags.tag_accesses 273390 # Number of tag accesses +system.cpu.icache.tags.data_accesses 273390 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 134928 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 134928 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 134928 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 134928 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 134928 # number of overall hits +system.cpu.icache.overall_hits::total 134928 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1178 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1178 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1178 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1178 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1178 # number of overall misses system.cpu.icache.overall_misses::total 1178 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 99945500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 99945500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 99945500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 99945500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 99945500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 99945500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 136259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 136259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 136259 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 136259 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 136259 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 136259 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008645 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008645 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008645 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008645 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008645 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008645 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 84843.378608 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 84843.378608 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 84843.378608 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 84843.378608 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 84843.378608 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 84843.378608 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 100185000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 100185000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 100185000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 100185000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 100185000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 100185000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 136106 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 136106 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 136106 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 136106 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 136106 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 136106 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008655 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008655 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008655 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008655 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008655 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008655 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85046.689304 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 85046.689304 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 85046.689304 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 85046.689304 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 85046.689304 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 85046.689304 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -524,36 +524,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1178 system.cpu.icache.demand_mshr_misses::total 1178 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1178 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1178 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 98767500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 98767500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 98767500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 98767500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 98767500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 98767500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008645 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008645 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008645 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83843.378608 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83843.378608 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83843.378608 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83843.378608 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83843.378608 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83843.378608 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 99007000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 99007000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 99007000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 99007000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 99007000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 99007000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008655 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008655 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008655 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84046.689304 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84046.689304 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84046.689304 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 84046.689304 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84046.689304 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 84046.689304 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 923.863116 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 924.252410 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 93 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1485 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.062626 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 671.109849 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 252.753267 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020481 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007713 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.028194 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 671.453398 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 252.799011 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020491 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007715 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.028206 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 1485 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id @@ -561,7 +561,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1201 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.045319 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 14109 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 14109 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 80 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 80 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 11 # number of ReadCleanReq hits @@ -588,16 +588,16 @@ system.cpu.l2cache.overall_misses::cpu.data 318 # system.cpu.l2cache.overall_misses::total 1485 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15818500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 15818500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 96885000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 96885000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10642000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 10642000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 96885000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 26460500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 123345500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 96885000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 26460500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 123345500 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 97124500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 97124500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10659000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 10659000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 97124500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 26477500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 123602000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 97124500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 26477500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 123602000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 80 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 80 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 202 # number of ReadExReq accesses(hits+misses) @@ -626,16 +626,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.993750 system.cpu.l2cache.overall_miss_rate::total 0.991322 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78309.405941 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78309.405941 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83020.565553 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83020.565553 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91741.379310 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91741.379310 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83020.565553 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83209.119497 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83060.942761 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83020.565553 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83209.119497 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83060.942761 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83225.792631 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83225.792631 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91887.931034 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91887.931034 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83225.792631 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83262.578616 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83233.670034 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83225.792631 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83262.578616 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83233.670034 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -656,16 +656,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 318 system.cpu.l2cache.overall_mshr_misses::total 1485 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13798500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13798500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85215000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85215000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9482000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9482000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85215000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23280500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 108495500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85215000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23280500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 108495500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85454500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85454500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9499000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9499000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85454500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23297500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 108752000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85454500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23297500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 108752000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for ReadCleanReq accesses @@ -680,23 +680,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993750 system.cpu.l2cache.overall_mshr_miss_rate::total 0.991322 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68309.405941 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68309.405941 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73020.565553 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73020.565553 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81741.379310 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81741.379310 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73020.565553 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73209.119497 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73060.942761 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73020.565553 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73209.119497 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73060.942761 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73225.792631 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73225.792631 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81887.931034 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81887.931034 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73225.792631 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73262.578616 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73233.670034 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73225.792631 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73262.578616 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73233.670034 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1578 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 82 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1296 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 80 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 202 # Transaction distribution @@ -734,7 +734,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1283 # Transaction distribution system.membus.trans_dist::ReadExReq 202 # Transaction distribution system.membus.trans_dist::ReadExResp 202 # Transaction distribution @@ -755,9 +755,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 1485 # Request fanout histogram -system.membus.reqLayer0.occupancy 1720000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1721500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 7877750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 7876000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt index fef27ae57..c7042114d 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.006394 # Nu sim_ticks 6393532 # Number of ticks simulated final_tick 6393532 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 13428 # Simulator instruction rate (inst/s) -host_op_rate 13428 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 286950 # Simulator tick rate (ticks/s) -host_mem_usage 412476 # Number of bytes of host memory used -host_seconds 22.28 # Real time elapsed on the host +host_inst_rate 80438 # Simulator instruction rate (inst/s) +host_op_rate 80438 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1718903 # Simulator tick rate (ticks/s) +host_mem_usage 429644 # Number of bytes of host memory used +host_seconds 3.72 # Real time elapsed on the host sim_insts 299191 # Number of instructions simulated sim_ops 299191 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -403,13 +403,35 @@ system.ruby.miss_latency_hist_seqr::stdev 36.989317 system.ruby.miss_latency_hist_seqr | 47894 48.99% 48.99% | 46330 47.39% 96.38% | 2431 2.49% 98.87% | 380 0.39% 99.26% | 382 0.39% 99.65% | 309 0.32% 99.97% | 15 0.02% 99.98% | 3 0.00% 99.98% | 0 0.00% 99.98% | 16 0.02% 100.00% system.ruby.miss_latency_hist_seqr::total 97760 system.ruby.Directory.incomplete_times_seqr 97759 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.999944 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.030580 # Average number of messages in buffer +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.755056 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999989 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.030580 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999989 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 319983 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 97760 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 417743 # Number of cache demand accesses +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.999599 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.065339 # Average number of messages in buffer +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 1.000000 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.061161 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999999 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.999918 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.999657 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.999931 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.091740 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.755068 # Average number of cycles messages are stalled in this MB system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 7.645070 system.ruby.network.routers0.msg_count.Control::2 97760 @@ -420,6 +442,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 782080 system.ruby.network.routers0.msg_bytes.Data::2 7038432 system.ruby.network.routers0.msg_bytes.Response_Data::4 7038720 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.030580 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.755059 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.999887 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.999978 # Average number of cycles messages are stalled in this MB system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 7.645070 system.ruby.network.routers1.msg_count.Control::2 97760 @@ -430,6 +458,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 782080 system.ruby.network.routers1.msg_bytes.Data::2 7038432 system.ruby.network.routers1.msg_bytes.Response_Data::4 7038720 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.030580 # Average number of messages in buffer +system.ruby.network.int_link_buffers02.avg_stall_time 7.755066 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.network.int_link_buffers08.avg_stall_time 2.999830 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.network.int_link_buffers09.avg_stall_time 2.999967 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.network.int_link_buffers13.avg_stall_time 4.999715 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.network.int_link_buffers14.avg_stall_time 4.999943 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.030580 # Average number of messages in buffer +system.ruby.network.int_link_buffers17.avg_stall_time 9.755062 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.999773 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.015290 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.999955 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.030580 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.755064 # Average number of cycles messages are stalled in this MB system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 7.645070 system.ruby.network.routers2.msg_count.Control::2 97760 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt index a1e10e23b..f8dd393b0 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000270 # Number of seconds simulated -sim_ticks 270200000 # Number of ticks simulated -final_tick 270200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 269998000 # Number of ticks simulated +final_tick 269998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24805 # Simulator instruction rate (inst/s) -host_op_rate 24804 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29619482 # Simulator tick rate (ticks/s) -host_mem_usage 244928 # Number of bytes of host memory used -host_seconds 9.12 # Real time elapsed on the host +host_inst_rate 216821 # Simulator instruction rate (inst/s) +host_op_rate 216819 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 258712153 # Simulator tick rate (ticks/s) +host_mem_usage 263004 # Number of bytes of host memory used +host_seconds 1.04 # Real time elapsed on the host sim_insts 226275 # Number of instructions simulated sim_ops 226275 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 67072 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 19264 # Number of bytes read from this memory system.physmem.bytes_read::total 86336 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 67072 # Nu system.physmem.num_reads::cpu.inst 1048 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 301 # Number of read requests responded to by this memory system.physmem.num_reads::total 1349 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 248230940 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 71295337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 319526277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 248230940 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 248230940 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 248230940 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 71295337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 319526277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 248416655 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 71348677 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 319765332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 248416655 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 248416655 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 248416655 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 71348677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 319765332 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1349 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 1349 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 269959000 # Total gap between requests +system.physmem.totGap 269757000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -189,27 +189,27 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 239 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 351.330544 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 238.583723 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 292.748127 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 53 22.18% 22.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 57 23.85% 46.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 30 12.55% 58.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 237.806193 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 293.628623 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54 22.59% 22.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 57 23.85% 46.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 29 12.13% 58.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 35 14.64% 73.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 21 8.79% 82.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 16 6.69% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 20 8.37% 81.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 17 7.11% 88.70% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 4 1.67% 90.38% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 3 1.26% 91.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 20 8.37% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 239 # Bytes accessed per row activation -system.physmem.totQLat 15283750 # Total ticks spent queuing -system.physmem.totMemAccLat 40577500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 15217250 # Total ticks spent queuing +system.physmem.totMemAccLat 40511000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 6745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11329.69 # Average queueing delay per DRAM burst +system.physmem.avgQLat 11280.39 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30079.69 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 319.53 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30030.39 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 319.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 319.53 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 319.77 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.50 # Data bus utilization in percentage @@ -221,59 +221,59 @@ system.physmem.readRowHits 1101 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.62 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 200117.87 # Average gap between requests +system.physmem.avgGap 199968.12 # Average gap between requests system.physmem.pageHitRate 81.62 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 899640 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 462990 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 5454960 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 20897760.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 13396710 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 455520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 92913420 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 13776960 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actBackEnergy 13384170 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 450240 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 94080210 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 12732960 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 148257960 # Total energy per rank (pJ) -system.physmem_0.averagePower 548.697113 # Core power per rank (mW) -system.physmem_0.totalIdleTime 238953500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 216000 # Time in different power states +system.physmem_0.totalEnergy 148362930 # Total energy per rank (pJ) +system.physmem_0.averagePower 549.494877 # Core power per rank (mW) +system.physmem_0.totalIdleTime 238782750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 210000 # Time in different power states system.physmem_0.memoryStateTime::REF 8840000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 35871500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 21502750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 203769750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 33151500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21477500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 206319000 # Time in different power states system.physmem_1.actEnergy 871080 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 444015 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 4176900 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 21512400.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11664480 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 3533280 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 82867740 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 20352000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 11660490 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3532800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 84455190 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 18941760 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 718140.000000 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 146140035 # Total energy per rank (pJ) -system.physmem_1.averagePower 540.858753 # Core power per rank (mW) -system.physmem_1.totalIdleTime 235236750 # Total Idle time Per DRAM Rank +system.physmem_1.totalEnergy 146312775 # Total energy per rank (pJ) +system.physmem_1.averagePower 541.901675 # Core power per rank (mW) +system.physmem_1.totalIdleTime 235034750 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 8236250 # Time in different power states system.physmem_1.memoryStateTime::REF 9106000 # Time in different power states system.physmem_1.memoryStateTime::SREF 690750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 53009000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 49337750 # Time in different power states system.physmem_1.memoryStateTime::ACT 17416750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 181741250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 61485 # Number of BP lookups -system.cpu.branchPred.condPredicted 39320 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4384 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 51667 # Number of BTB lookups -system.cpu.branchPred.BTBHits 29457 # Number of BTB hits +system.physmem_1.memoryStateTime::ACT_PDN 185210500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 61459 # Number of BP lookups +system.cpu.branchPred.condPredicted 39303 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4350 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 48024 # Number of BTB lookups +system.cpu.branchPred.BTBHits 29463 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 57.013181 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 61.350575 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 10264 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 6105 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 4159 # Number of indirect misses. +system.cpu.branchPred.indirectLookups 10253 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 6091 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 4162 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 2365 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -295,16 +295,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 115 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 270200000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 540400 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 269998000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 539996 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 226275 # Number of instructions committed system.cpu.committedOps 226275 # Number of ops (including micro ops) committed -system.cpu.discardedOps 10623 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 10605 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 2.388244 # CPI: cycles per instruction -system.cpu.ipc 0.418718 # IPC: instructions per cycle +system.cpu.cpi 2.386459 # CPI: cycles per instruction +system.cpu.ipc 0.419031 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 117 0.05% 0.05% # Class of committed instruction system.cpu.op_class_0::IntAlu 136540 60.34% 60.39% # Class of committed instruction system.cpu.op_class_0::IntMult 325 0.14% 60.54% # Class of committed instruction @@ -344,34 +344,34 @@ system.cpu.op_class_0::FloatMemWrite 136 0.06% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 226275 # Class of committed instruction -system.cpu.tickCycles 340080 # Number of cycles that the object actually ticked -system.cpu.idleCycles 200320 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 339832 # Number of cycles that the object actually ticked +system.cpu.idleCycles 200164 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 242.026814 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 90015 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 242.012615 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 90016 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 302 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 298.062914 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 298.066225 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 242.026814 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.059089 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.059089 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 242.012615 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.059085 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.059085 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.073730 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 181330 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 181330 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 53182 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 53182 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 181332 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 181332 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 53183 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 53183 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 36833 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 36833 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 90015 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 90015 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 90015 # number of overall hits -system.cpu.dcache.overall_hits::total 90015 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 90016 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 90016 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 90016 # number of overall hits +system.cpu.dcache.overall_hits::total 90016 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 103 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 103 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 396 # number of WriteReq misses @@ -380,22 +380,22 @@ system.cpu.dcache.demand_misses::cpu.data 499 # n system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses system.cpu.dcache.overall_misses::total 499 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9494000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9494000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9627000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9627000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 31678500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 31678500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41172500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41172500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41172500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41172500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 53285 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 53285 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 41305500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41305500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41305500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41305500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 53286 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 53286 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 37229 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 37229 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 90514 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 90514 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 90514 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 90514 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 90515 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 90515 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 90515 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 90515 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001933 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.001933 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010637 # miss rate for WriteReq accesses @@ -404,14 +404,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005513 system.cpu.dcache.demand_miss_rate::total 0.005513 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005513 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005513 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 92174.757282 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 92174.757282 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 93466.019417 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 93466.019417 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79996.212121 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 79996.212121 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 82510.020040 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 82510.020040 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 82510.020040 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 82510.020040 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 82776.553106 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 82776.553106 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 82776.553106 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 82776.553106 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -434,84 +434,84 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 302 system.cpu.dcache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 302 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8881000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8881000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9014000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9014000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16356000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 16356000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25237000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25237000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25237000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 25237000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25370000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25370000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25370000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25370000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005506 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005506 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003337 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003337 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003337 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003337 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91556.701031 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91556.701031 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003336 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003336 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003336 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003336 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92927.835052 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92927.835052 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79785.365854 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79785.365854 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83566.225166 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 83566.225166 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83566.225166 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 83566.225166 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84006.622517 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84006.622517 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84006.622517 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84006.622517 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 69 # number of replacements -system.cpu.icache.tags.tagsinuse 555.532163 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 101722 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 555.459146 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 101640 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 1051 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 96.785918 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 96.707897 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 555.532163 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.271256 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.271256 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 555.459146 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.271220 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.271220 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 982 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 189 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 724 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.479492 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 206597 # Number of tag accesses -system.cpu.icache.tags.data_accesses 206597 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 101722 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 101722 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 101722 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 101722 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 101722 # number of overall hits -system.cpu.icache.overall_hits::total 101722 # number of overall hits +system.cpu.icache.tags.tag_accesses 206433 # Number of tag accesses +system.cpu.icache.tags.data_accesses 206433 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 101640 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 101640 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 101640 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 101640 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 101640 # number of overall hits +system.cpu.icache.overall_hits::total 101640 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1051 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1051 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1051 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1051 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1051 # number of overall misses system.cpu.icache.overall_misses::total 1051 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 87209500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 87209500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 87209500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 87209500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 87209500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 87209500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 102773 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 102773 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 102773 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 102773 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 102773 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 102773 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.010226 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.010226 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.010226 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.010226 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.010226 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.010226 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 82977.640343 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 82977.640343 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 82977.640343 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 82977.640343 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 82977.640343 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 82977.640343 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 87010500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 87010500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 87010500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 87010500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 87010500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 87010500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 102691 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 102691 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 102691 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 102691 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 102691 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 102691 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.010235 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.010235 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.010235 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.010235 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.010235 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.010235 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 82788.296860 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 82788.296860 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 82788.296860 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 82788.296860 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 82788.296860 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 82788.296860 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -526,36 +526,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1051 system.cpu.icache.demand_mshr_misses::total 1051 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1051 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1051 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 86158500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 86158500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 86158500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 86158500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 86158500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 86158500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.010226 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.010226 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.010226 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81977.640343 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81977.640343 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81977.640343 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 81977.640343 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81977.640343 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 81977.640343 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 85959500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 85959500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 85959500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 85959500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 85959500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 85959500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.010235 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.010235 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.010235 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81788.296860 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81788.296860 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81788.296860 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 81788.296860 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81788.296860 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 81788.296860 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 827.037841 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 826.940635 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 73 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1349 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.054114 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 585.656330 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 241.381510 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017873 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 585.573058 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 241.367577 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017870 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.007366 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.025239 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.025236 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 1349 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id @@ -563,7 +563,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1060 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.041168 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 12725 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 12725 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 69 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 69 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits @@ -590,16 +590,16 @@ system.cpu.l2cache.overall_misses::cpu.data 301 # system.cpu.l2cache.overall_misses::total 1349 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16048500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 16048500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 84550500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 84550500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8723000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 8723000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 84550500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 24771500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 109322000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 84550500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 24771500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 109322000 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 84351500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 84351500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8856000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 8856000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 84351500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 24904500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 109256000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 84351500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 24904500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 109256000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 69 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 69 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 205 # number of ReadExReq accesses(hits+misses) @@ -628,16 +628,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.996689 system.cpu.l2cache.overall_miss_rate::total 0.997044 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78285.365854 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78285.365854 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80677.958015 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80677.958015 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 90864.583333 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 90864.583333 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80677.958015 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82297.342193 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81039.288362 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80677.958015 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82297.342193 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81039.288362 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80488.072519 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80488.072519 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92250 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92250 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80488.072519 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82739.202658 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80990.363232 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80488.072519 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82739.202658 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80990.363232 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -658,16 +658,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 301 system.cpu.l2cache.overall_mshr_misses::total 1349 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13998500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13998500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74070500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74070500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7763000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7763000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74070500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21761500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 95832000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74070500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21761500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 95832000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 73871500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 73871500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7896000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7896000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 73871500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21894500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 95766000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 73871500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21894500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 95766000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for ReadCleanReq accesses @@ -682,23 +682,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996689 system.cpu.l2cache.overall_mshr_miss_rate::total 0.997044 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68285.365854 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68285.365854 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70677.958015 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70677.958015 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80864.583333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80864.583333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70677.958015 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72297.342193 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71039.288362 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70677.958015 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72297.342193 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71039.288362 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70488.072519 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70488.072519 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82250 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70488.072519 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72739.202658 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70990.363232 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70488.072519 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72739.202658 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70990.363232 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1422 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 70 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1148 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 69 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 205 # Transaction distribution @@ -736,7 +736,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1144 # Transaction distribution system.membus.trans_dist::ReadExReq 205 # Transaction distribution system.membus.trans_dist::ReadExResp 205 # Transaction distribution @@ -757,9 +757,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 1349 # Request fanout histogram -system.membus.reqLayer0.occupancy 1554000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1553000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 7151000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 7152500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt index 7007d9f9a..5fcbb579c 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000113 # Number of seconds simulated -sim_ticks 113397000 # Number of ticks simulated -final_tick 113397000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 113383000 # Number of ticks simulated +final_tick 113383000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 22733 # Simulator instruction rate (inst/s) -host_op_rate 22733 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11398414 # Simulator tick rate (ticks/s) -host_mem_usage 246096 # Number of bytes of host memory used -host_seconds 9.95 # Real time elapsed on the host +host_inst_rate 167766 # Simulator instruction rate (inst/s) +host_op_rate 167765 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 84106882 # Simulator tick rate (ticks/s) +host_mem_usage 263760 # Number of bytes of host memory used +host_seconds 1.35 # Real time elapsed on the host sim_insts 226159 # Number of instructions simulated sim_ops 226159 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 65856 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 65920 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 19264 # Number of bytes read from this memory -system.physmem.bytes_read::total 85120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65856 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1029 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 85184 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65920 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1030 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 301 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1330 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 580756105 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 169881037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 750637142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 580756105 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 580756105 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 580756105 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 169881037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 750637142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1330 # Number of read requests accepted +system.physmem.num_reads::total 1331 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 581392272 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 169902014 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 751294286 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 581392272 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 581392272 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 581392272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 169902014 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 751294286 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1331 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 1330 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 1331 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 85120 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 85184 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 85120 # Total read bytes from the system interface side +system.physmem.bytesReadSys 85184 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -46,16 +46,16 @@ system.physmem.perBankRdBursts::0 174 # Pe system.physmem.perBankRdBursts::1 18 # Per bank write bursts system.physmem.perBankRdBursts::2 15 # Per bank write bursts system.physmem.perBankRdBursts::3 82 # Per bank write bursts -system.physmem.perBankRdBursts::4 195 # Per bank write bursts +system.physmem.perBankRdBursts::4 194 # Per bank write bursts system.physmem.perBankRdBursts::5 254 # Per bank write bursts system.physmem.perBankRdBursts::6 22 # Per bank write bursts system.physmem.perBankRdBursts::7 4 # Per bank write bursts system.physmem.perBankRdBursts::8 25 # Per bank write bursts system.physmem.perBankRdBursts::9 103 # Per bank write bursts -system.physmem.perBankRdBursts::10 149 # Per bank write bursts +system.physmem.perBankRdBursts::10 150 # Per bank write bursts system.physmem.perBankRdBursts::11 145 # Per bank write bursts system.physmem.perBankRdBursts::12 50 # Per bank write bursts -system.physmem.perBankRdBursts::13 51 # Per bank write bursts +system.physmem.perBankRdBursts::13 52 # Per bank write bursts system.physmem.perBankRdBursts::14 14 # Per bank write bursts system.physmem.perBankRdBursts::15 29 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 113291000 # Total gap between requests +system.physmem.totGap 113277000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1330 # Read request sizes (log2) +system.physmem.readPktSize::6 1331 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 807 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 43 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,94 +187,94 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 210 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 393.752381 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 254.589157 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.600882 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 48 22.86% 22.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 44 20.95% 43.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 35 16.67% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 18 8.57% 69.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13 6.19% 75.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10 4.76% 80.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5 2.38% 82.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5 2.38% 84.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 32 15.24% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 210 # Bytes accessed per row activation -system.physmem.totQLat 16749000 # Total ticks spent queuing -system.physmem.totMemAccLat 41686500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6650000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12593.23 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 212 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 390.641509 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 252.461189 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 341.274727 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 49 23.11% 23.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43 20.28% 43.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 38 17.92% 61.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 18 8.49% 69.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13 6.13% 75.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8 3.77% 79.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 2.83% 82.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5 2.36% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 32 15.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 212 # Bytes accessed per row activation +system.physmem.totQLat 17606250 # Total ticks spent queuing +system.physmem.totMemAccLat 42562500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6655000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13227.84 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31343.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 750.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31977.84 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 751.29 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 750.64 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 751.29 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 5.86 # Data bus utilization in percentage -system.physmem.busUtilRead 5.86 # Data bus utilization in percentage for reads +system.physmem.busUtil 5.87 # Data bus utilization in percentage +system.physmem.busUtilRead 5.87 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.57 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.58 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 1108 # Number of row buffer hits during reads +system.physmem.readRowHits 1107 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.31 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.17 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 85181.20 # Average gap between requests -system.physmem.pageHitRate 83.31 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 763980 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 387090 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5454960 # Energy for read commands per rank (pJ) +system.physmem.avgGap 85106.69 # Average gap between requests +system.physmem.pageHitRate 83.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 771120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 390885 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5447820 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 9828510 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 194400 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 40216350 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 1207200 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actBackEnergy 9821100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 199200 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 40147950 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 1260960 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 66657450 # Total energy per rank (pJ) -system.physmem_0.averagePower 587.821160 # Core power per rank (mW) -system.physmem_0.totalIdleTime 91041000 # Total Idle time Per DRAM Rank +system.physmem_0.totalEnergy 66643995 # Total energy per rank (pJ) +system.physmem_0.averagePower 587.773777 # Core power per rank (mW) +system.physmem_0.totalIdleTime 90897000 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 89500 # Time in different power states system.physmem_0.memoryStateTime::REF 3640000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 3144500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 18326750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 88196250 # Time in different power states -system.physmem_1.actEnergy 821100 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 409860 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4041240 # Energy for read commands per rank (pJ) +system.physmem_0.memoryStateTime::PRE_PDN 3282750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 18328750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 88042000 # Time in different power states +system.physmem_1.actEnergy 828240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 413655 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4055520 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 7868280 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 220800 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 41251470 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 1959840 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 7853460 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 220320 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 41175660 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 2031360 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 65177550 # Total energy per rank (pJ) -system.physmem_1.averagePower 574.770608 # Core power per rank (mW) -system.physmem_1.totalIdleTime 95505000 # Total Idle time Per DRAM Rank +system.physmem_1.totalEnergy 65183175 # Total energy per rank (pJ) +system.physmem_1.averagePower 574.889920 # Core power per rank (mW) +system.physmem_1.totalIdleTime 95520250 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 174500 # Time in different power states system.physmem_1.memoryStateTime::REF 3640000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 5102500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14007750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 90472250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 78040 # Number of BP lookups -system.cpu.branchPred.condPredicted 47825 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4968 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 59525 # Number of BTB lookups -system.cpu.branchPred.BTBHits 36023 # Number of BTB hits +system.physmem_1.memoryStateTime::PRE_PDN 5288750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 13978500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 90301250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 78097 # Number of BP lookups +system.cpu.branchPred.condPredicted 47857 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4973 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 59652 # Number of BTB lookups +system.cpu.branchPred.BTBHits 36130 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 60.517430 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 60.567961 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 14832 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 6672 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 8160 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 2577 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 14779 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 6634 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 8145 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 2576 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -295,244 +295,244 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 115 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 113397000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 226795 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 113383000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 226767 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 73757 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 336548 # Number of instructions fetch has processed -system.cpu.fetch.Branches 78040 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42695 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 87262 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 10228 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 401 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 60631 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2398 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 166726 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.018569 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.822541 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 73708 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 336580 # Number of instructions fetch has processed +system.cpu.fetch.Branches 78097 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42764 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 87814 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 10240 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 400 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 177 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 60514 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2320 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 167219 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.012810 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.818543 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 89937 53.94% 53.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 11784 7.07% 61.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 13843 8.30% 69.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 11668 7.00% 76.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 5791 3.47% 79.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6797 4.08% 83.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2856 1.71% 85.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4611 2.77% 88.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 19439 11.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 90347 54.03% 54.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 11793 7.05% 61.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 13895 8.31% 69.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 11689 6.99% 76.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5745 3.44% 79.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6911 4.13% 83.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2836 1.70% 85.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4645 2.78% 88.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 19358 11.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 166726 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.344099 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.483930 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 72653 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 18351 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 70165 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1269 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4288 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 13538 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 899 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 310274 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2536 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4288 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 75144 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 7711 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3158 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 68795 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 7630 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 298982 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 168 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 64 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 782 # Number of times rename has blocked due to LQ full +system.cpu.fetch.rateDist::total 167219 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.344393 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.484255 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 72610 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 18818 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 70228 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1268 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4295 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 35338 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 921 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 310147 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2548 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4295 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 75141 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8221 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3161 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 68810 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 7591 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 298778 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 161 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 69 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 743 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 6500 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 208109 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 389749 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 387389 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2360 # Number of floating rename lookups +system.cpu.rename.RenamedOperands 207984 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 389381 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 387034 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2347 # Number of floating rename lookups system.cpu.rename.CommittedMaps 155141 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 52968 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 52843 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 133 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 133 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 3030 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 62164 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 43440 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1172 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 335 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 273555 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 154 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 261697 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 610 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 47545 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 26182 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 33 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 166726 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.569623 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.886679 # Number of insts issued each cycle +system.cpu.rename.skidInsts 3092 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 62122 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 43306 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1169 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 342 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 273422 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 166 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 261550 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 571 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 47419 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 26031 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 167219 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.564117 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.884378 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 67362 40.40% 40.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36208 21.72% 62.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 23951 14.37% 76.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10817 6.49% 82.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10352 6.21% 89.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8029 4.82% 94.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7579 4.55% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1315 0.79% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1113 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 67857 40.58% 40.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36223 21.66% 62.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 23953 14.32% 76.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10828 6.48% 83.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10307 6.16% 89.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8097 4.84% 94.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7553 4.52% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1302 0.78% 99.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1099 0.66% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 166726 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 167219 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 704 10.43% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2989 44.27% 54.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2970 43.99% 98.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 88 1.30% 99.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 716 10.62% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2981 44.22% 54.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2955 43.84% 98.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 88 1.31% 99.99% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 1 0.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 117 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 159679 61.02% 61.06% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 326 0.12% 61.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 44 0.02% 61.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 172 0.07% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 120 0.05% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 58 0.02% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 30 0.01% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 12 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 5 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 59286 22.65% 84.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 40948 15.65% 99.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 721 0.28% 99.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 159688 61.05% 61.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 326 0.12% 61.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 44 0.02% 61.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 170 0.06% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 120 0.05% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 58 0.02% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 30 0.01% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 12 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 5 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 59226 22.64% 84.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 40848 15.62% 99.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 727 0.28% 99.93% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 179 0.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 261697 # Type of FU issued -system.cpu.iq.rate 1.153892 # Inst issue rate -system.cpu.iq.fu_busy_cnt 6752 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025801 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 694798 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 318360 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 249994 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2684 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2938 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1006 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266946 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1386 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5628 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 261550 # Type of FU issued +system.cpu.iq.rate 1.153387 # Inst issue rate +system.cpu.iq.fu_busy_cnt 6741 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025773 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 694940 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 318115 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 249943 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2691 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2944 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1007 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266784 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1390 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5624 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10453 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 28 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6211 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10411 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 34 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6077 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 9 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4288 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4913 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 272 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 273705 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3278 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 62164 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 43440 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 150 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 265 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 40 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1281 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3469 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4750 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 254156 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 58399 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7541 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4295 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4907 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 918 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 273579 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 3363 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 62122 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 43306 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 157 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 908 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1293 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3450 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4743 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 254044 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 58349 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7506 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 98174 # number of memory reference insts executed -system.cpu.iew.exec_branches 57098 # Number of branches executed -system.cpu.iew.exec_stores 39775 # Number of stores executed -system.cpu.iew.exec_rate 1.120642 # Inst execution rate -system.cpu.iew.wb_sent 252228 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 251000 # cumulative count of insts written-back -system.cpu.iew.wb_producers 95690 # num instructions producing a value -system.cpu.iew.wb_consumers 132115 # num instructions consuming a value -system.cpu.iew.wb_rate 1.106726 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.724293 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 47577 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 98069 # number of memory reference insts executed +system.cpu.iew.exec_branches 57083 # Number of branches executed +system.cpu.iew.exec_stores 39720 # Number of stores executed +system.cpu.iew.exec_rate 1.120286 # Inst execution rate +system.cpu.iew.wb_sent 252158 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 250950 # cumulative count of insts written-back +system.cpu.iew.wb_producers 95653 # num instructions producing a value +system.cpu.iew.wb_consumers 131997 # num instructions consuming a value +system.cpu.iew.wb_rate 1.106643 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.724660 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 47451 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 117 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4142 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 157673 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.434355 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.158076 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 4148 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158171 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.429839 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.156696 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 82961 52.62% 52.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 25849 16.39% 69.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14396 9.13% 78.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11000 6.98% 85.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5848 3.71% 88.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5974 3.79% 92.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3323 2.11% 94.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1258 0.80% 95.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7064 4.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 83501 52.79% 52.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 25809 16.32% 69.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14383 9.09% 78.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 10997 6.95% 85.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5860 3.70% 88.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5977 3.78% 92.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3309 2.09% 94.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1266 0.80% 95.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7069 4.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 157673 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158171 # Number of insts commited each cycle system.cpu.commit.committedInsts 226159 # Number of instructions committed system.cpu.commit.committedOps 226159 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -582,103 +582,103 @@ system.cpu.commit.op_class_0::FloatMemWrite 136 0.06% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 226159 # Class of committed instruction -system.cpu.commit.bw_lim_events 7064 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 422850 # The number of ROB reads -system.cpu.rob.rob_writes 556608 # The number of ROB writes -system.cpu.timesIdled 458 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 60069 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 7069 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 423217 # The number of ROB reads +system.cpu.rob.rob_writes 556357 # The number of ROB writes +system.cpu.timesIdled 459 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59548 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 226159 # Number of Instructions Simulated system.cpu.committedOps 226159 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.002812 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.002812 # CPI: Total CPI of All Threads -system.cpu.ipc 0.997196 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.997196 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 329004 # number of integer regfile reads -system.cpu.int_regfile_writes 174767 # number of integer regfile writes -system.cpu.fp_regfile_reads 880 # number of floating regfile reads -system.cpu.fp_regfile_writes 753 # number of floating regfile writes -system.cpu.misc_regfile_reads 448 # number of misc regfile reads +system.cpu.cpi 1.002688 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.002688 # CPI: Total CPI of All Threads +system.cpu.ipc 0.997319 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.997319 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 329254 # number of integer regfile reads +system.cpu.int_regfile_writes 174794 # number of integer regfile writes +system.cpu.fp_regfile_reads 878 # number of floating regfile reads +system.cpu.fp_regfile_writes 754 # number of floating regfile writes +system.cpu.misc_regfile_reads 446 # number of misc regfile reads system.cpu.misc_regfile_writes 313 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 244.736374 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 87597 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 244.658569 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 87565 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 291.019934 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 290.913621 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 244.736374 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.059750 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.059750 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 244.658569 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.059731 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.059731 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.073486 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179361 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179361 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 51858 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 51858 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 35739 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 35739 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 87597 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 87597 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 87597 # number of overall hits -system.cpu.dcache.overall_hits::total 87597 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 443 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 443 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1490 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1490 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1933 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1933 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1933 # number of overall misses -system.cpu.dcache.overall_misses::total 1933 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36817500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36817500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 96718425 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 96718425 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 133535925 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 133535925 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 133535925 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 133535925 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 52301 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 52301 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 179301 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179301 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 51833 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 51833 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 35732 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 35732 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 87565 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 87565 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 87565 # number of overall hits +system.cpu.dcache.overall_hits::total 87565 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 438 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 438 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1497 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1497 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1935 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1935 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1935 # number of overall misses +system.cpu.dcache.overall_misses::total 1935 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36015000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36015000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 97868425 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 97868425 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 133883425 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 133883425 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 133883425 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 133883425 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 52271 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 52271 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 37229 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 37229 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 89530 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 89530 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 89530 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 89530 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008470 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008470 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040023 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.040023 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021591 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.021591 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021591 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.021591 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83109.480813 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 83109.480813 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64911.694631 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64911.694631 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69082.216762 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69082.216762 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69082.216762 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69082.216762 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5513 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 89500 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 89500 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 89500 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 89500 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008379 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008379 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040211 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.040211 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021620 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.021620 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021620 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.021620 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 82226.027397 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 82226.027397 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65376.369405 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65376.369405 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69190.400517 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69190.400517 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69190.400517 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69190.400517 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6103 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 79 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.784810 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.253165 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 346 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 346 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1286 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1286 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1632 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1632 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1632 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1632 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 341 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 341 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1293 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1293 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1634 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1634 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1634 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1634 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 97 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 97 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 204 # number of WriteReq MSHR misses @@ -687,144 +687,144 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 301 system.cpu.dcache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 301 # 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mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8546500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8546500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17206500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17206500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25753000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25753000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25753000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25753000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001856 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001856 # 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average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 85558.139535 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 70 # number of replacements +system.cpu.icache.tags.tagsinuse 535.835535 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 59155 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1035 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 57.154589 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 535.650396 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.261548 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.261548 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 535.835535 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.261638 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.261638 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 738 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.471191 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 122286 # Number of tag accesses -system.cpu.icache.tags.data_accesses 122286 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 59273 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59273 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59273 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59273 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59273 # number of overall hits -system.cpu.icache.overall_hits::total 59273 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1353 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1353 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1353 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1353 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1353 # number of overall misses -system.cpu.icache.overall_misses::total 1353 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 109130497 # 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number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.022317 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.022317 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.022317 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.022317 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.022317 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.022317 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80658.164819 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 80658.164819 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 80658.164819 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 80658.164819 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 80658.164819 # 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number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1354 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1354 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1354 # number of overall misses +system.cpu.icache.overall_misses::total 1354 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 109143498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 109143498 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 109143498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 109143498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 109143498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 109143498 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 60509 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60509 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60509 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60509 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60509 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60509 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.022377 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.022377 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.022377 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.022377 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.022377 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.022377 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80608.196455 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 80608.196455 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 80608.196455 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 80608.196455 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 80608.196455 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 80608.196455 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2475 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 33 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 34 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 71.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 72.794118 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 86827498 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 86827498 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.017105 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.017105 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.017105 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.017105 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.017105 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.017105 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83891.302415 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83891.302415 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83891.302415 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 83891.302415 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83891.302415 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 83891.302415 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 808.401303 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 71 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1330 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.053383 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 808.901136 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 72 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1331 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.054095 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 563.637058 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 244.764245 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017201 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007470 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.024670 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 1330 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 879 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.040588 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12538 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12538 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 69 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 69 # number of WritebackClean hits +system.cpu.l2cache.tags.occ_blocks::cpu.inst 564.214692 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 244.686444 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017218 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007467 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.024686 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1331 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 880 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 338 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.040619 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 12555 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12555 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackClean_hits::writebacks 70 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 70 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 2 # 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number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74966500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21350500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 96317000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74966500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21350500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 96317000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 1331 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14860000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14860000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74945000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74945000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7431000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7431000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74945000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22291000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 97236000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74945000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22291000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 97236000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.998060 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.998060 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.998062 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.998062 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998060 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998062 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.998498 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998060 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.998500 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998062 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.998498 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67200.980392 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67200.980392 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72853.741497 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72853.741497 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78778.350515 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78778.350515 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72853.741497 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70931.893688 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72418.796992 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72853.741497 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70931.893688 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72418.796992 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1404 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 72 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.998500 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72843.137255 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72843.137255 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72762.135922 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72762.135922 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76608.247423 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76608.247423 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72762.135922 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74056.478405 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73054.845980 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72762.135922 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74056.478405 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73054.845980 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1406 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1131 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 69 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1132 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 70 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 204 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 204 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1035 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 97 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2134 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2137 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 602 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2736 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 70400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2739 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 70528 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 19264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 89664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 89792 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 3 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 192 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1335 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002247 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.047369 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1336 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002246 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.047351 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1332 99.78% 99.78% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1333 99.78% 99.78% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 3 0.22% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1335 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 771000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1336 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 773000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1551000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1552500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 451500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1330 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 1331 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1126 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1127 # Transaction distribution system.membus.trans_dist::ReadExReq 204 # Transaction distribution system.membus.trans_dist::ReadExResp 204 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1126 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2660 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2660 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 85120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 85120 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 1127 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2662 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2662 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 85184 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 85184 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1330 # Request fanout histogram +system.membus.snoop_fanout::samples 1331 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1330 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1331 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1330 # Request fanout histogram -system.membus.reqLayer0.occupancy 1627500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1331 # Request fanout histogram +system.membus.reqLayer0.occupancy 1624000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 7008750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 7014000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 6.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt index 2726406d4..8fec50473 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.004665 # Nu sim_ticks 4665394 # Number of ticks simulated final_tick 4665394 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 17585 # Simulator instruction rate (inst/s) -host_op_rate 17585 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 362753 # Simulator tick rate (ticks/s) -host_mem_usage 412420 # Number of bytes of host memory used -host_seconds 12.86 # Real time elapsed on the host +host_inst_rate 87650 # Simulator instruction rate (inst/s) +host_op_rate 87650 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1808106 # Simulator tick rate (ticks/s) +host_mem_usage 429644 # Number of bytes of host memory used +host_seconds 2.58 # Real time elapsed on the host sim_insts 226159 # Number of instructions simulated sim_ops 226159 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -402,13 +402,35 @@ system.ruby.miss_latency_hist_seqr::stdev 37.140999 system.ruby.miss_latency_hist_seqr | 36417 50.41% 50.41% | 33252 46.03% 96.43% | 1716 2.38% 98.81% | 307 0.42% 99.23% | 278 0.38% 99.62% | 236 0.33% 99.94% | 20 0.03% 99.97% | 8 0.01% 99.98% | 0 0.00% 99.98% | 13 0.02% 100.00% system.ruby.miss_latency_hist_seqr::total 72247 system.ruby.Directory.incomplete_times_seqr 72246 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.015485 # Average number of messages in buffer +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.999904 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.030971 # Average number of messages in buffer +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.751856 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015486 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999985 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.030971 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999985 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 242968 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 72247 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 315215 # Number of cache demand accesses +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.015485 # Average number of messages in buffer +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.999322 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.067565 # Average number of messages in buffer +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 1.000000 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.061941 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999999 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.015486 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.999887 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.015485 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.999420 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.015486 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.999905 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.092910 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.751873 # Average number of cycles messages are stalled in this MB system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 7.742647 system.ruby.network.routers0.msg_count.Control::2 72247 @@ -419,6 +441,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 577976 system.ruby.network.routers0.msg_bytes.Data::2 5201496 system.ruby.network.routers0.msg_bytes.Response_Data::4 5201784 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 577944 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.030971 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.751860 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.015485 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.999808 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.015486 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.999970 # Average number of cycles messages are stalled in this MB system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 7.742647 system.ruby.network.routers1.msg_count.Control::2 72247 @@ -429,6 +457,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 577976 system.ruby.network.routers1.msg_bytes.Data::2 5201496 system.ruby.network.routers1.msg_bytes.Response_Data::4 5201784 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 577944 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.030971 # Average number of messages in buffer +system.ruby.network.int_link_buffers02.avg_stall_time 7.751870 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015485 # Average number of messages in buffer +system.ruby.network.int_link_buffers08.avg_stall_time 2.999712 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.015486 # Average number of messages in buffer +system.ruby.network.int_link_buffers09.avg_stall_time 2.999954 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.015485 # Average number of messages in buffer +system.ruby.network.int_link_buffers13.avg_stall_time 4.999518 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.015486 # Average number of messages in buffer +system.ruby.network.int_link_buffers14.avg_stall_time 4.999922 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.030971 # Average number of messages in buffer +system.ruby.network.int_link_buffers17.avg_stall_time 9.751864 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.015485 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.999615 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.015486 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.999938 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.030971 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.751867 # Average number of cycles messages are stalled in this MB system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 7.742647 system.ruby.network.routers2.msg_count.Control::2 72247 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/stats.txt index 4aec07287..4c33c60ec 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000165 # Nu sim_ticks 165091500 # Number of ticks simulated final_tick 165091500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 30601 # Simulator instruction rate (inst/s) -host_op_rate 30601 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44574860 # Simulator tick rate (ticks/s) -host_mem_usage 244264 # Number of bytes of host memory used -host_seconds 3.70 # Real time elapsed on the host +host_inst_rate 261359 # Simulator instruction rate (inst/s) +host_op_rate 261351 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 380682439 # Simulator tick rate (ticks/s) +host_mem_usage 261856 # Number of bytes of host memory used +host_seconds 0.43 # Real time elapsed on the host sim_insts 113337 # Number of instructions simulated sim_ops 113337 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 6 2.87% 90.43% # By system.physmem.bytesPerActivate::896-1023 3 1.44% 91.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 17 8.13% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 209 # Bytes accessed per row activation -system.physmem.totQLat 16657750 # Total ticks spent queuing -system.physmem.totMemAccLat 36214000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 16727250 # Total ticks spent queuing +system.physmem.totMemAccLat 36283500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 5215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15971.00 # Average queueing delay per DRAM burst +system.physmem.avgQLat 16037.63 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34721.00 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 34787.63 # Average memory access latency per DRAM burst system.physmem.avgRdBW 404.33 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 404.33 # Average system read bandwidth in MiByte/s @@ -229,19 +229,19 @@ system.physmem_0.readEnergy 3348660 # En system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 9067560 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 480480 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 54701760 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 6869760 # Energy for precharge power-down per rank (pJ) +system.physmem_0.preBackEnergy 480000 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 54713160 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 6860640 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 2569980 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 91748400 # Total energy per rank (pJ) -system.physmem_0.averagePower 555.739358 # Core power per rank (mW) +system.physmem_0.totalEnergy 91750200 # Total energy per rank (pJ) +system.physmem_0.averagePower 555.750261 # Core power per rank (mW) system.physmem_0.totalIdleTime 143461250 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 642000 # Time in different power states system.physmem_0.memoryStateTime::REF 5732000 # Time in different power states system.physmem_0.memoryStateTime::SREF 6106000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 17892500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 17868500 # Time in different power states system.physmem_0.memoryStateTime::ACT 14770000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 119949000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 119973000 # Time in different power states system.physmem_1.actEnergy 749700 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 383295 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 4098360 # Energy for read commands per rank (pJ) @@ -249,31 +249,31 @@ system.physmem_1.writeEnergy 0 # En system.physmem_1.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 9572580 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 409440 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 46964580 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 13642080 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actPowerDownEnergy 46966860 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 13640160 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 1635840 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 90363315 # Total energy per rank (pJ) -system.physmem_1.averagePower 547.349607 # Core power per rank (mW) +system.physmem_1.totalEnergy 90363675 # Total energy per rank (pJ) +system.physmem_1.averagePower 547.351788 # Core power per rank (mW) system.physmem_1.totalIdleTime 142759500 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 477500 # Time in different power states system.physmem_1.memoryStateTime::REF 5472000 # Time in different power states system.physmem_1.memoryStateTime::SREF 4514500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 35521500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 35516500 # Time in different power states system.physmem_1.memoryStateTime::ACT 16091750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 103014250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 103019250 # Time in different power states system.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 31704 # Number of BP lookups -system.cpu.branchPred.condPredicted 20239 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2235 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 27881 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15332 # Number of BTB hits +system.cpu.branchPred.lookups 31695 # Number of BP lookups +system.cpu.branchPred.condPredicted 20247 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2223 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 27548 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15330 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 54.990854 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 55.648323 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 5600 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 3678 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1922 # Number of indirect misses. +system.cpu.branchPred.indirectLookups 5583 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 3675 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1908 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 1024 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -301,7 +301,7 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 113337 # Number of instructions committed system.cpu.committedOps 113337 # Number of ops (including micro ops) committed -system.cpu.discardedOps 5814 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 5802 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 2.913285 # CPI: cycles per instruction system.cpu.ipc 0.343255 # IPC: instructions per cycle @@ -344,16 +344,16 @@ system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 113337 # Class of committed instruction -system.cpu.tickCycles 171254 # Number of cycles that the object actually ticked -system.cpu.idleCycles 158929 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 171128 # Number of cycles that the object actually ticked +system.cpu.idleCycles 159055 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 213.474286 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43868 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 213.474358 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43871 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 263 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 166.798479 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 166.809886 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 213.474286 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 213.474358 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.052118 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.052118 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 263 # Occupied blocks per task id @@ -361,17 +361,17 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 202 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.064209 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88905 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88905 # Number of data accesses +system.cpu.dcache.tags.tag_accesses 88911 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88911 # Number of data accesses system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 24540 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 24540 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 24543 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 24543 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19328 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19328 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 43868 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 43868 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 43868 # number of overall hits -system.cpu.dcache.overall_hits::total 43868 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 43871 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 43871 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 43871 # number of overall hits +system.cpu.dcache.overall_hits::total 43871 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 69 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 69 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 384 # number of WriteReq misses @@ -380,38 +380,38 @@ system.cpu.dcache.demand_misses::cpu.data 453 # n system.cpu.dcache.demand_misses::total 453 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 453 # number of overall misses system.cpu.dcache.overall_misses::total 453 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7586500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7586500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7619000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7619000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 31133500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 31133500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 38720000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 38720000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 38720000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 38720000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24609 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24609 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 38752500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 38752500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 38752500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 38752500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24612 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24612 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19712 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19712 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 44321 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 44321 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 44321 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 44321 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 44324 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 44324 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 44324 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 44324 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002804 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002804 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019481 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.019481 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010221 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010221 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010221 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010221 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 109949.275362 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 109949.275362 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.010220 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010220 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010220 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010220 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 110420.289855 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 110420.289855 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81076.822917 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 81076.822917 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 85474.613687 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 85474.613687 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 85474.613687 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 85474.613687 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 85546.357616 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 85546.357616 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 85546.357616 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 85546.357616 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -434,14 +434,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 263 system.cpu.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 263 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7121500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7121500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7154000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7154000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16117500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 16117500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23239000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23239000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23239000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23239000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23271500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23271500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23271500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23271500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002641 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002641 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010045 # mshr miss rate for WriteReq accesses @@ -450,68 +450,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005934 system.cpu.dcache.demand_mshr_miss_rate::total 0.005934 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005934 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005934 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 109561.538462 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 109561.538462 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 110061.538462 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 110061.538462 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81401.515152 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81401.515152 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88361.216730 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 88361.216730 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88361.216730 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 88361.216730 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88484.790875 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 88484.790875 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88484.790875 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 88484.790875 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 14 # number of replacements -system.cpu.icache.tags.tagsinuse 386.834879 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 49717 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 386.835866 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 49670 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 781 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 63.658131 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 63.597951 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 386.834879 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.188884 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.188884 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 386.835866 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.188885 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.188885 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 767 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 497 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.374512 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 101777 # Number of tag accesses -system.cpu.icache.tags.data_accesses 101777 # Number of data accesses +system.cpu.icache.tags.tag_accesses 101683 # Number of tag accesses +system.cpu.icache.tags.data_accesses 101683 # Number of data accesses system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 49717 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 49717 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 49717 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 49717 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 49717 # number of overall hits -system.cpu.icache.overall_hits::total 49717 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 49670 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 49670 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 49670 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 49670 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 49670 # number of overall hits +system.cpu.icache.overall_hits::total 49670 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 781 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 781 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 781 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 781 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 781 # number of overall misses system.cpu.icache.overall_misses::total 781 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 68473000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 68473000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 68473000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 68473000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 68473000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 68473000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 50498 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 50498 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 50498 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 50498 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 50498 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 50498 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015466 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015466 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015466 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015466 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015466 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015466 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 87673.495519 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 87673.495519 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 87673.495519 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 87673.495519 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 87673.495519 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 87673.495519 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 68509500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 68509500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 68509500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 68509500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 68509500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 68509500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 50451 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 50451 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 50451 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 50451 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 50451 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 50451 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015480 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015480 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015480 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015480 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015480 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015480 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 87720.230474 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 87720.230474 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 87720.230474 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 87720.230474 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 87720.230474 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 87720.230474 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -526,33 +526,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 781 system.cpu.icache.demand_mshr_misses::total 781 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 781 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 781 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 67692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67692000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 67692000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67692000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 67692000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015466 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015466 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015466 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.015466 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015466 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.015466 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 86673.495519 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 86673.495519 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 86673.495519 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 86673.495519 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 86673.495519 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 86673.495519 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67728500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 67728500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67728500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 67728500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67728500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 67728500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015480 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.015480 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.015480 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 86720.230474 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 86720.230474 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 86720.230474 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 86720.230474 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 86720.230474 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 86720.230474 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 603.610931 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 603.611991 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1043 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.014382 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.574887 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 213.036044 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.575874 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 213.036117 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011919 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006501 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.018421 # Average percentage of cache occupancy @@ -586,16 +586,16 @@ system.cpu.l2cache.overall_misses::cpu.data 262 # system.cpu.l2cache.overall_misses::total 1043 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15820000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 15820000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 66520500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 66520500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7011500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7011500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 66520500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22831500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 89352000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 66520500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22831500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 89352000 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 66557000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 66557000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7044000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7044000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 66557000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22864000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 89421000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 66557000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22864000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 89421000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 14 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 14 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 198 # number of ReadExReq accesses(hits+misses) @@ -624,16 +624,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.996198 system.cpu.l2cache.overall_miss_rate::total 0.999042 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79898.989899 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79898.989899 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85173.495519 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85173.495519 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109554.687500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 109554.687500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85173.495519 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87143.129771 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 85668.264621 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85173.495519 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87143.129771 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 85668.264621 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85220.230474 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85220.230474 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 110062.500000 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 110062.500000 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85220.230474 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87267.175573 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 85734.419942 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85220.230474 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87267.175573 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 85734.419942 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -654,16 +654,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 262 system.cpu.l2cache.overall_mshr_misses::total 1043 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13840000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13840000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 58710500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 58710500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6371500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6371500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58710500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20211500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 78922000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58710500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20211500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 78922000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 58747000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 58747000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6404000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6404000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58747000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20244000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 78991000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58747000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20244000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 78991000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -678,16 +678,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996198 system.cpu.l2cache.overall_mshr_miss_rate::total 0.999042 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69898.989899 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69898.989899 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75173.495519 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75173.495519 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 99554.687500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 99554.687500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75173.495519 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77143.129771 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75668.264621 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75173.495519 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77143.129771 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75668.264621 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75220.230474 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75220.230474 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 100062.500000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 100062.500000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75220.230474 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77267.175573 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75734.419942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75220.230474 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77267.175573 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75734.419942 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1058 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 15 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -753,9 +753,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 1043 # Request fanout histogram -system.membus.reqLayer0.occupancy 1170500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1170000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 5536250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5535750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/stats.txt index 0be26640f..0c1b30ad6 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000067 # Number of seconds simulated -sim_ticks 66726000 # Number of ticks simulated -final_tick 66726000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 66743000 # Number of ticks simulated +final_tick 66743000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 30660 # Simulator instruction rate (inst/s) -host_op_rate 30660 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18058105 # Simulator tick rate (ticks/s) -host_mem_usage 245440 # Number of bytes of host memory used -host_seconds 3.70 # Real time elapsed on the host +host_inst_rate 234636 # Simulator instruction rate (inst/s) +host_op_rate 234630 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 138224430 # Simulator tick rate (ticks/s) +host_mem_usage 263644 # Number of bytes of host memory used +host_seconds 0.48 # Real time elapsed on the host sim_insts 113291 # Number of instructions simulated sim_ops 113291 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 49408 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 16960 # Number of bytes read from this memory -system.physmem.bytes_read::total 66432 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 66368 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 49408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 49408 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 772 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 265 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1038 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 741420136 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 254173785 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 995593921 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 741420136 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 741420136 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 741420136 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 254173785 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 995593921 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1039 # Number of read requests accepted +system.physmem.num_reads::total 1037 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 740272388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 254109045 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 994381433 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 740272388 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 740272388 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 740272388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 254109045 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 994381433 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1038 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 1039 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 1038 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 66496 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 66432 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 66496 # Total read bytes from the system interface side +system.physmem.bytesReadSys 66432 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -46,7 +46,7 @@ system.physmem.perBankRdBursts::0 89 # Pe system.physmem.perBankRdBursts::1 8 # Per bank write bursts system.physmem.perBankRdBursts::2 16 # Per bank write bursts system.physmem.perBankRdBursts::3 108 # Per bank write bursts -system.physmem.perBankRdBursts::4 64 # Per bank write bursts +system.physmem.perBankRdBursts::4 63 # Per bank write bursts system.physmem.perBankRdBursts::5 91 # Per bank write bursts system.physmem.perBankRdBursts::6 61 # Per bank write bursts system.physmem.perBankRdBursts::7 30 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 66707000 # Total gap between requests +system.physmem.totGap 66724000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1039 # Read request sizes (log2) +system.physmem.readPktSize::6 1038 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 580 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 579 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 110 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,94 +187,94 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 205 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 313.131707 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 191.178317 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 319.046077 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 71 34.63% 34.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 47 22.93% 57.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 29 14.15% 71.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 11 5.37% 77.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 11 5.37% 82.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6 2.93% 85.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 1.46% 86.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5 2.44% 89.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22 10.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 205 # Bytes accessed per row activation -system.physmem.totQLat 13576000 # Total ticks spent queuing -system.physmem.totMemAccLat 33057250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5195000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13066.41 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 201 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 318.407960 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 195.437814 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 320.986499 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 66 32.84% 32.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 49 24.38% 57.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 28 13.93% 71.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 11 5.47% 76.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 11 5.47% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6 2.99% 85.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 1.49% 86.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5 2.49% 89.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22 10.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 201 # Bytes accessed per row activation +system.physmem.totQLat 13663500 # Total ticks spent queuing +system.physmem.totMemAccLat 33126000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5190000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13163.29 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31816.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 996.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31913.29 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 995.34 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 996.55 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 995.34 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.79 # Data bus utilization in percentage -system.physmem.busUtilRead 7.79 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.78 # Data bus utilization in percentage +system.physmem.busUtilRead 7.78 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 821 # Number of row buffer hits during reads +system.physmem.readRowHits 824 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.02 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.38 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 64203.08 # Average gap between requests -system.physmem.pageHitRate 79.02 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 835380 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 413655 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3334380 # Energy for read commands per rank (pJ) +system.physmem.avgGap 64281.31 # Average gap between requests +system.physmem.pageHitRate 79.38 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 821100 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 406065 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3327240 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6568110 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 113280 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 22288140 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 1209600 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actBackEnergy 6538470 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 110400 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 22321770 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 1215840 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 39679665 # Total energy per rank (pJ) -system.physmem_0.averagePower 594.663495 # Core power per rank (mW) -system.physmem_0.totalIdleTime 51714500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 59500 # Time in different power states +system.physmem_0.totalEnergy 39658005 # Total energy per rank (pJ) +system.physmem_0.averagePower 594.183051 # Core power per rank (mW) +system.physmem_0.totalIdleTime 51789750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 53500 # Time in different power states system.physmem_0.memoryStateTime::REF 2080000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 3148750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 12569500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 48868250 # Time in different power states -system.physmem_1.actEnergy 721140 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 364320 # Energy for precharge commands per rank (pJ) +system.physmem_0.memoryStateTime::PRE_PDN 3164000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 12517250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 48928250 # Time in different power states +system.physmem_1.actEnergy 706860 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 356730 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 4084080 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6353220 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 143040 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 20623170 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 2762880 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 6307620 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 140640 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 21247890 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 2284320 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 39968970 # Total energy per rank (pJ) -system.physmem_1.averagePower 598.999194 # Core power per rank (mW) -system.physmem_1.totalIdleTime 52416000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 150500 # Time in different power states +system.physmem_1.totalEnergy 40045260 # Total energy per rank (pJ) +system.physmem_1.averagePower 599.985167 # Core power per rank (mW) +system.physmem_1.totalIdleTime 52550750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 144500 # Time in different power states system.physmem_1.memoryStateTime::REF 2080000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 7195250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 12079500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 45220750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 39966 # Number of BP lookups -system.cpu.branchPred.condPredicted 24999 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2671 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 33955 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19441 # Number of BTB hits +system.physmem_1.memoryStateTime::PRE_PDN 5948000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 11967750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 46602750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 40127 # Number of BP lookups +system.cpu.branchPred.condPredicted 25071 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2677 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 34324 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19560 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 57.255191 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 56.986365 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 7662 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 3924 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 3738 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 1190 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 7732 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 3910 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 3822 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1192 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -295,243 +295,243 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 45 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 66726000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 133453 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 66743000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 133487 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 32838 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 168786 # Number of instructions fetch has processed -system.cpu.fetch.Branches 39966 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23365 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 44071 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5482 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 503 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 181 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22322 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1285 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 80334 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.101053 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.833149 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 32821 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 168943 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40127 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23470 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 44129 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5494 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 504 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22264 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1272 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80357 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.102406 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.833567 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 43916 54.67% 54.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3396 4.23% 58.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6102 7.60% 66.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5424 6.75% 73.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2470 3.07% 76.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6562 8.17% 84.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1937 2.41% 86.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1614 2.01% 88.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8913 11.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 43897 54.63% 54.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3425 4.26% 58.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6099 7.59% 66.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5421 6.75% 73.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2445 3.04% 76.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6593 8.20% 84.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1925 2.40% 86.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1654 2.06% 88.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8898 11.07% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 80334 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.299476 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.264760 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 33037 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 11879 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 80357 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.300606 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.265614 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 33044 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 11875 # Number of cycles decode is blocked system.cpu.decode.RunCycles 32363 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 923 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2132 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6308 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 640 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 154953 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1928 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2132 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34625 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3379 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1413 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 31599 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 7186 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 148471 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 97 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 431 # Number of times rename has blocked due to LQ full +system.cpu.decode.UnblockCycles 936 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2139 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 19097 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 639 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 154927 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1938 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2139 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34647 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3538 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1406 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 31612 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 7015 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 148450 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 267 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 6512 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 101480 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 195404 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 195404 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 101534 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 195335 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 195335 # Number of integer rename lookups system.cpu.rename.CommittedMaps 76188 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 25292 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 58 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 58 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 3325 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 28879 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22638 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 630 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 25346 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 57 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 57 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 3248 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29003 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22614 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 628 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 17 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 137222 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 69 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 131068 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 381 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23997 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13432 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 22 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 80334 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.631538 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.013515 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 137191 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 60 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 131006 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 401 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23957 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13441 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80357 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.630300 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.012996 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 38041 47.35% 47.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10252 12.76% 60.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8094 10.08% 70.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 8074 10.05% 80.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5916 7.36% 87.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4749 5.91% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3775 4.70% 98.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1117 1.39% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 316 0.39% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 38076 47.38% 47.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10267 12.78% 60.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8067 10.04% 70.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 8077 10.05% 80.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5915 7.36% 87.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4760 5.92% 93.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3768 4.69% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1110 1.38% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 317 0.39% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 80334 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80357 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 175 6.09% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1363 47.43% 53.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1336 46.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 179 6.20% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1370 47.45% 53.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1338 46.35% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 45 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 81693 62.33% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 129 0.10% 62.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 30 0.02% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 27948 21.32% 83.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21223 16.19% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 81559 62.26% 62.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 129 0.10% 62.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 30 0.02% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 27992 21.37% 83.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21251 16.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 131068 # Type of FU issued -system.cpu.iq.rate 0.982129 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2874 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021928 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 345725 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 161326 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 125053 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 131006 # Type of FU issued +system.cpu.iq.rate 0.981414 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2887 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.022037 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 345657 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 161246 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 125018 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 133897 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 133848 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2531 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 2541 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5099 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 5223 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2926 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 2902 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 101 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2132 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2287 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 246 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 137289 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 950 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 28879 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22638 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 67 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 2139 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2305 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 218 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 137249 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 965 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29003 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22614 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 58 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 254 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 224 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 35 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 498 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1893 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2391 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 126811 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 27146 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4257 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 1896 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2394 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 126750 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 27173 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4256 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 47872 # number of memory reference insts executed -system.cpu.iew.exec_branches 29089 # Number of branches executed -system.cpu.iew.exec_stores 20726 # Number of stores executed -system.cpu.iew.exec_rate 0.950230 # Inst execution rate -system.cpu.iew.wb_sent 125714 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 125053 # cumulative count of insts written-back -system.cpu.iew.wb_producers 49299 # num instructions producing a value -system.cpu.iew.wb_consumers 72928 # num instructions consuming a value -system.cpu.iew.wb_rate 0.937056 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.675996 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 24018 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 47912 # number of memory reference insts executed +system.cpu.iew.exec_branches 29064 # Number of branches executed +system.cpu.iew.exec_stores 20739 # Number of stores executed +system.cpu.iew.exec_rate 0.949531 # Inst execution rate +system.cpu.iew.wb_sent 125653 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 125018 # cumulative count of insts written-back +system.cpu.iew.wb_producers 49237 # num instructions producing a value +system.cpu.iew.wb_consumers 72853 # num instructions consuming a value +system.cpu.iew.wb_rate 0.936556 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.675840 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 23968 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2062 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 75915 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.492340 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.298348 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2069 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 75913 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.492379 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.297345 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 42174 55.55% 55.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 10802 14.23% 69.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5429 7.15% 76.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4052 5.34% 82.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3273 4.31% 86.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3050 4.02% 90.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2519 3.32% 93.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 909 1.20% 95.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3707 4.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 42174 55.56% 55.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 10790 14.21% 69.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5413 7.13% 76.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4064 5.35% 82.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3292 4.34% 86.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3056 4.03% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2525 3.33% 93.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 907 1.19% 95.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3692 4.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 75915 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 75913 # Number of insts commited each cycle system.cpu.commit.committedInsts 113291 # Number of instructions committed system.cpu.commit.committedOps 113291 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -581,98 +581,98 @@ system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 113291 # Class of committed instruction -system.cpu.commit.bw_lim_events 3707 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 208932 # The number of ROB reads -system.cpu.rob.rob_writes 279096 # The number of ROB writes -system.cpu.timesIdled 413 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 53119 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3692 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 208895 # The number of ROB reads +system.cpu.rob.rob_writes 279024 # The number of ROB writes +system.cpu.timesIdled 415 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 53130 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 113291 # Number of Instructions Simulated system.cpu.committedOps 113291 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.177966 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.177966 # CPI: Total CPI of All Threads -system.cpu.ipc 0.848921 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.848921 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 166154 # number of integer regfile reads -system.cpu.int_regfile_writes 85972 # number of integer regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states +system.cpu.cpi 1.178267 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.178267 # CPI: Total CPI of All Threads +system.cpu.ipc 0.848704 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.848704 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 166268 # number of integer regfile reads +system.cpu.int_regfile_writes 85929 # number of integer regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 217.973737 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42393 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 217.985310 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42417 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 265 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 159.973585 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 160.064151 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 217.973737 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.053216 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.053216 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 217.985310 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.053219 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.053219 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 265 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.064697 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88473 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88473 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 24147 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 24147 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 88517 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88517 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 24171 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 24171 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18246 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 18246 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 42393 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42393 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42393 # number of overall hits -system.cpu.dcache.overall_hits::total 42393 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 245 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 245 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 42417 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42417 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42417 # number of overall hits +system.cpu.dcache.overall_hits::total 42417 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 243 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 243 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1466 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1466 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1711 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1711 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1711 # number of overall misses -system.cpu.dcache.overall_misses::total 1711 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 20376500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 20376500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 95969940 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 95969940 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 116346440 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 116346440 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 116346440 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 116346440 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24392 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24392 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1709 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1709 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1709 # 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number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009953 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009953 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.074371 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.074371 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.038795 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.038795 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.038795 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.038795 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83169.387755 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 83169.387755 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65463.806276 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65463.806276 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67999.088252 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67999.088252 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67999.088252 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67999.088252 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.038730 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.038730 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.038730 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.038730 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83259.259259 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 83259.259259 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65458.349250 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65458.349250 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67989.432417 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67989.432417 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67989.432417 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67989.432417 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 5526 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 63 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.714286 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1442 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1442 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 197 # number of WriteReq MSHR misses @@ -681,88 +681,88 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 267 system.cpu.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 267 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6394500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6394500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15710500 # 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average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 82790.262172 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006051 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006051 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006051 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006051 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91307.142857 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91307.142857 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79741.116751 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79741.116751 # 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Cycle average of tags in use +system.cpu.icache.tags.total_refs 21217 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 773 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 27.447607 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 390.097209 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.190477 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.190477 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 759 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 390.093191 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.190475 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.190475 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 757 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 680 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.370605 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45403 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45403 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 21273 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 21273 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 21273 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 21273 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 21273 # number of overall hits -system.cpu.icache.overall_hits::total 21273 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1041 # 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number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22314 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22314 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22314 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22314 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22314 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.046652 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.046652 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.046652 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.046652 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.046652 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.046652 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78291.543708 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 78291.543708 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 78291.543708 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 78291.543708 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 78291.543708 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 78291.543708 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2316 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::1 678 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.369629 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 45285 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45285 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 21217 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 21217 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 21217 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 21217 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 21217 # number of overall hits +system.cpu.icache.overall_hits::total 21217 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1039 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1039 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1039 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1039 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1039 # number of overall misses +system.cpu.icache.overall_misses::total 1039 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 81350998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 81350998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 81350998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 81350998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 81350998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 81350998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22256 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22256 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22256 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22256 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22256 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22256 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.046684 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.046684 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.046684 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.046684 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.046684 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.046684 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78297.399423 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 78297.399423 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 78297.399423 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 78297.399423 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 78297.399423 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 78297.399423 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84786.545925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 84786.545925 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 612.345284 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 612.540827 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 16 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1038 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.015414 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1037 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.015429 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 394.329847 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 218.015437 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.012034 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.006653 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.018687 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 1038 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 394.513827 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 218.027000 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.012040 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006654 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.018693 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1037 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 951 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.031677 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 9486 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 9486 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 950 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.031647 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 9477 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 9477 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 66743000 # 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system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78248.730964 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78248.730964 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83255.498060 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83255.498060 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89871.428571 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89871.428571 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83255.498060 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81295.880150 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82752.403846 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83255.498060 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81295.880150 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82752.403846 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78241.116751 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78241.116751 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83389.248705 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83389.248705 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89828.571429 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89828.571429 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83389.248705 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81279.026217 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82846.968239 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83389.248705 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81279.026217 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82846.968239 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -887,28 +887,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 197 # 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mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -921,86 +921,86 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68248.730964 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68248.730964 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73255.498060 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73255.498060 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80157.142857 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80157.142857 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73255.498060 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71370.786517 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72771.634615 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73255.498060 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71370.786517 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72771.634615 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1058 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 18 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68241.116751 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68241.116751 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73389.248705 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73389.248705 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80114.285714 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80114.285714 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73389.248705 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71353.932584 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72866.217517 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73389.248705 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71353.932584 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72866.217517 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1056 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 843 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 841 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 197 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 197 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 773 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 70 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1564 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1561 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 532 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2096 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2093 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50432 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 67456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 128 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1042 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001919 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.043790 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 67392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 64 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1040 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000962 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.031009 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1040 99.81% 99.81% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2 0.19% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1039 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1042 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 545000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1040 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 544000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1162500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1159500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 397500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1039 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 1038 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 841 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 840 # Transaction distribution system.membus.trans_dist::ReadExReq 197 # Transaction distribution system.membus.trans_dist::ReadExResp 197 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 842 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2077 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2077 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 66432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 66432 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 841 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2075 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2075 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 66368 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 66368 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1039 # Request fanout histogram +system.membus.snoop_fanout::samples 1038 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1039 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1038 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1039 # Request fanout histogram -system.membus.reqLayer0.occupancy 1253500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1038 # Request fanout histogram +system.membus.reqLayer0.occupancy 1251500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 5477500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5471250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 8.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/stats.txt index bf416790e..72cb05f08 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.001842 # Nu sim_ticks 1841805 # Number of ticks simulated final_tick 1841805 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 30529 # Simulator instruction rate (inst/s) -host_op_rate 30529 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 496310 # Simulator tick rate (ticks/s) -host_mem_usage 411128 # Number of bytes of host memory used -host_seconds 3.71 # Real time elapsed on the host +host_inst_rate 106701 # Simulator instruction rate (inst/s) +host_op_rate 106700 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1734637 # Simulator tick rate (ticks/s) +host_mem_usage 428500 # Number of bytes of host memory used +host_seconds 1.06 # Real time elapsed on the host sim_insts 113291 # Number of instructions simulated sim_ops 113291 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -402,13 +402,35 @@ system.ruby.miss_latency_hist_seqr::stdev 34.809845 system.ruby.miss_latency_hist_seqr | 17424 58.63% 58.63% | 11426 38.45% 97.08% | 606 2.04% 99.12% | 87 0.29% 99.41% | 95 0.32% 99.73% | 65 0.22% 99.95% | 1 0.00% 99.96% | 3 0.01% 99.97% | 0 0.00% 99.97% | 10 0.03% 100.00% system.ruby.miss_latency_hist_seqr::total 29717 system.ruby.Directory.incomplete_times_seqr 29716 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.016133 # Average number of messages in buffer +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.999752 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.032267 # Average number of messages in buffer +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.740878 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.016135 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999963 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.032267 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999963 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 127112 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 29717 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 156829 # Number of cache demand accesses +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.016133 # Average number of messages in buffer +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.998244 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.085150 # Average number of messages in buffer +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999999 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.064534 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999997 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.016135 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.999715 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.016133 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.998498 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.016135 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.999759 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.096797 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.740922 # Average number of cycles messages are stalled in this MB system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 8.066815 system.ruby.network.routers0.msg_count.Control::2 29717 @@ -419,6 +441,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 237736 system.ruby.network.routers0.msg_bytes.Data::2 2139336 system.ruby.network.routers0.msg_bytes.Response_Data::4 2139624 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 237704 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.032267 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.740889 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.016133 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.999504 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.016135 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.999924 # Average number of cycles messages are stalled in this MB system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 8.066815 system.ruby.network.routers1.msg_count.Control::2 29717 @@ -429,6 +457,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 237736 system.ruby.network.routers1.msg_bytes.Data::2 2139336 system.ruby.network.routers1.msg_bytes.Response_Data::4 2139624 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 237704 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.032267 # Average number of messages in buffer +system.ruby.network.int_link_buffers02.avg_stall_time 7.740915 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.016133 # Average number of messages in buffer +system.ruby.network.int_link_buffers08.avg_stall_time 2.999254 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.016135 # Average number of messages in buffer +system.ruby.network.int_link_buffers09.avg_stall_time 2.999884 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.016133 # Average number of messages in buffer +system.ruby.network.int_link_buffers13.avg_stall_time 4.998751 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.016135 # Average number of messages in buffer +system.ruby.network.int_link_buffers14.avg_stall_time 4.999802 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.032267 # Average number of messages in buffer +system.ruby.network.int_link_buffers17.avg_stall_time 9.740899 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.016133 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.999003 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.016135 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.999844 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.032267 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.740908 # Average number of cycles messages are stalled in this MB system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 8.066815 system.ruby.network.routers2.msg_count.Control::2 29717 diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 4050dbfe4..2de808a88 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 29908500 # Number of ticks simulated -final_tick 29908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 29673500 # Number of ticks simulated +final_tick 29673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 19226 # Simulator instruction rate (inst/s) -host_op_rate 19225 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39829510 # Simulator tick rate (ticks/s) -host_mem_usage 234412 # Number of bytes of host memory used -host_seconds 0.75 # Real time elapsed on the host +host_inst_rate 97740 # Simulator instruction rate (inst/s) +host_op_rate 97731 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 200871294 # Simulator tick rate (ticks/s) +host_mem_usage 251556 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 23360 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory -system.physmem.bytes_read::total 32768 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 23360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 23360 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 365 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 32640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory -system.physmem.num_reads::total 512 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 781048866 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 314559406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1095608272 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 781048866 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 781048866 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 781048866 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 314559406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1095608272 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 513 # Number of read requests accepted +system.physmem.num_reads::total 510 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 782920788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 317050567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1099971355 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 782920788 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 782920788 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 782920788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 317050567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1099971355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 511 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 513 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 511 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 32832 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 32704 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 32832 # Total read bytes from the system interface side +system.physmem.bytesReadSys 32704 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 105 # Per bank write bursts +system.physmem.perBankRdBursts::0 104 # Per bank write bursts system.physmem.perBankRdBursts::1 28 # Per bank write bursts -system.physmem.perBankRdBursts::2 55 # Per bank write bursts -system.physmem.perBankRdBursts::3 27 # Per bank write bursts -system.physmem.perBankRdBursts::4 23 # Per bank write bursts +system.physmem.perBankRdBursts::2 54 # Per bank write bursts +system.physmem.perBankRdBursts::3 28 # Per bank write bursts +system.physmem.perBankRdBursts::4 22 # Per bank write bursts system.physmem.perBankRdBursts::5 0 # Per bank write bursts system.physmem.perBankRdBursts::6 32 # Per bank write bursts system.physmem.perBankRdBursts::7 38 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 29877000 # Total gap between requests +system.physmem.totGap 29642000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 513 # Read request sizes (log2) +system.physmem.readPktSize::6 511 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -92,11 +92,11 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 156 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 153 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -188,328 +188,329 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 394.666667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 253.933476 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.475070 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 393.025641 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 252.718123 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 347.605052 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 17 21.79% 21.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19 24.36% 46.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12 15.38% 61.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 5 6.41% 67.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18 23.08% 44.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14 17.95% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 5.13% 67.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 5 6.41% 74.36% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1 1.28% 75.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6 7.69% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.28% 84.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7 8.97% 84.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 12 15.38% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation -system.physmem.totQLat 6719500 # Total ticks spent queuing -system.physmem.totMemAccLat 16338250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2565000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13098.44 # Average queueing delay per DRAM burst +system.physmem.totQLat 6610250 # Total ticks spent queuing +system.physmem.totMemAccLat 16191500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2555000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12935.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31848.44 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1097.75 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31685.91 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1102.13 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1097.75 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1102.13 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 8.58 # Data bus utilization in percentage -system.physmem.busUtilRead 8.58 # Data bus utilization in percentage for reads +system.physmem.busUtil 8.61 # Data bus utilization in percentage +system.physmem.busUtilRead 8.61 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 424 # Number of row buffer hits during reads +system.physmem.readRowHits 422 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.65 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 58239.77 # Average gap between requests -system.physmem.pageHitRate 82.65 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 357000 # Energy for activate commands per rank (pJ) +system.physmem.avgGap 58007.83 # Average gap between requests +system.physmem.pageHitRate 82.58 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 364140 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 174570 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2199120 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 2184840 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3644010 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 3606960 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 63360 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 9899190 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 16800 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actPowerDownEnergy 9847320 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 18197970 # Total energy per rank (pJ) -system.physmem_0.averagePower 608.449701 # Core power per rank (mW) -system.physmem_0.totalIdleTime 21617000 # Total Idle time Per DRAM Rank +system.physmem_0.totalEnergy 18086550 # Total energy per rank (pJ) +system.physmem_0.averagePower 609.513459 # Core power per rank (mW) +system.physmem_0.totalIdleTime 21469250 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 44000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7338500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 21705500 # Time in different power states -system.physmem_1.actEnergy 278460 # Energy for activate commands per rank (pJ) +system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7251250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 21598000 # Time in different power states +system.physmem_1.actEnergy 271320 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 121440 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1463700 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2521680 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 86880 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 10427010 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 493920 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 2504580 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 86400 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10184760 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 622560 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 17237010 # Total energy per rank (pJ) -system.physmem_1.averagePower 576.319973 # Core power per rank (mW) -system.physmem_1.totalIdleTime 24154250 # Total Idle time Per DRAM Rank +system.physmem_1.totalEnergy 17098680 # Total energy per rank (pJ) +system.physmem_1.averagePower 576.222419 # Core power per rank (mW) +system.physmem_1.totalIdleTime 23952750 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 143000 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1286000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 4831250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 22868250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 12304 # Number of BP lookups -system.cpu.branchPred.condPredicted 7429 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1435 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9156 # Number of BTB lookups +system.physmem_1.memoryStateTime::PRE_PDN 1619750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 4797750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 22333000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 11901 # Number of BP lookups +system.cpu.branchPred.condPredicted 7287 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1354 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9352 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 730 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 685 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 9156 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 1824 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 7332 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 865 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 9352 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 1949 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 7403 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 793 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 29908500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 59818 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 29673500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 59348 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15502 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 57440 # Number of instructions fetch has processed -system.cpu.fetch.Branches 12304 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2554 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 17524 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3065 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1117 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 15163 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 55604 # Number of instructions fetch has processed +system.cpu.fetch.Branches 11901 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2634 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 17364 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2905 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 12 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1168 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 7446 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 730 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 35692 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.609324 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.874327 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 7191 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 701 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 35180 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.580557 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.839184 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 23194 64.98% 64.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4479 12.55% 77.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 496 1.39% 78.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 441 1.24% 80.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 761 2.13% 82.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 680 1.91% 84.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 284 0.80% 84.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 358 1.00% 85.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4999 14.01% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 22867 65.00% 65.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4490 12.76% 77.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 508 1.44% 79.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 450 1.28% 80.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 761 2.16% 82.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 731 2.08% 84.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 296 0.84% 85.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 343 0.97% 86.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4734 13.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 35692 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.205691 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.960246 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12333 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 13299 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 7732 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 796 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1532 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 41071 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1532 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13082 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2036 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9748 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 7750 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1544 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 36233 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full +system.cpu.fetch.rateDist::total 35180 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.200529 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.936914 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12094 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 13233 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 7639 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 762 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1452 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 39805 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1452 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 12828 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1813 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9904 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 7640 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1543 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 35279 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full system.cpu.rename.SQFullEvents 1128 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 31392 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 65112 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 53717 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 30611 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 63420 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 52396 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 17573 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 793 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 793 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4281 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 4496 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2885 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 16792 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 761 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 767 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4154 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 4391 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2803 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 28450 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 744 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 25030 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 14758 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 11000 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 269 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 35692 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.701278 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.501683 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 27854 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 724 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 24627 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 122 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 14142 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 10452 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 249 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 35180 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.700028 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.493682 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 26611 74.56% 74.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3173 8.89% 83.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1585 4.44% 87.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1525 4.27% 92.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1196 3.35% 95.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 748 2.10% 97.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 484 1.36% 98.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 276 0.77% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 94 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 26218 74.53% 74.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3125 8.88% 83.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1567 4.45% 87.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1507 4.28% 92.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1190 3.38% 95.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 757 2.15% 97.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 486 1.38% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 254 0.72% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 76 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 35692 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 35180 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 164 53.07% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 53 17.15% 70.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 92 29.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 151 52.07% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 51 17.59% 69.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 88 30.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 18344 73.29% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.29% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 4185 16.72% 90.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2501 9.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 18085 73.44% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 4096 16.63% 90.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2446 9.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 25030 # Type of FU issued -system.cpu.iq.rate 0.418436 # Inst issue rate -system.cpu.iq.fu_busy_cnt 309 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012345 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 86193 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 43979 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 22369 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 24627 # Type of FU issued +system.cpu.iq.rate 0.414959 # Inst issue rate +system.cpu.iq.fu_busy_cnt 290 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011776 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 84846 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 42748 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 22066 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 25339 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 24917 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2271 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 2166 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1437 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1355 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1532 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2073 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 30726 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 235 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 4496 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2885 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 744 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 1452 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1841 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 30085 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 231 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 4391 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2803 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 724 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 207 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1574 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1781 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 23432 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3882 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1598 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 209 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1460 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1669 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 23080 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3816 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1547 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1532 # number of nop insts executed -system.cpu.iew.exec_refs 6190 # number of memory reference insts executed -system.cpu.iew.exec_branches 4984 # Number of branches executed -system.cpu.iew.exec_stores 2308 # Number of stores executed -system.cpu.iew.exec_rate 0.391722 # Inst execution rate -system.cpu.iew.wb_sent 22840 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 22369 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10409 # num instructions producing a value -system.cpu.iew.wb_consumers 13648 # num instructions consuming a value -system.cpu.iew.wb_rate 0.373951 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762676 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 15475 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1507 # number of nop insts executed +system.cpu.iew.exec_refs 6070 # number of memory reference insts executed +system.cpu.iew.exec_branches 4884 # Number of branches executed +system.cpu.iew.exec_stores 2254 # Number of stores executed +system.cpu.iew.exec_rate 0.388893 # Inst execution rate +system.cpu.iew.wb_sent 22529 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 22066 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10367 # num instructions producing a value +system.cpu.iew.wb_consumers 13651 # num instructions consuming a value +system.cpu.iew.wb_rate 0.371807 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.759432 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 14855 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1435 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 32615 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.464878 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.257144 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1354 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 32262 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.469965 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.260994 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 25974 79.64% 79.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3555 10.90% 90.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1191 3.65% 94.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 577 1.77% 95.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 319 0.98% 96.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 311 0.95% 97.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 392 1.20% 99.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 57 0.17% 99.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 239 0.73% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 25609 79.38% 79.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3577 11.09% 90.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1157 3.59% 94.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 603 1.87% 95.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 332 1.03% 96.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 298 0.92% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 393 1.22% 99.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 58 0.18% 99.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 235 0.73% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 32615 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 32262 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -559,104 +560,104 @@ system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 15162 # Class of committed instruction -system.cpu.commit.bw_lim_events 239 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 62190 # The number of ROB reads -system.cpu.rob.rob_writes 64431 # The number of ROB writes +system.cpu.commit.bw_lim_events 235 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 61221 # The number of ROB reads +system.cpu.rob.rob_writes 63021 # The number of ROB writes system.cpu.timesIdled 194 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24126 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 24168 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 4.143669 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.143669 # CPI: Total CPI of All Threads -system.cpu.ipc 0.241332 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.241332 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 36473 # number of integer regfile reads -system.cpu.int_regfile_writes 20293 # number of integer regfile writes -system.cpu.misc_regfile_reads 8093 # number of misc regfile reads +system.cpu.cpi 4.111111 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.111111 # CPI: Total CPI of All Threads +system.cpu.ipc 0.243243 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.243243 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 36173 # number of integer regfile reads +system.cpu.int_regfile_writes 20126 # number of integer regfile writes +system.cpu.misc_regfile_reads 7956 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 99.156027 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4579 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 98.931439 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4528 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 31.363014 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 31.013699 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 99.156027 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024208 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024208 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 98.931439 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024153 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024153 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 10412 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 10412 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 3540 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3540 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 10292 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 10292 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 3489 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3489 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4573 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4573 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4573 # number of overall hits -system.cpu.dcache.overall_hits::total 4573 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 145 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 145 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 4522 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4522 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4522 # number of overall hits +system.cpu.dcache.overall_hits::total 4522 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 554 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 554 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 554 # number of overall misses -system.cpu.dcache.overall_misses::total 554 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11443500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11443500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 29003985 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 29003985 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 40447485 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 40447485 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 40447485 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 40447485 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3685 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3685 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 545 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 545 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 545 # number of overall misses +system.cpu.dcache.overall_misses::total 545 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10734500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10734500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 29028485 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 29028485 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39762985 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39762985 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39762985 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39762985 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3625 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3625 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5127 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5127 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5127 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5127 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039349 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.039349 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 5067 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5067 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5067 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5067 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037517 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.037517 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.108055 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.108055 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.108055 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.108055 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78920.689655 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 78920.689655 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70914.388753 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70914.388753 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73009.900722 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73009.900722 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73009.900722 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73009.900722 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.107559 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.107559 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.107559 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.107559 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78930.147059 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 78930.147059 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70974.290954 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70974.290954 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72959.605505 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72959.605505 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72959.605505 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72959.605505 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 1437 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 75.631579 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 71 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 406 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 406 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 406 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 406 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 397 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 397 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 397 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 397 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses @@ -665,138 +666,138 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 148 system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6078000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6078000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6888000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6888000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12966000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12966000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12966000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12966000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017639 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017639 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6080000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6080000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6906500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6906500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12986500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12986500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12986500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12986500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017931 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017931 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028867 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028867 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028867 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028867 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93507.692308 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93507.692308 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82987.951807 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82987.951807 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87608.108108 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 87608.108108 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87608.108108 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 87608.108108 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029209 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029209 # 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average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 204.744610 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 6856 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.681199 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 202.053622 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 6606 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.098630 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 204.744610 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.099973 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.099973 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.179199 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 15259 # Number of tag accesses -system.cpu.icache.tags.data_accesses 15259 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 6856 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6856 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 6856 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6856 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 6856 # number of overall hits -system.cpu.icache.overall_hits::total 6856 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 590 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 590 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 590 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 590 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 590 # number of overall misses -system.cpu.icache.overall_misses::total 590 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 45890500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 45890500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 45890500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 45890500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 45890500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 45890500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 7446 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 7446 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 7446 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 7446 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 7446 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 7446 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.079237 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.079237 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.079237 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.079237 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.079237 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.079237 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77780.508475 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77780.508475 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77780.508475 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77780.508475 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77780.508475 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77780.508475 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 123 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 202.053622 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.098659 # 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number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 123 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 223 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 223 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 223 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 223 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 367 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 367 # 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mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.049288 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.049288 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82440.054496 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82440.054496 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82440.054496 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 82440.054496 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82440.054496 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 82440.054496 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 220 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 220 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 220 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 220 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 220 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 220 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29981500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 29981500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29981500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 29981500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29981500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 29981500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050758 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050758 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050758 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.050758 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050758 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.050758 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82141.095890 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82141.095890 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82141.095890 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 82141.095890 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82141.095890 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 82141.095890 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # 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Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.009256 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.015594 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4631 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4631 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::cpu.inst 201.414921 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 98.983101 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006147 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.003021 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.009167 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.015533 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4613 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4613 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -805,64 +806,64 @@ system.cpu.l2cache.overall_hits::cpu.inst 2 # n system.cpu.l2cache.overall_hits::total 2 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 365 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 365 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 363 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 65 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 65 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 365 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 363 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 513 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 365 # number of overall misses +system.cpu.l2cache.demand_misses::total 511 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses -system.cpu.l2cache.overall_misses::total 513 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6762500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6762500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29682000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 29682000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5983000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5983000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 29682000 # 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number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 365 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 365 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 367 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 365 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 515 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 367 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 513 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 365 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 515 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 513 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994550 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994550 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994521 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994521 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994550 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994521 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.996117 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994550 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.996101 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994521 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.996117 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81475.903614 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81475.903614 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81320.547945 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81320.547945 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92046.153846 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92046.153846 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81320.547945 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86118.243243 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82704.678363 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81320.547945 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86118.243243 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82704.678363 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.996101 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81698.795181 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81698.795181 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81022.038567 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81022.038567 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92076.923077 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92076.923077 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81022.038567 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86256.756757 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82538.160470 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81022.038567 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86256.756757 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82538.160470 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -871,119 +872,119 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 365 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 365 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 513 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 511 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 513 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5932500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5932500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26032000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26032000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5353000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5353000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26032000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11285500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 37317500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26032000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11285500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 37317500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 511 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5951000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5951000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25781000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25781000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5355000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5355000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25781000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11306000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 37087000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25781000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11306000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 37087000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994550 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994521 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.996117 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.996101 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.996117 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71475.903614 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71475.903614 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71320.547945 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71320.547945 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82353.846154 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82353.846154 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71320.547945 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76253.378378 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72743.664717 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71320.547945 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76253.378378 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72743.664717 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 515 # Total number of requests made to the snoop filter. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.996101 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71698.795181 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71698.795181 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71022.038567 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71022.038567 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82384.615385 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82384.615385 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71022.038567 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76391.891892 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72577.299413 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71022.038567 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76391.891892 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72577.299413 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 430 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 367 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 734 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1028 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1024 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 32832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 32704 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 515 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.003883 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.062257 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 513 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.003899 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.062378 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 513 99.61% 99.61% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 511 99.61% 99.61% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 2 0.39% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 515 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 257500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 513 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 256500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 550500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 547500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 428 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 426 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution system.membus.trans_dist::ReadExResp 83 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1024 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 32704 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 428 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1020 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1020 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 32576 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 513 # Request fanout histogram +system.membus.snoop_fanout::samples 511 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 513 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 511 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 513 # Request fanout histogram -system.membus.reqLayer0.occupancy 627500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 511 # Request fanout histogram +system.membus.reqLayer0.occupancy 623500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2707250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2697250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 9.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index e575d4b01..53a74ff2b 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,93 +1,93 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000126 # Number of seconds simulated -sim_ticks 125996000 # Number of ticks simulated -final_tick 125996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000124 # Number of seconds simulated +sim_ticks 123756000 # Number of ticks simulated +final_tick 123756000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 220398 # Simulator instruction rate (inst/s) -host_op_rate 220398 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23837880 # Simulator tick rate (ticks/s) -host_mem_usage 265580 # Number of bytes of host memory used -host_seconds 5.29 # Real time elapsed on the host -sim_insts 1164916 # Number of instructions simulated -sim_ops 1164916 # Number of ops (including micro ops) simulated +host_inst_rate 286843 # Simulator instruction rate (inst/s) +host_op_rate 286842 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31050897 # Simulator tick rate (ticks/s) +host_mem_usage 266468 # Number of bytes of host memory used +host_seconds 3.99 # Real time elapsed on the host +sim_insts 1143228 # Number of instructions simulated +sim_ops 1143228 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 23872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 10880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5888 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 23616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 6016 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 768 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 45440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 23872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 31296 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 373 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 170 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 92 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu3.inst 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 896 # Number of bytes read from this memory +system.physmem.bytes_read::total 45248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 23616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 6016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 31232 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 369 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 94 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 12 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 710 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 189466332 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 86351948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 46731642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11174958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 7111337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7111337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 5079526 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7619290 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 360646370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 189466332 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 46731642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 7111337 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 5079526 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 248388838 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 189466332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 86351948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 46731642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11174958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 7111337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7111337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 5079526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7619290 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 360646370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 710 # Number of read requests accepted +system.physmem.num_reads::cpu3.inst 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 14 # Number of read requests responded to by this memory +system.physmem.num_reads::total 707 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 190827111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 87397783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 48611784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11377226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 6205760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7240053 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 6722906 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7240053 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 365622677 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 190827111 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 48611784 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 6205760 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 6722906 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 252367562 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 190827111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 87397783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 48611784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11377226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 6205760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7240053 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 6722906 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7240053 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 365622677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 707 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 710 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 707 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 45440 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 45248 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 45440 # Total read bytes from the system interface side +system.physmem.bytesReadSys 45248 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 120 # Per bank write bursts -system.physmem.perBankRdBursts::1 44 # Per bank write bursts -system.physmem.perBankRdBursts::2 31 # Per bank write bursts -system.physmem.perBankRdBursts::3 62 # Per bank write bursts +system.physmem.perBankRdBursts::0 118 # Per bank write bursts +system.physmem.perBankRdBursts::1 45 # Per bank write bursts +system.physmem.perBankRdBursts::2 32 # Per bank write bursts +system.physmem.perBankRdBursts::3 63 # Per bank write bursts system.physmem.perBankRdBursts::4 69 # Per bank write bursts -system.physmem.perBankRdBursts::5 28 # Per bank write bursts +system.physmem.perBankRdBursts::5 27 # Per bank write bursts system.physmem.perBankRdBursts::6 19 # Per bank write bursts system.physmem.perBankRdBursts::7 27 # Per bank write bursts system.physmem.perBankRdBursts::8 7 # Per bank write bursts -system.physmem.perBankRdBursts::9 31 # Per bank write bursts +system.physmem.perBankRdBursts::9 29 # Per bank write bursts system.physmem.perBankRdBursts::10 23 # Per bank write bursts system.physmem.perBankRdBursts::11 13 # Per bank write bursts system.physmem.perBankRdBursts::12 70 # Per bank write bursts system.physmem.perBankRdBursts::13 47 # Per bank write bursts system.physmem.perBankRdBursts::14 18 # Per bank write bursts -system.physmem.perBankRdBursts::15 101 # Per bank write bursts +system.physmem.perBankRdBursts::15 100 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -106,14 +106,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 125756000 # Total gap between requests +system.physmem.totGap 123516000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 710 # Read request sizes (log2) +system.physmem.readPktSize::6 707 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -121,10 +121,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 412 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 215 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -217,476 +217,473 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 174 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 244.597701 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 161.475219 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 245.687167 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 66 37.93% 37.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43 24.71% 62.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 29 16.67% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 11 6.32% 85.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 3.45% 89.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8 4.60% 93.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 2.30% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 0.57% 96.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 3.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 174 # Bytes accessed per row activation -system.physmem.totQLat 13059500 # Total ticks spent queuing -system.physmem.totMemAccLat 26372000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18393.66 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 169 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 251.834320 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 169.411435 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 244.318432 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 58 34.32% 34.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 48 28.40% 62.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 26 15.38% 78.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12 7.10% 85.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 4.14% 89.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7 4.14% 93.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 2.37% 95.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.59% 96.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 3.55% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 169 # Bytes accessed per row activation +system.physmem.totQLat 11450750 # Total ticks spent queuing +system.physmem.totMemAccLat 24707000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3535000 # Total ticks spent in databus transfers +system.physmem.avgQLat 16196.25 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37143.66 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 360.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 34946.25 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 365.62 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 360.65 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 365.62 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.82 # Data bus utilization in percentage -system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads +system.physmem.busUtil 2.86 # Data bus utilization in percentage +system.physmem.busUtilRead 2.86 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.29 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 525 # Number of row buffer hits during reads +system.physmem.readRowHits 529 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.94 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.82 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 177121.13 # Average gap between requests -system.physmem.pageHitRate 73.94 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 856800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 432630 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 174704.38 # Average gap between requests +system.physmem.pageHitRate 74.82 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 835380 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 428835 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2856000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6114390 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 284160 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 31286160 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8898240 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 5367840 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 64701180 # Total energy per rank (pJ) -system.physmem_0.averagePower 513.516712 # Core power per rank (mW) -system.physmem_0.totalIdleTime 111273500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 346500 # Time in different power states -system.physmem_0.memoryStateTime::REF 3646000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 20064750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 23172500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 10159750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 68606500 # Time in different power states -system.physmem_1.actEnergy 464100 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 227700 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2213400 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 9219600.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6260880 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 309600 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 30851820 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 11364960 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 3424140 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 65551215 # Total energy per rank (pJ) +system.physmem_0.averagePower 529.680036 # Core power per rank (mW) +system.physmem_0.totalIdleTime 108655750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 358500 # Time in different power states +system.physmem_0.memoryStateTime::REF 3906000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 11965500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 29593750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 10265500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 67666750 # Time in different power states +system.physmem_1.actEnergy 435540 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 212520 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2191980 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4959000 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 596640 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 28649910 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 9231840 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 7511880 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 62459430 # Total energy per rank (pJ) -system.physmem_1.averagePower 495.724516 # Core power per rank (mW) -system.physmem_1.totalIdleTime 113374250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1113500 # Time in different power states -system.physmem_1.memoryStateTime::REF 3652000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 26697750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 24040500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7662500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 62829750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu0.branchPred.lookups 99694 # Number of BP lookups -system.cpu0.branchPred.condPredicted 94929 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1689 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 96632 # Number of BTB lookups +system.physmem_1.refreshEnergy 7375680.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4628970 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 469440 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 25813590 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 8390400 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 8693940 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 58212060 # Total energy per rank (pJ) +system.physmem_1.averagePower 470.376728 # Core power per rank (mW) +system.physmem_1.totalIdleTime 112190500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 843500 # Time in different power states +system.physmem_1.memoryStateTime::REF 3126000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 33923000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 21849000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7402250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 56612250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu0.branchPred.lookups 96945 # Number of BP lookups +system.cpu0.branchPred.condPredicted 92664 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1460 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 94281 # Number of BTB lookups system.cpu0.branchPred.BTBHits 0 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu0.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 1210 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.usedRAS 1072 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 96632 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 88884 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 7748 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 1163 # Number of mispredicted indirect branches. +system.cpu0.branchPred.indirectLookups 94281 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 87442 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 6839 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 944 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.pwrStateResidencyTicks::ON 125996000 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 251993 # number of cpu cycles simulated +system.cpu0.pwrStateResidencyTicks::ON 123756000 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 247513 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 23206 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 587602 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 99694 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 90094 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 195641 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3677 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 78 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 2245 # Number of stall cycles due to pending traps -system.cpu0.fetch.IcacheWaitRetryStallCycles 21 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8355 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 903 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 223034 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.634585 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.272061 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 22810 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 572402 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 96945 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 88514 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 191239 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3219 # Number of cycles fetch has spent squashing +system.cpu0.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 2152 # Number of stall cycles due to pending traps +system.cpu0.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7601 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 796 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 217827 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.627783 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.257744 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34543 15.49% 15.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 92075 41.28% 56.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 690 0.31% 57.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1016 0.46% 57.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 496 0.22% 57.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 87579 39.27% 97.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 656 0.29% 97.32% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 548 0.25% 97.56% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5431 2.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33416 15.34% 15.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 90280 41.45% 56.79% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 662 0.30% 57.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1022 0.47% 57.56% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 476 0.22% 57.78% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 86076 39.52% 97.29% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 627 0.29% 97.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 458 0.21% 97.79% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4810 2.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 223034 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.395622 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.331819 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18204 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 19474 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 182674 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 844 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1838 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 568807 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 1838 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18897 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2138 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 15951 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 182807 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1403 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 563480 # Number of instructions processed by rename -system.cpu0.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full +system.cpu0.fetch.rateDist::total 217827 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.391676 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.312614 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17128 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 19348 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 178981 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 761 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1609 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 555305 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 1609 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17781 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 1772 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 16195 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 179089 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1381 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 550438 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full system.cpu0.rename.SQFullEvents 925 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 385856 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1122771 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 848321 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 8 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 365359 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 20497 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1128 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1160 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5339 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 179490 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 90635 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 87474 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 87162 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 469651 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1149 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 465284 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 130 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 17670 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 14278 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 590 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 223034 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.086157 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.115238 # Number of insts issued each cycle +system.cpu0.rename.RenamedOperands 376177 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1097223 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 828510 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 359139 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 17038 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1047 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1085 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5185 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 175971 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 88955 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 85967 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 85657 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 459427 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1094 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 455664 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 95 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 15166 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 12611 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 535 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 217827 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.091862 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.108022 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 37655 16.88% 16.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4554 2.04% 18.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 88787 39.81% 58.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 88368 39.62% 98.35% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1704 0.76% 99.12% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1021 0.46% 99.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 603 0.27% 99.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 223 0.10% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 119 0.05% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 36217 16.63% 16.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4343 1.99% 18.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 87095 39.98% 58.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 86709 39.81% 98.41% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1627 0.75% 99.16% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 960 0.44% 99.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 547 0.25% 99.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 218 0.10% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 111 0.05% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 223034 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 217827 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 140 40.46% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMisc 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 83 23.99% 64.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 123 35.55% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 123 36.94% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMisc 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 36.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 85 25.53% 62.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 125 37.54% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 196646 42.26% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.26% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 178800 38.43% 80.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 89838 19.31% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 192140 42.17% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.17% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 175355 38.48% 80.65% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 88169 19.35% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 465284 # Type of FU issued -system.cpu0.iq.rate 1.846416 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 346 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000744 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1154078 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 488506 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 462560 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 455664 # Type of FU issued +system.cpu0.iq.rate 1.840970 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 333 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000731 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1129583 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 475739 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 453318 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 465630 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 455997 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 86875 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 85314 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 3221 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2812 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1994 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedStores 1869 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1838 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 2137 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 558923 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 171 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 179490 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 90635 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1033 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 30 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1609 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1760 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 31 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 547045 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 114 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 175971 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 88955 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 969 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 218 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1860 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 2078 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 463731 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 178412 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1553 # Number of squashed instructions skipped in execute +system.cpu0.iew.predictedTakenIncorrect 211 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1555 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1766 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 454327 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 175012 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1337 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 88123 # number of nop insts executed -system.cpu0.iew.exec_refs 268032 # number of memory reference insts executed -system.cpu0.iew.exec_branches 92124 # Number of branches executed -system.cpu0.iew.exec_stores 89620 # Number of stores executed -system.cpu0.iew.exec_rate 1.840253 # Inst execution rate -system.cpu0.iew.wb_sent 463047 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 462560 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 274104 # num instructions producing a value -system.cpu0.iew.wb_consumers 277790 # num instructions consuming a value -system.cpu0.iew.wb_rate 1.835607 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.986731 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 18452 # The number of squashed insts skipped by commit +system.cpu0.iew.exec_nop 86524 # number of nop insts executed +system.cpu0.iew.exec_refs 262985 # number of memory reference insts executed +system.cpu0.iew.exec_branches 90247 # Number of branches executed +system.cpu0.iew.exec_stores 87973 # Number of stores executed +system.cpu0.iew.exec_rate 1.835568 # Inst execution rate +system.cpu0.iew.wb_sent 453748 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 453318 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 268984 # num instructions producing a value +system.cpu0.iew.wb_consumers 272473 # num instructions consuming a value +system.cpu0.iew.wb_rate 1.831492 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.987195 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 15911 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1689 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 219410 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.462923 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.143392 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1460 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 214699 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.473509 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.143772 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 37598 17.14% 17.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 90827 41.40% 58.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2058 0.94% 59.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 592 0.27% 59.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 460 0.21% 59.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 86620 39.48% 99.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 500 0.23% 99.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 309 0.14% 99.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 446 0.20% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 36174 16.85% 16.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 89113 41.51% 58.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1996 0.93% 59.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 609 0.28% 59.57% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 464 0.22% 59.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 85076 39.63% 99.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 476 0.22% 99.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 292 0.14% 99.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 499 0.23% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 219410 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 540390 # Number of instructions committed -system.cpu0.commit.committedOps 540390 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 214699 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 531060 # Number of instructions committed +system.cpu0.commit.committedOps 531060 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 264910 # Number of memory references committed -system.cpu0.commit.loads 176269 # Number of loads committed +system.cpu0.commit.refs 260245 # Number of memory references committed +system.cpu0.commit.loads 173159 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 90528 # Number of branches committed +system.cpu0.commit.branches 88973 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 363690 # Number of committed integer instructions. +system.cpu0.commit.int_insts 357470 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 87260 16.15% 16.15% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 188136 34.81% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.96% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 176353 32.63% 83.60% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 88641 16.40% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 85705 16.14% 16.14% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 185026 34.84% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.98% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 173243 32.62% 83.60% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 87086 16.40% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 540390 # Class of committed instruction -system.cpu0.commit.bw_lim_events 446 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 776645 # The number of ROB reads -system.cpu0.rob.rob_writes 1121369 # The number of ROB writes -system.cpu0.timesIdled 318 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 28959 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 453046 # Number of Instructions Simulated -system.cpu0.committedOps 453046 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.556219 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.556219 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.797852 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.797852 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 828824 # number of integer regfile reads -system.cpu0.int_regfile_writes 373673 # number of integer regfile writes +system.cpu0.commit.op_class_0::total 531060 # Class of committed instruction +system.cpu0.commit.bw_lim_events 499 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 760010 # The number of ROB reads +system.cpu0.rob.rob_writes 1097116 # The number of ROB writes +system.cpu0.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 29686 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 445271 # Number of Instructions Simulated +system.cpu0.committedOps 445271 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.555870 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.555870 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.798980 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.798980 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 812559 # number of integer regfile reads +system.cpu0.int_regfile_writes 366073 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 270178 # number of misc regfile reads +system.cpu0.misc_regfile_reads 265038 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 142.283862 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 178830 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 172 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 1039.709302 # Average number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 142.111163 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 175455 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 1026.052632 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.283862 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277898 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.277898 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 170 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.111163 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277561 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.277561 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.332031 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 720603 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 720603 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 90862 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 90862 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 88053 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 88053 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 24 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 24 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 178915 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 178915 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 178915 # number of overall hits -system.cpu0.dcache.overall_hits::total 178915 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 568 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 568 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 546 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 546 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 18 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 18 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1114 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1114 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1114 # number of overall misses -system.cpu0.dcache.overall_misses::total 1114 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16630000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 16630000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35665989 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 35665989 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 490500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 490500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 52295989 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 52295989 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 52295989 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 52295989 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 91430 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 91430 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 88599 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 88599 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 707079 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 707079 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 89048 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 89048 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 86492 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 86492 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 18 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 18 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 175540 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 175540 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 175540 # number of overall hits +system.cpu0.dcache.overall_hits::total 175540 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 556 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 556 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 552 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 552 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 24 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 24 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1108 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1108 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1108 # number of overall misses +system.cpu0.dcache.overall_misses::total 1108 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15680500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 15680500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35675489 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 35675489 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 524500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 524500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 51355989 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 51355989 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 51355989 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 51355989 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 89604 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 89604 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 87044 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 87044 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 180029 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 180029 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 180029 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 180029 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006212 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006212 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006163 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.006163 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.428571 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.428571 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006188 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006188 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006188 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006188 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29278.169014 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 29278.169014 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65322.324176 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 65322.324176 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 27250 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 27250 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46944.334829 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 46944.334829 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46944.334829 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 46944.334829 # average overall miss latency +system.cpu0.dcache.demand_accesses::cpu0.data 176648 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 176648 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 176648 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 176648 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006205 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006205 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006342 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006342 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.571429 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.571429 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006272 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006272 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006272 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006272 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28202.338129 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28202.338129 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64629.509058 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 64629.509058 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 21854.166667 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 21854.166667 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46350.170578 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 46350.170578 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46350.170578 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 46350.170578 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 885 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked @@ -695,2236 +692,2231 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs 42.142857 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 370 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 370 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 375 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 375 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 745 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 745 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 745 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 745 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 198 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 198 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 171 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 171 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 18 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 18 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 369 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 369 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 369 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 369 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 7613500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7613500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8176500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8176500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 472500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 472500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15790000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15790000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15790000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15790000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002166 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002166 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.001930 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.001930 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.428571 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002050 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002050 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002050 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002050 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 38452.020202 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 38452.020202 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47815.789474 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47815.789474 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26250 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26250 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42791.327913 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42791.327913 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42791.327913 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42791.327913 # average overall mshr miss latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 391 # number of replacements -system.cpu0.icache.tags.tagsinuse 249.990139 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7433 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 696 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.679598 # Average number of references to valid blocks. +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 364 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 364 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 379 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 379 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 743 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 743 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 743 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 743 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 192 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 192 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 173 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 173 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 24 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 24 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 365 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 365 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 365 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 7301500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7301500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8155500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8155500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 500500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 500500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15457000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15457000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15457000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15457000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002143 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002143 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.001988 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.001988 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.571429 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.571429 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002066 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002066 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002066 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002066 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 38028.645833 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 38028.645833 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47141.618497 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47141.618497 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 20854.166667 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 20854.166667 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42347.945205 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42347.945205 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42347.945205 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42347.945205 # average overall mshr miss latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 381 # number of replacements +system.cpu0.icache.tags.tagsinuse 247.076486 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6698 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 681 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.835536 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 249.990139 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.488262 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.488262 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 305 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 44 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.595703 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9051 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9051 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 7433 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7433 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7433 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7433 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7433 # number of overall hits -system.cpu0.icache.overall_hits::total 7433 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 922 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 922 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 922 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 922 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 922 # number of overall misses -system.cpu0.icache.overall_misses::total 922 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 48154500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 48154500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 48154500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 48154500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 48154500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 48154500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8355 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8355 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8355 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8355 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8355 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8355 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110353 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.110353 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110353 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.110353 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110353 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.110353 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 52228.308026 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 52228.308026 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 52228.308026 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 52228.308026 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 52228.308026 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 52228.308026 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 401 # number of cycles access was blocked +system.cpu0.icache.tags.occ_blocks::cpu0.inst 247.076486 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.482571 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.482571 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 300 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 177 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.585938 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 8282 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 8282 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 6698 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6698 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6698 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6698 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6698 # number of overall hits +system.cpu0.icache.overall_hits::total 6698 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 903 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 903 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 903 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 903 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 903 # number of overall misses +system.cpu0.icache.overall_misses::total 903 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 46390500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 46390500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 46390500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 46390500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 46390500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 46390500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7601 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7601 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7601 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7601 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7601 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7601 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118800 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.118800 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118800 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.118800 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118800 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.118800 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51373.754153 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 51373.754153 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51373.754153 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 51373.754153 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51373.754153 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 51373.754153 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 84 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 50.125000 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 28 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 391 # number of writebacks -system.cpu0.icache.writebacks::total 391 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 225 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 225 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 225 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 225 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 225 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 225 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 697 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 697 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 697 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 697 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 697 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 697 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 36741500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 36741500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 36741500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 36741500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 36741500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 36741500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.083423 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.083423 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.083423 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.083423 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.083423 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.083423 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 52713.773314 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 52713.773314 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 52713.773314 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 52713.773314 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 52713.773314 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 52713.773314 # average overall mshr miss latency -system.cpu1.branchPred.lookups 67120 # Number of BP lookups -system.cpu1.branchPred.condPredicted 59252 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 2530 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 59078 # Number of BTB lookups +system.cpu0.icache.writebacks::writebacks 381 # number of writebacks +system.cpu0.icache.writebacks::total 381 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 221 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 221 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 221 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 221 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 221 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 682 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 682 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 682 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 682 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 682 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 682 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 35207000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 35207000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 35207000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 35207000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 35207000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 35207000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.089725 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.089725 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.089725 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.089725 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.089725 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.089725 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51623.167155 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51623.167155 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51623.167155 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 51623.167155 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51623.167155 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 51623.167155 # average overall mshr miss latency +system.cpu1.branchPred.lookups 61334 # Number of BP lookups +system.cpu1.branchPred.condPredicted 54401 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 2004 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 54412 # Number of BTB lookups system.cpu1.branchPred.BTBHits 0 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu1.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 2033 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.usedRAS 1793 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 59078 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 48199 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 10879 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 1412 # Number of mispredicted indirect branches. -system.cpu1.pwrStateResidencyTicks::ON 125996000 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 194937 # number of cpu cycles simulated +system.cpu1.branchPred.indirectLookups 54412 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 44729 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 9683 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 984 # Number of mispredicted indirect branches. +system.cpu1.pwrStateResidencyTicks::ON 123756000 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 189559 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 38450 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 366689 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 67120 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 50232 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 144025 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 5215 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.icacheStallCycles 38670 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 332272 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 61334 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 46522 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 140422 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4165 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1847 # Number of stall cycles due to pending traps -system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 26490 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1009 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 186966 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.961260 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.371242 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.PendingTrapStallCycles 1456 # Number of stall cycles due to pending traps +system.cpu1.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 27652 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 879 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 182684 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.818835 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.303785 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 66801 35.73% 35.73% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 58781 31.44% 67.17% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 7398 3.96% 71.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3358 1.80% 72.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 642 0.34% 73.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 38588 20.64% 93.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1104 0.59% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1446 0.77% 95.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 8848 4.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 70336 38.50% 38.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 55803 30.55% 69.05% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 8540 4.67% 73.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3408 1.87% 75.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 651 0.36% 75.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 33906 18.56% 94.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 999 0.55% 95.05% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1291 0.71% 95.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 7750 4.24% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 186966 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.344316 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.881064 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 23546 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 62450 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 94215 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 4138 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2607 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 335701 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2607 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 24537 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 29865 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 13172 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 95090 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 21685 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 329147 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 18681 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full +system.cpu1.fetch.rateDist::total 182684 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.323562 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.752869 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21125 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 71097 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 83834 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 4536 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2082 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 303611 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2082 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22030 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 34668 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13321 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 84450 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 26123 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 298128 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 22342 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 231661 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 629076 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 489741 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 26 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 200931 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 30730 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1664 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1812 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 26977 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 90636 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 43093 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 42743 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 36583 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 268793 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 7661 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 268125 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 136 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 26316 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 21262 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 1168 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 186966 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.434084 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.397924 # Number of insts issued each cycle +system.cpu1.rename.RenamedOperands 207771 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 563979 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 439786 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 36 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 183614 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 24157 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1533 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1680 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 31315 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 81609 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 38032 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 39208 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 31953 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 243349 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 8714 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 245236 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 76 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 21657 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 16615 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 1128 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 182684 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.342405 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.387446 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 71753 38.38% 38.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 24944 13.34% 51.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 41684 22.29% 74.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 41301 22.09% 96.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3557 1.90% 98.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1804 0.96% 98.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1118 0.60% 99.57% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 486 0.26% 99.83% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 319 0.17% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 74656 40.87% 40.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 27751 15.19% 56.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 36635 20.05% 76.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 36634 20.05% 96.16% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3526 1.93% 98.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1704 0.93% 99.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1046 0.57% 99.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 443 0.24% 99.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 289 0.16% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 186966 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 182684 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 231 42.39% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMisc 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 42.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 72 13.21% 55.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 242 44.40% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 163 36.88% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMisc 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 36.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 52 11.76% 48.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 227 51.36% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 130845 48.80% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 95251 35.52% 84.32% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 42029 15.68% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 120474 49.13% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.13% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 87542 35.70% 84.82% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 37220 15.18% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 268125 # Type of FU issued -system.cpu1.iq.rate 1.375444 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 545 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.002033 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 723897 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 302756 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 263753 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 245236 # Type of FU issued +system.cpu1.iq.rate 1.293719 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 442 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001802 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 673674 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 273687 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 241932 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_writes 72 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 268670 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 245678 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 36498 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 31875 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4839 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 41 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 2826 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3921 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 28 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 2368 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2607 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 8495 # Number of cycles IEW is blocking +system.cpu1.iew.iewSquashCycles 2082 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 9074 # Number of cycles IEW is blocking system.cpu1.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 320469 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 297 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 90636 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 43093 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1513 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 32 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewDispatchedInsts 292335 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 184 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 81609 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 38032 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1451 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 472 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2728 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 3200 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 265301 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 88817 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2824 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 39 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 411 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2165 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 2576 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 243135 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 80226 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2101 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 44015 # number of nop insts executed -system.cpu1.iew.exec_refs 130506 # number of memory reference insts executed -system.cpu1.iew.exec_branches 54427 # Number of branches executed -system.cpu1.iew.exec_stores 41689 # Number of stores executed -system.cpu1.iew.exec_rate 1.360958 # Inst execution rate -system.cpu1.iew.wb_sent 264333 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 263753 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 148277 # num instructions producing a value -system.cpu1.iew.wb_consumers 156026 # num instructions consuming a value -system.cpu1.iew.wb_rate 1.353017 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.950335 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 27498 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 6493 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 2530 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 181716 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.612048 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.042470 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 40272 # number of nop insts executed +system.cpu1.iew.exec_refs 117151 # number of memory reference insts executed +system.cpu1.iew.exec_branches 50431 # Number of branches executed +system.cpu1.iew.exec_stores 36925 # Number of stores executed +system.cpu1.iew.exec_rate 1.282635 # Inst execution rate +system.cpu1.iew.wb_sent 242358 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 241932 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 135113 # num instructions producing a value +system.cpu1.iew.wb_consumers 142615 # num instructions consuming a value +system.cpu1.iew.wb_rate 1.276289 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.947397 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 22606 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 7586 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 2004 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 178491 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.510961 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.003537 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 77632 42.72% 42.72% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 50511 27.80% 70.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5466 3.01% 73.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 7144 3.93% 77.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1253 0.69% 78.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 36670 20.18% 98.33% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 792 0.44% 98.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1038 0.57% 99.33% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1210 0.67% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 81773 45.81% 45.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 46692 26.16% 71.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5286 2.96% 74.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 8258 4.63% 79.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1311 0.73% 80.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 32106 17.99% 98.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 812 0.45% 98.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1015 0.57% 99.31% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1238 0.69% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 181716 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 292935 # Number of instructions committed -system.cpu1.commit.committedOps 292935 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 178491 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 269693 # Number of instructions committed +system.cpu1.commit.committedOps 269693 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 126064 # Number of memory references committed -system.cpu1.commit.loads 85797 # Number of loads committed -system.cpu1.commit.membars 5779 # Number of memory barriers committed -system.cpu1.commit.branches 52007 # Number of branches committed +system.cpu1.commit.refs 113352 # Number of memory references committed +system.cpu1.commit.loads 77688 # Number of loads committed +system.cpu1.commit.membars 6874 # Number of memory barriers committed +system.cpu1.commit.branches 48495 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 200194 # Number of committed integer instructions. +system.cpu1.commit.int_insts 183974 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 42797 14.61% 14.61% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 118295 40.38% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.99% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 91576 31.26% 86.25% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 40267 13.75% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 39287 14.57% 14.57% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 110180 40.85% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.42% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 84562 31.35% 86.78% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 35664 13.22% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 292935 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1210 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 500353 # The number of ROB reads -system.cpu1.rob.rob_writes 646173 # The number of ROB writes -system.cpu1.timesIdled 229 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 7971 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 49399 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 244359 # Number of Instructions Simulated -system.cpu1.committedOps 244359 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.797748 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.797748 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.253528 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.253528 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 456218 # number of integer regfile reads -system.cpu1.int_regfile_writes 213064 # number of integer regfile writes +system.cpu1.commit.op_class_0::total 269693 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1238 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 468966 # The number of ROB reads +system.cpu1.rob.rob_writes 588835 # The number of ROB writes +system.cpu1.timesIdled 217 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 6875 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 49435 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 223532 # Number of Instructions Simulated +system.cpu1.committedOps 223532 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.848017 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.848017 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.179221 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.179221 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 414823 # number of integer regfile reads +system.cpu1.int_regfile_writes 193738 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 132445 # number of misc regfile reads +system.cpu1.misc_regfile_reads 118957 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 27.060700 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 47652 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 26.585143 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 42712 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 31 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1537.161290 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1377.806452 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.060700 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.052853 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.052853 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.585143 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051924 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.051924 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 31 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.060547 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 370474 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 370474 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 51817 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 51817 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 40051 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 40051 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 91868 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 91868 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 91868 # number of overall hits -system.cpu1.dcache.overall_hits::total 91868 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 471 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 471 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 148 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 148 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 54 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 54 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 619 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 619 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 619 # number of overall misses -system.cpu1.dcache.overall_misses::total 619 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4841500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 4841500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3638000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3638000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 309000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 309000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8479500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8479500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8479500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8479500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 52288 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 52288 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 40199 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 40199 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 92487 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 92487 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 92487 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 92487 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009008 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.009008 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003682 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003682 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.794118 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006693 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.006693 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006693 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.006693 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 10279.193206 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 10279.193206 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24581.081081 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 24581.081081 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 5722.222222 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 5722.222222 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13698.707593 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 13698.707593 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13698.707593 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 13698.707593 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 336213 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 336213 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 47868 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 47868 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 35447 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 35447 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 83315 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 83315 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 83315 # number of overall hits +system.cpu1.dcache.overall_hits::total 83315 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 458 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 458 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 151 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 151 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 50 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 50 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 609 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 609 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 609 # number of overall misses +system.cpu1.dcache.overall_misses::total 609 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4693000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4693000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3635500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3635500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 328500 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 328500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8328500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8328500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8328500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8328500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 48326 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 48326 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 35598 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 35598 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 66 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 83924 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 83924 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 83924 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 83924 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009477 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.009477 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004242 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004242 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.757576 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.757576 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007257 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.007257 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007257 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.007257 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 10246.724891 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 10246.724891 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24076.158940 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 24076.158940 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6570 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 6570 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13675.697865 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 13675.697865 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13675.697865 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 13675.697865 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 312 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 312 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 44 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 44 # number of WriteReq MSHR hits -system.cpu1.dcache.SwapReq_mshr_hits::cpu1.data 1 # number of SwapReq MSHR hits -system.cpu1.dcache.SwapReq_mshr_hits::total 1 # number of SwapReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 356 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 356 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 356 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 356 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 159 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 292 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 292 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 47 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 47 # number of WriteReq MSHR hits +system.cpu1.dcache.SwapReq_mshr_hits::cpu1.data 4 # number of SwapReq MSHR hits +system.cpu1.dcache.SwapReq_mshr_hits::total 4 # number of SwapReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 339 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 339 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 104 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 53 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1599000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1599000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1536000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1536000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 255000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 255000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3135000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3135000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3135000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3135000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003041 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003041 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002587 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002587 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.779412 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.779412 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002844 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.002844 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002844 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.002844 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10056.603774 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10056.603774 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14769.230769 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14769.230769 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 4811.320755 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 4811.320755 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11920.152091 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11920.152091 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11920.152091 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11920.152091 # average overall mshr miss latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 598 # number of replacements -system.cpu1.icache.tags.tagsinuse 99.304712 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 25606 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 733 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 34.933151 # Average number of references to valid blocks. +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 46 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 46 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1641000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1641000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1541000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1541000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 278500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 278500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3182000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3182000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3182000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3182000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003435 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003435 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002922 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002922 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.696970 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.696970 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003217 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003217 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003217 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003217 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9885.542169 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9885.542169 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14817.307692 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14817.307692 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6054.347826 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6054.347826 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11785.185185 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11785.185185 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11785.185185 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11785.185185 # average overall mshr miss latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 507 # number of replacements +system.cpu1.icache.tags.tagsinuse 97.467355 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 26848 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 643 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 41.754277 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 99.304712 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.193955 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.193955 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.263672 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 27223 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 27223 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 25606 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 25606 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 25606 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 25606 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 25606 # number of overall hits -system.cpu1.icache.overall_hits::total 25606 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 884 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 884 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 884 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 884 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 884 # number of overall misses -system.cpu1.icache.overall_misses::total 884 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 21315000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 21315000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 21315000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 21315000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 21315000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 21315000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 26490 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 26490 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 26490 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 26490 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 26490 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 26490 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033371 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.033371 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033371 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.033371 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033371 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.033371 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24111.990950 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 24111.990950 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24111.990950 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 24111.990950 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24111.990950 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 24111.990950 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 175 # number of cycles access was blocked +system.cpu1.icache.tags.occ_blocks::cpu1.inst 97.467355 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.190366 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.190366 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 136 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 114 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.265625 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 28295 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 28295 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 26848 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 26848 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 26848 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 26848 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 26848 # number of overall hits +system.cpu1.icache.overall_hits::total 26848 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 804 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 804 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 804 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 804 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 804 # number of overall misses +system.cpu1.icache.overall_misses::total 804 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 19785000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 19785000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 19785000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 19785000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 19785000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 19785000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 27652 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 27652 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 27652 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 27652 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 27652 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 27652 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029076 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.029076 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029076 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.029076 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029076 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.029076 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24608.208955 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 24608.208955 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24608.208955 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 24608.208955 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24608.208955 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 24608.208955 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 207 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 35 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 34.500000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 598 # number of writebacks -system.cpu1.icache.writebacks::total 598 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 151 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 151 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 151 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 151 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 151 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 151 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 733 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 733 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 733 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 733 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 733 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 16848000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 16848000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 16848000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 16848000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 16848000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 16848000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027671 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027671 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027671 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.027671 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027671 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.027671 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22984.993179 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22984.993179 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22984.993179 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 22984.993179 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22984.993179 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 22984.993179 # average overall mshr miss latency -system.cpu2.branchPred.lookups 65968 # Number of BP lookups -system.cpu2.branchPred.condPredicted 58235 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 2375 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 57871 # Number of BTB lookups +system.cpu1.icache.writebacks::writebacks 507 # number of writebacks +system.cpu1.icache.writebacks::total 507 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 161 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 161 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 161 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 161 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 161 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 161 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 643 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 643 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 643 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 643 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 643 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 15397000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 15397000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 15397000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 15397000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 15397000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 15397000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023253 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023253 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023253 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023253 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023253 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023253 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23945.567652 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23945.567652 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23945.567652 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 23945.567652 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23945.567652 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 23945.567652 # average overall mshr miss latency +system.cpu2.branchPred.lookups 68293 # Number of BP lookups +system.cpu2.branchPred.condPredicted 60753 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 2314 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 60518 # Number of BTB lookups system.cpu2.branchPred.BTBHits 0 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu2.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 1935 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.usedRAS 1899 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 57871 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 47609 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 10262 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 1269 # Number of mispredicted indirect branches. -system.cpu2.pwrStateResidencyTicks::ON 125996000 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 194536 # number of cpu cycles simulated +system.cpu2.branchPred.indirectLookups 60518 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 50086 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 10432 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 1220 # Number of mispredicted indirect branches. +system.cpu2.pwrStateResidencyTicks::ON 123756000 # Cumulative time (in ticks) in various power states +system.cpu2.numCycles 189148 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 39274 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 356927 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 65968 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 49544 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 148178 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 4907 # Number of cycles fetch has spent squashing -system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.icacheStallCycles 37019 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 374433 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 68293 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 51985 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 146261 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 4785 # Number of cycles fetch has spent squashing +system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1834 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 28474 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 909 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 191752 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.861399 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.326800 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.PendingTrapStallCycles 1657 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 25650 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 889 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 187354 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.998532 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.363195 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 72282 37.70% 37.70% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 59093 30.82% 68.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 8567 4.47% 72.98% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3453 1.80% 74.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 714 0.37% 75.15% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 36701 19.14% 94.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1094 0.57% 94.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 1368 0.71% 95.58% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 8480 4.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 64471 34.41% 34.41% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 60026 32.04% 66.45% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 7128 3.80% 70.25% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3545 1.89% 72.15% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 670 0.36% 72.50% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 40604 21.67% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1041 0.56% 94.73% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 1382 0.74% 95.47% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 8487 4.53% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 191752 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.339104 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.834761 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 22274 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 72146 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 90170 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4699 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2453 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 325978 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2453 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 23346 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 35274 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13410 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 90655 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 26604 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 319217 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 22687 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full +system.cpu2.fetch.rateDist::total 187354 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.361056 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.979577 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 21923 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 61377 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 97674 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 3978 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2392 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 343665 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2392 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 22954 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 28666 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13829 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 98633 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 20870 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 337053 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 18126 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 18 # Number of times rename has blocked due to LQ full system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 222060 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 604225 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 470469 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 26 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 194795 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 27265 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1650 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1793 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 32366 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 87706 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 41007 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 42125 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 34727 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 259651 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 8925 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 260809 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 82 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 24016 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 18768 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 1234 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 191752 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.360137 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.380681 # Number of insts issued each cycle +system.cpu2.rename.RenamedOperands 236414 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 645955 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 501894 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 22 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 208648 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 27766 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1626 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1738 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 26523 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 93867 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 44893 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 44587 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 38578 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 275945 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 7527 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 275850 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 71 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 23937 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 18592 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 1173 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 187354 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.472346 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.381832 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 77057 40.19% 40.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 28387 14.80% 54.99% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 39839 20.78% 75.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 39454 20.58% 96.34% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3531 1.84% 98.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1665 0.87% 99.05% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 1093 0.57% 99.62% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 433 0.23% 99.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 293 0.15% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 68951 36.80% 36.80% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 24397 13.02% 49.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 43633 23.29% 73.11% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 43435 23.18% 96.30% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3472 1.85% 98.15% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1779 0.95% 99.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 1003 0.54% 99.63% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 391 0.21% 99.84% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 293 0.16% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 191752 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 187354 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 214 43.32% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMultAcc 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMisc 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 43.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 44 8.91% 52.23% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 236 47.77% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 191 39.71% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMultAcc 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMisc 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 39.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 64 13.31% 53.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 226 46.99% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 127216 48.78% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMultAcc 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMisc 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.78% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 93561 35.87% 84.65% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 40032 15.35% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 133523 48.40% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMultAcc 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMisc 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.40% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 98433 35.68% 84.09% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 43894 15.91% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 260809 # Type of FU issued -system.cpu2.iq.rate 1.340672 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 494 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001894 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 713946 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 292577 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 257120 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 275850 # Type of FU issued +system.cpu2.iq.rate 1.458382 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 481 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001744 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 739606 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 307404 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 272120 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_writes 44 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 261303 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 276331 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 34638 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 38492 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 4387 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 24 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 2568 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 4293 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 47 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 2655 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2453 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 9291 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 312015 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 352 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 87706 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 41007 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1521 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2392 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 7918 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 329268 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 414 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 93867 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 44893 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1518 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 454 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 2525 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 2979 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 258429 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 86072 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 2380 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 39 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 443 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 2459 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 2902 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 273426 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 92301 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 2424 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 43439 # number of nop insts executed -system.cpu2.iew.exec_refs 125830 # number of memory reference insts executed -system.cpu2.iew.exec_branches 53606 # Number of branches executed -system.cpu2.iew.exec_stores 39758 # Number of stores executed -system.cpu2.iew.exec_rate 1.328438 # Inst execution rate -system.cpu2.iew.wb_sent 257596 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 257120 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 143610 # num instructions producing a value -system.cpu2.iew.wb_consumers 151220 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.321709 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.949676 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 25270 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 7691 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 2375 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 186904 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.534044 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.009689 # Number of insts commited each cycle +system.cpu2.iew.exec_nop 45796 # number of nop insts executed +system.cpu2.iew.exec_refs 135892 # number of memory reference insts executed +system.cpu2.iew.exec_branches 56020 # Number of branches executed +system.cpu2.iew.exec_stores 43591 # Number of stores executed +system.cpu2.iew.exec_rate 1.445566 # Inst execution rate +system.cpu2.iew.wb_sent 272582 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 272120 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 153730 # num instructions producing a value +system.cpu2.iew.wb_consumers 161299 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.438662 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.953075 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 25088 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 6354 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 2314 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 182587 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.665803 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.057645 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 84130 45.01% 45.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 49844 26.67% 71.68% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5407 2.89% 74.57% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 8359 4.47% 79.05% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1323 0.71% 79.75% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 34855 18.65% 98.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 714 0.38% 98.78% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1043 0.56% 99.34% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1229 0.66% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 74839 40.99% 40.99% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 52317 28.65% 69.64% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5497 3.01% 72.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 6991 3.83% 76.48% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1341 0.73% 77.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 38632 21.16% 98.37% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 681 0.37% 98.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1052 0.58% 99.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1237 0.68% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 186904 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 286719 # Number of instructions committed -system.cpu2.commit.committedOps 286719 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 182587 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 304154 # Number of instructions committed +system.cpu2.commit.committedOps 304154 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 121758 # Number of memory references committed -system.cpu2.commit.loads 83319 # Number of loads committed -system.cpu2.commit.membars 6971 # Number of memory barriers committed -system.cpu2.commit.branches 51375 # Number of branches committed +system.cpu2.commit.refs 131812 # Number of memory references committed +system.cpu2.commit.loads 89574 # Number of loads committed +system.cpu2.commit.membars 5632 # Number of memory barriers committed +system.cpu2.commit.branches 53837 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 195248 # Number of committed integer instructions. +system.cpu2.commit.int_insts 207761 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 42159 14.70% 14.70% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 115831 40.40% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMultAcc 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMisc 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.10% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 90290 31.49% 86.59% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 38439 13.41% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 44619 14.67% 14.67% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 122091 40.14% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMultAcc 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMisc 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.81% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 95206 31.30% 86.11% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 42238 13.89% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 286719 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1229 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 497078 # The number of ROB reads -system.cpu2.rob.rob_writes 628878 # The number of ROB writes -system.cpu2.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 2784 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 49801 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 237589 # Number of Instructions Simulated -system.cpu2.committedOps 237589 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.818792 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.818792 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.221311 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.221311 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 441330 # number of integer regfile reads -system.cpu2.int_regfile_writes 205867 # number of integer regfile writes +system.cpu2.commit.op_class_0::total 304154 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1237 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 510006 # The number of ROB reads +system.cpu2.rob.rob_writes 663292 # The number of ROB writes +system.cpu2.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1794 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 49847 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 253903 # Number of Instructions Simulated +system.cpu2.committedOps 253903 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.744962 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.744962 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.342351 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.342351 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 471960 # number of integer regfile reads +system.cpu2.int_regfile_writes 219741 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 127741 # number of misc regfile reads +system.cpu2.misc_regfile_reads 137767 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes -system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 25.326014 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 45457 # Total number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 25.074061 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 49166 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1567.482759 # Average number of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1695.379310 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.326014 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.049465 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.049465 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.074061 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.048973 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.048973 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 359653 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 359653 # Number of data accesses -system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu2.dcache.ReadReq_hits::cpu2.data 50904 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 50904 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 38221 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 38221 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 89125 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 89125 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 89125 # number of overall hits -system.cpu2.dcache.overall_hits::total 89125 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 505 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 505 # number of ReadReq misses +system.cpu2.dcache.tags.tag_accesses 384293 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 384293 # Number of data accesses +system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu2.dcache.ReadReq_hits::cpu2.data 53240 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 53240 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 42018 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 42018 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 95258 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 95258 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 95258 # number of overall hits +system.cpu2.dcache.overall_hits::total 95258 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 529 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 529 # number of ReadReq misses system.cpu2.dcache.WriteReq_misses::cpu2.data 144 # number of WriteReq misses system.cpu2.dcache.WriteReq_misses::total 144 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 62 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 62 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 649 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 649 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 649 # number of overall misses -system.cpu2.dcache.overall_misses::total 649 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3857000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 3857000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3021500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 3021500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 367000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 367000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 6878500 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 6878500 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 6878500 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 6878500 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 51409 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 51409 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 38365 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 38365 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 74 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 74 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 89774 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 89774 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 89774 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 89774 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009823 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.009823 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003753 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.003753 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.837838 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.837838 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007229 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.007229 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007229 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.007229 # 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miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 7575.614367 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 7575.614367 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21079.861111 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 21079.861111 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 6453.846154 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 6453.846154 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10465.081724 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 10465.081724 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10465.081724 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 10465.081724 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 337 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 337 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 358 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 41 # number of WriteReq MSHR hits system.cpu2.dcache.WriteReq_mshr_hits::total 41 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 378 # 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number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 171 # number of ReadReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 103 # number of WriteReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 62 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 62 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1115500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1115500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1450500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1450500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 305000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 305000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2566000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 2566000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2566000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 2566000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003268 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003268 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002685 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002685 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.837838 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.837838 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003019 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003019 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003019 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003019 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 6639.880952 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 6639.880952 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14082.524272 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14082.524272 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 4919.354839 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 4919.354839 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9468.634686 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9468.634686 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9468.634686 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9468.634686 # average overall mshr miss latency -system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu2.icache.tags.replacements 551 # number of replacements -system.cpu2.icache.tags.tagsinuse 96.895068 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 27659 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 687 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 40.260553 # Average number of references to valid blocks. +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 64 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 64 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 274 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 274 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1122000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1122000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1473000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1473000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 354500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 354500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2595000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 2595000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2595000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 2595000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003180 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003180 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002443 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002443 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.842105 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.842105 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002856 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.002856 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002856 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.002856 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 6561.403509 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 6561.403509 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14300.970874 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14300.970874 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 5539.062500 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 5539.062500 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9470.802920 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9470.802920 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9470.802920 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9470.802920 # average overall mshr miss latency +system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu2.icache.tags.replacements 575 # number of replacements +system.cpu2.icache.tags.tagsinuse 93.413944 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 24822 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 707 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 35.108911 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 96.895068 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.189248 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.189248 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 136 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.265625 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 29161 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 29161 # Number of data accesses -system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu2.icache.ReadReq_hits::cpu2.inst 27659 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 27659 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 27659 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 27659 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 27659 # number of overall hits -system.cpu2.icache.overall_hits::total 27659 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 815 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 815 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 815 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 815 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 815 # number of overall misses -system.cpu2.icache.overall_misses::total 815 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 12882000 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 12882000 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 12882000 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 12882000 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 12882000 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 12882000 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 28474 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 28474 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 28474 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 28474 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 28474 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 28474 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.028623 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.028623 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.028623 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.028623 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.028623 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.028623 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15806.134969 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 15806.134969 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15806.134969 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 15806.134969 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15806.134969 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 15806.134969 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked +system.cpu2.icache.tags.occ_blocks::cpu2.inst 93.413944 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.182449 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.182449 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 132 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.257812 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 26357 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 26357 # Number of data accesses +system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu2.icache.ReadReq_hits::cpu2.inst 24822 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 24822 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 24822 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 24822 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 24822 # number of overall hits +system.cpu2.icache.overall_hits::total 24822 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 828 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 828 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 828 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 828 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 828 # number of overall misses +system.cpu2.icache.overall_misses::total 828 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 12872000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 12872000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 12872000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 12872000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 12872000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 12872000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 25650 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 25650 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 25650 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 25650 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 25650 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 25650 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.032281 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.032281 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.032281 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.032281 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.032281 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.032281 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15545.893720 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 15545.893720 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15545.893720 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 15545.893720 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15545.893720 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 15545.893720 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 69 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs 24 # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs 23 # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.writebacks::writebacks 551 # number of writebacks -system.cpu2.icache.writebacks::total 551 # number of writebacks -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 128 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 128 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 128 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 128 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 128 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 128 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 687 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 687 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 687 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 687 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 687 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 687 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10903000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 10903000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10903000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 10903000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10903000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 10903000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.024127 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.024127 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.024127 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.024127 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.024127 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.024127 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 15870.451237 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 15870.451237 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 15870.451237 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 15870.451237 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 15870.451237 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 15870.451237 # average overall mshr miss latency -system.cpu3.branchPred.lookups 64271 # Number of BP lookups -system.cpu3.branchPred.condPredicted 56758 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 2271 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 55794 # Number of BTB lookups +system.cpu2.icache.writebacks::writebacks 575 # number of writebacks +system.cpu2.icache.writebacks::total 575 # number of writebacks +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 121 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 121 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 121 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 121 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 121 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 121 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 707 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 707 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 707 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 707 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 707 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 707 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 11018000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 11018000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 11018000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 11018000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 11018000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 11018000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.027563 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.027563 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.027563 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.027563 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.027563 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.027563 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 15584.158416 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 15584.158416 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 15584.158416 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 15584.158416 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 15584.158416 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 15584.158416 # average overall mshr miss latency +system.cpu3.branchPred.lookups 62938 # Number of BP lookups +system.cpu3.branchPred.condPredicted 55062 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 2421 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 53856 # Number of BTB lookups system.cpu3.branchPred.BTBHits 0 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu3.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 1884 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.usedRAS 2064 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.branchPred.indirectLookups 55794 # Number of indirect predictor lookups. -system.cpu3.branchPred.indirectHits 46245 # Number of indirect target hits. -system.cpu3.branchPred.indirectMisses 9549 # Number of indirect misses. -system.cpu3.branchPredindirectMispredicted 1200 # Number of mispredicted indirect branches. -system.cpu3.pwrStateResidencyTicks::ON 125996000 # Cumulative time (in ticks) in various power states -system.cpu3.numCycles 194168 # number of cpu cycles simulated +system.cpu3.branchPred.indirectLookups 53856 # Number of indirect predictor lookups. +system.cpu3.branchPred.indirectHits 44056 # Number of indirect target hits. +system.cpu3.branchPred.indirectMisses 9800 # Number of indirect misses. +system.cpu3.branchPredindirectMispredicted 1349 # Number of mispredicted indirect branches. +system.cpu3.pwrStateResidencyTicks::ON 123756000 # Cumulative time (in ticks) in various power states +system.cpu3.numCycles 188742 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 40168 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 346607 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 64271 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 48129 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 146969 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 4697 # Number of cycles fetch has spent squashing +system.cpu3.fetch.icacheStallCycles 40214 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 338441 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 62938 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 46120 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 142180 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 4995 # Number of cycles fetch has spent squashing system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1673 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 29039 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 911 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 191171 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.813073 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.312592 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.PendingTrapStallCycles 1755 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 28914 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 967 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 186659 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.813151 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.333247 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 74400 38.92% 38.92% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 57993 30.34% 69.25% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 8887 4.65% 73.90% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3426 1.79% 75.69% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 613 0.32% 76.02% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 35081 18.35% 94.37% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1105 0.58% 94.94% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 1253 0.66% 95.60% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 8413 4.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 73605 39.43% 39.43% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 55869 29.93% 69.36% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 8647 4.63% 74.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3452 1.85% 75.85% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 624 0.33% 76.18% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 33274 17.83% 94.01% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1074 0.58% 94.58% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 1300 0.70% 95.28% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 8814 4.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 191171 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.331007 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.785088 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 21895 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 75534 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 86562 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 4822 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2348 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 316867 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2348 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 22878 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 37474 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 13003 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 86814 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 28644 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 310654 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 24310 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full -system.cpu3.rename.RenamedOperands 215725 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 585696 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 456528 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 32 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 188410 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 27315 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1561 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1705 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 33909 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 84645 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 39227 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 40799 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 33015 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 251387 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 9227 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 253114 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 23294 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 18618 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 1117 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 191171 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.324019 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.377234 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 186659 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.333460 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.793141 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 22716 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 73421 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 83265 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 4750 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2497 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 307410 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2497 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 23704 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 36346 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 12933 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 84283 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 26886 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 301080 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 23387 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full +system.cpu3.rename.RenamedOperands 210366 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 567874 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 443450 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 24 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 181055 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 29311 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1630 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1783 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 32120 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 81178 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 37704 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 38749 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 31258 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 243640 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 9008 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 244569 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 85 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 25003 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 20491 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 1173 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 186659 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.310245 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.388449 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 78925 41.29% 41.29% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 29485 15.42% 56.71% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 37890 19.82% 76.53% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 37772 19.76% 96.29% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3652 1.91% 98.20% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1740 0.91% 99.11% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 1013 0.53% 99.64% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 405 0.21% 99.85% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 289 0.15% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 78461 42.03% 42.03% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 28833 15.45% 57.48% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 36126 19.35% 76.84% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 35957 19.26% 96.10% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3664 1.96% 98.06% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1804 0.97% 99.03% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 1069 0.57% 99.60% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 437 0.23% 99.83% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 308 0.17% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 191171 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 186659 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 186 40.88% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMultAcc 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMisc 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 40.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 39 8.57% 49.45% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 230 50.55% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 212 43.80% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMultAcc 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMisc 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 43.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 41 8.47% 52.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 231 47.73% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 123835 48.92% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMultAcc 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMisc 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.92% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 91015 35.96% 84.88% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 38264 15.12% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 120712 49.36% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMultAcc 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMisc 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.36% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 87244 35.67% 85.03% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 36613 14.97% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 253114 # Type of FU issued -system.cpu3.iq.rate 1.303582 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 455 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001798 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 697933 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 283879 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 249400 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 244569 # Type of FU issued +system.cpu3.iq.rate 1.295785 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 484 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001979 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 676366 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 277636 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 240444 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 64 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 253569 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 245053 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 32960 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 31180 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 4297 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 40 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 2496 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 4645 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 43 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 33 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 2744 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2348 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 9647 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 302650 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 426 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 84645 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 39227 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1449 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 30 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2497 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 9575 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 52 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 292625 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 421 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 81178 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 37704 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1504 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 32 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 35 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 408 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 2445 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 2853 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 250680 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 83030 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 2434 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 33 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 434 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 2602 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 3036 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 241934 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 79457 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 2635 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 42036 # number of nop insts executed -system.cpu3.iew.exec_refs 121032 # number of memory reference insts executed -system.cpu3.iew.exec_branches 52206 # Number of branches executed -system.cpu3.iew.exec_stores 38002 # Number of stores executed -system.cpu3.iew.exec_rate 1.291047 # Inst execution rate -system.cpu3.iew.wb_sent 249859 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 249400 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 138774 # num instructions producing a value -system.cpu3.iew.wb_consumers 146167 # num instructions consuming a value -system.cpu3.iew.wb_rate 1.284455 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.949421 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 24422 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 8110 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 2271 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 186514 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.491588 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.991895 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 39977 # number of nop insts executed +system.cpu3.iew.exec_refs 115781 # number of memory reference insts executed +system.cpu3.iew.exec_branches 50244 # Number of branches executed +system.cpu3.iew.exec_stores 36324 # Number of stores executed +system.cpu3.iew.exec_rate 1.281824 # Inst execution rate +system.cpu3.iew.wb_sent 241008 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 240444 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 133441 # num instructions producing a value +system.cpu3.iew.wb_consumers 140864 # num instructions consuming a value +system.cpu3.iew.wb_rate 1.273929 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.947304 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 26116 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7835 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 2421 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 181669 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.466860 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.985223 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 86424 46.34% 46.34% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 48393 25.95% 72.28% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5395 2.89% 75.18% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8809 4.72% 79.90% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1333 0.71% 80.61% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 33156 17.78% 98.39% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 761 0.41% 98.80% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1030 0.55% 99.35% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1213 0.65% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 85663 47.15% 47.15% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 46447 25.57% 72.72% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5344 2.94% 75.66% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8472 4.66% 80.33% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1289 0.71% 81.03% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 31374 17.27% 98.30% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 856 0.47% 98.78% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1022 0.56% 99.34% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1202 0.66% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 186514 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 278202 # Number of instructions committed -system.cpu3.commit.committedOps 278202 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 181669 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 266483 # Number of instructions committed +system.cpu3.commit.committedOps 266483 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 117079 # Number of memory references committed -system.cpu3.commit.loads 80348 # Number of loads committed -system.cpu3.commit.membars 7398 # Number of memory barriers committed -system.cpu3.commit.branches 50090 # Number of branches committed +system.cpu3.commit.refs 111493 # Number of memory references committed +system.cpu3.commit.loads 76533 # Number of loads committed +system.cpu3.commit.membars 7123 # Number of memory barriers committed +system.cpu3.commit.branches 48046 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 189293 # Number of committed integer instructions. +system.cpu3.commit.int_insts 181662 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 40882 14.70% 14.70% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 112843 40.56% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMultAcc 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMisc 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.26% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 87746 31.54% 86.80% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 36731 13.20% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 38838 14.57% 14.57% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 109029 40.91% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMultAcc 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMisc 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.49% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 83656 31.39% 86.88% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 34960 13.12% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 278202 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1213 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 487339 # The number of ROB reads -system.cpu3.rob.rob_writes 609957 # The number of ROB writes -system.cpu3.timesIdled 210 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 2997 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 50169 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 229922 # Number of Instructions Simulated -system.cpu3.committedOps 229922 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 0.844495 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.844495 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.184140 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.184140 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 426644 # number of integer regfile reads -system.cpu3.int_regfile_writes 199085 # number of integer regfile writes +system.cpu3.commit.op_class_0::total 266483 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1202 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 472480 # The number of ROB reads +system.cpu3.rob.rob_writes 590253 # The number of ROB writes +system.cpu3.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 2083 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 50253 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 220522 # Number of Instructions Simulated +system.cpu3.committedOps 220522 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.855887 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.855887 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.168378 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.168378 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 411294 # number of integer regfile reads +system.cpu3.int_regfile_writes 192402 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 122920 # number of misc regfile reads +system.cpu3.misc_regfile_reads 117678 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes -system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 24.889715 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 43728 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1457.600000 # Average number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 24.245200 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 42083 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1451.137931 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.889715 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048613 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.048613 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 347346 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 347346 # Number of data accesses -system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu3.dcache.ReadReq_hits::cpu3.data 49561 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 49561 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 36521 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 36521 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 86082 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 86082 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 86082 # number of overall hits -system.cpu3.dcache.overall_hits::total 86082 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 482 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 482 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 144 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 144 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 626 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 626 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 626 # number of overall misses -system.cpu3.dcache.overall_misses::total 626 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4340000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 4340000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3297000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 3297000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 320500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 320500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 7637000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 7637000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 7637000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 7637000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 50043 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 50043 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 36665 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 36665 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.245200 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047354 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.047354 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 333051 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 333051 # Number of data accesses +system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu3.dcache.ReadReq_hits::cpu3.data 47761 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 47761 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 34756 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 34756 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 82517 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 82517 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 82517 # number of overall hits +system.cpu3.dcache.overall_hits::total 82517 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 480 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 480 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 138 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 138 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 53 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 53 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 618 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 618 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 618 # number of overall misses +system.cpu3.dcache.overall_misses::total 618 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4264500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 4264500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3342000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3342000 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 357000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 357000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 7606500 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 7606500 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 7606500 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 7606500 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 48241 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 48241 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 34894 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 34894 # number of WriteReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::cpu3.data 66 # number of SwapReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 86708 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 86708 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 86708 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 86708 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009632 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.009632 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003927 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.003927 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.787879 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.787879 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007220 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.007220 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007220 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.007220 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 9004.149378 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 9004.149378 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 22895.833333 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 22895.833333 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6163.461538 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 6163.461538 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 12199.680511 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 12199.680511 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 12199.680511 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 12199.680511 # average overall miss latency +system.cpu3.dcache.demand_accesses::cpu3.data 83135 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 83135 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 83135 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 83135 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009950 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.009950 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003955 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.003955 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.803030 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.803030 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007434 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.007434 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007434 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.007434 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 8884.375000 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 8884.375000 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 24217.391304 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 24217.391304 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6735.849057 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 6735.849057 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 12308.252427 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 12308.252427 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 12308.252427 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 12308.252427 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 322 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 322 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 40 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 40 # number of WriteReq MSHR hits -system.cpu3.dcache.SwapReq_mshr_hits::cpu3.data 1 # number of SwapReq MSHR hits -system.cpu3.dcache.SwapReq_mshr_hits::total 1 # number of SwapReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 362 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 362 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 362 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 362 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 160 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 104 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 51 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 264 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 264 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 264 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1241000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1241000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1631000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1631000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 268500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 268500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2872000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2872000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2872000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2872000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003197 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003197 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002836 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002836 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.772727 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.772727 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003045 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003045 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003045 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003045 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 7756.250000 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 7756.250000 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15682.692308 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15682.692308 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 5264.705882 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 5264.705882 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 10878.787879 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 10878.787879 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 10878.787879 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 10878.787879 # average overall mshr miss latency -system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu3.icache.tags.replacements 575 # number of replacements -system.cpu3.icache.tags.tagsinuse 93.289458 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 28201 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 712 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 39.608146 # Average number of references to valid blocks. +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 324 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 324 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 31 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 355 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 355 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 156 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 53 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 263 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 263 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1092500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1092500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1676500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1676500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 304000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 304000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2769000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2769000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2769000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2769000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003234 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003234 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003066 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003066 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.803030 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.803030 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003164 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003164 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003164 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003164 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 7003.205128 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 7003.205128 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15668.224299 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15668.224299 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 5735.849057 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 5735.849057 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 10528.517110 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 10528.517110 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 10528.517110 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 10528.517110 # average overall mshr miss latency +system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.cpu3.icache.tags.replacements 578 # number of replacements +system.cpu3.icache.tags.tagsinuse 92.244162 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 28072 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 714 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 39.316527 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 93.289458 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.182206 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.182206 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id +system.cpu3.icache.tags.occ_blocks::cpu3.inst 92.244162 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.180164 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.180164 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_task_id_blocks::1024 136 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.267578 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 29751 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 29751 # Number of data accesses -system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.cpu3.icache.ReadReq_hits::cpu3.inst 28201 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 28201 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 28201 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 28201 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 28201 # number of overall hits -system.cpu3.icache.overall_hits::total 28201 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 838 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 838 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 838 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 838 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 838 # number of overall misses -system.cpu3.icache.overall_misses::total 838 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 13273000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 13273000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 13273000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 13273000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 13273000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 13273000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 29039 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 29039 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 29039 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 29039 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 29039 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 29039 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.028858 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.028858 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.028858 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.028858 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.028858 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.028858 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15838.902148 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 15838.902148 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15838.902148 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 15838.902148 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15838.902148 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 15838.902148 # average overall miss latency +system.cpu3.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.265625 # 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average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 14742.280285 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14742.280285 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 14742.280285 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.writebacks::writebacks 575 # number of writebacks -system.cpu3.icache.writebacks::total 575 # number of writebacks -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 126 # 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number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 10783500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 10783500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 10783500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 10783500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 10783500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 10783500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.024694 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.024694 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.024694 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.024694 # 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Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 9.533779 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 10.075907 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 5.908934 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 10.319248 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::cpu0.inst 0.004582 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.002208 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.001057 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000250 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000145 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000154 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000090 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000157 # 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mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.020378 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.016973 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.560000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.014045 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.576923 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.230694 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.536585 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.971429 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.125512 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.018207 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.560000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.236236 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.542522 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.146190 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.814815 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.020378 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.016973 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.560000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.014045 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.576923 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.230694 # mshr miss rate for overall accesses -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74707.446809 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 75076.923077 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 75208.333333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 89958.333333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 76187.022901 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 75655.080214 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 80353.260870 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 76750 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 159150 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 78272.448980 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80822.368421 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 75222.222222 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 79500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 103000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 80972.222222 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75655.080214 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77441.176471 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 80353.260870 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75136.363636 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 76750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 75821.428571 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 159150 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 92566.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 78229.957806 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75655.080214 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77441.176471 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 80353.260870 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75136.363636 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 76750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 75821.428571 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 159150 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 92566.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 78229.957806 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 961 # Total number of requests made to the snoop filter. +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.018207 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.560000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.236236 # mshr miss rate for overall accesses +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74457.446809 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73923.076923 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 77750 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 92083.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 76320.610687 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72800 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75234.042553 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 121708.333333 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 115115.384615 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 75593.047035 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78100 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 75333.333333 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 79750 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 89750 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 78119.318182 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72800 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76073.964497 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75234.042553 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 121708.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 78035.714286 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 115115.384615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 91750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 76041.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72800 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76073.964497 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75234.042553 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 121708.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 78035.714286 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 115115.384615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 91750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 76041.666667 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 958 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 251 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 579 # Transaction distribution -system.membus.trans_dist::UpgradeReq 193 # Transaction distribution -system.membus.trans_dist::ReadExReq 189 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 576 # Transaction distribution +system.membus.trans_dist::UpgradeReq 200 # Transaction distribution +system.membus.trans_dist::ReadExReq 182 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 579 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1671 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1671 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45440 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 576 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1665 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1665 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45248 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 251 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 961 # Request fanout histogram +system.membus.snoop_fanout::samples 958 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 961 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 958 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 961 # Request fanout histogram -system.membus.reqLayer0.occupancy 879000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 958 # Request fanout histogram +system.membus.reqLayer0.occupancy 881500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3778500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3759250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 6307 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1711 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 3247 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 6160 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1652 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 3166 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadResp 3510 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 123756000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadResp 3429 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 2115 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 2041 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 399 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 399 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 2829 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 685 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1784 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 594 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 2064 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 364 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1925 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 379 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1999 # Packet count per connected master and slave (bytes) +system.toL2Bus.trans_dist::UpgradeReq 287 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 287 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 398 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 398 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 2746 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 686 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1744 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 595 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1793 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 369 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1989 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 384 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 2006 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 363 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 9472 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 69568 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11264 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 85184 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 9243 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 67968 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 73600 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1728 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 79232 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 82048 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 82368 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 332608 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1024 # Total snoops (count) -system.toL2Bus.snoopTraffic 53184 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 4190 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.302625 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.130775 # Request fanout histogram +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 82688 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 322432 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1033 # Total snoops (count) +system.toL2Bus.snoopTraffic 53312 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 4117 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.305805 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.138383 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1349 32.20% 32.20% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1111 26.52% 58.71% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 843 20.12% 78.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 887 21.17% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1342 32.60% 32.60% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1062 25.80% 58.39% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 825 20.04% 78.43% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 888 21.57% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram @@ -2933,24 +2925,24 @@ system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4190 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5284470 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 4.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1044996 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4117 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5135473 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 4.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 1023494 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 522995 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 524487 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1103492 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.9 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 425474 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 967494 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.8 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 424479 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1034985 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 0.8 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 441461 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 1065487 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.9 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 451954 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 1070994 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 1072994 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.9 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 421970 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 419968 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt index 7dd43386c..4c28ac0bc 100644 --- a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt +++ b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000014 # Nu sim_ticks 13821 # Number of ticks simulated final_tick 13821 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 213268 # Simulator tick rate (ticks/s) -host_mem_usage 483832 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 253620 # Simulator tick rate (ticks/s) +host_mem_usage 491252 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states @@ -332,11 +332,23 @@ system.cp_cntrl0.L2cache.num_data_array_reads 81 system.cp_cntrl0.L2cache.num_data_array_writes 85 # number of data array writes system.cp_cntrl0.L2cache.num_tag_array_reads 372 # number of tag array reads system.cp_cntrl0.L2cache.num_tag_array_writes 362 # number of tag array writes +system.cp_cntrl0.mandatoryQueue.avg_buf_msgs 25.716177 # Average number of messages in buffer +system.cp_cntrl0.mandatoryQueue.avg_stall_time 2962.798293 # Average number of cycles messages are stalled in this MB +system.cp_cntrl0.probeToCore.avg_buf_msgs 0.015627 # Average number of messages in buffer +system.cp_cntrl0.probeToCore.avg_stall_time 33.503111 # Average number of cycles messages are stalled in this MB +system.cp_cntrl0.requestFromCore.avg_buf_msgs 0.169512 # Average number of messages in buffer +system.cp_cntrl0.requestFromCore.avg_stall_time 14.915352 # Average number of cycles messages are stalled in this MB +system.cp_cntrl0.responseFromCore.avg_buf_msgs 0.311460 # Average number of messages in buffer +system.cp_cntrl0.responseFromCore.avg_stall_time 14.764506 # Average number of cycles messages are stalled in this MB +system.cp_cntrl0.responseToCore.avg_buf_msgs 0.011069 # Average number of messages in buffer +system.cp_cntrl0.responseToCore.avg_stall_time 14.645999 # Average number of cycles messages are stalled in this MB system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.cp_cntrl0.sequencer.store_waiting_on_load 1 # Number of times a store aliased with a pending load system.cp_cntrl0.sequencer.store_waiting_on_store 4 # Number of times a store aliased with a pending store system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.cp_cntrl0.sequencer1.store_waiting_on_store 4 # Number of times a store aliased with a pending store +system.cp_cntrl0.unblockFromCore.avg_buf_msgs 0.088699 # Average number of messages in buffer +system.cp_cntrl0.unblockFromCore.avg_stall_time 14.634279 # Average number of cycles messages are stalled in this MB system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.cpu.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits @@ -347,7 +359,38 @@ system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 372 system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 369 # number of tag array writes system.dir_cntrl0.L3CacheMemory.num_tag_array_stalls 9126 # number of stalls caused by tag array system.dir_cntrl0.L3CacheMemory.num_data_array_stalls 4922 # number of stalls caused by data array +system.dir_cntrl0.L3triggerQueue.avg_buf_msgs 0.048835 # Average number of messages in buffer +system.dir_cntrl0.L3triggerQueue.avg_stall_time 12.961945 # Average number of cycles messages are stalled in this MB +system.dir_cntrl0.probeToCore.avg_buf_msgs 0.653306 # Average number of messages in buffer +system.dir_cntrl0.probeToCore.avg_stall_time 29.756909 # Average number of cycles messages are stalled in this MB +system.dir_cntrl0.requestFromCores.avg_buf_msgs 4.168499 # Average number of messages in buffer +system.dir_cntrl0.requestFromCores.avg_stall_time 219.183837 # Average number of cycles messages are stalled in this MB +system.dir_cntrl0.requestFromCores.num_msg_stalls 6 # Number of times messages were stalled +system.dir_cntrl0.responseFromCores.avg_buf_msgs 0.236001 # Average number of messages in buffer +system.dir_cntrl0.responseFromCores.avg_stall_time 44.490812 # Average number of cycles messages are stalled in this MB +system.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.033280 # Average number of messages in buffer +system.dir_cntrl0.responseFromMemory.avg_stall_time 1.594198 # Average number of cycles messages are stalled in this MB +system.dir_cntrl0.responseToCore.avg_buf_msgs 0.651932 # Average number of messages in buffer +system.dir_cntrl0.responseToCore.avg_stall_time 21.888945 # Average number of cycles messages are stalled in this MB +system.dir_cntrl0.triggerQueue.avg_buf_msgs 0.808711 # Average number of messages in buffer +system.dir_cntrl0.triggerQueue.avg_stall_time 28.172406 # Average number of cycles messages are stalled in this MB +system.dir_cntrl0.unblockFromCores.avg_buf_msgs 0.021343 # Average number of messages in buffer +system.dir_cntrl0.unblockFromCores.avg_stall_time 89.749240 # Average number of cycles messages are stalled in this MB system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links00.int_node.port_buffers000.avg_buf_msgs 0.026914 # Average number of messages in buffer +system.ruby.network.ext_links00.int_node.port_buffers000.avg_stall_time 83.794892 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links00.int_node.port_buffers002.avg_buf_msgs 0.026697 # Average number of messages in buffer +system.ruby.network.ext_links00.int_node.port_buffers002.avg_stall_time 39.227029 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links00.int_node.port_buffers004.avg_buf_msgs 0.021343 # Average number of messages in buffer +system.ruby.network.ext_links00.int_node.port_buffers004.avg_stall_time 88.782810 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links00.int_node.port_buffers005.avg_buf_msgs 0.015627 # Average number of messages in buffer +system.ruby.network.ext_links00.int_node.port_buffers005.avg_stall_time 30.553683 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links00.int_node.port_buffers007.avg_buf_msgs 0.011069 # Average number of messages in buffer +system.ruby.network.ext_links00.int_node.port_buffers007.avg_stall_time 11.722616 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links00.int_node.port_buffers015.avg_buf_msgs 0.006077 # Average number of messages in buffer +system.ruby.network.ext_links00.int_node.port_buffers015.avg_stall_time 30.746563 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links00.int_node.port_buffers017.avg_buf_msgs 0.015627 # Average number of messages in buffer +system.ruby.network.ext_links00.int_node.port_buffers017.avg_stall_time 30.419114 # Average number of cycles messages are stalled in this MB system.ruby.network.ext_links00.int_node.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.ruby.network.ext_links00.int_node.percent_links_utilized 0.199915 system.ruby.network.ext_links00.int_node.msg_count.Control::0 300 @@ -364,6 +407,16 @@ system.ruby.network.ext_links00.int_node.msg_bytes.Response_Control::2 1 system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Data::2 4824 system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Control::2 568 system.ruby.network.ext_links00.int_node.msg_bytes.Unblock_Control::4 2360 +system.ruby.network.ext_links01.int_node.port_buffers000.avg_buf_msgs 0.015627 # Average number of messages in buffer +system.ruby.network.ext_links01.int_node.port_buffers000.avg_stall_time 32.520113 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links01.int_node.port_buffers002.avg_buf_msgs 0.011069 # Average number of messages in buffer +system.ruby.network.ext_links01.int_node.port_buffers002.avg_stall_time 13.671683 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links01.int_node.port_buffers003.avg_buf_msgs 0.011214 # Average number of messages in buffer +system.ruby.network.ext_links01.int_node.port_buffers003.avg_stall_time 15.908552 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links01.int_node.port_buffers005.avg_buf_msgs 0.020764 # Average number of messages in buffer +system.ruby.network.ext_links01.int_node.port_buffers005.avg_stall_time 15.747649 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links01.int_node.port_buffers007.avg_buf_msgs 0.005860 # Average number of messages in buffer +system.ruby.network.ext_links01.int_node.port_buffers007.avg_stall_time 15.608740 # Average number of cycles messages are stalled in this MB system.ruby.network.ext_links01.int_node.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.ruby.network.ext_links01.int_node.percent_links_utilized 0.123680 system.ruby.network.ext_links01.int_node.msg_count.Control::0 216 @@ -405,8 +458,76 @@ system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl0.mandatoryQueue.avg_buf_msgs 0.009767 # Average number of messages in buffer +system.tcp_cntrl0.mandatoryQueue.avg_stall_time 1.140790 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl0.probeToTCP.avg_buf_msgs 0.007741 # Average number of messages in buffer +system.tcp_cntrl0.probeToTCP.avg_stall_time 6.886268 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl0.requestFromTCP.avg_buf_msgs 0.308928 # Average number of messages in buffer +system.tcp_cntrl0.requestFromTCP.avg_stall_time 39.646940 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl0.responseFromTCP.avg_buf_msgs 0.289249 # Average number of messages in buffer +system.tcp_cntrl0.responseFromTCP.avg_stall_time 38.260744 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl0.responseToTCP.avg_buf_msgs 0.007597 # Average number of messages in buffer +system.tcp_cntrl0.responseToTCP.avg_stall_time 2.919621 # Average number of cycles messages are stalled in this MB system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.tcp_cntrl0.unblockFromCore.avg_buf_msgs 0.298076 # Average number of messages in buffer +system.tcp_cntrl0.unblockFromCore.avg_stall_time 38.422804 # Average number of cycles messages are stalled in this MB system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links02.int_node.port_buffers001.avg_buf_msgs 0.007235 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers001.avg_stall_time 5.756909 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers003.avg_buf_msgs 0.007452 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers003.avg_stall_time 1.927073 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers005.avg_buf_msgs 0.007018 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers005.avg_stall_time 5.309796 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers007.avg_buf_msgs 0.007018 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers007.avg_stall_time 1.940095 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers009.avg_buf_msgs 0.006656 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers009.avg_stall_time 5.861091 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers011.avg_buf_msgs 0.006945 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers011.avg_stall_time 1.961800 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers013.avg_buf_msgs 0.006222 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers013.avg_stall_time 5.483432 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers015.avg_buf_msgs 0.006367 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers015.avg_stall_time 1.879323 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers017.avg_buf_msgs 0.007524 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers017.avg_stall_time 5.492114 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers019.avg_buf_msgs 0.007452 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers019.avg_stall_time 1.931414 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers021.avg_buf_msgs 0.006367 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers021.avg_stall_time 5.539864 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers023.avg_buf_msgs 0.006656 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers023.avg_stall_time 1.957459 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers025.avg_buf_msgs 0.008031 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers025.avg_stall_time 5.544205 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers027.avg_buf_msgs 0.008320 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers027.avg_stall_time 1.947041 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers029.avg_buf_msgs 0.006439 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers029.avg_stall_time 5.457387 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers031.avg_buf_msgs 0.006728 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers031.avg_stall_time 1.901027 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers036.avg_buf_msgs 0.006077 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers036.avg_stall_time 32.725438 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers037.avg_buf_msgs 0.059543 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers037.avg_stall_time 41.896903 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers038.avg_buf_msgs 0.015627 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers038.avg_stall_time 32.376863 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers039.avg_buf_msgs 0.056794 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers039.avg_stall_time 40.742295 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers041.avg_buf_msgs 0.058602 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers041.avg_stall_time 41.125452 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers043.avg_buf_msgs 0.000796 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers043.avg_stall_time 2.867168 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers045.avg_buf_msgs 0.000868 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers045.avg_stall_time 1.317610 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers047.avg_buf_msgs 0.000796 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers047.avg_stall_time 3.139343 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers049.avg_buf_msgs 0.000868 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers049.avg_stall_time 1.151208 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers050.avg_buf_msgs 0.015700 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers050.avg_stall_time 119.555564 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers052.avg_buf_msgs 0.005933 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers052.avg_stall_time 118.925264 # Average number of cycles messages are stalled in this MB +system.ruby.network.ext_links02.int_node.port_buffers054.avg_buf_msgs 0.015483 # Average number of messages in buffer +system.ruby.network.ext_links02.int_node.port_buffers054.avg_stall_time 117.253220 # Average number of cycles messages are stalled in this MB system.ruby.network.ext_links02.int_node.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.ruby.network.ext_links02.int_node.percent_links_utilized 0.172944 system.ruby.network.ext_links02.int_node.msg_count.Control::0 84 @@ -454,7 +575,19 @@ system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl1.mandatoryQueue.avg_buf_msgs 0.010491 # Average number of messages in buffer +system.tcp_cntrl1.mandatoryQueue.avg_stall_time 1.432571 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl1.probeToTCP.avg_buf_msgs 0.007524 # Average number of messages in buffer +system.tcp_cntrl1.probeToTCP.avg_stall_time 6.242584 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl1.requestFromTCP.avg_buf_msgs 0.289394 # Average number of messages in buffer +system.tcp_cntrl1.requestFromTCP.avg_stall_time 39.762697 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl1.responseFromTCP.avg_buf_msgs 0.280712 # Average number of messages in buffer +system.tcp_cntrl1.responseFromTCP.avg_stall_time 35.279988 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl1.responseToTCP.avg_buf_msgs 0.007235 # Average number of messages in buffer +system.tcp_cntrl1.responseToTCP.avg_stall_time 2.914484 # Average number of cycles messages are stalled in this MB system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.tcp_cntrl1.unblockFromCore.avg_buf_msgs 0.280712 # Average number of messages in buffer +system.tcp_cntrl1.unblockFromCore.avg_stall_time 38.683259 # Average number of cycles messages are stalled in this MB system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.tcp_cntrl2.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl2.L1cache.demand_misses 0 # Number of cache demand misses @@ -481,7 +614,19 @@ system.tcp_cntrl2.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl2.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl2.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl2.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl2.mandatoryQueue.avg_buf_msgs 0.010418 # Average number of messages in buffer +system.tcp_cntrl2.mandatoryQueue.avg_stall_time 1.277312 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl2.probeToTCP.avg_buf_msgs 0.006728 # Average number of messages in buffer +system.tcp_cntrl2.probeToTCP.avg_stall_time 6.844596 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl2.requestFromTCP.avg_buf_msgs 0.280712 # Average number of messages in buffer +system.tcp_cntrl2.requestFromTCP.avg_stall_time 39.878455 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl2.responseFromTCP.avg_buf_msgs 0.266242 # Average number of messages in buffer +system.tcp_cntrl2.responseFromTCP.avg_stall_time 38.955289 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl2.responseToTCP.avg_buf_msgs 0.007307 # Average number of messages in buffer +system.tcp_cntrl2.responseToTCP.avg_stall_time 2.965417 # Average number of cycles messages are stalled in this MB system.tcp_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.tcp_cntrl2.unblockFromCore.avg_buf_msgs 0.277818 # Average number of messages in buffer +system.tcp_cntrl2.unblockFromCore.avg_stall_time 39.117349 # Average number of cycles messages are stalled in this MB system.tcp_cntrl2.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.tcp_cntrl3.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl3.L1cache.demand_misses 0 # Number of cache demand misses @@ -509,7 +654,19 @@ system.tcp_cntrl3.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl3.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl3.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl3.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl3.mandatoryQueue.avg_buf_msgs 0.008465 # Average number of messages in buffer +system.tcp_cntrl3.mandatoryQueue.avg_stall_time 1.170164 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl3.probeToTCP.avg_buf_msgs 0.006728 # Average number of messages in buffer +system.tcp_cntrl3.probeToTCP.avg_stall_time 6.502170 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl3.requestFromTCP.avg_buf_msgs 0.261684 # Average number of messages in buffer +system.tcp_cntrl3.requestFromTCP.avg_stall_time 39.039213 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl3.responseFromTCP.avg_buf_msgs 0.247504 # Average number of messages in buffer +system.tcp_cntrl3.responseFromTCP.avg_stall_time 36.437563 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl3.responseToTCP.avg_buf_msgs 0.006801 # Average number of messages in buffer +system.tcp_cntrl3.responseToTCP.avg_stall_time 2.855954 # Average number of cycles messages are stalled in this MB system.tcp_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.tcp_cntrl3.unblockFromCore.avg_buf_msgs 0.254666 # Average number of messages in buffer +system.tcp_cntrl3.unblockFromCore.avg_stall_time 37.467805 # Average number of cycles messages are stalled in this MB system.tcp_cntrl3.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.tcp_cntrl4.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl4.L1cache.demand_misses 0 # Number of cache demand misses @@ -537,7 +694,19 @@ system.tcp_cntrl4.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl4.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl4.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl4.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl4.mandatoryQueue.avg_buf_msgs 0.009478 # Average number of messages in buffer +system.tcp_cntrl4.mandatoryQueue.avg_stall_time 1.107365 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl4.probeToTCP.avg_buf_msgs 0.008031 # Average number of messages in buffer +system.tcp_cntrl4.probeToTCP.avg_stall_time 6.466141 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl4.requestFromTCP.avg_buf_msgs 0.298076 # Average number of messages in buffer +system.tcp_cntrl4.requestFromTCP.avg_stall_time 39.733758 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl4.responseFromTCP.avg_buf_msgs 0.300969 # Average number of messages in buffer +system.tcp_cntrl4.responseFromTCP.avg_stall_time 36.495442 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl4.responseToTCP.avg_buf_msgs 0.008175 # Average number of messages in buffer +system.tcp_cntrl4.responseToTCP.avg_stall_time 2.934380 # Average number of cycles messages are stalled in this MB system.tcp_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.tcp_cntrl4.unblockFromCore.avg_buf_msgs 0.298076 # Average number of messages in buffer +system.tcp_cntrl4.unblockFromCore.avg_stall_time 38.509622 # Average number of cycles messages are stalled in this MB system.tcp_cntrl4.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.tcp_cntrl5.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl5.L1cache.demand_misses 0 # Number of cache demand misses @@ -564,7 +733,19 @@ system.tcp_cntrl5.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl5.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl5.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl5.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl5.mandatoryQueue.avg_buf_msgs 0.008465 # Average number of messages in buffer +system.tcp_cntrl5.mandatoryQueue.avg_stall_time 1.079728 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl5.probeToTCP.avg_buf_msgs 0.006511 # Average number of messages in buffer +system.tcp_cntrl5.probeToTCP.avg_stall_time 6.478585 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl5.requestFromTCP.avg_buf_msgs 0.269136 # Average number of messages in buffer +system.tcp_cntrl5.requestFromTCP.avg_stall_time 39.849515 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl5.responseFromTCP.avg_buf_msgs 0.254015 # Average number of messages in buffer +system.tcp_cntrl5.responseFromTCP.avg_stall_time 36.813775 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl5.responseToTCP.avg_buf_msgs 0.006945 # Average number of messages in buffer +system.tcp_cntrl5.responseToTCP.avg_stall_time 2.959991 # Average number of cycles messages are stalled in this MB system.tcp_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.tcp_cntrl5.unblockFromCore.avg_buf_msgs 0.266242 # Average number of messages in buffer +system.tcp_cntrl5.unblockFromCore.avg_stall_time 39.030531 # Average number of cycles messages are stalled in this MB system.tcp_cntrl5.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.tcp_cntrl6.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl6.L1cache.demand_misses 0 # Number of cache demand misses @@ -591,7 +772,19 @@ system.tcp_cntrl6.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl6.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl6.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl6.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl6.mandatoryQueue.avg_buf_msgs 0.010201 # Average number of messages in buffer +system.tcp_cntrl6.mandatoryQueue.avg_stall_time 1.122414 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl6.probeToTCP.avg_buf_msgs 0.009405 # Average number of messages in buffer +system.tcp_cntrl6.probeToTCP.avg_stall_time 6.666763 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl6.requestFromTCP.avg_buf_msgs 0.335697 # Average number of messages in buffer +system.tcp_cntrl6.requestFromTCP.avg_stall_time 39.618000 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl6.responseFromTCP.avg_buf_msgs 0.321227 # Average number of messages in buffer +system.tcp_cntrl6.responseFromTCP.avg_stall_time 36.842715 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl6.responseToTCP.avg_buf_msgs 0.008682 # Average number of messages in buffer +system.tcp_cntrl6.responseToTCP.avg_stall_time 2.959051 # Average number of cycles messages are stalled in this MB system.tcp_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.tcp_cntrl6.unblockFromCore.avg_buf_msgs 0.331718 # Average number of messages in buffer +system.tcp_cntrl6.unblockFromCore.avg_stall_time 38.822168 # Average number of cycles messages are stalled in this MB system.tcp_cntrl6.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.tcp_cntrl7.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl7.L1cache.demand_misses 0 # Number of cache demand misses @@ -618,7 +811,19 @@ system.tcp_cntrl7.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl7.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl7.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl7.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl7.mandatoryQueue.avg_buf_msgs 0.008103 # Average number of messages in buffer +system.tcp_cntrl7.mandatoryQueue.avg_stall_time 1.097743 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl7.probeToTCP.avg_buf_msgs 0.006511 # Average number of messages in buffer +system.tcp_cntrl7.probeToTCP.avg_stall_time 6.394371 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl7.requestFromTCP.avg_buf_msgs 0.272030 # Average number of messages in buffer +system.tcp_cntrl7.requestFromTCP.avg_stall_time 39.357546 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl7.responseFromTCP.avg_buf_msgs 0.254739 # Average number of messages in buffer +system.tcp_cntrl7.responseFromTCP.avg_stall_time 36.263927 # Average number of cycles messages are stalled in this MB +system.tcp_cntrl7.responseToTCP.avg_buf_msgs 0.006801 # Average number of messages in buffer +system.tcp_cntrl7.responseToTCP.avg_stall_time 2.863696 # Average number of cycles messages are stalled in this MB system.tcp_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.tcp_cntrl7.unblockFromCore.avg_buf_msgs 0.269136 # Average number of messages in buffer +system.tcp_cntrl7.unblockFromCore.avg_stall_time 37.901896 # Average number of cycles messages are stalled in this MB system.tcp_cntrl7.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses @@ -627,7 +832,19 @@ system.sqc_cntrl0.L1cache.num_data_array_reads 12 system.sqc_cntrl0.L1cache.num_data_array_writes 12 # number of data array writes system.sqc_cntrl0.L1cache.num_tag_array_reads 23 # number of tag array reads system.sqc_cntrl0.L1cache.num_tag_array_writes 23 # number of tag array writes +system.sqc_cntrl0.mandatoryQueue.avg_buf_msgs 0.000868 # Average number of messages in buffer +system.sqc_cntrl0.mandatoryQueue.avg_stall_time 0.668499 # Average number of cycles messages are stalled in this MB +system.sqc_cntrl0.probeToSQC.avg_buf_msgs 0.000796 # Average number of messages in buffer +system.sqc_cntrl0.probeToSQC.avg_stall_time 3.344523 # Average number of cycles messages are stalled in this MB +system.sqc_cntrl0.requestFromSQC.avg_buf_msgs 0.069454 # Average number of messages in buffer +system.sqc_cntrl0.requestFromSQC.avg_stall_time 53.016930 # Average number of cycles messages are stalled in this MB +system.sqc_cntrl0.responseFromSQC.avg_buf_msgs 0.063667 # Average number of messages in buffer +system.sqc_cntrl0.responseFromSQC.avg_stall_time 37.760093 # Average number of cycles messages are stalled in this MB +system.sqc_cntrl0.responseToSQC.avg_buf_msgs 0.000868 # Average number of messages in buffer +system.sqc_cntrl0.responseToSQC.avg_stall_time 1.976197 # Average number of cycles messages are stalled in this MB system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.sqc_cntrl0.unblockFromCore.avg_buf_msgs 0.069454 # Average number of messages in buffer +system.sqc_cntrl0.unblockFromCore.avg_stall_time 52.235566 # Average number of cycles messages are stalled in this MB system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.sqc_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits system.sqc_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses @@ -636,7 +853,19 @@ system.sqc_cntrl1.L1cache.num_data_array_reads 12 system.sqc_cntrl1.L1cache.num_data_array_writes 12 # number of data array writes system.sqc_cntrl1.L1cache.num_tag_array_reads 23 # number of tag array reads system.sqc_cntrl1.L1cache.num_tag_array_writes 23 # number of tag array writes +system.sqc_cntrl1.mandatoryQueue.avg_buf_msgs 0.000868 # Average number of messages in buffer +system.sqc_cntrl1.mandatoryQueue.avg_stall_time 0.585299 # Average number of cycles messages are stalled in this MB +system.sqc_cntrl1.probeToSQC.avg_buf_msgs 0.000796 # Average number of messages in buffer +system.sqc_cntrl1.probeToSQC.avg_stall_time 3.662060 # Average number of cycles messages are stalled in this MB +system.sqc_cntrl1.requestFromSQC.avg_buf_msgs 0.069454 # Average number of messages in buffer +system.sqc_cntrl1.requestFromSQC.avg_stall_time 46.360874 # Average number of cycles messages are stalled in this MB +system.sqc_cntrl1.responseFromSQC.avg_buf_msgs 0.063667 # Average number of messages in buffer +system.sqc_cntrl1.responseFromSQC.avg_stall_time 41.389090 # Average number of cycles messages are stalled in this MB +system.sqc_cntrl1.responseToSQC.avg_buf_msgs 0.000868 # Average number of messages in buffer +system.sqc_cntrl1.responseToSQC.avg_stall_time 1.726595 # Average number of cycles messages are stalled in this MB system.sqc_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.sqc_cntrl1.unblockFromCore.avg_buf_msgs 0.069454 # Average number of messages in buffer +system.sqc_cntrl1.unblockFromCore.avg_stall_time 45.579511 # Average number of cycles messages are stalled in this MB system.sqc_cntrl1.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses @@ -647,7 +876,49 @@ system.tccdir_cntrl0.directory.demand_misses 0 system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses system.tccdir_cntrl0.directory.num_tag_array_reads 896 # number of tag array reads system.tccdir_cntrl0.directory.num_tag_array_writes 882 # number of tag array writes +system.tccdir_cntrl0.probeFromNB.avg_buf_msgs 0.035740 # Average number of messages in buffer +system.tccdir_cntrl0.probeFromNB.avg_stall_time 35.754884 # Average number of cycles messages are stalled in this MB +system.tccdir_cntrl0.probeToCore.avg_buf_msgs 0.265157 # Average number of messages in buffer +system.tccdir_cntrl0.probeToCore.avg_stall_time 4.884604 # Average number of cycles messages are stalled in this MB +system.tccdir_cntrl0.requestFromTCP.avg_buf_msgs 1.395239 # Average number of messages in buffer +system.tccdir_cntrl0.requestFromTCP.avg_stall_time 55.396180 # Average number of cycles messages are stalled in this MB +system.tccdir_cntrl0.requestToNB.avg_buf_msgs 1.900159 # Average number of messages in buffer +system.tccdir_cntrl0.requestToNB.avg_stall_time 118.576183 # Average number of cycles messages are stalled in this MB +system.tccdir_cntrl0.responseFromNB.avg_buf_msgs 0.015627 # Average number of messages in buffer +system.tccdir_cntrl0.responseFromNB.avg_stall_time 33.355520 # Average number of cycles messages are stalled in this MB +system.tccdir_cntrl0.responseFromTCP.avg_buf_msgs 0.056794 # Average number of messages in buffer +system.tccdir_cntrl0.responseFromTCP.avg_stall_time 41.713066 # Average number of cycles messages are stalled in this MB +system.tccdir_cntrl0.responseToCore.avg_buf_msgs 0.058602 # Average number of messages in buffer +system.tccdir_cntrl0.responseToCore.avg_stall_time 0.980972 # Average number of cycles messages are stalled in this MB +system.tccdir_cntrl0.responseToNB.avg_buf_msgs 0.718203 # Average number of messages in buffer +system.tccdir_cntrl0.responseToNB.avg_stall_time 117.951092 # Average number of cycles messages are stalled in this MB +system.tccdir_cntrl0.triggerQueue.avg_buf_msgs 0.052814 # Average number of messages in buffer +system.tccdir_cntrl0.triggerQueue.avg_stall_time 0.973665 # Average number of cycles messages are stalled in this MB +system.tccdir_cntrl0.unblockFromTCP.avg_buf_msgs 0.058602 # Average number of messages in buffer +system.tccdir_cntrl0.unblockFromTCP.avg_stall_time 42.100275 # Average number of cycles messages are stalled in this MB +system.tccdir_cntrl0.unblockToNB.avg_buf_msgs 1.864274 # Average number of messages in buffer +system.tccdir_cntrl0.unblockToNB.avg_stall_time 116.292866 # Average number of cycles messages are stalled in this MB system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.ruby.network.int_link_buffers00.avg_buf_msgs 0.015627 # Average number of messages in buffer +system.ruby.network.int_link_buffers00.avg_stall_time 31.536970 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.011069 # Average number of messages in buffer +system.ruby.network.int_link_buffers02.avg_stall_time 12.697222 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers10.avg_buf_msgs 0.006077 # Average number of messages in buffer +system.ruby.network.int_link_buffers10.avg_stall_time 31.736073 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers12.avg_buf_msgs 0.015627 # Average number of messages in buffer +system.ruby.network.int_link_buffers12.avg_stall_time 31.398061 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers20.avg_buf_msgs 0.011214 # Average number of messages in buffer +system.ruby.network.int_link_buffers20.avg_stall_time 16.901606 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers22.avg_buf_msgs 0.020764 # Average number of messages in buffer +system.ruby.network.int_link_buffers22.avg_stall_time 16.730647 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers24.avg_buf_msgs 0.005860 # Average number of messages in buffer +system.ruby.network.int_link_buffers24.avg_stall_time 16.583056 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers30.avg_buf_msgs 0.015700 # Average number of messages in buffer +system.ruby.network.int_link_buffers30.avg_stall_time 120.534800 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers32.avg_buf_msgs 0.005933 # Average number of messages in buffer +system.ruby.network.int_link_buffers32.avg_stall_time 119.899291 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers34.avg_buf_msgs 0.015483 # Average number of messages in buffer +system.ruby.network.int_link_buffers34.avg_stall_time 118.213428 # Average number of cycles messages are stalled in this MB system.ruby.network.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 1389 system.ruby.network.msg_count.Request_Control 1567 diff --git a/tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MESI_Two_Level/stats.txt index ed12265fc..eb24a41c8 100644 --- a/tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MESI_Two_Level/stats.txt @@ -4,8 +4,8 @@ sim_seconds 0.000044 # Nu sim_ticks 44021 # Number of ticks simulated final_tick 44021 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 728057 # Simulator tick rate (ticks/s) -host_mem_usage 409368 # Number of bytes of host memory used +host_tick_rate 749300 # Simulator tick rate (ticks/s) +host_mem_usage 393900 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks @@ -314,6 +314,14 @@ system.ruby.miss_latency_hist_seqr::gmean 665.813242 system.ruby.miss_latency_hist_seqr::stdev 238.941361 system.ruby.miss_latency_hist_seqr | 54 5.98% 5.98% | 28 3.10% 9.08% | 4 0.44% 9.52% | 3 0.33% 9.86% | 6 0.66% 10.52% | 263 29.13% 39.65% | 367 40.64% 80.29% | 113 12.51% 92.80% | 53 5.87% 98.67% | 12 1.33% 100.00% system.ruby.miss_latency_hist_seqr::total 903 +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.019672 # Average number of messages in buffer +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.800736 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.039208 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.998319 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.037345 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.998342 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseToDir.avg_buf_msgs 0.019581 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseToDir.avg_stall_time 8.079642 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 101 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 855 # Number of cache demand misses @@ -321,6 +329,9 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 956 system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 50 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 50 # Number of cache demand accesses +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 13.866976 # Average number of messages in buffer +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 7.367248 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.mandatoryQueue.num_msg_stalls 11024 # Number of times messages were stalled system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -330,16 +341,49 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l1_cntrl0.requestFromL1Cache.avg_buf_msgs 0.077552 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestFromL1Cache.avg_stall_time 1.999818 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.requestToL1Cache.avg_buf_msgs 0.006088 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestToL1Cache.avg_stall_time 6.577348 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseFromL1Cache.avg_buf_msgs 0.012176 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseFromL1Cache.avg_stall_time 1.879151 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseToL1Cache.avg_buf_msgs 0.038731 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseToL1Cache.avg_stall_time 8.395552 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 4 # Number of times a store aliased with a pending load system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 86 # Number of times a store aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 8 # Number of times a load aliased with a pending store +system.ruby.l1_cntrl0.unblockFromL1Cache.avg_buf_msgs 0.019354 # Average number of messages in buffer +system.ruby.l1_cntrl0.unblockFromL1Cache.avg_stall_time 0.998001 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states +system.ruby.l2_cntrl0.DirRequestFromL2Cache.avg_buf_msgs 0.039344 # Average number of messages in buffer +system.ruby.l2_cntrl0.DirRequestFromL2Cache.avg_stall_time 1.999455 # Average number of cycles messages are stalled in this MB +system.ruby.l2_cntrl0.L1RequestFromL2Cache.avg_buf_msgs 0.006201 # Average number of messages in buffer +system.ruby.l2_cntrl0.L1RequestFromL2Cache.avg_stall_time 0.939757 # Average number of cycles messages are stalled in this MB +system.ruby.l2_cntrl0.L1RequestToL2Cache.avg_buf_msgs 0.394962 # Average number of messages in buffer +system.ruby.l2_cntrl0.L1RequestToL2Cache.avg_stall_time 24.096134 # Average number of cycles messages are stalled in this MB +system.ruby.l2_cntrl0.L1RequestToL2Cache.num_msg_stalls 396 # Number of times messages were stalled system.ruby.l2_cntrl0.L2cache.demand_hits 39 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 866 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 905 # Number of cache demand accesses +system.ruby.l2_cntrl0.responseFromL2Cache.avg_buf_msgs 0.078756 # Average number of messages in buffer +system.ruby.l2_cntrl0.responseFromL2Cache.avg_stall_time 1.598428 # Average number of cycles messages are stalled in this MB +system.ruby.l2_cntrl0.responseToL2Cache.avg_buf_msgs 0.045273 # Average number of messages in buffer +system.ruby.l2_cntrl0.responseToL2Cache.avg_stall_time 7.165917 # Average number of cycles messages are stalled in this MB +system.ruby.l2_cntrl0.unblockToL2Cache.avg_buf_msgs 0.019354 # Average number of messages in buffer +system.ruby.l2_cntrl0.unblockToL2Cache.avg_stall_time 6.985053 # Average number of cycles messages are stalled in this MB system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.port_buffers01.avg_buf_msgs 0.038731 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers01.avg_stall_time 7.397778 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers02.avg_buf_msgs 0.006088 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers02.avg_stall_time 5.637863 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.204034 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers03.avg_stall_time 11.022807 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.006542 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers04.avg_stall_time 2.850416 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers05.avg_buf_msgs 0.019354 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers05.avg_stall_time 1.995957 # Average number of cycles messages are stalled in this MB system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 11.308239 system.ruby.network.routers0.msg_count.Control::0 905 @@ -358,6 +402,18 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 6816 system.ruby.network.routers0.msg_bytes.Writeback_Data::0 55368 system.ruby.network.routers0.msg_bytes.Writeback_Data::1 15696 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 264 +system.ruby.network.routers1.port_buffers00.avg_buf_msgs 0.038776 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers00.avg_stall_time 15.044228 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers01.avg_buf_msgs 0.045273 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers01.avg_stall_time 6.167871 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.019354 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers02.avg_stall_time 5.987325 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers03.avg_buf_msgs 0.099337 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers03.avg_stall_time 6.730339 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers04.avg_buf_msgs 0.085185 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers04.avg_stall_time 2.717936 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers05.avg_buf_msgs 0.006088 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers05.avg_stall_time 1.879469 # Average number of cycles messages are stalled in this MB system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 20.738398 system.ruby.network.routers1.msg_count.Control::0 1771 @@ -376,6 +432,12 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2 6816 system.ruby.network.routers1.msg_bytes.Writeback_Data::0 55368 system.ruby.network.routers1.msg_bytes.Writeback_Data::1 15696 system.ruby.network.routers1.msg_bytes.Writeback_Control::0 264 +system.ruby.network.routers2.port_buffers00.avg_buf_msgs 0.019672 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers00.avg_stall_time 10.801508 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers01.avg_buf_msgs 0.019581 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers01.avg_stall_time 7.082459 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.041570 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers03.avg_stall_time 2.061628 # Average number of cycles messages are stalled in this MB system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 9.432430 system.ruby.network.routers2.msg_count.Control::0 866 @@ -384,6 +446,48 @@ system.ruby.network.routers2.msg_count.Response_Control::1 943 system.ruby.network.routers2.msg_bytes.Control::0 6928 system.ruby.network.routers2.msg_bytes.Response_Data::1 118440 system.ruby.network.routers2.msg_bytes.Response_Control::1 7544 +system.ruby.network.int_link_buffers00.avg_buf_msgs 0.038776 # Average number of messages in buffer +system.ruby.network.int_link_buffers00.avg_stall_time 12.022534 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers01.avg_buf_msgs 0.006088 # Average number of messages in buffer +system.ruby.network.int_link_buffers01.avg_stall_time 3.789878 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.019354 # Average number of messages in buffer +system.ruby.network.int_link_buffers02.avg_stall_time 2.993867 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers03.avg_buf_msgs 0.019672 # Average number of messages in buffer +system.ruby.network.int_link_buffers03.avg_stall_time 7.729749 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers04.avg_buf_msgs 0.058312 # Average number of messages in buffer +system.ruby.network.int_link_buffers04.avg_stall_time 3.715892 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers05.avg_buf_msgs 0.006088 # Average number of messages in buffer +system.ruby.network.int_link_buffers05.avg_stall_time 2.819136 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers07.avg_buf_msgs 0.039208 # Average number of messages in buffer +system.ruby.network.int_link_buffers07.avg_stall_time 3.059856 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers10.avg_buf_msgs 0.038731 # Average number of messages in buffer +system.ruby.network.int_link_buffers10.avg_stall_time 6.399959 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers11.avg_buf_msgs 0.006088 # Average number of messages in buffer +system.ruby.network.int_link_buffers11.avg_stall_time 4.698333 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers12.avg_buf_msgs 0.038776 # Average number of messages in buffer +system.ruby.network.int_link_buffers12.avg_stall_time 14.044637 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.045273 # Average number of messages in buffer +system.ruby.network.int_link_buffers13.avg_stall_time 5.169779 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.019354 # Average number of messages in buffer +system.ruby.network.int_link_buffers14.avg_stall_time 4.989551 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers15.avg_buf_msgs 0.019672 # Average number of messages in buffer +system.ruby.network.int_link_buffers15.avg_stall_time 9.802235 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers16.avg_buf_msgs 0.019581 # Average number of messages in buffer +system.ruby.network.int_link_buffers16.avg_stall_time 6.085230 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers3.port_buffers01.avg_buf_msgs 0.038731 # Average number of messages in buffer +system.ruby.network.routers3.port_buffers01.avg_stall_time 5.402094 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers3.port_buffers02.avg_buf_msgs 0.006088 # Average number of messages in buffer +system.ruby.network.routers3.port_buffers02.avg_stall_time 3.758757 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers3.port_buffers03.avg_buf_msgs 0.039094 # Average number of messages in buffer +system.ruby.network.routers3.port_buffers03.avg_stall_time 13.045000 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers3.port_buffers04.avg_buf_msgs 0.046045 # Average number of messages in buffer +system.ruby.network.routers3.port_buffers04.avg_stall_time 4.171641 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers3.port_buffers05.avg_buf_msgs 0.019354 # Average number of messages in buffer +system.ruby.network.routers3.port_buffers05.avg_stall_time 3.991731 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers3.port_buffers06.avg_buf_msgs 0.021171 # Average number of messages in buffer +system.ruby.network.routers3.port_buffers06.avg_stall_time 8.802917 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers3.port_buffers07.avg_buf_msgs 0.019581 # Average number of messages in buffer +system.ruby.network.routers3.port_buffers07.avg_stall_time 5.087956 # Average number of cycles messages are stalled in this MB system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states system.ruby.network.routers3.percent_links_utilized 13.825598 system.ruby.network.routers3.msg_count.Control::0 1771 diff --git a/tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_directory/stats.txt index c3a7f3ee2..55da9bfb2 100644 --- a/tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_directory/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000057 # Nu sim_ticks 57351 # Number of ticks simulated final_tick 57351 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 527309 # Simulator tick rate (ticks/s) -host_mem_usage 410220 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_tick_rate 566783 # Simulator tick rate (ticks/s) +host_mem_usage 396800 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states @@ -311,6 +311,16 @@ system.ruby.miss_latency_hist_seqr::gmean 881.514808 system.ruby.miss_latency_hist_seqr::stdev 261.625282 system.ruby.miss_latency_hist_seqr | 55 6.05% 6.05% | 9 0.99% 7.04% | 4 0.44% 7.48% | 380 41.80% 49.28% | 412 45.32% 94.61% | 49 5.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 909 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.082752 # Average number of messages in buffer +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 5.967569 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029153 # Average number of messages in buffer +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 8.096701 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015361 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.998710 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029153 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.998727 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseToDir.avg_buf_msgs 0.029136 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseToDir.avg_stall_time 8.057888 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 88 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 859 # Number of cache demand misses @@ -318,16 +328,50 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 947 system.ruby.l1_cntrl0.L1Icache.demand_hits 2 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 50 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 52 # Number of cache demand accesses +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 14.523364 # Average number of messages in buffer +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 864.375262 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.requestFromL1Cache.avg_buf_msgs 0.063224 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestFromL1Cache.avg_stall_time 1.999861 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.requestToL1Cache.avg_buf_msgs 0.015762 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestToL1Cache.avg_stall_time 8.191536 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseFromL1Cache.avg_buf_msgs 0.063224 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseFromL1Cache.avg_stall_time 1.996792 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseToL1Cache.avg_buf_msgs 0.015849 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseToL1Cache.avg_stall_time 8.002040 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 2 # Number of times a store aliased with a pending load system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 89 # Number of times a store aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 5 # Number of times a load aliased with a pending store +system.ruby.l1_cntrl0.triggerQueue.avg_buf_msgs 0.014263 # Average number of messages in buffer +system.ruby.l1_cntrl0.triggerQueue.avg_stall_time 0.998431 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states +system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.avg_buf_msgs 0.058307 # Average number of messages in buffer +system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.avg_stall_time 1.999582 # Average number of cycles messages are stalled in this MB +system.ruby.l2_cntrl0.GlobalRequestToL2Cache.avg_buf_msgs 0.013792 # Average number of messages in buffer +system.ruby.l2_cntrl0.GlobalRequestToL2Cache.avg_stall_time 12.105995 # Average number of cycles messages are stalled in this MB +system.ruby.l2_cntrl0.L1RequestFromL2Cache.avg_buf_msgs 0.031525 # Average number of messages in buffer +system.ruby.l2_cntrl0.L1RequestFromL2Cache.avg_stall_time 1.994699 # Average number of cycles messages are stalled in this MB +system.ruby.l2_cntrl0.L1RequestToL2Cache.avg_buf_msgs 0.031612 # Average number of messages in buffer +system.ruby.l2_cntrl0.L1RequestToL2Cache.avg_stall_time 8.273016 # Average number of cycles messages are stalled in this MB system.ruby.l2_cntrl0.L2cache.demand_hits 28 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 881 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 909 # Number of cache demand accesses +system.ruby.l2_cntrl0.responseFromL2Cache.avg_buf_msgs 0.089971 # Average number of messages in buffer +system.ruby.l2_cntrl0.responseFromL2Cache.avg_stall_time 1.997106 # Average number of cycles messages are stalled in this MB +system.ruby.l2_cntrl0.responseToL2Cache.avg_buf_msgs 0.046956 # Average number of messages in buffer +system.ruby.l2_cntrl0.responseToL2Cache.avg_stall_time 7.981239 # Average number of cycles messages are stalled in this MB +system.ruby.l2_cntrl0.triggerQueue.avg_buf_msgs 0.013879 # Average number of messages in buffer +system.ruby.l2_cntrl0.triggerQueue.avg_stall_time 0.998588 # Average number of cycles messages are stalled in this MB system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.port_buffers00.avg_buf_msgs 0.015762 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers00.avg_stall_time 7.194431 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers02.avg_buf_msgs 0.015849 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers02.avg_stall_time 7.003714 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.035622 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers03.avg_stall_time 3.255039 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers05.avg_buf_msgs 0.034628 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers05.avg_stall_time 3.156385 # Average number of cycles messages are stalled in this MB system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 8.691653 system.ruby.network.routers0.msg_count.Request_Control::0 909 @@ -342,6 +386,18 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 2016 system.ruby.network.routers0.msg_bytes.Writeback_Data::2 65088 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 14464 system.ruby.network.routers0.msg_bytes.Unblock_Control::2 7264 +system.ruby.network.routers1.port_buffers00.avg_buf_msgs 0.031612 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers00.avg_stall_time 7.273312 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers01.avg_buf_msgs 0.013792 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers01.avg_stall_time 11.111696 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.046956 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers02.avg_stall_time 6.982738 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers03.avg_buf_msgs 0.019127 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers03.avg_stall_time 3.205660 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers04.avg_buf_msgs 0.030740 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers04.avg_stall_time 3.098532 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers05.avg_buf_msgs 0.048542 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers05.avg_stall_time 3.049118 # Average number of cycles messages are stalled in this MB system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 16.709822 system.ruby.network.routers1.msg_count.Request_Control::0 909 @@ -360,6 +416,14 @@ system.ruby.network.routers1.msg_bytes.Writeback_Data::2 122040 system.ruby.network.routers1.msg_bytes.Writeback_Control::0 14464 system.ruby.network.routers1.msg_bytes.Writeback_Control::1 12656 system.ruby.network.routers1.msg_bytes.Unblock_Control::2 14304 +system.ruby.network.routers2.port_buffers01.avg_buf_msgs 0.029153 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers01.avg_stall_time 7.097137 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers02.avg_buf_msgs 0.029136 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers02.avg_stall_time 7.059858 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014891 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers04.avg_stall_time 7.047653 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers05.avg_buf_msgs 0.016006 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers05.avg_stall_time 2.063241 # Average number of cycles messages are stalled in this MB system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 8.016861 system.ruby.network.routers2.msg_count.Request_Control::1 881 @@ -372,6 +436,48 @@ system.ruby.network.routers2.msg_bytes.Response_Data::2 63432 system.ruby.network.routers2.msg_bytes.Writeback_Data::2 56952 system.ruby.network.routers2.msg_bytes.Writeback_Control::1 12656 system.ruby.network.routers2.msg_bytes.Unblock_Control::2 7040 +system.ruby.network.int_link_buffers00.avg_buf_msgs 0.031612 # Average number of messages in buffer +system.ruby.network.int_link_buffers00.avg_stall_time 4.254882 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.031594 # Average number of messages in buffer +system.ruby.network.int_link_buffers02.avg_stall_time 4.154694 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers03.avg_buf_msgs 0.015762 # Average number of messages in buffer +system.ruby.network.int_link_buffers03.avg_stall_time 4.202905 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers04.avg_buf_msgs 0.029153 # Average number of messages in buffer +system.ruby.network.int_link_buffers04.avg_stall_time 4.098235 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers05.avg_buf_msgs 0.044985 # Average number of messages in buffer +system.ruby.network.int_link_buffers05.avg_stall_time 4.047583 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers07.avg_buf_msgs 0.013792 # Average number of messages in buffer +system.ruby.network.int_link_buffers07.avg_stall_time 8.042091 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015361 # Average number of messages in buffer +system.ruby.network.int_link_buffers08.avg_stall_time 3.061881 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.015762 # Average number of messages in buffer +system.ruby.network.int_link_buffers09.avg_stall_time 6.197290 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers11.avg_buf_msgs 0.015849 # Average number of messages in buffer +system.ruby.network.int_link_buffers11.avg_stall_time 6.005353 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers12.avg_buf_msgs 0.031612 # Average number of messages in buffer +system.ruby.network.int_link_buffers12.avg_stall_time 6.273574 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.013792 # Average number of messages in buffer +system.ruby.network.int_link_buffers13.avg_stall_time 10.117363 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.046956 # Average number of messages in buffer +system.ruby.network.int_link_buffers14.avg_stall_time 5.984203 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers16.avg_buf_msgs 0.029153 # Average number of messages in buffer +system.ruby.network.int_link_buffers16.avg_stall_time 6.097538 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.029136 # Average number of messages in buffer +system.ruby.network.int_link_buffers17.avg_stall_time 6.061794 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers3.port_buffers00.avg_buf_msgs 0.015762 # Average number of messages in buffer +system.ruby.network.routers3.port_buffers00.avg_stall_time 5.200115 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers3.port_buffers02.avg_buf_msgs 0.015849 # Average number of messages in buffer +system.ruby.network.routers3.port_buffers02.avg_stall_time 5.006957 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers3.port_buffers03.avg_buf_msgs 0.032030 # Average number of messages in buffer +system.ruby.network.routers3.port_buffers03.avg_stall_time 5.273800 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers3.port_buffers04.avg_buf_msgs 0.017140 # Average number of messages in buffer +system.ruby.network.routers3.port_buffers04.avg_stall_time 9.122995 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers3.port_buffers05.avg_buf_msgs 0.050792 # Average number of messages in buffer +system.ruby.network.routers3.port_buffers05.avg_stall_time 4.985633 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers3.port_buffers07.avg_buf_msgs 0.029153 # Average number of messages in buffer +system.ruby.network.routers3.port_buffers07.avg_stall_time 5.097904 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers3.port_buffers08.avg_buf_msgs 0.029136 # Average number of messages in buffer +system.ruby.network.routers3.port_buffers08.avg_stall_time 5.063694 # Average number of cycles messages are stalled in this MB system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states system.ruby.network.routers3.percent_links_utilized 11.139881 system.ruby.network.routers3.msg_count.Request_Control::0 909 diff --git a/tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_token/stats.txt index e0aa11056..a4dd0e4a7 100644 --- a/tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_token/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000054 # Nu sim_ticks 53801 # Number of ticks simulated final_tick 53801 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 784976 # Simulator tick rate (ticks/s) -host_mem_usage 409916 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 1148907 # Simulator tick rate (ticks/s) +host_mem_usage 394184 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states @@ -310,6 +310,16 @@ system.ruby.miss_latency_hist_seqr::stdev 300.791358 system.ruby.miss_latency_hist_seqr | 70 8.52% 8.52% | 6 0.73% 9.25% | 4 0.49% 9.73% | 204 24.82% 34.55% | 503 61.19% 95.74% | 35 4.26% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 822 system.ruby.Directory.incomplete_times_seqr 822 +system.ruby.dir_cntrl0.persistentToDir.avg_buf_msgs 0.000706 # Average number of messages in buffer +system.ruby.dir_cntrl0.persistentToDir.avg_stall_time 7.203896 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.015334 # Average number of messages in buffer +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.130237 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015297 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.998569 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029107 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.998587 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseToDir.avg_buf_msgs 0.015204 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseToDir.avg_stall_time 10.935597 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 92 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 820 # Number of cache demand misses @@ -317,16 +327,49 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 912 system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 48 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 48 # Number of cache demand accesses +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 14.571763 # Average number of messages in buffer +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 24.837199 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.mandatoryQueue.num_msg_stalls 22280 # Number of times messages were stalled +system.ruby.l1_cntrl0.persistentFromL1Cache.avg_buf_msgs 0.001413 # Average number of messages in buffer +system.ruby.l1_cntrl0.persistentFromL1Cache.avg_stall_time 1.410728 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.persistentToL1Cache.avg_buf_msgs 0.000706 # Average number of messages in buffer +system.ruby.l1_cntrl0.persistentToL1Cache.avg_stall_time 2.822237 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.requestFromL1Cache.avg_buf_msgs 0.064533 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestFromL1Cache.avg_stall_time 1.999851 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseFromL1Cache.avg_buf_msgs 0.032285 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseFromL1Cache.avg_stall_time 1.976135 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseToL1Cache.avg_buf_msgs 0.016356 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseToL1Cache.avg_stall_time 7.201145 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 4 # Number of times a store aliased with a pending load system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 91 # Number of times a store aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 7 # Number of times a load aliased with a pending store system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states +system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.avg_buf_msgs 0.076670 # Average number of messages in buffer +system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.avg_stall_time 4.998606 # Average number of cycles messages are stalled in this MB +system.ruby.l2_cntrl0.L1RequestToL2Cache.avg_buf_msgs 0.016133 # Average number of messages in buffer +system.ruby.l2_cntrl0.L1RequestToL2Cache.avg_stall_time 12.070443 # Average number of cycles messages are stalled in this MB system.ruby.l2_cntrl0.L2cache.demand_hits 43 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 825 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 868 # Number of cache demand accesses +system.ruby.l2_cntrl0.persistentToL2Cache.avg_buf_msgs 0.000706 # Average number of messages in buffer +system.ruby.l2_cntrl0.persistentToL2Cache.avg_stall_time 7.203896 # Average number of cycles messages are stalled in this MB +system.ruby.l2_cntrl0.responseFromL2Cache.avg_buf_msgs 0.079142 # Average number of messages in buffer +system.ruby.l2_cntrl0.responseFromL2Cache.avg_stall_time 4.970763 # Average number of cycles messages are stalled in this MB +system.ruby.l2_cntrl0.responseToL2Cache.avg_buf_msgs 0.016022 # Average number of messages in buffer +system.ruby.l2_cntrl0.responseToL2Cache.avg_stall_time 8.050407 # Average number of cycles messages are stalled in this MB system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.000725 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers03.avg_stall_time 2.116966 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.016356 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers04.avg_stall_time 6.202799 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers06.avg_buf_msgs 0.081800 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers06.avg_stall_time 7.012881 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers08.avg_buf_msgs 0.001673 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers08.avg_stall_time 3.678283 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers09.avg_buf_msgs 0.016932 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers09.avg_stall_time 3.044943 # Average number of cycles messages are stalled in this MB system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 7.774948 system.ruby.network.routers0.msg_count.Request_Control::1 868 @@ -339,6 +382,16 @@ system.ruby.network.routers0.msg_bytes.Response_Data::4 59256 system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 3168 system.ruby.network.routers0.msg_bytes.Writeback_Data::4 63936 system.ruby.network.routers0.msg_bytes.Persistent_Control::3 608 +system.ruby.network.routers1.port_buffers01.avg_buf_msgs 0.016133 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers01.avg_stall_time 11.070834 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers03.avg_buf_msgs 0.000706 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers03.avg_stall_time 6.498848 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers04.avg_buf_msgs 0.016022 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers04.avg_stall_time 7.053158 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.016747 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers07.avg_stall_time 6.087710 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers09.avg_buf_msgs 0.016672 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers09.avg_stall_time 6.054478 # Average number of cycles messages are stalled in this MB system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 7.735451 system.ruby.network.routers1.msg_count.Request_Control::1 868 @@ -353,6 +406,14 @@ system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 3168 system.ruby.network.routers1.msg_bytes.Writeback_Data::4 115560 system.ruby.network.routers1.msg_bytes.Writeback_Control::4 600 system.ruby.network.routers1.msg_bytes.Persistent_Control::3 304 +system.ruby.network.routers2.port_buffers02.avg_buf_msgs 0.015334 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers02.avg_stall_time 10.130813 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.000706 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers03.avg_stall_time 6.498848 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.015204 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers04.avg_stall_time 9.940969 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers09.avg_buf_msgs 0.015576 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers09.avg_stall_time 2.034924 # Average number of cycles messages are stalled in this MB system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 6.985000 system.ruby.network.routers2.msg_count.Request_Control::2 825 @@ -365,6 +426,46 @@ system.ruby.network.routers2.msg_bytes.Response_Data::4 59256 system.ruby.network.routers2.msg_bytes.Writeback_Data::4 53496 system.ruby.network.routers2.msg_bytes.Writeback_Control::4 600 system.ruby.network.routers2.msg_bytes.Persistent_Control::3 304 +system.ruby.network.int_link_buffers01.avg_buf_msgs 0.016133 # Average number of messages in buffer +system.ruby.network.int_link_buffers01.avg_stall_time 8.012639 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers03.avg_buf_msgs 0.000706 # Average number of messages in buffer +system.ruby.network.int_link_buffers03.avg_stall_time 4.383480 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers04.avg_buf_msgs 0.016263 # Average number of messages in buffer +system.ruby.network.int_link_buffers04.avg_stall_time 4.042340 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015334 # Average number of messages in buffer +system.ruby.network.int_link_buffers08.avg_stall_time 7.087283 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers10.avg_buf_msgs 0.016022 # Average number of messages in buffer +system.ruby.network.int_link_buffers10.avg_stall_time 7.049255 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers16.avg_buf_msgs 0.015297 # Average number of messages in buffer +system.ruby.network.int_link_buffers16.avg_stall_time 3.033419 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers22.avg_buf_msgs 0.016356 # Average number of messages in buffer +system.ruby.network.int_link_buffers22.avg_stall_time 5.204416 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers25.avg_buf_msgs 0.016133 # Average number of messages in buffer +system.ruby.network.int_link_buffers25.avg_stall_time 10.071187 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers27.avg_buf_msgs 0.000706 # Average number of messages in buffer +system.ruby.network.int_link_buffers27.avg_stall_time 5.793762 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers28.avg_buf_msgs 0.016022 # Average number of messages in buffer +system.ruby.network.int_link_buffers28.avg_stall_time 6.055872 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers32.avg_buf_msgs 0.015334 # Average number of messages in buffer +system.ruby.network.int_link_buffers32.avg_stall_time 9.131352 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers33.avg_buf_msgs 0.000706 # Average number of messages in buffer +system.ruby.network.int_link_buffers33.avg_stall_time 5.793762 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers34.avg_buf_msgs 0.015204 # Average number of messages in buffer +system.ruby.network.int_link_buffers34.avg_stall_time 8.946303 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers3.port_buffers04.avg_buf_msgs 0.016449 # Average number of messages in buffer +system.ruby.network.routers3.port_buffers04.avg_stall_time 4.205996 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers3.port_buffers07.avg_buf_msgs 0.017063 # Average number of messages in buffer +system.ruby.network.routers3.port_buffers07.avg_stall_time 9.071503 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers3.port_buffers09.avg_buf_msgs 0.000706 # Average number of messages in buffer +system.ruby.network.routers3.port_buffers09.avg_stall_time 5.088640 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers3.port_buffers10.avg_buf_msgs 0.016022 # Average number of messages in buffer +system.ruby.network.routers3.port_buffers10.avg_stall_time 5.058548 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers3.port_buffers14.avg_buf_msgs 0.015947 # Average number of messages in buffer +system.ruby.network.routers3.port_buffers14.avg_stall_time 8.131854 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers3.port_buffers15.avg_buf_msgs 0.000706 # Average number of messages in buffer +system.ruby.network.routers3.port_buffers15.avg_stall_time 5.088640 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers3.port_buffers16.avg_buf_msgs 0.015464 # Average number of messages in buffer +system.ruby.network.routers3.port_buffers16.avg_stall_time 7.951600 # Average number of cycles messages are stalled in this MB system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states system.ruby.network.routers3.percent_links_utilized 7.498621 system.ruby.network.routers3.msg_count.Request_Control::1 868 diff --git a/tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_hammer/stats.txt index 43510f355..bfef52611 100644 --- a/tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_hammer/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000031 # Nu sim_ticks 31071 # Number of ticks simulated final_tick 31071 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 307258 # Simulator tick rate (ticks/s) -host_mem_usage 409592 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 718641 # Simulator tick rate (ticks/s) +host_mem_usage 392596 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states @@ -308,9 +308,20 @@ system.ruby.miss_latency_hist_seqr::stdev 216.457686 system.ruby.miss_latency_hist_seqr | 122 14.19% 14.19% | 9 1.05% 15.23% | 5 0.58% 15.81% | 55 6.40% 22.21% | 380 44.19% 66.40% | 233 27.09% 93.49% | 55 6.40% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 860 system.ruby.Directory.incomplete_times_seqr 860 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.055098 # Average number of messages in buffer +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 1.993950 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.079332 # Average number of messages in buffer +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 9.743402 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.requestToDir.num_msg_stalls 247 # Number of times messages were stalled +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.027710 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.997779 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.052877 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.997812 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.unblockToDir.avg_buf_msgs 0.055098 # Average number of messages in buffer +system.ruby.dir_cntrl0.unblockToDir.avg_stall_time 16.445417 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 79 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 852 # Number of cache demand misses @@ -321,13 +332,34 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 63 system.ruby.l1_cntrl0.L2cache.demand_hits 54 # Number of cache demand hits system.ruby.l1_cntrl0.L2cache.demand_misses 861 # Number of cache demand misses system.ruby.l1_cntrl0.L2cache.demand_accesses 915 # Number of cache demand accesses +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.027549 # Average number of messages in buffer +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 7.992179 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 13.810859 # Average number of messages in buffer +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 11.674884 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.mandatoryQueue.num_msg_stalls 17591 # Number of times messages were stalled +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.110582 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999743 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.027710 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 7.080072 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 3 # Number of times a store aliased with a pending load system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 84 # Number of times a store aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 7 # Number of times a load aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load +system.ruby.l1_cntrl0.triggerQueue.avg_buf_msgs 0.045411 # Average number of messages in buffer +system.ruby.l1_cntrl0.triggerQueue.avg_stall_time 1.709803 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.unblockFromCache.avg_buf_msgs 0.551686 # Average number of messages in buffer +system.ruby.l1_cntrl0.unblockFromCache.avg_stall_time 9.972322 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.027549 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers03.avg_stall_time 6.995623 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.027710 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers04.avg_stall_time 6.082679 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.063755 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers07.avg_stall_time 3.199504 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers10.avg_buf_msgs 0.069355 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers10.avg_stall_time 11.461992 # Average number of cycles messages are stalled in this MB system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 14.722732 system.ruby.network.routers0.msg_count.Request_Control::2 863 @@ -344,6 +376,14 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2 6840 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 6848 system.ruby.network.routers0.msg_bytes.Writeback_Control::5 568 system.ruby.network.routers0.msg_bytes.Unblock_Control::5 6872 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.055291 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers02.avg_stall_time 7.197960 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers05.avg_buf_msgs 0.055130 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers05.avg_stall_time 15.448861 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers09.avg_buf_msgs 0.027871 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers09.avg_stall_time 3.008754 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers10.avg_buf_msgs 0.029480 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers10.avg_stall_time 2.092463 # Average number of cycles messages are stalled in this MB system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 14.717100 system.ruby.network.routers1.msg_count.Request_Control::2 863 @@ -360,6 +400,30 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::2 6840 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 6848 system.ruby.network.routers1.msg_bytes.Writeback_Control::5 568 system.ruby.network.routers1.msg_bytes.Unblock_Control::5 6872 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.055291 # Average number of messages in buffer +system.ruby.network.int_link_buffers02.avg_stall_time 4.199215 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers05.avg_buf_msgs 0.055130 # Average number of messages in buffer +system.ruby.network.int_link_buffers05.avg_stall_time 12.458805 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.027549 # Average number of messages in buffer +system.ruby.network.int_link_buffers09.avg_stall_time 4.005568 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers10.avg_buf_msgs 0.027710 # Average number of messages in buffer +system.ruby.network.int_link_buffers10.avg_stall_time 3.090113 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers15.avg_buf_msgs 0.027549 # Average number of messages in buffer +system.ruby.network.int_link_buffers15.avg_stall_time 5.999002 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers16.avg_buf_msgs 0.027710 # Average number of messages in buffer +system.ruby.network.int_link_buffers16.avg_stall_time 5.085221 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers20.avg_buf_msgs 0.055291 # Average number of messages in buffer +system.ruby.network.int_link_buffers20.avg_stall_time 6.198442 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers23.avg_buf_msgs 0.055130 # Average number of messages in buffer +system.ruby.network.int_link_buffers23.avg_stall_time 14.452240 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.027549 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers03.avg_stall_time 5.002317 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.027710 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers04.avg_stall_time 4.087700 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers08.avg_buf_msgs 0.055291 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers08.avg_stall_time 5.198861 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers11.avg_buf_msgs 0.055130 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers11.avg_stall_time 13.455555 # Average number of cycles messages are stalled in this MB system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 14.720318 system.ruby.network.routers2.msg_count.Request_Control::2 863 diff --git a/tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby/stats.txt index 0fabd5bae..22b31e012 100644 --- a/tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby/stats.txt +++ b/tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby/stats.txt @@ -4,8 +4,8 @@ sim_seconds 0.000039 # Nu sim_ticks 39431 # Number of ticks simulated final_tick 39431 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 979592 # Simulator tick rate (ticks/s) -host_mem_usage 407616 # Number of bytes of host memory used +host_tick_rate 995299 # Simulator tick rate (ticks/s) +host_mem_usage 392160 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks @@ -315,16 +315,38 @@ system.ruby.miss_latency_hist_seqr::stdev 106.107284 system.ruby.miss_latency_hist_seqr | 2 0.21% 0.21% | 7 0.74% 0.96% | 6 0.64% 1.60% | 71 7.55% 9.15% | 434 46.17% 55.32% | 354 37.66% 92.98% | 33 3.51% 96.49% | 33 3.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 940 system.ruby.Directory.incomplete_times_seqr 940 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.023788 # Average number of messages in buffer +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.997388 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.047652 # Average number of messages in buffer +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 16.301050 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.023864 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.998250 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.047652 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.998276 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 42 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 941 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 983 # Number of cache demand accesses +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.023788 # Average number of messages in buffer +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 7.382152 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 13.964749 # Average number of messages in buffer +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 523.362675 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.095303 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999797 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.023839 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.986686 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 14 # Number of times a store aliased with a pending load system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 141 # Number of times a store aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 15 # Number of times a load aliased with a pending store system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.023788 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers03.avg_stall_time 6.385068 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.023839 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.988740 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.261894 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers07.avg_stall_time 11.303840 # Average number of cycles messages are stalled in this MB system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 11.905607 system.ruby.network.routers0.msg_count.Control::2 941 @@ -335,6 +357,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 7528 system.ruby.network.routers0.msg_bytes.Data::2 67536 system.ruby.network.routers0.msg_bytes.Response_Data::4 67680 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 7504 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.047652 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers02.avg_stall_time 15.301709 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.029063 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers06.avg_stall_time 2.396226 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.023864 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.996450 # Average number of cycles messages are stalled in this MB system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 11.910045 system.ruby.network.routers1.msg_count.Control::2 941 @@ -345,6 +373,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 7528 system.ruby.network.routers1.msg_bytes.Data::2 67536 system.ruby.network.routers1.msg_bytes.Response_Data::4 67752 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 7504 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.047652 # Average number of messages in buffer +system.ruby.network.int_link_buffers02.avg_stall_time 12.303383 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.023788 # Average number of messages in buffer +system.ruby.network.int_link_buffers08.avg_stall_time 3.393513 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.023864 # Average number of messages in buffer +system.ruby.network.int_link_buffers09.avg_stall_time 2.994598 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.023788 # Average number of messages in buffer +system.ruby.network.int_link_buffers13.avg_stall_time 5.387934 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.023839 # Average number of messages in buffer +system.ruby.network.int_link_buffers14.avg_stall_time 4.990744 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.047652 # Average number of messages in buffer +system.ruby.network.int_link_buffers17.avg_stall_time 14.302318 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.023788 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers03.avg_stall_time 4.390749 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.023864 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.992696 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.047652 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers07.avg_stall_time 13.302876 # Average number of cycles messages are stalled in this MB system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 11.907509 system.ruby.network.routers2.msg_count.Control::2 941 |