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authorNilay Vaish <nilay@cs.wisc.edu>2015-09-15 08:14:09 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-09-15 08:14:09 -0500
commit0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e (patch)
tree45d559d0511bdca749a08a2f42eeafdcf25739cf /tests/quick
parent3de9def6c1ad38d6a5068b07512cbefffafcb758 (diff)
downloadgem5-0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e.tar.xz
stats: updates due to recent changesets including d0934b57735a
Diffstat (limited to 'tests/quick')
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini30
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini20
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini30
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal2
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini20
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal2
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini23
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json45
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini31
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini23
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini31
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini23
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini23
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini23
-rw-r--r--tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini12
-rw-r--r--tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini12
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt464
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout12
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt1198
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt326
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt885
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt386
-rwxr-xr-xtests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout14
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt974
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt1094
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt1028
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt1212
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini1
-rw-r--r--tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt1412
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt1174
-rwxr-xr-xtests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout68
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt4419
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini1
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr147
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini1
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr147
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini1
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr147
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini1
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr147
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini1
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr147
-rw-r--r--tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini1
-rw-r--r--tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini1
-rw-r--r--tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini1
-rw-r--r--tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini1
-rw-r--r--tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini1
57 files changed, 7892 insertions, 7880 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index 78cb13dcc..b567a20c2 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -98,7 +98,7 @@ dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
[system.cpu0.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
@@ -107,7 +107,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
-is_top_level=true
+is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@@ -118,7 +118,6 @@ size=32768
system=system
tags=system.cpu0.dcache.tags
tgts_per_mshr=20
-two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
mem_side=system.toL2Bus.slave[1]
@@ -139,7 +138,7 @@ eventq_index=0
size=64
[system.cpu0.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
@@ -148,7 +147,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
-is_top_level=true
+is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@@ -159,7 +158,6 @@ size=32768
system=system
tags=system.cpu0.icache.tags
tgts_per_mshr=20
-two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.slave[0]
@@ -230,7 +228,7 @@ dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side
[system.cpu1.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
@@ -239,7 +237,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
-is_top_level=true
+is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@@ -250,7 +248,6 @@ size=32768
system=system
tags=system.cpu1.dcache.tags
tgts_per_mshr=20
-two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
mem_side=system.toL2Bus.slave[3]
@@ -271,7 +268,7 @@ eventq_index=0
size=64
[system.cpu1.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
@@ -280,7 +277,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
-is_top_level=true
+is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@@ -291,7 +288,6 @@ size=32768
system=system
tags=system.cpu1.icache.tags
tgts_per_mshr=20
-two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.slave[2]
@@ -405,7 +401,7 @@ master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
[system.iocache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:134217727
assoc=8
@@ -414,7 +410,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
-is_top_level=true
+is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@@ -425,7 +421,6 @@ size=1024
system=system
tags=system.iocache.tags
tgts_per_mshr=12
-two_queue=false
write_buffers=8
cpu_side=system.iobus.master[29]
mem_side=system.membus.slave[2]
@@ -441,7 +436,7 @@ sequential_access=false
size=1024
[system.l2c]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
@@ -450,7 +445,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
-is_top_level=false
+is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@@ -461,7 +456,6 @@ size=4194304
system=system
tags=system.l2c.tags
tgts_per_mshr=12
-two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[1]
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index 0b689db35..8a8f59ba6 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -98,7 +98,7 @@ dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
@@ -107,7 +107,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
-is_top_level=true
+is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@@ -118,7 +118,6 @@ size=32768
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
-two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -139,7 +138,7 @@ eventq_index=0
size=64
[system.cpu.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
@@ -148,7 +147,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
-is_top_level=true
+is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@@ -159,7 +158,6 @@ size=32768
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
-two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@@ -189,7 +187,7 @@ eventq_index=0
size=48
[system.cpu.l2cache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
@@ -198,7 +196,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
-is_top_level=false
+is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@@ -209,7 +207,6 @@ size=4194304
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
-two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@@ -324,7 +321,7 @@ master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
[system.iocache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:134217727
assoc=8
@@ -333,7 +330,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
-is_top_level=true
+is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@@ -344,7 +341,6 @@ size=1024
system=system
tags=system.iocache.tags
tgts_per_mshr=12
-two_queue=false
write_buffers=8
cpu_side=system.iobus.master[29]
mem_side=system.membus.slave[2]
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index 6dd8362e8..e1d35dff5 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -94,7 +94,7 @@ dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
[system.cpu0.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
@@ -103,7 +103,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
-is_top_level=true
+is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@@ -114,7 +114,6 @@ size=32768
system=system
tags=system.cpu0.dcache.tags
tgts_per_mshr=20
-two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
mem_side=system.toL2Bus.slave[1]
@@ -135,7 +134,7 @@ eventq_index=0
size=64
[system.cpu0.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
@@ -144,7 +143,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
-is_top_level=true
+is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@@ -155,7 +154,6 @@ size=32768
system=system
tags=system.cpu0.icache.tags
tgts_per_mshr=20
-two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.slave[0]
@@ -222,7 +220,7 @@ dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side
[system.cpu1.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
@@ -231,7 +229,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
-is_top_level=true
+is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@@ -242,7 +240,6 @@ size=32768
system=system
tags=system.cpu1.dcache.tags
tgts_per_mshr=20
-two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
mem_side=system.toL2Bus.slave[3]
@@ -263,7 +260,7 @@ eventq_index=0
size=64
[system.cpu1.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
@@ -272,7 +269,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
-is_top_level=true
+is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@@ -283,7 +280,6 @@ size=32768
system=system
tags=system.cpu1.icache.tags
tgts_per_mshr=20
-two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.slave[2]
@@ -397,7 +393,7 @@ master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
[system.iocache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:134217727
assoc=8
@@ -406,7 +402,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
-is_top_level=true
+is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@@ -417,7 +413,6 @@ size=1024
system=system
tags=system.iocache.tags
tgts_per_mshr=12
-two_queue=false
write_buffers=8
cpu_side=system.iobus.master[29]
mem_side=system.membus.slave[2]
@@ -433,7 +428,7 @@ sequential_access=false
size=1024
[system.l2c]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
@@ -442,7 +437,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
-is_top_level=false
+is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@@ -453,7 +448,6 @@ size=4194304
system=system
tags=system.l2c.tags
tgts_per_mshr=12
-two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[1]
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
index 9e87f65da..8176c3d31 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
@@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070
- 4096K Bcache detected; load hit latency 38 cycles, load miss latency 148 cycles
+ 4096K Bcache detected; load hit latency 38 cycles, load miss latency 160 cycles
SMP: 2 CPUs probed -- cpu_present_mask = 3
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 586901b21..191ca5cbb 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -94,7 +94,7 @@ dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
@@ -103,7 +103,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
-is_top_level=true
+is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@@ -114,7 +114,6 @@ size=32768
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
-two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -135,7 +134,7 @@ eventq_index=0
size=64
[system.cpu.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
@@ -144,7 +143,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
-is_top_level=true
+is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@@ -155,7 +154,6 @@ size=32768
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
-two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@@ -185,7 +183,7 @@ eventq_index=0
size=48
[system.cpu.l2cache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
@@ -194,7 +192,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
-is_top_level=false
+is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@@ -205,7 +203,6 @@ size=4194304
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
-two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@@ -320,7 +317,7 @@ master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
[system.iocache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:134217727
assoc=8
@@ -329,7 +326,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
-is_top_level=true
+is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@@ -340,7 +337,6 @@ size=1024
system=system
tags=system.iocache.tags
tgts_per_mshr=12
-two_queue=false
write_buffers=8
cpu_side=system.iobus.master[29]
mem_side=system.membus.slave[2]
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
index d6ca9b555..64d8e02a2 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
@@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070
- 4096K Bcache detected; load hit latency 38 cycles, load miss latency 148 cycles
+ 4096K Bcache detected; load hit latency 38 cycles, load miss latency 160 cycles
SMP: 1 CPUs probed -- cpu_present_mask = 1
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini
index 92530cc80..5d89a381f 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
@@ -136,7 +136,7 @@ dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
@@ -212,7 +212,7 @@ sys=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
@@ -322,7 +322,7 @@ sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
@@ -410,7 +410,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=2147483648:2415919103
assoc=8
@@ -761,9 +761,12 @@ gic=system.realview.gic
int_num=117
pio_addr=721420288
pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
system=system
vnc=system.vncserver
+workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json
index 72353edee..47529e9ec 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json
@@ -6,7 +6,7 @@
"mmap_using_noreserve": false,
"kernel_addr_check": true,
"highest_el_is_64": false,
- "kernel": "/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5",
+ "kernel": "/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5",
"iobus": {
"slave": {
"peer": [
@@ -68,7 +68,7 @@
"frontend_latency": 2
},
"symbolfile": "",
- "readfile": "/work/gem5/outgoing/gem5/tests/halt.sh",
+ "readfile": "/scratch/nilay/GEM5/gem5/tests/halt.sh",
"have_large_asid_64": false,
"phys_addr_range_64": 40,
"have_lpae": false,
@@ -87,7 +87,7 @@
"multi_proc": true,
"early_kernel_symbols": false,
"panic_on_oops": true,
- "dtb_filename": "/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb",
+ "dtb_filename": "/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb",
"enable_context_switch_stats_dump": false,
"work_begin_ckpt_count": 0,
"clk_domain": {
@@ -108,30 +108,33 @@
],
"realview": {
"hdlcd": {
- "dma": {
- "peer": "system.membus.slave[0]",
- "role": "MASTER"
- },
- "pixel_clock": 7299,
"vnc": "system.vncserver",
+ "pxl_clk": "system.realview.realview_io.osc_pxl",
"name": "hdlcd",
+ "workaround_dma_line_count": true,
+ "amba_id": 1314816,
"pio": {
"peer": "system.iobus.master[5]",
"role": "SLAVE"
},
- "amba_id": 1314816,
"pio_latency": 10000,
"clk_domain": "system.clk_domain",
"system": "system",
"gic": "system.realview.gic",
"int_num": 117,
"eventq_index": 0,
+ "pixel_buffer_size": 2048,
"cxx_class": "HDLcd",
"enable_capture": true,
"path": "system.realview.hdlcd",
"pio_addr": 721420288,
"workaround_swap_rb": true,
- "type": "HDLcd"
+ "type": "HDLcd",
+ "pixel_chunk": 32,
+ "dma": {
+ "peer": "system.membus.slave[0]",
+ "role": "MASTER"
+ }
},
"mmc_fake": {
"name": "mmc_fake",
@@ -893,7 +896,7 @@
"MSIXCAPNextCapability": 0,
"PXCAPLinkCtrl": 0,
"Revision": 0,
- "hardware_address": "<m5.params.EthernetAddr object at 0x7f90678a01d0>",
+ "hardware_address": "<m5.params.EthernetAddr object at 0x488d6d0>",
"LegacyIOBase": 0,
"pio_latency": 30000,
"platform": "system.realview",
@@ -1176,7 +1179,7 @@
"clk_domain": "system.clk_domain",
"write_buffers": 8,
"response_latency": 50,
- "cxx_class": "BaseCache",
+ "cxx_class": "Cache",
"size": 1024,
"tags": {
"name": "tags",
@@ -1210,7 +1213,7 @@
"prefetch_on_access": false,
"path": "system.iocache",
"name": "iocache",
- "type": "BaseCache",
+ "type": "Cache",
"sequential_access": false,
"assoc": 8
},
@@ -1416,7 +1419,7 @@
"clk_domain": "system.cpu_clk_domain",
"write_buffers": 8,
"response_latency": 2,
- "cxx_class": "BaseCache",
+ "cxx_class": "Cache",
"size": 32768,
"tags": {
"name": "tags",
@@ -1450,7 +1453,7 @@
"prefetch_on_access": false,
"path": "system.cpu.icache",
"name": "icache",
- "type": "BaseCache",
+ "type": "Cache",
"sequential_access": false,
"assoc": 1
},
@@ -1505,7 +1508,7 @@
"clk_domain": "system.cpu_clk_domain",
"write_buffers": 8,
"response_latency": 20,
- "cxx_class": "BaseCache",
+ "cxx_class": "Cache",
"size": 4194304,
"tags": {
"name": "tags",
@@ -1539,7 +1542,7 @@
"prefetch_on_access": false,
"path": "system.cpu.l2cache",
"name": "l2cache",
- "type": "BaseCache",
+ "type": "Cache",
"sequential_access": false,
"assoc": 8
},
@@ -1586,7 +1589,7 @@
"clk_domain": "system.cpu_clk_domain",
"write_buffers": 8,
"response_latency": 2,
- "cxx_class": "BaseCache",
+ "cxx_class": "Cache",
"size": 32768,
"tags": {
"name": "tags",
@@ -1620,7 +1623,7 @@
"prefetch_on_access": false,
"path": "system.cpu.dcache",
"name": "dcache",
- "type": "BaseCache",
+ "type": "Cache",
"sequential_access": false,
"assoc": 4
},
@@ -1701,7 +1704,7 @@
"eventq_index": 0,
"cxx_class": "RawDiskImage",
"path": "system.cf0.image.child",
- "image_file": "/work/gem5/dist/disks/linux-aarch32-ael.img",
+ "image_file": "/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img",
"type": "RawDiskImage"
},
"path": "system.cf0.image",
@@ -1741,7 +1744,7 @@
"system.realview.vram"
],
"work_begin_cpu_id_exit": -1,
- "boot_loader": "/work/gem5/dist/binaries/boot_emm.arm",
+ "boot_loader": "/scratch/nilay/GEM5/system/binaries/boot_emm.arm",
"num_work_ids": 16
},
"time_sync_period": 100000000000,
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
index bf070ce25..87bce23ee 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
@@ -136,7 +136,7 @@ dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
[system.cpu0.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -212,7 +212,7 @@ sys=system
port=system.cpu0.toL2Bus.slave[3]
[system.cpu0.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -322,7 +322,7 @@ sys=system
port=system.cpu0.toL2Bus.slave[2]
[system.cpu0.l2cache]
-type=BaseCache
+type=Cache
children=prefetcher tags
addr_ranges=0:18446744073709551615
assoc=16
@@ -440,7 +440,7 @@ dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side
[system.cpu1.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -516,7 +516,7 @@ sys=system
port=system.cpu1.toL2Bus.slave[3]
[system.cpu1.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -626,7 +626,7 @@ sys=system
port=system.cpu1.toL2Bus.slave[2]
[system.cpu1.l2cache]
-type=BaseCache
+type=Cache
children=prefetcher tags
addr_ranges=0:18446744073709551615
assoc=16
@@ -739,7 +739,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=2147483648:2415919103
assoc=8
@@ -774,7 +774,7 @@ sequential_access=false
size=1024
[system.l2c]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
@@ -1125,9 +1125,12 @@ gic=system.realview.gic
int_num=117
pio_addr=721420288
pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
system=system
vnc=system.vncserver
+workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
index 92530cc80..5d89a381f 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
@@ -136,7 +136,7 @@ dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
@@ -212,7 +212,7 @@ sys=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
@@ -322,7 +322,7 @@ sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
@@ -410,7 +410,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=2147483648:2415919103
assoc=8
@@ -761,9 +761,12 @@ gic=system.realview.gic
int_num=117
pio_addr=721420288
pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
system=system
vnc=system.vncserver
+workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index 8cc96dcc1..c265e688a 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
@@ -132,7 +132,7 @@ dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
[system.cpu0.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -208,7 +208,7 @@ sys=system
port=system.cpu0.toL2Bus.slave[3]
[system.cpu0.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -318,7 +318,7 @@ sys=system
port=system.cpu0.toL2Bus.slave[2]
[system.cpu0.l2cache]
-type=BaseCache
+type=Cache
children=prefetcher tags
addr_ranges=0:18446744073709551615
assoc=16
@@ -432,7 +432,7 @@ dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side
[system.cpu1.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -508,7 +508,7 @@ sys=system
port=system.cpu1.toL2Bus.slave[3]
[system.cpu1.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -618,7 +618,7 @@ sys=system
port=system.cpu1.toL2Bus.slave[2]
[system.cpu1.l2cache]
-type=BaseCache
+type=Cache
children=prefetcher tags
addr_ranges=0:18446744073709551615
assoc=16
@@ -731,7 +731,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=2147483648:2415919103
assoc=8
@@ -766,7 +766,7 @@ sequential_access=false
size=1024
[system.l2c]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
@@ -1181,9 +1181,12 @@ gic=system.realview.gic
int_num=117
pio_addr=721420288
pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
system=system
vnc=system.vncserver
+workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index 8b289555b..97c6a61d0 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
@@ -132,7 +132,7 @@ dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
@@ -208,7 +208,7 @@ sys=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
@@ -318,7 +318,7 @@ sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
@@ -406,7 +406,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=2147483648:2415919103
assoc=8
@@ -821,9 +821,12 @@ gic=system.realview.gic
int_num=117
pio_addr=721420288
pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
system=system
vnc=system.vncserver
+workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
index d3065f7a2..48de3cce2 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
@@ -136,7 +136,7 @@ dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
[system.cpu0.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
@@ -212,7 +212,7 @@ sys=system
port=system.toL2Bus.slave[3]
[system.cpu0.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
@@ -511,7 +511,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=2147483648:2415919103
assoc=8
@@ -546,7 +546,7 @@ sequential_access=false
size=1024
[system.l2c]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
@@ -897,9 +897,12 @@ gic=system.realview.gic
int_num=117
pio_addr=721420288
pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
system=system
vnc=system.vncserver
+workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
index c837f36d0..57e7a28ac 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
@@ -132,7 +132,7 @@ dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
[system.cpu0.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
@@ -208,7 +208,7 @@ sys=system
port=system.toL2Bus.slave[3]
[system.cpu0.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
@@ -503,7 +503,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=2147483648:2415919103
assoc=8
@@ -538,7 +538,7 @@ sequential_access=false
size=1024
[system.l2c]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
@@ -953,9 +953,12 @@ gic=system.realview.gic
int_num=117
pio_addr=721420288
pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
system=system
vnc=system.vncserver
+workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
index be7901250..84c6f9a49 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
@@ -134,7 +134,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
[system.cpu.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
@@ -184,7 +184,7 @@ system=system
port=system.cpu.dtb_walker_cache.cpu_side
[system.cpu.dtb_walker_cache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -219,7 +219,7 @@ sequential_access=false
size=1024
[system.cpu.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
@@ -285,7 +285,7 @@ system=system
port=system.cpu.itb_walker_cache.cpu_side
[system.cpu.itb_walker_cache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -320,7 +320,7 @@ sequential_access=false
size=1024
[system.cpu.l2cache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
@@ -827,7 +827,7 @@ master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_b
slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
[system.iocache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:134217727
assoc=8
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
index 1ddef3c2e..f5be22536 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
@@ -130,7 +130,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
[system.cpu.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
@@ -180,7 +180,7 @@ system=system
port=system.cpu.dtb_walker_cache.cpu_side
[system.cpu.dtb_walker_cache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -215,7 +215,7 @@ sequential_access=false
size=1024
[system.cpu.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
@@ -281,7 +281,7 @@ system=system
port=system.cpu.itb_walker_cache.cpu_side
[system.cpu.itb_walker_cache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -316,7 +316,7 @@ sequential_access=false
size=1024
[system.cpu.l2cache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
@@ -823,7 +823,7 @@ master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_b
slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
[system.iocache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:134217727
assoc=8
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
index b5554ceae..1a6e00d22 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000038 # Number of seconds simulated
-sim_ticks 37623000 # Number of ticks simulated
-final_tick 37623000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 37552000 # Number of ticks simulated
+final_tick 37552000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 152308 # Simulator instruction rate (inst/s)
-host_op_rate 152258 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 894784408 # Simulator tick rate (ticks/s)
-host_mem_usage 293572 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
+host_inst_rate 72134 # Simulator instruction rate (inst/s)
+host_op_rate 72118 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 423067865 # Simulator tick rate (ticks/s)
+host_mem_usage 288748 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
sim_insts 6400 # Number of instructions simulated
sim_ops 6400 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 23296 # Nu
system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory
system.physmem.num_reads::total 533 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 619195705 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 287483720 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 906679425 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 619195705 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 619195705 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 619195705 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 287483720 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 906679425 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 620366425 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 288027269 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 908393694 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 620366425 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 620366425 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 620366425 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 288027269 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 908393694 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 533 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 37518500 # Total gap between requests
+system.physmem.totGap 37447500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@@ -188,8 +188,8 @@ system.physmem.wrQLenPdf::62 0 # Wh
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 84 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 384 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 247.494057 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 333.812732 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 247.290862 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 334.108272 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 20 23.81% 23.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 19 22.62% 46.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 10 11.90% 58.33% # Bytes accessed per row activation
@@ -200,19 +200,19 @@ system.physmem.bytesPerActivate::768-895 3 3.57% 83.33% # By
system.physmem.bytesPerActivate::896-1023 6 7.14% 90.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8 9.52% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 84 # Bytes accessed per row activation
-system.physmem.totQLat 3336750 # Total ticks spent queuing
-system.physmem.totMemAccLat 13330500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 3307750 # Total ticks spent queuing
+system.physmem.totMemAccLat 13301500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 6260.32 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 6205.91 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 25010.32 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 906.68 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 24955.91 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 908.39 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 906.68 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 908.39 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 7.08 # Data bus utilization in percentage
-system.physmem.busUtilRead 7.08 # Data bus utilization in percentage for reads
+system.physmem.busUtil 7.10 # Data bus utilization in percentage
+system.physmem.busUtilRead 7.10 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
@@ -220,7 +220,7 @@ system.physmem.readRowHits 437 # Nu
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 70391.18 # Average gap between requests
+system.physmem.avgGap 70257.97 # Average gap between requests
system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 226800 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 123750 # Energy for precharge commands per rank (pJ)
@@ -231,32 +231,32 @@ system.physmem_0.actBackEnergy 21178350 # En
system.physmem_0.preBackEnergy 265500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 25872240 # Total energy per rank (pJ)
system.physmem_0.averagePower 823.825505 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 435750 # Time in different power states
+system.physmem_0.memoryStateTime::IDLE 346000 # Time in different power states
system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 30032750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 347760 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 189750 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1544400 # Energy for read commands per rank (pJ)
+system.physmem_1.readEnergy 1552200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 20558475 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 809250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 25483875 # Total energy per rank (pJ)
-system.physmem_1.averagePower 811.459163 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 1209750 # Time in different power states
+system.physmem_1.actBackEnergy 20535390 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 831750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 25491090 # Total energy per rank (pJ)
+system.physmem_1.averagePower 811.591993 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 1333500 # Time in different power states
system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 29169000 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 29134000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 1965 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1205 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 1556 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 382 # Number of BTB hits
+system.cpu.branchPred.lookups 1929 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1187 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 360 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1557 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 398 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 24.550129 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 25.561978 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
@@ -264,22 +264,22 @@ system.cpu.dtb.fetch_hits 0 # IT
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 1371 # DTB read hits
+system.cpu.dtb.read_hits 1369 # DTB read hits
system.cpu.dtb.read_misses 11 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 1382 # DTB read accesses
+system.cpu.dtb.read_accesses 1380 # DTB read accesses
system.cpu.dtb.write_hits 884 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 887 # DTB write accesses
-system.cpu.dtb.data_hits 2255 # DTB hits
+system.cpu.dtb.data_hits 2253 # DTB hits
system.cpu.dtb.data_misses 14 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 2269 # DTB accesses
-system.cpu.itb.fetch_hits 2639 # ITB hits
+system.cpu.dtb.data_accesses 2267 # DTB accesses
+system.cpu.itb.fetch_hits 2651 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 2656 # ITB accesses
+system.cpu.itb.fetch_accesses 2668 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -293,40 +293,40 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 75246 # number of cpu cycles simulated
+system.cpu.numCycles 75104 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6400 # Number of instructions committed
system.cpu.committedOps 6400 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 1115 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 1085 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 11.757188 # CPI: cycles per instruction
-system.cpu.ipc 0.085054 # IPC: instructions per cycle
-system.cpu.tickCycles 12577 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 62669 # Total number of cycles that the object has spent stopped
+system.cpu.cpi 11.735000 # CPI: cycles per instruction
+system.cpu.ipc 0.085215 # IPC: instructions per cycle
+system.cpu.tickCycles 12517 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 62587 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 103.998872 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 1975 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 103.919220 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 1972 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 11.686391 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 11.668639 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 103.998872 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.025390 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.025390 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 103.919220 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.025371 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.025371 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 4573 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 4573 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1235 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1235 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 4567 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 4567 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1232 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1232 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1975 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1975 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1975 # number of overall hits
-system.cpu.dcache.overall_hits::total 1975 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 1972 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1972 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1972 # number of overall hits
+system.cpu.dcache.overall_hits::total 1972 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 102 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses
@@ -335,38 +335,38 @@ system.cpu.dcache.demand_misses::cpu.data 227 # n
system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 227 # number of overall misses
system.cpu.dcache.overall_misses::total 227 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 8109500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 8109500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 9137500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 9137500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 17247000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 17247000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 17247000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 17247000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1337 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1337 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 8311500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 8311500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 9136500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 9136500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 17448000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 17448000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 17448000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 17448000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1334 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1334 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2202 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2202 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2202 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2202 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076290 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.076290 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2199 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2199 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2199 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2199 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076462 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.076462 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.103088 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.103088 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.103088 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.103088 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79504.901961 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 79504.901961 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73100 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 73100 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 75977.973568 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 75977.973568 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 75977.973568 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 75977.973568 # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.103229 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.103229 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.103229 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.103229 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81485.294118 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 81485.294118 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73092 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 73092 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 76863.436123 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 76863.436123 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 76863.436123 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 76863.436123 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -391,82 +391,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 169
system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7616500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 7616500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5372000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 5372000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12988500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 12988500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12988500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 12988500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071803 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071803 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7818500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 7818500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5371500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5371500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13190000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 13190000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13190000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 13190000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071964 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071964 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.076748 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.076748 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79338.541667 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79338.541667 # average ReadReq mshr miss latency
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-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23601500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11042500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 34644000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23601500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11042500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 34644000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4531000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4531000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23368000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23368000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6713000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6713000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23368000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11244000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 34612000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23368000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11244000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 34612000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for ReadCleanReq accesses
@@ -627,18 +627,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62075.342466 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62075.342466 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64839.285714 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64839.285714 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67822.916667 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67822.916667 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64839.285714 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65340.236686 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64998.123827 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64839.285714 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65340.236686 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64998.123827 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62068.493151 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62068.493151 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64197.802198 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64197.802198 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69927.083333 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69927.083333 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64197.802198 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66532.544379 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64938.086304 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64197.802198 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66532.544379 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64938.086304 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
@@ -688,7 +688,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 533 # Request fanout histogram
-system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 602500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
system.membus.respLayer1.occupancy 2833000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 7.5 # Layer utilization (%)
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
index 5a166e70e..7f87c40d6 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
@@ -1,13 +1,15 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Apr 22 2015 07:55:25
-gem5 started Apr 22 2015 08:11:59
-gem5 executing on phenom
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
+gem5 compiled Sep 14 2015 20:54:01
+gem5 started Sep 14 2015 21:14:59
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 22074000 because target called exit()
+Exiting @ tick 21900500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
index 96f652b92..85a8b430a 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -1,51 +1,51 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000022 # Number of seconds simulated
-sim_ticks 21947000 # Number of ticks simulated
-final_tick 21947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 21900500 # Number of ticks simulated
+final_tick 21900500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 95577 # Simulator instruction rate (inst/s)
-host_op_rate 95558 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 329070081 # Simulator tick rate (ticks/s)
-host_mem_usage 294868 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
+host_inst_rate 43231 # Simulator instruction rate (inst/s)
+host_op_rate 43225 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 148545474 # Simulator tick rate (ticks/s)
+host_mem_usage 289772 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
sim_insts 6372 # Number of instructions simulated
sim_ops 6372 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory
-system.physmem.bytes_read::total 31104 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 486 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 912744339 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 504488085 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1417232424 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 912744339 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 912744339 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 912744339 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 504488085 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1417232424 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 486 # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst 19840 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10944 # Number of bytes read from this memory
+system.physmem.bytes_read::total 30784 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 19840 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 19840 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 310 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 171 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 481 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 905915390 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 499714618 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1405630008 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 905915390 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 905915390 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 905915390 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 499714618 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1405630008 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 481 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 486 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 481 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 31104 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 30784 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 31104 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 30784 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 69 # Per bank write bursts
-system.physmem.perBankRdBursts::1 33 # Per bank write bursts
+system.physmem.perBankRdBursts::0 68 # Per bank write bursts
+system.physmem.perBankRdBursts::1 32 # Per bank write bursts
system.physmem.perBankRdBursts::2 32 # Per bank write bursts
system.physmem.perBankRdBursts::3 47 # Per bank write bursts
-system.physmem.perBankRdBursts::4 42 # Per bank write bursts
+system.physmem.perBankRdBursts::4 41 # Per bank write bursts
system.physmem.perBankRdBursts::5 20 # Per bank write bursts
system.physmem.perBankRdBursts::6 1 # Per bank write bursts
system.physmem.perBankRdBursts::7 3 # Per bank write bursts
@@ -54,7 +54,7 @@ system.physmem.perBankRdBursts::9 1 # Pe
system.physmem.perBankRdBursts::10 22 # Per bank write bursts
system.physmem.perBankRdBursts::11 25 # Per bank write bursts
system.physmem.perBankRdBursts::12 14 # Per bank write bursts
-system.physmem.perBankRdBursts::13 120 # Per bank write bursts
+system.physmem.perBankRdBursts::13 118 # Per bank write bursts
system.physmem.perBankRdBursts::14 45 # Per bank write bursts
system.physmem.perBankRdBursts::15 12 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 21815000 # Total gap between requests
+system.physmem.totGap 21763000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 486 # Read request sizes (log2)
+system.physmem.readPktSize::6 481 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 138 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 56 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 270 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -186,99 +186,99 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 81 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 332.641975 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 207.725130 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 321.981029 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 25 30.86% 30.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 18 22.22% 53.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 9 11.11% 64.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 9 11.11% 75.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 6 7.41% 82.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1 1.23% 83.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 3 3.70% 87.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 10 12.35% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 81 # Bytes accessed per row activation
-system.physmem.totQLat 4379250 # Total ticks spent queuing
-system.physmem.totMemAccLat 13491750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2430000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 9010.80 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 337.822785 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 215.071445 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 323.417518 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 21 26.58% 26.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 22 27.85% 54.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 9 11.39% 65.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 9 11.39% 77.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 4 5.06% 82.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1 1.27% 83.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 3 3.80% 87.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 10 12.66% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation
+system.physmem.totQLat 3965000 # Total ticks spent queuing
+system.physmem.totMemAccLat 12983750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2405000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 8243.24 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 27760.80 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1417.23 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 26993.24 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1405.63 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1417.23 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1405.63 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 11.07 # Data bus utilization in percentage
-system.physmem.busUtilRead 11.07 # Data bus utilization in percentage for reads
+system.physmem.busUtil 10.98 # Data bus utilization in percentage
+system.physmem.busUtilRead 10.98 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 390 # Number of row buffer hits during reads
+system.physmem.readRowHits 387 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 80.25 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 80.46 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 44886.83 # Average gap between requests
-system.physmem.pageHitRate 80.25 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 219240 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 119625 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 1653600 # Energy for read commands per rank (pJ)
+system.physmem.avgGap 45245.32 # Average gap between requests
+system.physmem.pageHitRate 80.46 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 1630200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 13833660 # Total energy per rank (pJ)
-system.physmem_0.averagePower 873.750829 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states
+system.physmem_0.totalEnergy 13775205 # Total energy per rank (pJ)
+system.physmem_0.averagePower 870.058740 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 209750 # Time in different power states
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 325080 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 177375 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1271400 # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy 317520 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 173250 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1287000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 10129185 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 614250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 13534410 # Total energy per rank (pJ)
-system.physmem_1.averagePower 854.849834 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 953500 # Time in different power states
+system.physmem_1.actBackEnergy 10183905 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 566250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 13545045 # Total energy per rank (pJ)
+system.physmem_1.averagePower 855.521554 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 873500 # Time in different power states
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 14372750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 14452750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 2810 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1662 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 478 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 2116 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 679 # Number of BTB hits
+system.cpu.branchPred.lookups 2551 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1518 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 429 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1991 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 726 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 32.088847 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 396 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 36.464088 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 383 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 29 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 2105 # DTB read hits
-system.cpu.dtb.read_misses 55 # DTB read misses
+system.cpu.dtb.read_hits 2033 # DTB read hits
+system.cpu.dtb.read_misses 43 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 2160 # DTB read accesses
-system.cpu.dtb.write_hits 1074 # DTB write hits
-system.cpu.dtb.write_misses 30 # DTB write misses
+system.cpu.dtb.read_accesses 2076 # DTB read accesses
+system.cpu.dtb.write_hits 1052 # DTB write hits
+system.cpu.dtb.write_misses 28 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 1104 # DTB write accesses
-system.cpu.dtb.data_hits 3179 # DTB hits
-system.cpu.dtb.data_misses 85 # DTB misses
+system.cpu.dtb.write_accesses 1080 # DTB write accesses
+system.cpu.dtb.data_hits 3085 # DTB hits
+system.cpu.dtb.data_misses 71 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 3264 # DTB accesses
-system.cpu.itb.fetch_hits 2194 # ITB hits
-system.cpu.itb.fetch_misses 34 # ITB misses
+system.cpu.dtb.data_accesses 3156 # DTB accesses
+system.cpu.itb.fetch_hits 2086 # ITB hits
+system.cpu.itb.fetch_misses 32 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 2228 # ITB accesses
+system.cpu.itb.fetch_accesses 2118 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -292,237 +292,237 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 43895 # number of cpu cycles simulated
+system.cpu.numCycles 43802 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 8597 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 16278 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2810 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1075 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 4298 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1038 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 740 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 2194 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 14179 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.148036 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.557344 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 8360 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 14953 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2551 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1109 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 4527 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 940 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 730 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 2086 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 308 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 14111 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.059670 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.447373 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 11320 79.84% 79.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 289 2.04% 81.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 216 1.52% 83.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 204 1.44% 84.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 243 1.71% 86.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 208 1.47% 88.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 242 1.71% 89.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 175 1.23% 90.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1282 9.04% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 11381 80.65% 80.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 309 2.19% 82.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 232 1.64% 84.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 210 1.49% 85.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 257 1.82% 87.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 204 1.45% 89.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 249 1.76% 91.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 144 1.02% 92.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1125 7.97% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 14179 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.064016 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.370840 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 8623 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 2500 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2414 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 200 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 442 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 227 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 14886 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 224 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 442 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 8796 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 1074 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 427 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2425 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 1015 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 14276 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 33 # Number of times rename has blocked due to LQ full
+system.cpu.fetch.rateDist::total 14111 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.058239 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.341377 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 8350 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 2903 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2283 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 178 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 397 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 199 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 74 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 13658 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 213 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 397 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 8499 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 1362 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 551 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2297 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 1005 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 13185 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 29 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 937 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 10794 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 17927 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 17918 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 9916 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 16517 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 16508 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6224 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 32 # count of serializing insts renamed
+system.cpu.rename.UndoneMaps 5346 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 30 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 538 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2680 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1315 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts 571 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2513 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1264 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 12940 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 12094 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 10735 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 6595 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 3561 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 10150 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 8 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 5749 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 3122 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 14179 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.757106 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.490778 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 14111 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.719297 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.444291 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 10173 71.75% 71.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1278 9.01% 80.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 898 6.33% 87.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 679 4.79% 91.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 528 3.72% 95.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 333 2.35% 97.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 209 1.47% 99.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 55 0.39% 99.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 26 0.18% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 10252 72.65% 72.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1258 8.92% 81.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 873 6.19% 87.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 669 4.74% 92.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 489 3.47% 95.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 327 2.32% 98.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 176 1.25% 99.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 44 0.31% 99.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 23 0.16% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 14179 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 14111 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 29 20.14% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 73 50.69% 70.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 42 29.17% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 18 13.64% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 73 55.30% 68.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 41 31.06% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 7243 67.47% 67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.50% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2356 21.95% 89.46% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1131 10.54% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 6822 67.21% 67.23% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2214 21.81% 89.07% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1109 10.93% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 10735 # Type of FU issued
-system.cpu.iq.rate 0.244561 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 144 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.013414 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 35792 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 19571 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 9784 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 10150 # Type of FU issued
+system.cpu.iq.rate 0.231725 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 132 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.013005 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 34530 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 17879 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 9316 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 10866 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 10269 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 71 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1497 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1330 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 450 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 399 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 65 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 71 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 442 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1033 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 13054 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 109 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2680 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1315 # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles 397 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1267 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 12206 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2513 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1264 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 20 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 81 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 395 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 476 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 10242 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2163 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 493 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect 85 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 341 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 426 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 9752 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2076 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 86 # number of nop insts executed
-system.cpu.iew.exec_refs 3269 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1598 # Number of branches executed
-system.cpu.iew.exec_stores 1106 # Number of stores executed
-system.cpu.iew.exec_rate 0.233330 # Inst execution rate
-system.cpu.iew.wb_sent 9957 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 9794 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 5300 # num instructions producing a value
-system.cpu.iew.wb_consumers 7297 # num instructions consuming a value
+system.cpu.iew.exec_nop 84 # number of nop insts executed
+system.cpu.iew.exec_refs 3158 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1540 # Number of branches executed
+system.cpu.iew.exec_stores 1082 # Number of stores executed
+system.cpu.iew.exec_rate 0.222638 # Inst execution rate
+system.cpu.iew.wb_sent 9474 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 9326 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 4992 # num instructions producing a value
+system.cpu.iew.wb_consumers 6833 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.223123 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.726326 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.212913 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.730572 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 6664 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 5821 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 401 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 12978 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.492295 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.405132 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 356 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 13063 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.489091 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.409393 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 10520 81.06% 81.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1167 8.99% 90.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 504 3.88% 93.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 209 1.61% 95.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 136 1.05% 96.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 76 0.59% 97.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 89 0.69% 97.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 87 0.67% 98.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 190 1.46% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 10626 81.34% 81.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1163 8.90% 90.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 487 3.73% 93.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 202 1.55% 95.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 127 0.97% 96.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 82 0.63% 97.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 98 0.75% 97.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 84 0.64% 98.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 194 1.49% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 12978 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 13063 # Number of insts commited each cycle
system.cpu.commit.committedInsts 6389 # Number of instructions committed
system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -568,186 +568,186 @@ system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 6389 # Class of committed instruction
-system.cpu.commit.bw_lim_events 190 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 25490 # The number of ROB reads
-system.cpu.rob.rob_writes 27321 # The number of ROB writes
-system.cpu.timesIdled 258 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 29716 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events 194 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 24728 # The number of ROB reads
+system.cpu.rob.rob_writes 25475 # The number of ROB writes
+system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 29691 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 6372 # Number of Instructions Simulated
system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 6.888732 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 6.888732 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.145165 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.145165 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 13013 # number of integer regfile reads
-system.cpu.int_regfile_writes 7460 # number of integer regfile writes
+system.cpu.cpi 6.874137 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 6.874137 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.145473 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.145473 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 12362 # number of integer regfile reads
+system.cpu.int_regfile_writes 7056 # number of integer regfile writes
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 107.548347 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 2343 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 13.543353 # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 107.516544 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 2276 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 13.309942 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 107.548347 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.026257 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.026257 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data 107.516544 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.026249 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.026249 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 171 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 5891 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 5891 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1835 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1835 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 508 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 508 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 2343 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2343 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2343 # number of overall hits
-system.cpu.dcache.overall_hits::total 2343 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 159 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 159 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 357 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 357 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 516 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 516 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 516 # number of overall misses
-system.cpu.dcache.overall_misses::total 516 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11993500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11993500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 24175975 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 24175975 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 36169475 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 36169475 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 36169475 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 36169475 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1994 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1994 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.041748 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 5747 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 5747 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1770 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1770 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 2276 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2276 # number of demand (read+write) hits
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@@ -756,54 +756,54 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20280000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12033500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 32313500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20280000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12033500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 32313500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996815 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996785 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.997925 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70555.555556 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70555.555556 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65575.079872 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65575.079872 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73450.495050 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73450.495050 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65575.079872 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72245.664740 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67949.588477 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65575.079872 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72245.664740 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67949.588477 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.997925 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67201.388889 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67201.388889 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65419.354839 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65419.354839 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72676.767677 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72676.767677 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65419.354839 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65419.354839 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 314 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 974 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 311 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 99 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 622 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 342 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 964 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19904 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 487 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 482 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 487 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 482 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 487 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 243500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 482 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 471000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 466500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 256500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 414 # Transaction distribution
+system.membus.trans_dist::ReadResp 409 # Transaction distribution
system.membus.trans_dist::ReadExReq 72 # Transaction distribution
system.membus.trans_dist::ReadExResp 72 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 414 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 972 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 972 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31104 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 31104 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq 409 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 962 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 962 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30784 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 30784 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 486 # Request fanout histogram
+system.membus.snoop_fanout::samples 481 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 486 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 481 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 486 # Request fanout histogram
-system.membus.reqLayer0.occupancy 594500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 481 # Request fanout histogram
+system.membus.reqLayer0.occupancy 586000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2585500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 11.8 # Layer utilization (%)
+system.membus.respLayer1.occupancy 2558250 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 11.7 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
index e07ba072a..5b279bd35 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -228,7 +228,6 @@ hot_lines=false
memory_size_bits=48
num_of_sequencers=1
phys_mem=Null
-random_seed=1234
randomization=false
[system.ruby.clk_domain]
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
index 011f7e597..bf628f608 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
@@ -228,7 +228,6 @@ hot_lines=false
memory_size_bits=48
num_of_sequencers=1
phys_mem=Null
-random_seed=1234
randomization=false
[system.ruby.clk_domain]
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
index 3ff859531..7d246ed9e 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
@@ -228,7 +228,6 @@ hot_lines=false
memory_size_bits=48
num_of_sequencers=1
phys_mem=Null
-random_seed=1234
randomization=false
[system.ruby.clk_domain]
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
index 7c57b2554..2f7c0906a 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000020 # Number of seconds simulated
-sim_ticks 20091000 # Number of ticks simulated
-final_tick 20091000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 20075000 # Number of ticks simulated
+final_tick 20075000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 125803 # Simulator instruction rate (inst/s)
-host_op_rate 125723 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 976523768 # Simulator tick rate (ticks/s)
-host_mem_usage 293292 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
+host_inst_rate 42420 # Simulator instruction rate (inst/s)
+host_op_rate 42407 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 329231154 # Simulator tick rate (ticks/s)
+host_mem_usage 287436 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 2585 # Number of instructions simulated
sim_ops 2585 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14272 # Nu
system.physmem.num_reads::cpu.inst 223 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
system.physmem.num_reads::total 308 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 710367826 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 270768006 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 981135832 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 710367826 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 710367826 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 710367826 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 270768006 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 981135832 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 710933998 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 270983811 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 981917808 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 710933998 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 710933998 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 710933998 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 270983811 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 981917808 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 308 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 308 # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 20003000 # Total gap between requests
+system.physmem.totGap 19987000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@@ -200,15 +200,15 @@ system.physmem.bytesPerActivate::768-895 3 7.32% 85.37% # By
system.physmem.bytesPerActivate::896-1023 3 7.32% 92.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 3 7.32% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation
-system.physmem.totQLat 1567250 # Total ticks spent queuing
-system.physmem.totMemAccLat 7342250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 1568250 # Total ticks spent queuing
+system.physmem.totMemAccLat 7343250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 5088.47 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 5091.72 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 23838.47 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 981.14 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 23841.72 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 981.92 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 981.14 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 981.92 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 7.67 # Data bus utilization in percentage
@@ -220,7 +220,7 @@ system.physmem.readRowHits 258 # Nu
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.77 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 64944.81 # Average gap between requests
+system.physmem.avgGap 64892.86 # Average gap between requests
system.physmem.pageHitRate 83.77 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ)
@@ -231,7 +231,7 @@ system.physmem_0.actBackEnergy 10605420 # En
system.physmem_0.preBackEnergy 196500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 12727575 # Total energy per rank (pJ)
system.physmem_0.averagePower 803.889152 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 536250 # Time in different power states
+system.physmem_0.memoryStateTime::IDLE 534250 # Time in different power states
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 15041250 # Time in different power states
@@ -241,22 +241,22 @@ system.physmem_1.preEnergy 103125 # En
system.physmem_1.readEnergy 1201200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 10489995 # Energy for active background per rank (pJ)
+system.physmem_1.actBackEnergy 10488285 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 299250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 13299690 # Total energy per rank (pJ)
-system.physmem_1.averagePower 839.892011 # Core power per rank (mW)
+system.physmem_1.totalEnergy 13297980 # Total energy per rank (pJ)
+system.physmem_1.averagePower 839.916627 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 457000 # Time in different power states
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 14871250 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 14869250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 793 # Number of BP lookups
-system.cpu.branchPred.condPredicted 397 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 168 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 563 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 58 # Number of BTB hits
+system.cpu.branchPred.lookups 787 # Number of BP lookups
+system.cpu.branchPred.condPredicted 394 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 164 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 560 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 60 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 10.301954 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 10.714286 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 138 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
@@ -264,22 +264,22 @@ system.cpu.dtb.fetch_hits 0 # IT
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 509 # DTB read hits
+system.cpu.dtb.read_hits 506 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 1 # DTB read access violations
-system.cpu.dtb.read_accesses 516 # DTB read accesses
+system.cpu.dtb.read_accesses 513 # DTB read accesses
system.cpu.dtb.write_hits 307 # DTB write hits
system.cpu.dtb.write_misses 6 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 313 # DTB write accesses
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+system.cpu.dtb.data_hits 813 # DTB hits
system.cpu.dtb.data_misses 13 # DTB misses
system.cpu.dtb.data_acv 1 # DTB access violations
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-system.cpu.itb.fetch_hits 971 # ITB hits
+system.cpu.dtb.data_accesses 826 # DTB accesses
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system.cpu.itb.fetch_misses 13 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
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+system.cpu.itb.fetch_accesses 978 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -293,40 +293,40 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2585 # Number of instructions committed
system.cpu.committedOps 2585 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 594 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 581 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
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-system.cpu.ipc 0.064332 # IPC: instructions per cycle
-system.cpu.tickCycles 5392 # Number of cycles that the object actually ticked
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+system.cpu.cpi 15.531915 # CPI: cycles per instruction
+system.cpu.ipc 0.064384 # IPC: instructions per cycle
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system.cpu.dcache.tags.replacements 0 # number of replacements
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system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
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+system.cpu.dcache.tags.avg_refs 8.105882 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id
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system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 251 # number of WriteReq hits
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system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses
@@ -343,22 +343,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7981500
system.cpu.dcache.demand_miss_latency::total 7981500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7981500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7981500 # number of overall miss cycles
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system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.146259 # miss rate for WriteReq accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77426.229508 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 77426.229508 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75779.069767 # average WriteReq miss latency
@@ -399,14 +399,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6459500
system.cpu.dcache.demand_mshr_miss_latency::total 6459500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6459500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6459500 # number of overall MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76586.206897 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76586.206897 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74722.222222 # average WriteReq mshr miss latency
@@ -417,56 +417,56 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75994.117647
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75994.117647 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 0 # number of replacements
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system.cpu.icache.tags.sampled_refs 223 # Sample count of references to valid blocks.
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system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -481,36 +481,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 223
system.cpu.icache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 281 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 118.051720 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 27.801853 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003603 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 117.989893 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 27.790736 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003601 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000848 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.004451 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.004449 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 281 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id
@@ -531,16 +531,16 @@ system.cpu.l2cache.overall_misses::cpu.data 85 #
system.cpu.l2cache.overall_misses::total 308 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1977000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1977000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16421000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 16421000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16422000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 16422000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4354000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 4354000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 16421000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 16422000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 6331000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 22752000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 16421000 # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::total 22753000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 16422000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 6331000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 22752000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 22753000 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 223 # number of ReadCleanReq accesses(hits+misses)
@@ -567,16 +567,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73222.222222 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73222.222222 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73636.771300 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73636.771300 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73641.255605 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73641.255605 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75068.965517 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75068.965517 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73636.771300 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73641.255605 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74482.352941 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73870.129870 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73636.771300 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73873.376623 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73641.255605 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74482.352941 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73870.129870 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73873.376623 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -599,16 +599,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 85
system.cpu.l2cache.overall_mshr_misses::total 308 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1707000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1707000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14191000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14191000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14192000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14192000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3774000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3774000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14191000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14192000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5481000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 19672000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14191000 # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 19673000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14192000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5481000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 19672000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 19673000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
@@ -623,16 +623,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63222.222222 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63222.222222 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63636.771300 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63636.771300 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63641.255605 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63641.255605 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65068.965517 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65068.965517 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63636.771300 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63641.255605 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64482.352941 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63870.129870 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63636.771300 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63873.376623 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63641.255605 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64482.352941 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63870.129870 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63873.376623 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index ee80959b5..6ee889334 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000013 # Number of seconds simulated
-sim_ticks 12591500 # Number of ticks simulated
-final_tick 12591500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000012 # Number of seconds simulated
+sim_ticks 12363500 # Number of ticks simulated
+final_tick 12363500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 74456 # Simulator instruction rate (inst/s)
-host_op_rate 74426 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 392441951 # Simulator tick rate (ticks/s)
-host_mem_usage 293552 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
+host_inst_rate 20992 # Simulator instruction rate (inst/s)
+host_op_rate 20989 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 108692792 # Simulator tick rate (ticks/s)
+host_mem_usage 288464 # Number of bytes of host memory used
+host_seconds 0.11 # Real time elapsed on the host
sim_insts 2387 # Number of instructions simulated
sim_ops 2387 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu
system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
system.physmem.num_reads::total 272 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 950482468 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 432037486 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1382519954 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 950482468 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 950482468 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 950482468 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 432037486 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1382519954 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 968010677 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 440004853 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1408015530 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 968010677 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 968010677 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 968010677 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 440004853 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1408015530 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 272 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 12495000 # Total gap between requests
+system.physmem.totGap 12267000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 156 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 82 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 27 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 152 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 31 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
@@ -200,27 +200,27 @@ system.physmem.bytesPerActivate::768-895 2 5.56% 83.33% # By
system.physmem.bytesPerActivate::896-1023 1 2.78% 86.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 5 13.89% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation
-system.physmem.totQLat 1676750 # Total ticks spent queuing
-system.physmem.totMemAccLat 6776750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 1685750 # Total ticks spent queuing
+system.physmem.totMemAccLat 6785750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 6164.52 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 6197.61 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 24914.52 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1382.52 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 24947.61 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1408.02 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1382.52 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1408.02 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 10.80 # Data bus utilization in percentage
-system.physmem.busUtilRead 10.80 # Data bus utilization in percentage for reads
+system.physmem.busUtil 11.00 # Data bus utilization in percentage
+system.physmem.busUtilRead 11.00 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 226 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.09 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 45937.50 # Average gap between requests
+system.physmem.avgGap 45099.26 # Average gap between requests
system.physmem.pageHitRate 83.09 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ)
@@ -250,36 +250,36 @@ system.physmem_1.memoryStateTime::REF 260000 # Ti
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 7371500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 1086 # Number of BP lookups
-system.cpu.branchPred.condPredicted 546 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 229 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 723 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 206 # Number of BTB hits
+system.cpu.branchPred.lookups 890 # Number of BP lookups
+system.cpu.branchPred.condPredicted 443 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 195 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 616 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 164 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 28.492393 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 197 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 26.623377 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 186 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 688 # DTB read hits
-system.cpu.dtb.read_misses 18 # DTB read misses
+system.cpu.dtb.read_hits 719 # DTB read hits
+system.cpu.dtb.read_misses 10 # DTB read misses
system.cpu.dtb.read_acv 1 # DTB read access violations
-system.cpu.dtb.read_accesses 706 # DTB read accesses
-system.cpu.dtb.write_hits 353 # DTB write hits
-system.cpu.dtb.write_misses 17 # DTB write misses
+system.cpu.dtb.read_accesses 729 # DTB read accesses
+system.cpu.dtb.write_hits 347 # DTB write hits
+system.cpu.dtb.write_misses 16 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 370 # DTB write accesses
-system.cpu.dtb.data_hits 1041 # DTB hits
-system.cpu.dtb.data_misses 35 # DTB misses
+system.cpu.dtb.write_accesses 363 # DTB write accesses
+system.cpu.dtb.data_hits 1066 # DTB hits
+system.cpu.dtb.data_misses 26 # DTB misses
system.cpu.dtb.data_acv 1 # DTB access violations
-system.cpu.dtb.data_accesses 1076 # DTB accesses
-system.cpu.itb.fetch_hits 931 # ITB hits
-system.cpu.itb.fetch_misses 26 # ITB misses
+system.cpu.dtb.data_accesses 1092 # DTB accesses
+system.cpu.itb.fetch_hits 802 # ITB hits
+system.cpu.itb.fetch_misses 35 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 957 # ITB accesses
+system.cpu.itb.fetch_accesses 837 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -293,236 +293,235 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
-system.cpu.numCycles 25184 # number of cpu cycles simulated
+system.cpu.numCycles 24728 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 4404 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 6508 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 1086 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 403 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 1405 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 504 # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles 4265 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 5512 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 890 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 350 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 1015 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 436 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1109 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingTrapStallCycles 1206 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 931 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 153 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 7199 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.904014 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.325149 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 802 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 146 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 6733 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.818654 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.224131 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 6086 84.54% 84.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 49 0.68% 85.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 124 1.72% 86.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 82 1.14% 88.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 134 1.86% 89.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 58 0.81% 90.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 66 0.92% 91.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 57 0.79% 92.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 543 7.54% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 5799 86.13% 86.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 30 0.45% 86.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 91 1.35% 87.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 76 1.13% 89.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 118 1.75% 90.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 72 1.07% 91.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 40 0.59% 92.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 56 0.83% 93.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 451 6.70% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 7199 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.043123 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.258418 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 5197 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 794 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 972 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 58 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 178 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 76 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 5639 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 276 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 178 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 5280 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 486 # Number of cycles rename is blocking
+system.cpu.fetch.rateDist::total 6733 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.035992 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.222905 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 5190 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 505 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 865 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 28 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 145 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 132 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 4839 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 268 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 145 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 5257 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 212 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 288 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 942 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 25 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 5401 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RenamedOperands 3881 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 6093 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 6086 # Number of integer rename lookups
+system.cpu.rename.RunCycles 824 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 7 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 4680 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RenamedOperands 3347 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5277 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 5270 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 2113 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 1579 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 109 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 882 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 453 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 2 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 4674 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts 52 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 795 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 418 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 4078 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 3880 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 2292 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1214 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 3608 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 32 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 1696 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 859 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 7199 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.538964 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.280196 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 6733 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.535868 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.279819 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 5699 79.16% 79.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 500 6.95% 86.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 351 4.88% 90.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 251 3.49% 94.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 194 2.69% 97.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 116 1.61% 98.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 57 0.79% 99.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 21 0.29% 99.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 10 0.14% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 5352 79.49% 79.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 449 6.67% 86.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 318 4.72% 90.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 240 3.56% 94.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 185 2.75% 97.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 110 1.63% 98.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 49 0.73% 99.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 21 0.31% 99.87% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 7199 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 6733 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 6 11.76% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 22 43.14% 54.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 23 45.10% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 6 8.70% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 39 56.52% 65.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 24 34.78% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 2765 71.26% 71.26% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 738 19.02% 90.31% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 376 9.69% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 2482 68.79% 68.79% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.03% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 757 20.98% 89.80% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 368 10.20% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 3880 # Type of FU issued
-system.cpu.iq.rate 0.154066 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 51 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.013144 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 15012 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 6969 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 3584 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 3608 # Type of FU issued
+system.cpu.iq.rate 0.145907 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 69 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.019124 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 14037 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 5777 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 3273 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 3924 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 3670 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 28 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 467 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 380 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 159 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 124 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 91 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 178 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 422 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 5018 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 28 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 882 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 453 # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles 145 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 186 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 4365 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 29 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 795 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 418 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 21 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 168 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 189 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 3751 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 707 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 129 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect 20 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 120 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 140 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 3509 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 730 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 99 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 338 # number of nop insts executed
-system.cpu.iew.exec_refs 1077 # number of memory reference insts executed
-system.cpu.iew.exec_branches 639 # Number of branches executed
-system.cpu.iew.exec_stores 370 # Number of stores executed
-system.cpu.iew.exec_rate 0.148944 # Inst execution rate
-system.cpu.iew.wb_sent 3648 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 3590 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1708 # num instructions producing a value
-system.cpu.iew.wb_consumers 2182 # num instructions consuming a value
+system.cpu.iew.exec_nop 281 # number of nop insts executed
+system.cpu.iew.exec_refs 1093 # number of memory reference insts executed
+system.cpu.iew.exec_branches 570 # Number of branches executed
+system.cpu.iew.exec_stores 363 # Number of stores executed
+system.cpu.iew.exec_rate 0.141904 # Inst execution rate
+system.cpu.iew.wb_sent 3329 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 3279 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1560 # num instructions producing a value
+system.cpu.iew.wb_consumers 1998 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.142551 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.782768 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.132603 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.780781 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 2428 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 1787 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 155 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 6748 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.381743 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.245988 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 122 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 6402 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.402374 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.273029 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 5894 87.34% 87.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 193 2.86% 90.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 303 4.49% 94.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 109 1.62% 96.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 72 1.07% 97.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 56 0.83% 98.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 33 0.49% 98.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 20 0.30% 98.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 68 1.01% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 5545 86.61% 86.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 194 3.03% 89.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 304 4.75% 94.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 116 1.81% 96.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 62 0.97% 97.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 60 0.94% 98.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 35 0.55% 98.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 20 0.31% 98.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 66 1.03% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 6748 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 6402 # Number of insts commited each cycle
system.cpu.commit.committedInsts 2576 # Number of instructions committed
system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -568,101 +567,101 @@ system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 2576 # Class of committed instruction
-system.cpu.commit.bw_lim_events 68 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 11437 # The number of ROB reads
-system.cpu.rob.rob_writes 10476 # The number of ROB writes
-system.cpu.timesIdled 151 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 17985 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events 66 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 10452 # The number of ROB reads
+system.cpu.rob.rob_writes 9060 # The number of ROB writes
+system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 17995 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 2387 # Number of Instructions Simulated
system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 10.550482 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 10.550482 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.094782 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.094782 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 4532 # number of integer regfile reads
-system.cpu.int_regfile_writes 2777 # number of integer regfile writes
+system.cpu.cpi 10.359447 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 10.359447 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.096530 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.096530 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 4249 # number of integer regfile reads
+system.cpu.int_regfile_writes 2511 # number of integer regfile writes
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 45.864197 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 731 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 45.334739 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 716 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 8.600000 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 8.423529 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 45.864197 # Average occupied blocks per requestor
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system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id
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-system.cpu.dcache.tags.data_accesses 1937 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 518 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 518 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 1873 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1873 # Number of data accesses
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+system.cpu.dcache.ReadReq_hits::total 503 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits
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-system.cpu.dcache.demand_hits::total 731 # number of demand (read+write) hits
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-system.cpu.dcache.overall_hits::total 731 # number of overall hits
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-system.cpu.dcache.ReadReq_misses::total 114 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
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-system.cpu.dcache.demand_misses::total 195 # number of demand (read+write) misses
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-system.cpu.dcache.overall_misses::total 195 # number of overall misses
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-system.cpu.dcache.overall_miss_latency::total 13256000 # number of overall miss cycles
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system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses
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-system.cpu.dcache.overall_miss_rate::total 0.210583 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66574.561404 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 66574.561404 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69956.790123 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69956.790123 # average WriteReq miss latency
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-system.cpu.dcache.demand_avg_miss_latency::total 67979.487179 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 67979.487179 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 67979.487179 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 139 # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data 0.199105 # miss rate for demand accesses
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+system.cpu.dcache.overall_miss_rate::total 0.199105 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67865.979381 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 67865.979381 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70024.691358 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 70024.691358 # average WriteReq miss latency
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+system.cpu.dcache.demand_avg_miss_latency::total 68848.314607 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 68848.314607 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 68848.314607 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 292 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 9 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.500000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.444444 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 36 # number of ReadReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 110 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 110 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 110 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 110 # number of overall MSHR hits
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@@ -671,82 +670,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
@@ -755,51 +754,51 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 62.500000
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 248 # Sample count of references to valid blocks.
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@@ -817,16 +816,16 @@ system.cpu.l2cache.overall_misses::cpu.data 85 #
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+system.cpu.l2cache.demand_miss_latency::cpu.inst 13898000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 6532000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 20430000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 13898000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 6532000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 20430000 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187 # number of ReadCleanReq accesses(hits+misses)
@@ -853,16 +852,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75562.500000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75562.500000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74288.770053 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74288.770053 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77344.262295 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77344.262295 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74288.770053 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76841.176471 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75086.397059 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74288.770053 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76841.176471 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75086.397059 # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74320.855615 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74320.855615 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77352.459016 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77352.459016 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74320.855615 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76847.058824 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75110.294118 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74320.855615 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76847.058824 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75110.294118 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -885,16 +884,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 85
system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1573500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1573500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12022000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12022000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4108000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4108000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12022000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5681500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 17703500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12022000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5681500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 17703500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12028000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12028000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4108500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4108500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12028000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5682000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 17710000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12028000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5682000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 17710000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
@@ -909,16 +908,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65562.500000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65562.500000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64288.770053 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64288.770053 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67344.262295 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67344.262295 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64288.770053 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66841.176471 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65086.397059 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64288.770053 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66841.176471 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65086.397059 # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64320.855615 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64320.855615 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67352.459016 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67352.459016 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64320.855615 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66847.058824 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65110.294118 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64320.855615 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66847.058824 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65110.294118 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution
@@ -946,7 +945,7 @@ system.cpu.toL2Bus.snoop_fanout::total 272 # Re
system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 280500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
system.membus.trans_dist::ReadResp 248 # Transaction distribution
@@ -968,9 +967,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 272 # Request fanout histogram
-system.membus.reqLayer0.occupancy 337000 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 335500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1441250 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 11.4 # Layer utilization (%)
+system.membus.respLayer1.occupancy 1441000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 11.7 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
index 32421c7b3..0c42ac84b 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
@@ -228,7 +228,6 @@ hot_lines=false
memory_size_bits=48
num_of_sequencers=1
phys_mem=Null
-random_seed=1234
randomization=false
[system.ruby.clk_domain]
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 0d1926cd4..f0b756165 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -228,7 +228,6 @@ hot_lines=false
memory_size_bits=48
num_of_sequencers=1
phys_mem=Null
-random_seed=1234
randomization=false
[system.ruby.clk_domain]
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
index ebc9b7aa1..a00344038 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -228,7 +228,6 @@ hot_lines=false
memory_size_bits=48
num_of_sequencers=1
phys_mem=Null
-random_seed=1234
randomization=false
[system.ruby.clk_domain]
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
index d78920aa6..6e0294d29 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
@@ -228,7 +228,6 @@ hot_lines=false
memory_size_bits=48
num_of_sequencers=1
phys_mem=Null
-random_seed=1234
randomization=false
[system.ruby.clk_domain]
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
index 408894bb9..46fd0f447 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
@@ -228,7 +228,6 @@ hot_lines=false
memory_size_bits=48
num_of_sequencers=1
phys_mem=Null
-random_seed=1234
randomization=false
[system.ruby.clk_domain]
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
index e5ff065c1..3e86bd3ac 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000030 # Number of seconds simulated
-sim_ticks 29934500 # Number of ticks simulated
-final_tick 29934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 29941500 # Number of ticks simulated
+final_tick 29941500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 115469 # Simulator instruction rate (inst/s)
-host_op_rate 135130 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 750106498 # Simulator tick rate (ticks/s)
-host_mem_usage 310152 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
+host_inst_rate 58660 # Simulator instruction rate (inst/s)
+host_op_rate 68656 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 381226078 # Simulator tick rate (ticks/s)
+host_mem_usage 304332 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 4605 # Number of instructions simulated
sim_ops 5391 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu
system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory
system.physmem.num_reads::total 421 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 652090397 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 248008151 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 900098548 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 652090397 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 652090397 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 652090397 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 248008151 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 900098548 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 651937946 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 247950169 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 899888115 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 651937946 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 651937946 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 651937946 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 247950169 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 899888115 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 421 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 29844000 # Total gap between requests
+system.physmem.totGap 29851000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@@ -200,15 +200,15 @@ system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # By
system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation
-system.physmem.totQLat 2214000 # Total ticks spent queuing
-system.physmem.totMemAccLat 10107750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 2218000 # Total ticks spent queuing
+system.physmem.totMemAccLat 10111750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 5258.91 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 5268.41 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 24008.91 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 900.10 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 24018.41 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 899.89 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 900.10 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 899.89 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 7.03 # Data bus utilization in percentage
@@ -220,7 +220,7 @@ system.physmem.readRowHits 350 # Nu
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 70888.36 # Average gap between requests
+system.physmem.avgGap 70904.99 # Average gap between requests
system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ)
@@ -250,14 +250,14 @@ system.physmem_1.memoryStateTime::REF 780000 # Ti
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 22328250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 1918 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1150 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 336 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 1604 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 341 # Number of BTB hits
+system.cpu.branchPred.lookups 1912 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1153 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 338 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1608 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 347 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 21.259352 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 218 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 21.579602 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
@@ -377,44 +377,44 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
-system.cpu.numCycles 59869 # number of cpu cycles simulated
+system.cpu.numCycles 59883 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 4605 # Number of instructions committed
system.cpu.committedOps 5391 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 1116 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 1120 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 13.000869 # CPI: cycles per instruction
-system.cpu.ipc 0.076918 # IPC: instructions per cycle
-system.cpu.tickCycles 10574 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 49295 # Total number of cycles that the object has spent stopped
+system.cpu.cpi 13.003909 # CPI: cycles per instruction
+system.cpu.ipc 0.076900 # IPC: instructions per cycle
+system.cpu.tickCycles 10593 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 49290 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 86.493580 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 86.506122 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks.
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@@ -423,42 +423,42 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n
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@@ -483,82 +483,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146
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@@ -573,36 +573,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 322
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72273.291925 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72273.291925 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 72273.291925 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72273.291925 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 72273.291925 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23275500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 23275500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23275500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 23275500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23275500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 23275500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143622 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.143622 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.143622 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72284.161491 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72284.161491 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72284.161491 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 72284.161491 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72284.161491 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 72284.161491 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 195.411120 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 195.452372 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 41 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.108466 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.281002 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 41.130118 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004708 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.314702 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 41.137670 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004709 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.005963 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.005965 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id
@@ -633,16 +633,16 @@ system.cpu.l2cache.overall_misses::cpu.data 124 #
system.cpu.l2cache.overall_misses::total 429 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3133500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3133500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22610500 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 22610500 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5960500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 5960500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 22610500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 9094000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 31704500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 22610500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 9094000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 31704500 # number of overall miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22614000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 22614000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5961000 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 5961000 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 22614000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 9094500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 31708500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 22614000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 9094500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 31708500 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses)
@@ -669,16 +669,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315
system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72872.093023 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72872.093023 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74132.786885 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74132.786885 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73586.419753 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73586.419753 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74132.786885 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73338.709677 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73903.263403 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74132.786885 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73338.709677 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73903.263403 # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74144.262295 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74144.262295 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73592.592593 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73592.592593 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74144.262295 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73912.587413 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74144.262295 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73912.587413 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -707,16 +707,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 116
system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2703500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2703500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19560500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19560500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4700500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4700500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19560500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7404000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 26964500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19560500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7404000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 26964500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19564000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19564000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4701000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4701000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19564000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7404500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 26968500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19564000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7404500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 26968500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses
@@ -731,16 +731,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521
system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62872.093023 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62872.093023 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64132.786885 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64132.786885 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64390.410959 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64390.410959 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64132.786885 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63827.586207 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64048.693587 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64132.786885 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63827.586207 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64048.693587 # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64144.262295 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64144.262295 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64397.260274 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64397.260274 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64144.262295 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64058.194774 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64144.262295 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64058.194774 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 2 # Transaction distribution
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
index e4986f157..800acea54 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
@@ -1,14 +1,14 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Apr 22 2015 10:58:25
-gem5 started Apr 22 2015 14:33:28
-gem5 executing on phenom
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 14 2015 23:30:05
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.checker.isa: ISA system set to: 0 0x38f90a0
- 0: system.cpu.isa: ISA system set to: 0 0x38f90a0
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 17307500 because target called exit()
+Exiting @ tick 17163000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index 80e232875..be50d79db 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000017 # Number of seconds simulated
-sim_ticks 17226500 # Number of ticks simulated
-final_tick 17226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 17163000 # Number of ticks simulated
+final_tick 17163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 55427 # Simulator instruction rate (inst/s)
-host_op_rate 64904 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 207866253 # Simulator tick rate (ticks/s)
-host_mem_usage 311436 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 25428 # Simulator instruction rate (inst/s)
+host_op_rate 29777 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 95019968 # Simulator tick rate (ticks/s)
+host_mem_usage 305352 # Number of bytes of host memory used
+host_seconds 0.18 # Real time elapsed on the host
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17600 # Nu
system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory
system.physmem.num_reads::total 396 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1021681711 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 449539953 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1471221664 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1021681711 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1021681711 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1021681711 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 449539953 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1471221664 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1025461749 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 451203170 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1476664919 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1025461749 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1025461749 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1025461749 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 451203170 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1476664919 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 396 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 17159000 # Total gap between requests
+system.physmem.totGap 17090000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -186,78 +186,78 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 395.354839 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 263.720067 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 338.958245 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 11 17.74% 17.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 19 30.65% 48.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6 9.68% 58.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 8 12.90% 70.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 3 4.84% 75.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2 3.23% 79.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 2 3.23% 82.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 2 3.23% 85.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation
-system.physmem.totQLat 3039250 # Total ticks spent queuing
-system.physmem.totMemAccLat 10464250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 389.079365 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 252.523009 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 343.171701 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 13 20.63% 20.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 18 28.57% 49.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 6 9.52% 58.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 8 12.70% 71.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 2 3.17% 85.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
+system.physmem.totQLat 3055250 # Total ticks spent queuing
+system.physmem.totMemAccLat 10480250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 7674.87 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 7715.28 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 26424.87 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1471.22 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 26465.28 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1476.66 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1471.22 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1476.66 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 11.49 # Data bus utilization in percentage
-system.physmem.busUtilRead 11.49 # Data bus utilization in percentage for reads
+system.physmem.busUtil 11.54 # Data bus utilization in percentage
+system.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 331 # Number of row buffer hits during reads
+system.physmem.readRowHits 330 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.59 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 83.33 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 43330.81 # Average gap between requests
-system.physmem.pageHitRate 83.59 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 302400 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 165000 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ)
+system.physmem.avgGap 43156.57 # Average gap between requests
+system.physmem.pageHitRate 83.33 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 2106000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 10797795 # Energy for active background per rank (pJ)
+system.physmem_0.actBackEnergy 10794375 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 14404965 # Total energy per rank (pJ)
-system.physmem_0.averagePower 909.404356 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 69250 # Time in different power states
+system.physmem_0.totalEnergy 14428830 # Total energy per rank (pJ)
+system.physmem_0.averagePower 911.198611 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 65750 # Time in different power states
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 16109250 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 16176750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 10359180 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 412500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 12771300 # Total energy per rank (pJ)
-system.physmem_1.averagePower 806.650876 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 820250 # Time in different power states
+system.physmem_1.actBackEnergy 10407915 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 369750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 12777285 # Total energy per rank (pJ)
+system.physmem_1.averagePower 807.028896 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 665250 # Time in different power states
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 14680750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 2576 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1602 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 469 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 2087 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 781 # Number of BTB hits
+system.cpu.branchPred.lookups 2533 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1576 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 452 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 2102 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 812 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 37.422137 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 336 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 38.629876 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 321 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
@@ -496,237 +496,237 @@ system.cpu.itb.inst_accesses 0 # IT
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.numCycles 34454 # number of cpu cycles simulated
+system.cpu.numCycles 34327 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 7709 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 12205 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2576 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1117 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 4748 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 987 # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles 7647 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 11725 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2533 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1133 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 4667 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 953 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 2016 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 13219 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.088585 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.463952 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 1968 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 290 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 13059 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.059729 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.422792 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 10589 80.10% 80.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 274 2.07% 82.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 212 1.60% 83.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 221 1.67% 85.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 236 1.79% 87.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 324 2.45% 89.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 139 1.05% 90.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 161 1.22% 91.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1063 8.04% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 10498 80.39% 80.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 262 2.01% 82.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 215 1.65% 84.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 219 1.68% 85.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 263 2.01% 87.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 312 2.39% 90.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 142 1.09% 91.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 158 1.21% 92.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 990 7.58% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 13219 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.074766 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.354240 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 6369 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 4276 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2102 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 134 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 338 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total 13059 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.073790 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.341568 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 6338 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 4216 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2063 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 121 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 321 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 380 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 11852 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 468 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 338 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 6584 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 692 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 2356 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2013 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 1236 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 11200 # Number of instructions processed by rename
+system.cpu.decode.DecodedInsts 11316 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 321 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 6551 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 647 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 2328 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 1964 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 1248 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 10673 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 1064 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 11331 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 51672 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 12441 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups
+system.cpu.rename.SQFullEvents 1076 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 10857 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 48954 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 11788 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 74 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 5837 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 43 # count of serializing insts renamed
+system.cpu.rename.UndoneMaps 5363 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 42 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 422 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2287 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1689 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 38 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 34 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 10125 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts 428 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2126 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1537 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 9711 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8202 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 55 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 4793 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 12371 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 7972 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 4379 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 10941 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 13219 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.620471 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.365465 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 13059 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.610460 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.342240 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 10002 75.66% 75.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1166 8.82% 84.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 755 5.71% 90.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 451 3.41% 93.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 357 2.70% 96.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 278 2.10% 98.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 131 0.99% 99.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 63 0.48% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 16 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 9876 75.63% 75.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1174 8.99% 84.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 762 5.84% 90.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 454 3.48% 93.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 326 2.50% 96.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 278 2.13% 98.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 116 0.89% 99.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 62 0.47% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 13219 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 13059 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 9 5.26% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 84 49.12% 54.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 78 45.61% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 9 5.92% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 67 44.08% 50.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 76 50.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 4937 60.19% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.30% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 1959 23.88% 84.19% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1297 15.81% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 4885 61.28% 61.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.40% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 1831 22.97% 84.37% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1246 15.63% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8202 # Type of FU issued
-system.cpu.iq.rate 0.238057 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 171 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.020849 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 29750 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 14855 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 7430 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total 7972 # Type of FU issued
+system.cpu.iq.rate 0.232237 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 152 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.019067 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 29107 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 14039 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 7309 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 93 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 116 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 8330 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 8081 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 24 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1260 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1099 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 751 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 599 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads 34 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 660 # Number of cycles IEW is blocking
+system.cpu.iew.iewSquashCycles 321 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 613 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 10180 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 127 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2287 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1689 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 9766 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 119 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2126 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1537 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 111 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 234 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 345 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 7868 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 1843 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 334 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 215 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 327 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 7697 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 1736 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 275 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 9 # number of nop insts executed
-system.cpu.iew.exec_refs 3072 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1434 # Number of branches executed
-system.cpu.iew.exec_stores 1229 # Number of stores executed
-system.cpu.iew.exec_rate 0.228362 # Inst execution rate
-system.cpu.iew.wb_sent 7574 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 7462 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 3524 # num instructions producing a value
-system.cpu.iew.wb_consumers 6897 # num instructions consuming a value
+system.cpu.iew.exec_refs 2930 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1433 # Number of branches executed
+system.cpu.iew.exec_stores 1194 # Number of stores executed
+system.cpu.iew.exec_rate 0.224226 # Inst execution rate
+system.cpu.iew.wb_sent 7432 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 7341 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 3456 # num instructions producing a value
+system.cpu.iew.wb_consumers 6757 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.216579 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.510947 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.213855 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.511470 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 4801 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 4387 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 314 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 12382 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.434340 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.281233 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 297 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 12286 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.437734 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.284067 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 10327 83.40% 83.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 891 7.20% 90.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 421 3.40% 94.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 214 1.73% 95.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 114 0.92% 96.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 212 1.71% 98.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 49 0.40% 98.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 39 0.31% 99.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 115 0.93% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 10235 83.31% 83.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 882 7.18% 90.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 420 3.42% 93.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 222 1.81% 95.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 111 0.90% 96.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 213 1.73% 98.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 51 0.42% 98.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 41 0.33% 99.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 111 0.90% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 12382 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 12286 # Number of insts commited each cycle
system.cpu.commit.committedInsts 4592 # Number of instructions committed
system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -772,121 +772,121 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 5378 # Class of committed instruction
-system.cpu.commit.bw_lim_events 115 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 22289 # The number of ROB reads
-system.cpu.rob.rob_writes 21210 # The number of ROB writes
-system.cpu.timesIdled 194 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 21235 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 21783 # The number of ROB reads
+system.cpu.rob.rob_writes 20313 # The number of ROB writes
+system.cpu.timesIdled 192 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 21268 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4592 # Number of Instructions Simulated
system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 7.503049 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.503049 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.133279 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.133279 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 7752 # number of integer regfile reads
-system.cpu.int_regfile_writes 4259 # number of integer regfile writes
+system.cpu.cpi 7.475392 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.475392 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.133772 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.133772 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 7631 # number of integer regfile reads
+system.cpu.int_regfile_writes 4176 # number of integer regfile writes
system.cpu.fp_regfile_reads 32 # number of floating regfile reads
-system.cpu.cc_regfile_reads 28119 # number of cc regfile reads
-system.cpu.cc_regfile_writes 3280 # number of cc regfile writes
-system.cpu.misc_regfile_reads 3175 # number of misc regfile reads
+system.cpu.cc_regfile_reads 27375 # number of cc regfile reads
+system.cpu.cc_regfile_writes 3204 # number of cc regfile writes
+system.cpu.misc_regfile_reads 3054 # number of misc regfile reads
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 87.080084 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 2156 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 14.767123 # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 87.851603 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 2054 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 13.972789 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 87.080084 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.021260 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.021260 # Average percentage of cache occupancy
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@@ -895,135 +895,135 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147
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+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69164.556962 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65476.363636 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69231.404959 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66623.737374 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65476.363636 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69231.404959 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66623.737374 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp 397 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 586 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 879 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 880 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 28096 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
@@ -1187,7 +1187,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy 220500 # La
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 439500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 221495 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 222995 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
system.membus.trans_dist::ReadResp 354 # Transaction distribution
system.membus.trans_dist::ReadExReq 42 # Transaction distribution
@@ -1210,7 +1210,7 @@ system.membus.snoop_fanout::max_value 0 # Re
system.membus.snoop_fanout::total 396 # Request fanout histogram
system.membus.reqLayer0.occupancy 485500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2095750 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2097000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 12.2 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
index 5213b7cc0..d3878acf4 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -1,42 +1,42 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000022 # Number of seconds simulated
-sim_ticks 22403000 # Number of ticks simulated
-final_tick 22403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 22451000 # Number of ticks simulated
+final_tick 22451000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 79030 # Simulator instruction rate (inst/s)
-host_op_rate 79012 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 354943993 # Simulator tick rate (ticks/s)
-host_mem_usage 292784 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 41665 # Simulator instruction rate (inst/s)
+host_op_rate 41658 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 187549895 # Simulator tick rate (ticks/s)
+host_mem_usage 287968 # Number of bytes of host memory used
+host_seconds 0.12 # Real time elapsed on the host
sim_insts 4986 # Number of instructions simulated
sim_ops 4986 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 21120 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 20992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30144 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 21120 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 21120 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 330 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 30016 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 20992 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 20992 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 328 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 471 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 942730884 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 402803196 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1345534080 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 942730884 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 942730884 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 942730884 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 402803196 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1345534080 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 471 # Number of read requests accepted
+system.physmem.num_reads::total 469 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 935014031 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 401942007 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1336956038 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 935014031 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 935014031 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 935014031 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 401942007 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1336956038 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 469 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 471 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 30144 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 30144 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 30016 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
@@ -55,7 +55,7 @@ system.physmem.perBankRdBursts::10 43 # Pe
system.physmem.perBankRdBursts::11 20 # Per bank write bursts
system.physmem.perBankRdBursts::12 51 # Per bank write bursts
system.physmem.perBankRdBursts::13 29 # Per bank write bursts
-system.physmem.perBankRdBursts::14 80 # Per bank write bursts
+system.physmem.perBankRdBursts::14 78 # Per bank write bursts
system.physmem.perBankRdBursts::15 7 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 22316000 # Total gap between requests
+system.physmem.totGap 22364000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 471 # Read request sizes (log2)
+system.physmem.readPktSize::6 469 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 277 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -186,79 +186,79 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 105 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 260.876190 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 178.828028 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 254.099908 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 30 28.57% 28.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 33 31.43% 60.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 19 18.10% 78.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 10 9.52% 87.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 3 2.86% 90.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2 1.90% 92.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1 0.95% 93.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1 0.95% 94.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 6 5.71% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 105 # Bytes accessed per row activation
-system.physmem.totQLat 4348750 # Total ticks spent queuing
-system.physmem.totMemAccLat 13180000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2355000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 9233.01 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 104 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 262.153846 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 180.926322 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 251.694944 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 29 27.88% 27.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 32 30.77% 58.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 20 19.23% 77.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 9 8.65% 86.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 4 3.85% 90.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2 1.92% 92.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1 0.96% 93.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1 0.96% 94.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 6 5.77% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 104 # Bytes accessed per row activation
+system.physmem.totQLat 4505500 # Total ticks spent queuing
+system.physmem.totMemAccLat 13299250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 9606.61 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 27983.01 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1345.53 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 28356.61 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1336.96 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1345.53 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1336.96 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 10.51 # Data bus utilization in percentage
-system.physmem.busUtilRead 10.51 # Data bus utilization in percentage for reads
+system.physmem.busUtil 10.44 # Data bus utilization in percentage
+system.physmem.busUtilRead 10.44 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.71 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 356 # Number of row buffer hits during reads
+system.physmem.readRowHits 355 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 75.69 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 47380.04 # Average gap between requests
-system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined
+system.physmem.avgGap 47684.43 # Average gap between requests
+system.physmem.pageHitRate 75.69 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 538200 # Energy for read commands per rank (pJ)
+system.physmem_0.readEnergy 530400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 9525555 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1143750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 12423270 # Total energy per rank (pJ)
-system.physmem_0.averagePower 784.668877 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2113750 # Time in different power states
+system.physmem_0.actBackEnergy 9542655 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1130250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 12419070 # Total energy per rank (pJ)
+system.physmem_0.averagePower 784.279760 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 1840500 # Time in different power states
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 13462250 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 13487750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 521640 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 284625 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 2191800 # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy 514080 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 280500 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 2168400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 10738800 # Energy for active background per rank (pJ)
+system.physmem_1.actBackEnergy 10730250 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 87000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 14840985 # Total energy per rank (pJ)
-system.physmem_1.averagePower 936.635216 # Core power per rank (mW)
+system.physmem_1.totalEnergy 14797350 # Total energy per rank (pJ)
+system.physmem_1.averagePower 934.618664 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 103500 # Time in different power states
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 15234500 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 15222750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 2126 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1379 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 429 # Number of conditional branches incorrect
+system.cpu.branchPred.lookups 2031 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1362 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 402 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 1641 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 514 # Number of BTB hits
+system.cpu.branchPred.BTBHits 605 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 31.322364 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 281 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 36.867764 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 242 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 66 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@@ -279,236 +279,236 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 7 # Number of system calls
-system.cpu.numCycles 44807 # number of cpu cycles simulated
+system.cpu.numCycles 44903 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 8961 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 12993 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2126 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 795 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 4908 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 876 # Number of cycles fetch has spent squashing
-system.cpu.fetch.PendingTrapStallCycles 194 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 2040 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 14501 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.896007 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.195594 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 8843 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 12328 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2031 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 847 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 4817 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 822 # Number of cycles fetch has spent squashing
+system.cpu.fetch.PendingTrapStallCycles 190 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 1979 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 255 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 14261 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.864456 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.133927 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 11177 77.08% 77.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1470 10.14% 87.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 121 0.83% 88.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 160 1.10% 89.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 283 1.95% 91.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 95 0.66% 91.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 127 0.88% 92.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 112 0.77% 93.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 956 6.59% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 10999 77.13% 77.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1480 10.38% 87.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 118 0.83% 88.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 169 1.19% 89.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 282 1.98% 91.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 102 0.72% 92.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 134 0.94% 93.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 153 1.07% 94.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 824 5.78% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 14501 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.047448 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.289977 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 8511 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 2687 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2777 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 129 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 397 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 172 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 12008 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 170 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 397 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 8669 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 506 # Number of cycles rename is blocking
+system.cpu.fetch.rateDist::total 14261 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.045231 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.274547 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 8380 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 2677 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2707 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 371 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 41 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 11351 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 162 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 371 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 8518 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 542 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 996 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2735 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 1198 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 11509 # Number of instructions processed by rename
+system.cpu.rename.RunCycles 2675 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 1159 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 10918 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 229 # Number of times rename has blocked due to LQ full
+system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 179 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 954 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 6966 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 13566 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 13315 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 6512 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 12905 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 12683 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 3282 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 3684 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 3230 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 14 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 296 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2503 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1169 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts 314 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2295 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1159 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 9007 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 8632 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8237 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 4031 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1845 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 7937 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 3656 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1608 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 14501 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.568030 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.308332 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::2 739 5.10% 91.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 423 2.92% 94.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 353 2.43% 96.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 304 2.10% 98.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 105 0.72% 99.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 58 0.40% 99.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 24 0.17% 100.00% # Number of insts issued each cycle
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+system.cpu.iq.issued_per_cycle::3 439 3.08% 94.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 350 2.45% 96.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 277 1.94% 98.88% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 14501 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 14261 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 7 3.57% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 131 66.84% 70.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 58 29.59% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 6 3.41% 3.41% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.41% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.41% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 112 63.64% 67.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 58 32.95% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 4840 58.76% 58.76% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.81% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.82% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2319 28.15% 87.00% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1071 13.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 4719 59.46% 59.46% # Type of FU issued
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+system.cpu.iq.FU_type_0::IntDiv 1 0.01% 59.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2143 27.00% 86.54% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1068 13.46% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8237 # Type of FU issued
-system.cpu.iq.rate 0.183833 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 196 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.023795 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 31205 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 13056 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 7426 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 7937 # Type of FU issued
+system.cpu.iq.rate 0.176759 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 176 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.022175 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 30327 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 12306 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 7277 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 8431 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 8111 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 83 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 89 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1371 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1163 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 258 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 397 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 472 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 7 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 10561 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 155 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2503 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1169 # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles 371 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 425 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 88 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 10126 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2295 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1159 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 9 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 89 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 354 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 452 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 7898 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2175 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 339 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 419 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 7671 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2045 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 266 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1543 # number of nop insts executed
-system.cpu.iew.exec_refs 3228 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1368 # Number of branches executed
+system.cpu.iew.exec_nop 1483 # number of nop insts executed
+system.cpu.iew.exec_refs 3098 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1353 # Number of branches executed
system.cpu.iew.exec_stores 1053 # Number of stores executed
-system.cpu.iew.exec_rate 0.176267 # Inst execution rate
-system.cpu.iew.wb_sent 7529 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 7428 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 2859 # num instructions producing a value
-system.cpu.iew.wb_consumers 4251 # num instructions consuming a value
+system.cpu.iew.exec_rate 0.170835 # Inst execution rate
+system.cpu.iew.wb_sent 7354 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 7279 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 2832 # num instructions producing a value
+system.cpu.iew.wb_consumers 4198 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.165778 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.672548 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.162105 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.674607 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 4937 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 4505 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 388 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 13632 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.412485 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.223639 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 362 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 13468 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.417508 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.246465 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 11448 83.98% 83.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 886 6.50% 90.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 511 3.75% 94.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 255 1.87% 96.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 161 1.18% 97.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 164 1.20% 98.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 65 0.48% 98.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 40 0.29% 99.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 102 0.75% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 11324 84.08% 84.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 857 6.36% 90.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 503 3.73% 94.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 247 1.83% 96.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 153 1.14% 97.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 168 1.25% 98.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 61 0.45% 98.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 39 0.29% 99.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 116 0.86% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 13632 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 13468 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5623 # Number of instructions committed
system.cpu.commit.committedOps 5623 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -554,101 +554,101 @@ system.cpu.commit.op_class_0::MemWrite 901 16.02% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 5623 # Class of committed instruction
-system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 24077 # The number of ROB reads
-system.cpu.rob.rob_writes 22001 # The number of ROB writes
-system.cpu.timesIdled 266 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 30306 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events 116 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 23467 # The number of ROB reads
+system.cpu.rob.rob_writes 21056 # The number of ROB writes
+system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 30642 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4986 # Number of Instructions Simulated
system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 8.986562 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 8.986562 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.111277 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.111277 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 10682 # number of integer regfile reads
-system.cpu.int_regfile_writes 5223 # number of integer regfile writes
+system.cpu.cpi 9.005816 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 9.005816 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.111039 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.111039 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 10418 # number of integer regfile reads
+system.cpu.int_regfile_writes 5064 # number of integer regfile writes
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
-system.cpu.misc_regfile_reads 167 # number of misc regfile reads
+system.cpu.misc_regfile_reads 158 # number of misc regfile reads
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 91.242537 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 2427 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 90.670819 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 2302 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 17.212766 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 16.326241 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 91.242537 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.022276 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.022276 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 90.670819 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.022136 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.022136 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 6025 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 6025 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1871 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1871 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 5765 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 5765 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1746 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1746 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 2427 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2427 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2427 # number of overall hits
-system.cpu.dcache.overall_hits::total 2427 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data 2302 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2302 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2302 # number of overall hits
+system.cpu.dcache.overall_hits::total 2302 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 165 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 165 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 515 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 515 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 515 # number of overall misses
-system.cpu.dcache.overall_misses::total 515 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11738500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11738500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 24073999 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 24073999 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 35812499 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 35812499 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 35812499 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 35812499 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 2041 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 2041 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses
+system.cpu.dcache.overall_misses::total 510 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 11734000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 11734000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 24014999 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 24014999 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 35748999 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 35748999 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 35748999 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 35748999 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1911 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1911 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2942 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2942 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2942 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2942 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083293 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.083293 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2812 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2812 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2812 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2812 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086342 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.086342 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.175051 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.175051 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.175051 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.175051 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69050 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 69050 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69779.707246 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69779.707246 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 69538.833010 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 69538.833010 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 69538.833010 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 69538.833010 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 615 # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data 0.181366 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.181366 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.181366 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.181366 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71115.151515 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 71115.151515 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69608.692754 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 69608.692754 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 70096.076471 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 70096.076471 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 70096.076471 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 70096.076471 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 587 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.909091 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.700000 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 295 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 369 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 369 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 369 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
@@ -657,82 +657,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141
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@@ -741,54 +741,54 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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@@ -865,105 +865,105 @@ system.cpu.l2cache.fast_writes 0 # nu
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system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 471 # Request fanout histogram
+system.membus.snoop_fanout::samples 469 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 471 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 469 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 471 # Request fanout histogram
-system.membus.reqLayer0.occupancy 582000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 469 # Request fanout histogram
+system.membus.reqLayer0.occupancy 580000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.6 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2503500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 11.2 # Layer utilization (%)
+system.membus.respLayer1.occupancy 2493500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 11.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
index 4915dc4bb..ff8cb9e3e 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
@@ -230,7 +230,6 @@ hot_lines=false
memory_size_bits=48
num_of_sequencers=1
phys_mem=Null
-random_seed=1234
randomization=false
[system.ruby.clk_domain]
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
index 8f334ebb7..585054648 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000020 # Number of seconds simulated
-sim_ticks 19998000 # Number of ticks simulated
-final_tick 19998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 19922000 # Number of ticks simulated
+final_tick 19922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 99740 # Simulator instruction rate (inst/s)
-host_op_rate 99716 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 344211505 # Simulator tick rate (ticks/s)
-host_mem_usage 290580 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 38523 # Simulator instruction rate (inst/s)
+host_op_rate 38518 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 132470471 # Simulator tick rate (ticks/s)
+host_mem_usage 286104 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21952 # Nu
system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory
system.physmem.num_reads::total 444 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1097709771 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 323232323 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1420942094 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1097709771 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1097709771 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1097709771 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 323232323 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1420942094 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1101897400 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 324465415 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1426362815 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1101897400 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1101897400 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1101897400 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 324465415 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1426362815 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 444 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 19858500 # Total gap between requests
+system.physmem.totGap 19782500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 242 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 141 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -186,79 +186,79 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 332.307692 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 194.430832 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 340.544877 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 29 37.18% 37.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 17 21.79% 58.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 7 8.97% 67.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 4 5.13% 73.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 4 5.13% 78.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 3 3.85% 82.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 2 2.56% 84.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 3 3.85% 88.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 9 11.54% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation
-system.physmem.totQLat 3950250 # Total ticks spent queuing
-system.physmem.totMemAccLat 12275250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 340.210526 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 203.437950 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 338.690117 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 26 34.21% 34.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 17 22.37% 56.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 8 10.53% 67.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 4 5.26% 72.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 4 5.26% 77.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 4 5.26% 82.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1 1.32% 84.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 9 11.84% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation
+system.physmem.totQLat 3750750 # Total ticks spent queuing
+system.physmem.totMemAccLat 12075750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 8896.96 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 8447.64 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 27646.96 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1420.94 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 27197.64 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1426.36 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1420.94 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1426.36 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 11.10 # Data bus utilization in percentage
-system.physmem.busUtilRead 11.10 # Data bus utilization in percentage for reads
+system.physmem.busUtil 11.14 # Data bus utilization in percentage
+system.physmem.busUtilRead 11.14 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.79 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 357 # Number of row buffer hits during reads
+system.physmem.readRowHits 359 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 80.41 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 80.86 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 44726.35 # Average gap between requests
-system.physmem.pageHitRate 80.41 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 461160 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 251625 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 2519400 # Energy for read commands per rank (pJ)
+system.physmem.avgGap 44555.18 # Average gap between requests
+system.physmem.pageHitRate 80.86 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 438480 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 239250 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 2511600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 15077640 # Total energy per rank (pJ)
-system.physmem_0.averagePower 952.021468 # Core power per rank (mW)
+system.physmem_0.actBackEnergy 10783260 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 40500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 15030210 # Total energy per rank (pJ)
+system.physmem_0.averagePower 949.326386 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 15318750 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 68040 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 7492365 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 2927250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 11830500 # Total energy per rank (pJ)
-system.physmem_1.averagePower 747.228802 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 6597250 # Time in different power states
+system.physmem_1.actBackEnergy 7628310 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 2808000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 11847195 # Total energy per rank (pJ)
+system.physmem_1.averagePower 748.283278 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 6322250 # Time in different power states
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 10517250 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 10715250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 2331 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1883 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 415 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 1931 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 661 # Number of BTB hits
+system.cpu.branchPred.lookups 2359 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1936 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 404 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1982 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 725 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 34.230968 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 218 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 36.579213 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@@ -279,237 +279,237 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 9 # Number of system calls
-system.cpu.numCycles 39997 # number of cpu cycles simulated
+system.cpu.numCycles 39845 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 7837 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 13501 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2331 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 879 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 4391 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 863 # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles 7679 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 13188 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2359 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 949 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 3750 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 839 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 153 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingTrapStallCycles 147 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 1828 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 299 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 12836 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.051807 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.461524 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 1822 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 291 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 12019 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.097263 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.493815 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 10473 81.59% 81.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 190 1.48% 83.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 215 1.67% 84.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 153 1.19% 85.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 248 1.93% 87.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 135 1.05% 88.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 253 1.97% 90.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 115 0.90% 91.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1054 8.21% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 9698 80.69% 80.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 176 1.46% 82.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 221 1.84% 83.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 153 1.27% 85.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 238 1.98% 87.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 147 1.22% 88.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 274 2.28% 90.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 116 0.97% 91.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 996 8.29% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 12836 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.058279 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.337550 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 7233 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 3240 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 1952 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 129 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 282 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 335 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 150 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 11562 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 472 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 282 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 7391 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 953 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 624 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 1916 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 1670 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 11195 # Number of instructions processed by rename
+system.cpu.fetch.rateDist::total 12019 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.059204 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.330983 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 7188 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 2504 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 1924 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 271 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 317 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 149 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 11315 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 469 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 271 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 7350 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 927 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 518 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 1884 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 1069 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 10932 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 1610 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 9626 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 18124 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 18098 # Number of integer rename lookups
+system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 1028 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 9574 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 17720 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 17694 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 4628 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 4576 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 27 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 362 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2015 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1832 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads.
+system.cpu.memDep0.insertedLoads 1935 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1629 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 53 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 10320 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 10141 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 9101 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 4591 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqInstsIssued 8840 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 52 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 4412 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3358 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 12836 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.709022 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.537942 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 12019 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.735502 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.540494 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 9696 75.54% 75.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 959 7.47% 83.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 638 4.97% 87.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 461 3.59% 91.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 440 3.43% 95.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 291 2.27% 97.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 236 1.84% 99.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 68 0.53% 99.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 47 0.37% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 8914 74.17% 74.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 959 7.98% 82.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 649 5.40% 87.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 465 3.87% 91.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 426 3.54% 94.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 281 2.34% 97.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 228 1.90% 99.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 65 0.54% 99.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 32 0.27% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 12836 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 12019 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 11 4.38% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 121 48.21% 52.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 119 47.41% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 13 6.47% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 95 47.26% 53.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 93 46.27% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5531 60.77% 60.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.77% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 1910 20.99% 81.78% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1658 18.22% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 5519 62.43% 62.43% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.43% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 1819 20.58% 83.03% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1500 16.97% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 9101 # Type of FU issued
-system.cpu.iq.rate 0.227542 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 251 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.027579 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 31302 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 14945 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 8267 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 8840 # Type of FU issued
+system.cpu.iq.rate 0.221860 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 201 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.022738 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 29890 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 14587 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 8120 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 9318 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 9007 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1054 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 974 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 786 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 583 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 282 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 869 # Number of cycles IEW is blocking
+system.cpu.iew.iewSquashCycles 271 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 843 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 77 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 10383 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 18 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2015 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1832 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 10204 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 34 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 1935 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1629 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 66 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 345 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8700 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 1776 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect 72 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 254 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 326 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 8485 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 1707 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 355 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3330 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1363 # Number of branches executed
-system.cpu.iew.exec_stores 1554 # Number of stores executed
-system.cpu.iew.exec_rate 0.217516 # Inst execution rate
-system.cpu.iew.wb_sent 8425 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 8294 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 4459 # num instructions producing a value
-system.cpu.iew.wb_consumers 7044 # num instructions consuming a value
+system.cpu.iew.exec_refs 3121 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1355 # Number of branches executed
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+system.cpu.iew.exec_rate 0.212950 # Inst execution rate
+system.cpu.iew.wb_sent 8249 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 8147 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 4452 # num instructions producing a value
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.207366 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.633021 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.204467 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.625808 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 4593 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 4414 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 276 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 12125 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.477691 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.335541 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 265 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 11324 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.511480 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.378975 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 9949 82.05% 82.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 859 7.08% 89.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 524 4.32% 93.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 226 1.86% 95.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 182 1.50% 96.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 108 0.89% 97.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 109 0.90% 98.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 59 0.49% 99.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 109 0.90% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 9160 80.89% 80.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 847 7.48% 88.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 528 4.66% 93.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 216 1.91% 94.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 182 1.61% 96.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 106 0.94% 97.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 122 1.08% 98.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 53 0.47% 99.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 110 0.97% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 12125 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 11324 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5792 # Number of instructions committed
system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -555,250 +555,250 @@ system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 5792 # Class of committed instruction
-system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 22401 # The number of ROB reads
-system.cpu.rob.rob_writes 21482 # The number of ROB writes
-system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 27161 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 21420 # The number of ROB reads
+system.cpu.rob.rob_writes 21108 # The number of ROB writes
+system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 27826 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5792 # Number of Instructions Simulated
system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 6.905559 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 6.905559 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.144811 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.144811 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 13740 # number of integer regfile reads
-system.cpu.int_regfile_writes 7170 # number of integer regfile writes
+system.cpu.cpi 6.879316 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 6.879316 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.145363 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.145363 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 13451 # number of integer regfile reads
+system.cpu.int_regfile_writes 7138 # number of integer regfile writes
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
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-system.cpu.dcache.tags.avg_refs 22.274510 # Average number of references to valid blocks.
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+system.cpu.dcache.tags.avg_refs 21.485437 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.982857 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.982857 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.981818 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.981818 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.964286 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.964286 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982857 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.990196 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.984513 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.980583 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.982340 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.984513 # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95276.595745 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95276.595745 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74481.104651 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74481.104651 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82564.814815 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82564.814815 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74481.104651 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88480.198020 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77658.426966 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74481.104651 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88480.198020 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77658.426966 # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.980583 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.982340 # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83670.212766 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83670.212766 # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75588.662791 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75588.662791 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81898.148148 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81898.148148 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75588.662791 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82722.772277 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77207.865169 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75588.662791 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82722.772277 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77207.865169 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -879,71 +879,71 @@ system.cpu.l2cache.demand_mshr_misses::total 445
system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4008000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4008000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22191500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22191500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3918500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3918500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22191500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7926500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 30118000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22191500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7926500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 30118000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3462500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3462500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22572500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22572500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3882500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3882500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22572500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7345000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 29917500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22572500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7345000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 29917500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.982857 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.981818 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.964286 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.964286 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.984513 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980583 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.982340 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.984513 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85276.595745 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85276.595745 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64510.174419 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64510.174419 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72564.814815 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72564.814815 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64510.174419 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78480.198020 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67680.898876 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64510.174419 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78480.198020 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67680.898876 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980583 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.982340 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73670.212766 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73670.212766 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65617.732558 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65617.732558 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71898.148148 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71898.148148 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65617.732558 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72722.772277 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67230.337079 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65617.732558 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72722.772277 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67230.337079 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 405 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 350 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 56 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 903 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 206 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 905 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6592 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 28928 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 453 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 453 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 453 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 523500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 154500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
system.membus.trans_dist::ReadResp 397 # Transaction distribution
system.membus.trans_dist::ReadExReq 47 # Transaction distribution
@@ -964,9 +964,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 444 # Request fanout histogram
-system.membus.reqLayer0.occupancy 550500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 551000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2342500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 11.7 # Layer utilization (%)
+system.membus.respLayer1.occupancy 2342750 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 11.8 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
index cf52ef870..d45cde2de 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
@@ -227,7 +227,6 @@ hot_lines=false
memory_size_bits=48
num_of_sequencers=1
phys_mem=Null
-random_seed=1234
randomization=false
[system.ruby.clk_domain]
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index ef02c087f..e476df038 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -1,58 +1,58 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000021 # Number of seconds simulated
-sim_ticks 21012000 # Number of ticks simulated
-final_tick 21012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 20817000 # Number of ticks simulated
+final_tick 20817000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 49067 # Simulator instruction rate (inst/s)
-host_op_rate 88883 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 191585973 # Simulator tick rate (ticks/s)
-host_mem_usage 310932 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
+host_inst_rate 31285 # Simulator instruction rate (inst/s)
+host_op_rate 56673 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 121026192 # Simulator tick rate (ticks/s)
+host_mem_usage 306568 # Number of bytes of host memory used
+host_seconds 0.17 # Real time elapsed on the host
sim_insts 5380 # Number of instructions simulated
sim_ops 9747 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory
-system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 837616600 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 429468875 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1267085475 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 837616600 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 837616600 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 837616600 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 429468875 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1267085475 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 417 # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 8896 # Number of bytes read from this memory
+system.physmem.bytes_read::total 26560 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 139 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 415 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 848537253 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 427343037 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1275880290 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 848537253 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 848537253 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 848537253 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 427343037 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1275880290 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 415 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 26688 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 26560 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 26688 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 26560 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 34 # Per bank write bursts
+system.physmem.perBankRdBursts::0 32 # Per bank write bursts
system.physmem.perBankRdBursts::1 1 # Per bank write bursts
system.physmem.perBankRdBursts::2 6 # Per bank write bursts
system.physmem.perBankRdBursts::3 8 # Per bank write bursts
system.physmem.perBankRdBursts::4 50 # Per bank write bursts
-system.physmem.perBankRdBursts::5 45 # Per bank write bursts
+system.physmem.perBankRdBursts::5 46 # Per bank write bursts
system.physmem.perBankRdBursts::6 21 # Per bank write bursts
-system.physmem.perBankRdBursts::7 34 # Per bank write bursts
-system.physmem.perBankRdBursts::8 22 # Per bank write bursts
-system.physmem.perBankRdBursts::9 74 # Per bank write bursts
+system.physmem.perBankRdBursts::7 33 # Per bank write bursts
+system.physmem.perBankRdBursts::8 25 # Per bank write bursts
+system.physmem.perBankRdBursts::9 72 # Per bank write bursts
system.physmem.perBankRdBursts::10 63 # Per bank write bursts
-system.physmem.perBankRdBursts::11 17 # Per bank write bursts
+system.physmem.perBankRdBursts::11 16 # Per bank write bursts
system.physmem.perBankRdBursts::12 2 # Per bank write bursts
system.physmem.perBankRdBursts::13 17 # Per bank write bursts
system.physmem.perBankRdBursts::14 6 # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 20963500 # Total gap between requests
+system.physmem.totGap 20721000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 417 # Read request sizes (log2)
+system.physmem.readPktSize::6 415 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 244 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -186,310 +186,310 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 99 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 239.838384 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 160.844462 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 248.938264 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 34 34.34% 34.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 32 32.32% 66.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 15 15.15% 81.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 5 5.05% 86.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2 2.02% 88.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 4 4.04% 92.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1 1.01% 93.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 2 2.02% 95.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 4 4.04% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 99 # Bytes accessed per row activation
-system.physmem.totQLat 3956500 # Total ticks spent queuing
-system.physmem.totMemAccLat 11775250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 9488.01 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 96 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 252 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 164.484740 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 262.126687 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 35 36.46% 36.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 26 27.08% 63.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 15 15.62% 79.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 6 6.25% 85.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 3 3.12% 88.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 3 3.12% 91.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 2 2.08% 93.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1 1.04% 94.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 5 5.21% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 96 # Bytes accessed per row activation
+system.physmem.totQLat 4745000 # Total ticks spent queuing
+system.physmem.totMemAccLat 12526250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2075000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 11433.73 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 28238.01 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1270.13 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 30183.73 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1275.88 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1270.13 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1275.88 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 9.92 # Data bus utilization in percentage
-system.physmem.busUtilRead 9.92 # Data bus utilization in percentage for reads
+system.physmem.busUtil 9.97 # Data bus utilization in percentage
+system.physmem.busUtilRead 9.97 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 308 # Number of row buffer hits during reads
+system.physmem.readRowHits 309 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 73.86 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 74.46 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 50272.18 # Average gap between requests
-system.physmem.pageHitRate 73.86 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 189000 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 103125 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 951600 # Energy for read commands per rank (pJ)
+system.physmem.avgGap 49930.12 # Average gap between requests
+system.physmem.pageHitRate 74.46 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 959400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 13085760 # Total energy per rank (pJ)
-system.physmem_0.averagePower 826.512553 # Core power per rank (mW)
+system.physmem_0.totalEnergy 13105245 # Total energy per rank (pJ)
+system.physmem_0.averagePower 827.743250 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 430920 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 235125 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy 423360 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 231000 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1536600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 10315575 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 450750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 13970490 # Total energy per rank (pJ)
-system.physmem_1.averagePower 882.393179 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 973750 # Time in different power states
+system.physmem_1.actBackEnergy 10696905 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 116250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 14021235 # Total energy per rank (pJ)
+system.physmem_1.averagePower 885.598295 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 271750 # Time in different power states
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 14667250 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 15224250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 3416 # Number of BP lookups
-system.cpu.branchPred.condPredicted 3416 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 534 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 2538 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 864 # Number of BTB hits
+system.cpu.branchPred.lookups 3234 # Number of BP lookups
+system.cpu.branchPred.condPredicted 3234 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 514 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 2557 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 881 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 34.042553 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 247 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 34.454439 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 280 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 86 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 42025 # number of cpu cycles simulated
+system.cpu.numCycles 41635 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 11194 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 15490 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 3416 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1111 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 9646 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1195 # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles 11661 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 14637 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 3234 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1161 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 9674 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1159 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1127 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.CacheLines 2165 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 22628 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.226003 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.725670 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.CacheLines 2075 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 22725 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.149527 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.648759 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 18363 81.15% 81.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 236 1.04% 82.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 174 0.77% 82.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 258 1.14% 84.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 208 0.92% 85.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 227 1.00% 86.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 337 1.49% 87.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 205 0.91% 88.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 2620 11.58% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 18699 82.28% 82.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 221 0.97% 83.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 146 0.64% 83.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 231 1.02% 84.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 214 0.94% 85.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 258 1.14% 86.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 336 1.48% 88.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 205 0.90% 89.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 2415 10.63% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 22628 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.081285 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.368590 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 10919 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 7328 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 3329 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 455 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 597 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 25699 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 597 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 11189 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 2276 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 782 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 3470 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 4314 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 24173 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 93 # Number of times rename has blocked due to IQ full
+system.cpu.fetch.rateDist::total 22725 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.077675 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.351555 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 11462 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 7072 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 3206 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 406 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 579 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 24310 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 579 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 11710 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 1815 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 1004 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 3327 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 4290 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 23005 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 71 # Number of times rename has blocked due to IQ full
system.cpu.rename.SQFullEvents 4163 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 27542 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 59265 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 33505 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 26169 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 57126 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 32219 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 16479 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 29 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 1507 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2438 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1611 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads.
+system.cpu.rename.UndoneMaps 15106 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 28 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 1472 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2371 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1574 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 20 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 21416 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 17876 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 11694 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 16519 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 22628 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.789995 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.748596 # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded 20445 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 17161 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 65 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 10724 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 15317 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 22725 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.755160 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.702113 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 17504 77.36% 77.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1142 5.05% 82.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 891 3.94% 86.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 637 2.82% 89.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 831 3.67% 92.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 584 2.58% 95.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 600 2.65% 98.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 315 1.39% 99.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 124 0.55% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 17737 78.05% 78.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1126 4.95% 83.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 880 3.87% 86.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 631 2.78% 89.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 810 3.56% 93.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 590 2.60% 95.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 568 2.50% 98.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 280 1.23% 99.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 103 0.45% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 22628 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 22725 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 174 77.68% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 31 13.84% 91.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 19 8.48% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 151 71.23% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 43 20.28% 91.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 18 8.49% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 14362 80.34% 80.36% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.38% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2121 11.87% 92.29% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1379 7.71% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 13707 79.87% 79.89% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 4 0.02% 79.91% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 7 0.04% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2071 12.07% 92.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1369 7.98% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 17876 # Type of FU issued
-system.cpu.iq.rate 0.425366 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 224 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.012531 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 58676 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 33142 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 16350 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 17161 # Type of FU issued
+system.cpu.iq.rate 0.412177 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 212 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.012354 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 57316 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 31202 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 15767 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 18093 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 17366 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 235 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 220 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1385 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1318 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 676 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 639 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 597 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1916 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 21441 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2438 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1611 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 58 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 565 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 690 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 16903 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 1966 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 973 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 579 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1449 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 20471 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 46 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2371 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1574 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 34 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 15 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 136 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 524 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 660 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 16265 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 1913 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 896 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3248 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1659 # Number of branches executed
-system.cpu.iew.exec_stores 1282 # Number of stores executed
-system.cpu.iew.exec_rate 0.402213 # Inst execution rate
-system.cpu.iew.wb_sent 16611 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 16354 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 10992 # num instructions producing a value
-system.cpu.iew.wb_consumers 17112 # num instructions consuming a value
+system.cpu.iew.exec_refs 3175 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1626 # Number of branches executed
+system.cpu.iew.exec_stores 1262 # Number of stores executed
+system.cpu.iew.exec_rate 0.390657 # Inst execution rate
+system.cpu.iew.wb_sent 16001 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 15771 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 10637 # num instructions producing a value
+system.cpu.iew.wb_consumers 16589 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.389149 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.642356 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.378792 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.641208 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 11693 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 10723 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 584 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 20667 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.471621 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.370778 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 565 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 20943 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.465406 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.357230 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 17422 84.30% 84.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1008 4.88% 89.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 544 2.63% 91.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 740 3.58% 95.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 368 1.78% 97.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 141 0.68% 97.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 113 0.55% 98.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 72 0.35% 98.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 259 1.25% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 17686 84.45% 84.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 994 4.75% 89.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 561 2.68% 91.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 764 3.65% 95.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 370 1.77% 97.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 129 0.62% 97.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 114 0.54% 98.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 70 0.33% 98.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 255 1.22% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.committedInsts 5380 # Number of instructions committed
system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -535,185 +535,185 @@ system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu.committedInsts 5380 # Number of Instructions Simulated
system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated
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-system.cpu.cpi_total 7.811338 # CPI: Total CPI of All Threads
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-system.cpu.ipc_total 0.128019 # IPC: Total IPC of All Threads
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996377 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996390 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.997608 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996377 # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total 0.997596 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996390 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77512.820513 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77512.820513 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77061.818182 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77061.818182 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83468.750000 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83468.750000 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77061.818182 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80197.183099 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 78129.496403 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77061.818182 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80197.183099 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 78129.496403 # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total 0.997596 # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81045.454545 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81045.454545 # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79317.028986 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79317.028986 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83758.064516 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83758.064516 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79317.028986 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82255.395683 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 80301.204819 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79317.028986 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82255.395683 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 80301.204819 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -844,108 +844,108 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 78 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 78 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 275 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 275 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 64 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 64 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5266000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5266000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18442000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18442000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4712000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4712000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18442000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9978000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 28420000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18442000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9978000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 28420000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 77 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 77 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 276 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 276 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 62 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 62 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 139 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 415 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 139 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 415 # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5470500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5470500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19131500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19131500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4573000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4573000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19131500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10043500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 29175000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19131500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10043500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 29175000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996377 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996390 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996390 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996390 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.997596 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996390 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67512.820513 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67512.820513 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67061.818182 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67061.818182 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73625 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73625 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67061.818182 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70267.605634 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68153.477218 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67061.818182 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70267.605634 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68153.477218 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.997596 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71045.454545 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71045.454545 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69317.028986 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69317.028986 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73758.064516 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73758.064516 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69317.028986 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72255.395683 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70301.204819 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69317.028986 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72255.395683 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70301.204819 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 78 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 78 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 276 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 64 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 552 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 283 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17664 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 277 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 62 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 554 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 278 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 832 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17728 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8896 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 416 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 418 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 416 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 416 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 208000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 414000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 415500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 208500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
system.membus.trans_dist::ReadResp 338 # Transaction distribution
-system.membus.trans_dist::ReadExReq 78 # Transaction distribution
-system.membus.trans_dist::ReadExResp 78 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 339 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq 77 # Transaction distribution
+system.membus.trans_dist::ReadExResp 77 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 338 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 830 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 830 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 830 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26560 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26560 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 26560 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 417 # Request fanout histogram
+system.membus.snoop_fanout::samples 415 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 415 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 417 # Request fanout histogram
-system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 415 # Request fanout histogram
+system.membus.reqLayer0.occupancy 500000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2222250 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2216750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 10.6 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
index c1f4aa57f..56411f6d5 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
@@ -261,7 +261,6 @@ hot_lines=false
memory_size_bits=48
num_of_sequencers=1
phys_mem=Null
-random_seed=1234
randomization=false
[system.ruby.clk_domain]
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index 95258693a..3cf449dc8 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -1,61 +1,61 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000025 # Number of seconds simulated
-sim_ticks 24760000 # Number of ticks simulated
-final_tick 24760000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 24832500 # Number of ticks simulated
+final_tick 24832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 82189 # Simulator instruction rate (inst/s)
-host_op_rate 82182 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 159657472 # Simulator tick rate (ticks/s)
-host_mem_usage 295960 # Number of bytes of host memory used
-host_seconds 0.16 # Real time elapsed on the host
+host_inst_rate 45282 # Simulator instruction rate (inst/s)
+host_op_rate 45279 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 88223588 # Simulator tick rate (ticks/s)
+host_mem_usage 290360 # Number of bytes of host memory used
+host_seconds 0.28 # Real time elapsed on the host
sim_insts 12744 # Number of instructions simulated
sim_ops 12744 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 40576 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 22144 # Number of bytes read from this memory
-system.physmem.bytes_read::total 62720 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 40576 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 40576 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 634 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 346 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 980 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1638772213 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 894345719 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2533117932 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1638772213 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1638772213 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1638772213 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 894345719 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2533117932 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 980 # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst 40448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 22016 # Number of bytes read from this memory
+system.physmem.bytes_read::total 62464 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 40448 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 40448 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 632 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 344 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 976 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1628833182 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 886580087 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2515413269 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1628833182 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1628833182 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1628833182 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 886580087 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2515413269 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 976 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 980 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 976 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 62720 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 62464 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 62720 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 62464 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 83 # Per bank write bursts
-system.physmem.perBankRdBursts::1 155 # Per bank write bursts
-system.physmem.perBankRdBursts::2 77 # Per bank write bursts
+system.physmem.perBankRdBursts::0 84 # Per bank write bursts
+system.physmem.perBankRdBursts::1 152 # Per bank write bursts
+system.physmem.perBankRdBursts::2 78 # Per bank write bursts
system.physmem.perBankRdBursts::3 59 # Per bank write bursts
system.physmem.perBankRdBursts::4 88 # Per bank write bursts
-system.physmem.perBankRdBursts::5 49 # Per bank write bursts
+system.physmem.perBankRdBursts::5 48 # Per bank write bursts
system.physmem.perBankRdBursts::6 33 # Per bank write bursts
system.physmem.perBankRdBursts::7 50 # Per bank write bursts
system.physmem.perBankRdBursts::8 42 # Per bank write bursts
system.physmem.perBankRdBursts::9 39 # Per bank write bursts
-system.physmem.perBankRdBursts::10 30 # Per bank write bursts
+system.physmem.perBankRdBursts::10 29 # Per bank write bursts
system.physmem.perBankRdBursts::11 34 # Per bank write bursts
system.physmem.perBankRdBursts::12 15 # Per bank write bursts
system.physmem.perBankRdBursts::13 120 # Per bank write bursts
-system.physmem.perBankRdBursts::14 69 # Per bank write bursts
+system.physmem.perBankRdBursts::14 68 # Per bank write bursts
system.physmem.perBankRdBursts::15 37 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 24609000 # Total gap between requests
+system.physmem.totGap 24688000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 980 # Read request sizes (log2)
+system.physmem.readPktSize::6 976 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 346 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 324 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 194 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 80 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 31 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 340 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 321 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 209 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 78 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 21 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
@@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 211 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 289.971564 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 183.051447 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 289.757171 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 69 32.70% 32.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 60 28.44% 61.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 22 10.43% 71.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 12 5.69% 77.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 14 6.64% 83.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 12 5.69% 89.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 3 1.42% 91.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 8 3.79% 94.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 11 5.21% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 211 # Bytes accessed per row activation
-system.physmem.totQLat 12705250 # Total ticks spent queuing
-system.physmem.totMemAccLat 31080250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 4900000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 12964.54 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 217 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 280.184332 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 175.894103 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 284.655938 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 78 35.94% 35.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 61 28.11% 64.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 19 8.76% 72.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 11 5.07% 77.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 14 6.45% 84.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 13 5.99% 90.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 4 1.84% 92.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 6 2.76% 94.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 11 5.07% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 217 # Bytes accessed per row activation
+system.physmem.totQLat 12728500 # Total ticks spent queuing
+system.physmem.totMemAccLat 31028500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 4880000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 13041.50 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 31714.54 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 2533.12 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 31791.50 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2515.41 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 2533.12 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2515.41 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 19.79 # Data bus utilization in percentage
-system.physmem.busUtilRead 19.79 # Data bus utilization in percentage for reads
+system.physmem.busUtil 19.65 # Data bus utilization in percentage
+system.physmem.busUtilRead 19.65 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 2.43 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 2.42 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 761 # Number of row buffer hits during reads
+system.physmem.readRowHits 749 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 77.65 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 76.74 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 25111.22 # Average gap between requests
-system.physmem.pageHitRate 77.65 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 861840 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 470250 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 4539600 # Energy for read commands per rank (pJ)
+system.physmem.avgGap 25295.08 # Average gap between requests
+system.physmem.pageHitRate 76.74 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 892080 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 486750 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 4516200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 16083405 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 63000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 23543775 # Total energy per rank (pJ)
-system.physmem_0.averagePower 996.825615 # Core power per rank (mW)
+system.physmem_0.actBackEnergy 16092810 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 54750 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 23568270 # Total energy per rank (pJ)
+system.physmem_0.averagePower 997.862715 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states
system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 703080 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 383625 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 2878200 # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy 718200 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 391875 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 2847000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 15819210 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 295500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 21605295 # Total energy per rank (pJ)
-system.physmem_1.averagePower 914.703429 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 407500 # Time in different power states
+system.physmem_1.actBackEnergy 15524235 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 557250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 21564240 # Total energy per rank (pJ)
+system.physmem_1.averagePower 912.772063 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 830500 # Time in different power states
system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 22446250 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 22027750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 7026 # Number of BP lookups
-system.cpu.branchPred.condPredicted 3965 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1425 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 5143 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 872 # Number of BTB hits
+system.cpu.branchPred.lookups 6978 # Number of BP lookups
+system.cpu.branchPred.condPredicted 3979 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1366 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 5343 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 988 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 16.955085 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1033 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 18.491484 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1115 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 79 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 4832 # DTB read hits
-system.cpu.dtb.read_misses 93 # DTB read misses
+system.cpu.dtb.read_hits 4756 # DTB read hits
+system.cpu.dtb.read_misses 94 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 4925 # DTB read accesses
-system.cpu.dtb.write_hits 2065 # DTB write hits
-system.cpu.dtb.write_misses 72 # DTB write misses
+system.cpu.dtb.read_accesses 4850 # DTB read accesses
+system.cpu.dtb.write_hits 2093 # DTB write hits
+system.cpu.dtb.write_misses 69 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 2137 # DTB write accesses
-system.cpu.dtb.data_hits 6897 # DTB hits
-system.cpu.dtb.data_misses 165 # DTB misses
+system.cpu.dtb.write_accesses 2162 # DTB write accesses
+system.cpu.dtb.data_hits 6849 # DTB hits
+system.cpu.dtb.data_misses 163 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 7062 # DTB accesses
-system.cpu.itb.fetch_hits 5266 # ITB hits
-system.cpu.itb.fetch_misses 59 # ITB misses
+system.cpu.dtb.data_accesses 7012 # DTB accesses
+system.cpu.itb.fetch_hits 5404 # ITB hits
+system.cpu.itb.fetch_misses 57 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 5325 # ITB accesses
+system.cpu.itb.fetch_accesses 5461 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -294,318 +294,318 @@ system.cpu.itb.data_acv 0 # DT
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload0.num_syscalls 17 # Number of system calls
system.cpu.workload1.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 49521 # number of cpu cycles simulated
+system.cpu.numCycles 49666 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 1262 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 39496 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 7026 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1905 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 11647 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1505 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 695 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines 5266 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 809 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 28518 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.384950 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.783550 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 1235 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 39559 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 6978 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 2103 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 10834 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1446 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 389 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines 5404 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 838 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 27534 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.436733 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.801651 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 21883 76.73% 76.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 531 1.86% 78.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 405 1.42% 80.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 525 1.84% 81.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 527 1.85% 83.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 419 1.47% 85.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 492 1.73% 86.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 463 1.62% 88.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 3273 11.48% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 20750 75.36% 75.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 584 2.12% 77.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 426 1.55% 79.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 584 2.12% 81.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 571 2.07% 83.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 441 1.60% 84.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 491 1.78% 86.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 560 2.03% 88.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 3127 11.36% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 28518 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.141879 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.797561 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 38016 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 11989 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 5115 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 629 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1147 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 585 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 376 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 32323 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 785 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1147 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 38621 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 5295 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 1200 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 5143 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5490 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 30197 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 57 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 302 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 566 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 4493 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 22785 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 37650 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 37632 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 27534 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.140499 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.796501 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 37298 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 10659 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 5112 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 613 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1127 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 528 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 328 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 32201 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 725 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1127 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 37873 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 4968 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 1226 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 5149 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 4466 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 30276 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 78 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 324 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 847 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 3132 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 22817 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 37709 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 37691 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 13645 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 56 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 2153 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2897 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1434 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 31 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 21 # Number of conflicting stores.
-system.cpu.memDep1.insertedLoads 2813 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep1.insertedStores 1365 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep1.conflictingLoads 3 # Number of conflicting loads.
+system.cpu.rename.UndoneMaps 13677 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 60 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 2263 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2834 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1407 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores.
+system.cpu.memDep1.insertedLoads 2862 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep1.insertedStores 1462 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep1.conflictingLoads 2 # Number of conflicting loads.
system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 26855 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 22315 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 102 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 14161 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 7975 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 28518 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.782488 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.503369 # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded 27015 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 50 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 22338 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 130 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 14320 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 8141 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 27534 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.811288 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.520707 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 20180 70.76% 70.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 2624 9.20% 79.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 1911 6.70% 86.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 1348 4.73% 91.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 1241 4.35% 95.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 673 2.36% 98.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 344 1.21% 99.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 144 0.50% 99.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 53 0.19% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 19179 69.66% 69.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 2638 9.58% 79.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 1919 6.97% 86.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 1327 4.82% 91.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 1227 4.46% 95.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 711 2.58% 98.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 354 1.29% 99.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 138 0.50% 99.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 41 0.15% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 28518 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 27534 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 33 9.65% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 224 65.50% 75.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 85 24.85% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 32 9.64% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 217 65.36% 75.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 83 25.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 7386 65.50% 65.52% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.53% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2741 24.31% 89.85% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1144 10.15% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 7321 66.01% 66.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2641 23.81% 89.87% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1123 10.13% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 11276 # Type of FU issued
+system.cpu.iq.FU_type_0::total 11090 # Type of FU issued
system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_1::IntAlu 7337 66.46% 66.48% # Type of FU issued
-system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.49% # Type of FU issued
-system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.49% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::MemRead 2570 23.28% 89.79% # Type of FU issued
-system.cpu.iq.FU_type_1::MemWrite 1127 10.21% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_1::IntAlu 7446 66.20% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.23% # Type of FU issued
+system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.23% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::MemRead 2645 23.52% 89.76% # Type of FU issued
+system.cpu.iq.FU_type_1::MemWrite 1152 10.24% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_1::total 11039 # Type of FU issued
-system.cpu.iq.FU_type::total 22315 0.00% 0.00% # Type of FU issued
-system.cpu.iq.rate 0.450617 # Inst issue rate
-system.cpu.iq.fu_busy_cnt::0 168 # FU busy when requested
-system.cpu.iq.fu_busy_cnt::1 174 # FU busy when requested
-system.cpu.iq.fu_busy_cnt::total 342 # FU busy when requested
-system.cpu.iq.fu_busy_rate::0 0.007529 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::1 0.007797 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::total 0.015326 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 73550 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 41081 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 19615 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_1::total 11248 # Type of FU issued
+system.cpu.iq.FU_type::total 22338 0.00% 0.00% # Type of FU issued
+system.cpu.iq.rate 0.449764 # Inst issue rate
+system.cpu.iq.fu_busy_cnt::0 166 # FU busy when requested
+system.cpu.iq.fu_busy_cnt::1 166 # FU busy when requested
+system.cpu.iq.fu_busy_cnt::total 332 # FU busy when requested
+system.cpu.iq.fu_busy_rate::0 0.007431 # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::1 0.007431 # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::total 0.014863 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 72630 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 41400 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 19613 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 22631 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 22644 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 87 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1714 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 569 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1651 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 542 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 342 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread1.forwLoads 63 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.cacheBlocked 309 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.forwLoads 73 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread1.squashedLoads 1630 # Number of loads squashed
-system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread1.memOrderViolation 18 # Number of memory ordering violations
-system.cpu.iew.lsq.thread1.squashedStores 500 # Number of stores squashed
+system.cpu.iew.lsq.thread1.squashedLoads 1679 # Number of loads squashed
+system.cpu.iew.lsq.thread1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread1.memOrderViolation 17 # Number of memory ordering violations
+system.cpu.iew.lsq.thread1.squashedStores 597 # Number of stores squashed
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread1.cacheBlocked 278 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.cacheBlocked 327 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1147 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 2841 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 538 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 27054 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 353 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 5710 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 2799 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 505 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 36 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 142 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1136 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1278 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 21041 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts::0 2537 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::1 2397 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::total 4934 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1274 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 1127 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 2708 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 614 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 27211 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 237 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 5696 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 2869 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 50 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 589 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 37 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 160 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1089 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1249 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 21052 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts::0 2447 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::1 2411 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::total 4858 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1286 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
system.cpu.iew.exec_nop::0 74 # number of nop insts executed
-system.cpu.iew.exec_nop::1 74 # number of nop insts executed
-system.cpu.iew.exec_nop::total 148 # number of nop insts executed
-system.cpu.iew.exec_refs::0 3628 # number of memory reference insts executed
-system.cpu.iew.exec_refs::1 3464 # number of memory reference insts executed
-system.cpu.iew.exec_refs::total 7092 # number of memory reference insts executed
-system.cpu.iew.exec_branches::0 1676 # Number of branches executed
-system.cpu.iew.exec_branches::1 1656 # Number of branches executed
-system.cpu.iew.exec_branches::total 3332 # Number of branches executed
-system.cpu.iew.exec_stores::0 1091 # Number of stores executed
-system.cpu.iew.exec_stores::1 1067 # Number of stores executed
-system.cpu.iew.exec_stores::total 2158 # Number of stores executed
-system.cpu.iew.exec_rate 0.424890 # Inst execution rate
-system.cpu.iew.wb_sent::0 10100 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::1 9901 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::total 20001 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count::0 9896 # cumulative count of insts written-back
-system.cpu.iew.wb_count::1 9739 # cumulative count of insts written-back
-system.cpu.iew.wb_count::total 19635 # cumulative count of insts written-back
-system.cpu.iew.wb_producers::0 5244 # num instructions producing a value
-system.cpu.iew.wb_producers::1 5132 # num instructions producing a value
-system.cpu.iew.wb_producers::total 10376 # num instructions producing a value
-system.cpu.iew.wb_consumers::0 6970 # num instructions consuming a value
-system.cpu.iew.wb_consumers::1 6831 # num instructions consuming a value
-system.cpu.iew.wb_consumers::total 13801 # num instructions consuming a value
+system.cpu.iew.exec_nop::1 72 # number of nop insts executed
+system.cpu.iew.exec_nop::total 146 # number of nop insts executed
+system.cpu.iew.exec_refs::0 3514 # number of memory reference insts executed
+system.cpu.iew.exec_refs::1 3522 # number of memory reference insts executed
+system.cpu.iew.exec_refs::total 7036 # number of memory reference insts executed
+system.cpu.iew.exec_branches::0 1644 # Number of branches executed
+system.cpu.iew.exec_branches::1 1639 # Number of branches executed
+system.cpu.iew.exec_branches::total 3283 # Number of branches executed
+system.cpu.iew.exec_stores::0 1067 # Number of stores executed
+system.cpu.iew.exec_stores::1 1111 # Number of stores executed
+system.cpu.iew.exec_stores::total 2178 # Number of stores executed
+system.cpu.iew.exec_rate 0.423871 # Inst execution rate
+system.cpu.iew.wb_sent::0 9939 # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::1 10068 # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::total 20007 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count::0 9740 # cumulative count of insts written-back
+system.cpu.iew.wb_count::1 9893 # cumulative count of insts written-back
+system.cpu.iew.wb_count::total 19633 # cumulative count of insts written-back
+system.cpu.iew.wb_producers::0 5189 # num instructions producing a value
+system.cpu.iew.wb_producers::1 5256 # num instructions producing a value
+system.cpu.iew.wb_producers::total 10445 # num instructions producing a value
+system.cpu.iew.wb_consumers::0 6868 # num instructions consuming a value
+system.cpu.iew.wb_consumers::1 6926 # num instructions consuming a value
+system.cpu.iew.wb_consumers::total 13794 # num instructions consuming a value
system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate::0 0.199834 # insts written-back per cycle
-system.cpu.iew.wb_rate::1 0.196664 # insts written-back per cycle
-system.cpu.iew.wb_rate::total 0.396498 # insts written-back per cycle
-system.cpu.iew.wb_fanout::0 0.752367 # average fanout of values written-back
-system.cpu.iew.wb_fanout::1 0.751281 # average fanout of values written-back
-system.cpu.iew.wb_fanout::total 0.751830 # average fanout of values written-back
+system.cpu.iew.wb_rate::0 0.196110 # insts written-back per cycle
+system.cpu.iew.wb_rate::1 0.199191 # insts written-back per cycle
+system.cpu.iew.wb_rate::total 0.395301 # insts written-back per cycle
+system.cpu.iew.wb_fanout::0 0.755533 # average fanout of values written-back
+system.cpu.iew.wb_fanout::1 0.758880 # average fanout of values written-back
+system.cpu.iew.wb_fanout::total 0.757213 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 14269 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 14447 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1068 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 28453 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.449091 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.311891 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1048 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 27467 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.465213 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.343088 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 23365 82.12% 82.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 2421 8.51% 90.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 1102 3.87% 94.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 384 1.35% 95.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 323 1.14% 96.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 209 0.73% 97.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 206 0.72% 98.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 116 0.41% 98.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 327 1.15% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 22438 81.69% 81.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 2371 8.63% 90.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 1089 3.96% 94.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 414 1.51% 95.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 277 1.01% 96.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 199 0.72% 97.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 197 0.72% 98.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 154 0.56% 98.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 328 1.19% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 28453 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 27467 # Number of insts commited each cycle
system.cpu.commit.committedInsts::0 6389 # Number of instructions committed
system.cpu.commit.committedInsts::1 6389 # Number of instructions committed
system.cpu.commit.committedInsts::total 12778 # Number of instructions committed
@@ -707,25 +707,25 @@ system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Cl
system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_1::total 6389 # Class of committed instruction
system.cpu.commit.op_class::total 12778 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.bw_lim_events 327 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 131668 # The number of ROB reads
-system.cpu.rob.rob_writes 56750 # The number of ROB writes
-system.cpu.timesIdled 392 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 21003 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events 328 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 129836 # The number of ROB reads
+system.cpu.rob.rob_writes 57114 # The number of ROB writes
+system.cpu.timesIdled 383 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 22132 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts::0 6372 # Number of Instructions Simulated
system.cpu.committedInsts::1 6372 # Number of Instructions Simulated
system.cpu.committedInsts::total 12744 # Number of Instructions Simulated
system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated
system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated
system.cpu.committedOps::total 12744 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi::0 7.771657 # CPI: Cycles Per Instruction
-system.cpu.cpi::1 7.771657 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.885829 # CPI: Total CPI of All Threads
-system.cpu.ipc::0 0.128673 # IPC: Instructions Per Cycle
-system.cpu.ipc::1 0.128673 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.257345 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 26413 # number of integer regfile reads
-system.cpu.int_regfile_writes 14990 # number of integer regfile writes
+system.cpu.cpi::0 7.794413 # CPI: Cycles Per Instruction
+system.cpu.cpi::1 7.794413 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.897207 # CPI: Total CPI of All Threads
+system.cpu.ipc::0 0.128297 # IPC: Instructions Per Cycle
+system.cpu.ipc::1 0.128297 # IPC: Instructions Per Cycle
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system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
@@ -733,294 +733,294 @@ system.cpu.misc_regfile_writes 2 # nu
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-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85527.586207 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85527.586207 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79787.066246 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79787.066246 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85997.512438 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85997.512438 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79787.066246 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85800.578035 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 81910.204082 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79787.066246 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85800.578035 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 81910.204082 # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85236.301370 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85236.301370 # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80036.392405 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80036.392405 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85828.282828 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85828.282828 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80036.392405 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85577.034884 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 81989.241803 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80036.392405 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85577.034884 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81989.241803 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1029,107 +1029,107 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 145 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 145 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 634 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 634 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 201 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 201 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 634 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 346 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 980 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 634 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 346 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 980 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10951500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10951500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44245000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44245000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15275500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15275500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44245000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26227000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 70472000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44245000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26227000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 70472000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 632 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 632 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 198 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 198 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 632 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 344 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 976 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 632 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 344 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 976 # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10984500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10984500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44263000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44263000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15014000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15014000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44263000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25998500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 70261500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44263000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25998500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 70261500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996855 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996855 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996845 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996845 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996855 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996845 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.997963 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996855 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996845 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.997963 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75527.586207 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75527.586207 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69787.066246 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69787.066246 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75997.512438 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75997.512438 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69787.066246 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75800.578035 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71910.204082 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69787.066246 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75800.578035 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71910.204082 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75236.301370 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75236.301370 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70036.392405 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70036.392405 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75828.282828 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75828.282828 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70036.392405 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75577.034884 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71989.241803 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70036.392405 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75577.034884 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71989.241803 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp 837 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 832 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 8 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 145 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 145 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 636 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 201 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1280 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 1972 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 62848 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 634 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 198 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 688 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 1964 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40576 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22016 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 62592 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 990 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 986 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 990 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 986 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 990 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 495000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 986 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 493000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 954000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 3.9 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 519000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 951000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 3.8 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 516000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 835 # Transaction distribution
-system.membus.trans_dist::ReadExReq 145 # Transaction distribution
-system.membus.trans_dist::ReadExResp 145 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 835 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1960 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1960 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62720 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 62720 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp 830 # Transaction distribution
+system.membus.trans_dist::ReadExReq 146 # Transaction distribution
+system.membus.trans_dist::ReadExResp 146 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 830 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1952 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1952 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62464 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 62464 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 980 # Request fanout histogram
+system.membus.snoop_fanout::samples 976 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 980 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 976 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 980 # Request fanout histogram
-system.membus.reqLayer0.occupancy 1192500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 976 # Request fanout histogram
+system.membus.reqLayer0.occupancy 1189000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 4.8 # Layer utilization (%)
-system.membus.respLayer1.occupancy 5223750 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 21.1 # Layer utilization (%)
+system.membus.respLayer1.occupancy 5195000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 20.9 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index 85270cbb1..82d581de7 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000027 # Number of seconds simulated
-sim_ticks 27401500 # Number of ticks simulated
-final_tick 27401500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 26943000 # Number of ticks simulated
+final_tick 26943000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 94035 # Simulator instruction rate (inst/s)
-host_op_rate 94027 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 178462571 # Simulator tick rate (ticks/s)
-host_mem_usage 293360 # Number of bytes of host memory used
-host_seconds 0.15 # Real time elapsed on the host
+host_inst_rate 30305 # Simulator instruction rate (inst/s)
+host_op_rate 30304 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 56555572 # Simulator tick rate (ticks/s)
+host_mem_usage 288252 # Number of bytes of host memory used
+host_seconds 0.48 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 22016 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9472 # Number of bytes read from this memory
-system.physmem.bytes_read::total 31488 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 22016 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 22016 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 344 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 148 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 492 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 803459665 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 345674507 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1149134171 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 803459665 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 803459665 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 803459665 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 345674507 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1149134171 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 492 # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst 21888 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory
+system.physmem.bytes_read::total 31296 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 21888 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 21888 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 342 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 489 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 812381695 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 349181606 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1161563300 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 812381695 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 812381695 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 812381695 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 349181606 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1161563300 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 489 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 492 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 489 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 31488 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 31296 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 31488 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 31296 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 107 # Per bank write bursts
-system.physmem.perBankRdBursts::1 28 # Per bank write bursts
-system.physmem.perBankRdBursts::2 51 # Per bank write bursts
+system.physmem.perBankRdBursts::1 27 # Per bank write bursts
+system.physmem.perBankRdBursts::2 49 # Per bank write bursts
system.physmem.perBankRdBursts::3 24 # Per bank write bursts
system.physmem.perBankRdBursts::4 20 # Per bank write bursts
system.physmem.perBankRdBursts::5 0 # Per bank write bursts
system.physmem.perBankRdBursts::6 32 # Per bank write bursts
-system.physmem.perBankRdBursts::7 35 # Per bank write bursts
+system.physmem.perBankRdBursts::7 36 # Per bank write bursts
system.physmem.perBankRdBursts::8 4 # Per bank write bursts
system.physmem.perBankRdBursts::9 2 # Per bank write bursts
system.physmem.perBankRdBursts::10 1 # Per bank write bursts
system.physmem.perBankRdBursts::11 0 # Per bank write bursts
-system.physmem.perBankRdBursts::12 57 # Per bank write bursts
+system.physmem.perBankRdBursts::12 56 # Per bank write bursts
system.physmem.perBankRdBursts::13 31 # Per bank write bursts
system.physmem.perBankRdBursts::14 61 # Per bank write bursts
system.physmem.perBankRdBursts::15 39 # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 27350000 # Total gap between requests
+system.physmem.totGap 26890000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 492 # Read request sizes (log2)
+system.physmem.readPktSize::6 489 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 293 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 297 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
@@ -186,306 +186,306 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 71 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 405.633803 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 274.142926 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 337.087748 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 12 16.90% 16.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 19 26.76% 43.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 9 12.68% 56.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 7 9.86% 66.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 8 11.27% 77.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 4 5.63% 83.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 2 2.82% 85.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 10 14.08% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 71 # Bytes accessed per row activation
-system.physmem.totQLat 3217000 # Total ticks spent queuing
-system.physmem.totMemAccLat 12442000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2460000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 6538.62 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 73 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 396.273973 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 268.840282 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 332.152795 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 12 16.44% 16.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 20 27.40% 43.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 11 15.07% 58.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 7 9.59% 68.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 6 8.22% 76.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1 1.37% 78.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 5 6.85% 84.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1 1.37% 86.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 10 13.70% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 73 # Bytes accessed per row activation
+system.physmem.totQLat 3681750 # Total ticks spent queuing
+system.physmem.totMemAccLat 12850500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2445000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 7529.14 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 25288.62 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1149.13 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 26279.14 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1161.56 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1149.13 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1161.56 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 8.98 # Data bus utilization in percentage
-system.physmem.busUtilRead 8.98 # Data bus utilization in percentage for reads
+system.physmem.busUtil 9.07 # Data bus utilization in percentage
+system.physmem.busUtilRead 9.07 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.53 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 412 # Number of row buffer hits during reads
+system.physmem.readRowHits 409 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.74 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 83.64 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 55589.43 # Average gap between requests
-system.physmem.pageHitRate 83.74 # Row buffer hit rate, read and write combined
+system.physmem.avgGap 54989.78 # Average gap between requests
+system.physmem.pageHitRate 83.64 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 302400 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 165000 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 2067000 # Energy for read commands per rank (pJ)
+system.physmem_0.readEnergy 2082600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 15796980 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 314250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 20171310 # Total energy per rank (pJ)
-system.physmem_0.averagePower 854.037999 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 440750 # Time in different power states
+system.physmem_0.actBackEnergy 15849990 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 267750 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 20193420 # Total energy per rank (pJ)
+system.physmem_0.averagePower 854.974120 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 363750 # Time in different power states
system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 22411750 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 22488750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 226800 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 123750 # Energy for precharge commands per rank (pJ)
+system.physmem_1.actEnergy 241920 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 132000 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1318200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 15639660 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 452250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 19286340 # Total energy per rank (pJ)
-system.physmem_1.averagePower 816.569039 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2456000 # Time in different power states
+system.physmem_1.actBackEnergy 15637950 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 453750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 19309500 # Total energy per rank (pJ)
+system.physmem_1.averagePower 817.549616 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2039000 # Time in different power states
system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 22168500 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 22166500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 8543 # Number of BP lookups
-system.cpu.branchPred.condPredicted 5466 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1058 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 5976 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 3053 # Number of BTB hits
+system.cpu.branchPred.lookups 8026 # Number of BP lookups
+system.cpu.branchPred.condPredicted 5198 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 978 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 5876 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 3165 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 51.087684 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 609 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 53.863172 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 554 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 18 # Number of system calls
-system.cpu.numCycles 54804 # number of cpu cycles simulated
+system.cpu.numCycles 53887 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 14234 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 40091 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 8543 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 3662 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 15933 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2311 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1045 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 6440 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 572 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 32383 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.238026 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.380017 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 13793 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 37180 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 8026 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 3719 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 15451 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2149 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1088 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 6095 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 549 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 31410 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.183699 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.297330 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 20844 64.37% 64.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 5506 17.00% 81.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 683 2.11% 83.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 516 1.59% 85.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 807 2.49% 87.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 911 2.81% 90.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 334 1.03% 91.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 372 1.15% 92.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 2410 7.44% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 20227 64.40% 64.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 5497 17.50% 81.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 701 2.23% 84.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 561 1.79% 85.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 758 2.41% 88.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 907 2.89% 91.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 332 1.06% 92.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 377 1.20% 93.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 2050 6.53% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 32383 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.155883 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.731534 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 11354 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 12386 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 6823 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 665 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1155 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 30509 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 1155 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 11949 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 1145 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 9839 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 6913 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 1382 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 27687 # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
-system.cpu.rename.SQFullEvents 986 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 25054 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 51693 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 42839 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 31410 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.148941 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.689962 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 10981 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 12209 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 6549 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 597 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1074 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 28093 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 1074 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 11557 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 929 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 9876 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 6585 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 1389 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 25671 # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full
+system.cpu.rename.SQFullEvents 994 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 23124 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 48097 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 39637 # Number of integer rename lookups
system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 11235 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 766 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 785 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 3795 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 3676 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 2349 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads.
+system.cpu.rename.UndoneMaps 9305 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 731 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 747 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 3478 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 3489 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 2288 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 23661 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 726 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 21924 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 9951 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 6530 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 251 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 32383 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.677022 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.427893 # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded 22031 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 704 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 20835 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 8 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 8299 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 5262 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 229 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 31410 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.663324 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.403192 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 23977 74.04% 74.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 3084 9.52% 83.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 1575 4.86% 88.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 1484 4.58% 93.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 922 2.85% 95.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 733 2.26% 98.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 411 1.27% 99.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 157 0.48% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 40 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 23338 74.30% 74.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 2945 9.38% 83.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 1556 4.95% 88.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 1448 4.61% 93.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 938 2.99% 96.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 645 2.05% 98.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 357 1.14% 99.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 149 0.47% 99.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 34 0.11% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 32383 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 31410 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 111 49.55% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 49 21.88% 71.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 64 28.57% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 59 33.33% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 51 28.81% 62.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 67 37.85% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 16295 74.32% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 3505 15.99% 90.31% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 2124 9.69% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 15392 73.88% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 3355 16.10% 89.98% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 2088 10.02% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 21924 # Type of FU issued
-system.cpu.iq.rate 0.400044 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 224 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.010217 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 76509 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 34365 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 20239 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 20835 # Type of FU issued
+system.cpu.iq.rate 0.386642 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 177 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.008495 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 73265 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 31060 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 19408 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 22148 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 21012 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 30 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1451 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1264 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 901 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 840 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1155 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1144 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 25514 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 200 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 3676 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 2349 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 726 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 1074 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 918 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 23852 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 173 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 3489 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 2288 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 704 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 260 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 934 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1194 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 20912 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 3349 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect 261 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 835 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1096 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 20012 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 3241 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 823 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1127 # number of nop insts executed
-system.cpu.iew.exec_refs 5373 # number of memory reference insts executed
-system.cpu.iew.exec_branches 4424 # Number of branches executed
-system.cpu.iew.exec_stores 2024 # Number of stores executed
-system.cpu.iew.exec_rate 0.381578 # Inst execution rate
-system.cpu.iew.wb_sent 20497 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 20239 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 9852 # num instructions producing a value
-system.cpu.iew.wb_consumers 12795 # num instructions consuming a value
+system.cpu.iew.exec_nop 1117 # number of nop insts executed
+system.cpu.iew.exec_refs 5240 # number of memory reference insts executed
+system.cpu.iew.exec_branches 4296 # Number of branches executed
+system.cpu.iew.exec_stores 1999 # Number of stores executed
+system.cpu.iew.exec_rate 0.371370 # Inst execution rate
+system.cpu.iew.wb_sent 19648 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 19408 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 9326 # num instructions producing a value
+system.cpu.iew.wb_consumers 12017 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.369298 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.769988 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.360161 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.776067 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 10294 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 8625 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1058 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 30320 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.500066 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.312560 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committedInsts 15162 # Number of instructions committed
system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -531,244 +531,244 @@ system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
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-system.cpu.cpi_total 3.796342 # CPI: Total CPI of All Threads
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 494 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 344 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total 344 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total 64 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 344 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 491 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 344 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 491 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994220 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994220 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994186 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994186 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994220 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994186 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.995951 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994220 # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total 0.995927 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994186 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.995951 # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75825.301205 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75825.301205 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74630.813953 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74630.813953 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77938.461538 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77938.461538 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74630.813953 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76753.378378 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75269.308943 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74630.813953 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76753.378378 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75269.308943 # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total 0.995927 # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75397.590361 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75397.590361 # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76001.461988 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76001.461988 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78812.500000 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78812.500000 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76001.461988 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76884.353741 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 76266.871166 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76001.461988 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76884.353741 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 76266.871166 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -845,104 +845,104 @@ system.cpu.l2cache.fast_writes 0 # nu
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 344 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 344 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 492 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 492 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5463500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5463500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22233000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22233000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4426000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4426000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22233000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9889500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 32122500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22233000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9889500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 32122500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 342 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 342 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 64 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 64 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 342 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 489 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 342 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 489 # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5428000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5428000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22572500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22572500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4414000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4414000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22572500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9842000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 32414500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22572500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9842000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 32414500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994220 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994186 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994186 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994186 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.995951 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.995927 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994186 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.995951 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65825.301205 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65825.301205 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64630.813953 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64630.813953 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68092.307692 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68092.307692 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64630.813953 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66820.945946 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65289.634146 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64630.813953 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66820.945946 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65289.634146 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.995927 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65397.590361 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65397.590361 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66001.461988 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66001.461988 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68968.750000 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68968.750000 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66001.461988 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66952.380952 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66287.321063 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66001.461988 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66952.380952 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66287.321063 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 407 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 346 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 295 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 987 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 344 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 64 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 688 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 981 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22016 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 31360 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 494 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 491 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 494 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 491 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 491 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 245500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 519000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 516000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 220500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 408 # Transaction distribution
+system.membus.trans_dist::ReadResp 405 # Transaction distribution
system.membus.trans_dist::ReadExReq 83 # Transaction distribution
system.membus.trans_dist::ReadExResp 83 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 409 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 983 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 983 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq 406 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 977 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 977 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31232 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 492 # Request fanout histogram
+system.membus.snoop_fanout::samples 489 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 489 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 492 # Request fanout histogram
+system.membus.snoop_fanout::total 489 # Request fanout histogram
system.membus.reqLayer0.occupancy 593500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2604000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 9.5 # Layer utilization (%)
+system.membus.respLayer1.occupancy 2584750 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 9.6 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
index 679d3d472..9368b9f49 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 3 2015 17:16:20
-gem5 started Jul 3 2015 17:20:44
+gem5 compiled Sep 14 2015 22:05:26
+gem5 started Sep 14 2015 22:09:42
gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
@@ -18,33 +18,33 @@ Init done
[Iteration 1, Thread 2] Got lock
[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2
Iteration 1 completed
-[Iteration 2, Thread 3] Got lock
-[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 2, Thread 2] Got lock
-[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
[Iteration 2, Thread 1] Got lock
-[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 2, Thread 2] Got lock
+[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 2, Thread 3] Got lock
+[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3
Iteration 2 completed
-[Iteration 3, Thread 2] Got lock
-[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 3, Thread 3] Got lock
-[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 3, Thread 2] Got lock
+[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2
[Iteration 3, Thread 1] Got lock
-[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1
Iteration 3 completed
[Iteration 4, Thread 3] Got lock
[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 4, Thread 1] Got lock
-[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
[Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 4, Thread 1] Got lock
+[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1
Iteration 4 completed
[Iteration 5, Thread 3] Got lock
[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
[Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 5, Thread 2] Got lock
+[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2
Iteration 5 completed
[Iteration 6, Thread 3] Got lock
[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3
@@ -53,33 +53,33 @@ Iteration 5 completed
[Iteration 6, Thread 2] Got lock
[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2
Iteration 6 completed
-[Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 7, Thread 1] Got lock
+[Iteration 7, Thread 1] Critical section done, previously next=3, now next=1
[Iteration 7, Thread 2] Got lock
-[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2
Iteration 7 completed
-[Iteration 8, Thread 3] Got lock
-[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1
[Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 8, Thread 1] Got lock
+[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 8, Thread 3] Got lock
+[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3
Iteration 8 completed
-[Iteration 9, Thread 1] Got lock
-[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 9, Thread 3] Got lock
-[Iteration 9, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 9, Thread 1] Got lock
+[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1
[Iteration 9, Thread 2] Got lock
-[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2
Iteration 9 completed
-[Iteration 10, Thread 1] Got lock
-[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 10, Thread 2] Got lock
[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 10, Thread 1] Got lock
+[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
Iteration 10 completed
PASSED :-)
-Exiting @ tick 107900000 because target called exit()
+Exiting @ tick 107049000 because target called exit()
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index 37bdd5ca5..b23c645a0 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -1,85 +1,91 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000108 # Number of seconds simulated
-sim_ticks 107900000 # Number of ticks simulated
-final_tick 107900000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000107 # Number of seconds simulated
+sim_ticks 107049000 # Number of ticks simulated
+final_tick 107049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 161691 # Simulator instruction rate (inst/s)
-host_op_rate 161690 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 17527940 # Simulator tick rate (ticks/s)
-host_mem_usage 308804 # Number of bytes of host memory used
-host_seconds 6.16 # Real time elapsed on the host
-sim_insts 995346 # Number of instructions simulated
-sim_ops 995346 # Number of ops (including micro ops) simulated
+host_inst_rate 93620 # Simulator instruction rate (inst/s)
+host_op_rate 93620 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 10161795 # Simulator tick rate (ticks/s)
+host_mem_usage 304708 # Number of bytes of host memory used
+host_seconds 10.53 # Real time elapsed on the host
+sim_insts 986230 # Number of instructions simulated
+sim_ops 986230 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst 23168 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 5440 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 5248 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst 576 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
-system.physmem.bytes_read::total 42944 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 23168 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 5440 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst 576 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 29184 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst 362 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 42560 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 5248 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst 320 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 85 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 82 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst 9 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 671 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 214717331 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 100240964 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 50417053 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 11862836 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 7710843 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 5338276 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 7710843 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 397998146 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 214717331 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 50417053 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 5338276 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 270472660 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 214717331 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 100240964 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 50417053 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 11862836 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 7710843 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 5338276 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 7710843 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 397998146 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 672 # Number of read requests accepted
+system.physmem.num_reads::total 665 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 215228540 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 101037842 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 49024279 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 11957141 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 1793571 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 7772142 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 2989285 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 7772142 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 397574942 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 215228540 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 49024279 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 1793571 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 2989285 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 269035675 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 215228540 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 101037842 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 49024279 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 11957141 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 1793571 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 7772142 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 2989285 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 7772142 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 397574942 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 666 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 672 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 666 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 43008 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 42624 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 43008 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 42624 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 75 # Number of requests that are neither read nor write
+system.physmem.neitherReadNorWriteReqs 89 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 114 # Per bank write bursts
system.physmem.perBankRdBursts::1 42 # Per bank write bursts
system.physmem.perBankRdBursts::2 30 # Per bank write bursts
system.physmem.perBankRdBursts::3 60 # Per bank write bursts
system.physmem.perBankRdBursts::4 66 # Per bank write bursts
-system.physmem.perBankRdBursts::5 28 # Per bank write bursts
+system.physmem.perBankRdBursts::5 27 # Per bank write bursts
system.physmem.perBankRdBursts::6 18 # Per bank write bursts
system.physmem.perBankRdBursts::7 24 # Per bank write bursts
system.physmem.perBankRdBursts::8 7 # Per bank write bursts
-system.physmem.perBankRdBursts::9 29 # Per bank write bursts
+system.physmem.perBankRdBursts::9 28 # Per bank write bursts
system.physmem.perBankRdBursts::10 23 # Per bank write bursts
-system.physmem.perBankRdBursts::11 14 # Per bank write bursts
-system.physmem.perBankRdBursts::12 65 # Per bank write bursts
+system.physmem.perBankRdBursts::11 13 # Per bank write bursts
+system.physmem.perBankRdBursts::12 61 # Per bank write bursts
system.physmem.perBankRdBursts::13 38 # Per bank write bursts
-system.physmem.perBankRdBursts::14 17 # Per bank write bursts
+system.physmem.perBankRdBursts::14 18 # Per bank write bursts
system.physmem.perBankRdBursts::15 97 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
@@ -99,14 +105,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 107872000 # Total gap between requests
+system.physmem.totGap 107021000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 672 # Read request sizes (log2)
+system.physmem.readPktSize::6 666 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -114,11 +120,11 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 402 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 188 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 399 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 198 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -210,966 +216,970 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 149 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 269.744966 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 188.953250 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 233.682770 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 43 28.86% 28.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 40 26.85% 55.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 25 16.78% 72.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 17 11.41% 83.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 8 5.37% 89.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 7 4.70% 93.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 4 2.68% 96.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 2 1.34% 97.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 3 2.01% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 149 # Bytes accessed per row activation
-system.physmem.totQLat 7242000 # Total ticks spent queuing
-system.physmem.totMemAccLat 19842000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 3360000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10776.79 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 144 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 276.444444 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 188.969078 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 251.786617 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 43 29.86% 29.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 36 25.00% 54.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 28 19.44% 74.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 12 8.33% 82.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 7 4.86% 87.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 8 5.56% 93.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 2 1.39% 94.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 3 2.08% 96.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 5 3.47% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 144 # Bytes accessed per row activation
+system.physmem.totQLat 6009250 # Total ticks spent queuing
+system.physmem.totMemAccLat 18496750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 3330000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 9022.90 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29526.79 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 398.59 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 27772.90 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 398.17 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 398.59 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 398.17 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 3.11 # Data bus utilization in percentage
system.physmem.busUtilRead 3.11 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.38 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 512 # Number of row buffer hits during reads
+system.physmem.readRowHits 511 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 76.19 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 76.73 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 160523.81 # Average gap between requests
-system.physmem.pageHitRate 76.19 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 710640 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 387750 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 2776800 # Energy for read commands per rank (pJ)
+system.physmem.avgGap 160692.19 # Average gap between requests
+system.physmem.pageHitRate 76.73 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 703080 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 383625 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 2769000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 34825860 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 30339750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 75652080 # Total energy per rank (pJ)
-system.physmem_0.averagePower 745.478401 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 52910500 # Time in different power states
+system.physmem_0.actBackEnergy 37638810 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 27872250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 75978045 # Total energy per rank (pJ)
+system.physmem_0.averagePower 748.690472 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 47858250 # Time in different power states
system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 47852500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 51979250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 385560 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 210375 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 2067000 # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 2028000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 31297275 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 33426750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 73998240 # Total energy per rank (pJ)
-system.physmem_1.averagePower 729.280213 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 59054500 # Time in different power states
+system.physmem_1.actBackEnergy 32994450 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 31946250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 74129175 # Total energy per rank (pJ)
+system.physmem_1.averagePower 730.471639 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 55670750 # Time in different power states
system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 42666000 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 45162250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu0.branchPred.lookups 81516 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 78639 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 1206 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 78220 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 75547 # Number of BTB hits
+system.cpu0.branchPred.lookups 81022 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 78376 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 1100 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 78355 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 75640 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 96.582715 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 751 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.BTBHitPct 96.535001 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 645 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.workload.num_syscalls 89 # Number of system calls
-system.cpu0.numCycles 215801 # number of cpu cycles simulated
+system.cpu0.numCycles 214099 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 19984 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 481810 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 81516 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 76298 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 165347 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 2711 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.icacheStallCycles 19687 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 478911 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 81022 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 76285 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 164512 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 2501 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 96 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 2206 # Number of stall cycles due to pending traps
-system.cpu0.fetch.CacheLines 7238 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 649 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples 188895 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 2.550676 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.226315 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.PendingTrapStallCycles 1992 # Number of stall cycles due to pending traps
+system.cpu0.fetch.CacheLines 6733 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 617 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 187540 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 2.553647 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.214546 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 31263 16.55% 16.55% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 77878 41.23% 57.78% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 817 0.43% 58.21% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 1146 0.61% 58.82% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 622 0.33% 59.15% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 73043 38.67% 97.82% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 702 0.37% 98.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 447 0.24% 98.42% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 2977 1.58% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 30407 16.21% 16.21% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 77695 41.43% 57.64% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 798 0.43% 58.07% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 1205 0.64% 58.71% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 612 0.33% 59.04% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 73095 38.98% 98.01% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 670 0.36% 98.37% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 402 0.21% 98.58% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 2656 1.42% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 188895 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.377737 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 2.232659 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 15795 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 18848 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 152228 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 669 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1355 # Number of cycles decode is squashing
-system.cpu0.decode.DecodedInsts 470263 # Number of instructions handled by decode
-system.cpu0.rename.SquashCycles 1355 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 16424 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 2157 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 15249 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 152226 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 1484 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 466822 # Number of instructions processed by rename
-system.cpu0.rename.IQFullEvents 20 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents 991 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands 319803 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 930944 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 703631 # Number of integer rename lookups
-system.cpu0.rename.CommittedMaps 305659 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 14144 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 901 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 908 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 4515 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 148895 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 75333 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 72583 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 72320 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 390748 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 967 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 387435 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 13210 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 11146 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 408 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 188895 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 2.051060 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.134423 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 187540 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.378432 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 2.236867 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 15435 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 18383 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 151822 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 650 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1250 # Number of cycles decode is squashing
+system.cpu0.decode.DecodedInsts 468409 # Number of instructions handled by decode
+system.cpu0.rename.SquashCycles 1250 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 16041 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 2079 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 14982 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 151818 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 1370 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 465227 # Number of instructions processed by rename
+system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 867 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands 318145 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 927822 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 700792 # Number of integer rename lookups
+system.cpu0.rename.CommittedMaps 305063 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 13082 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 821 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 831 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 4377 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 148776 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 75241 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 72733 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 72329 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 389183 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 889 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 385745 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 12312 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 11729 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 330 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 187540 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 2.056868 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.126403 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 34285 18.15% 18.15% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 4265 2.26% 20.41% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 73704 39.02% 59.43% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 73391 38.85% 98.28% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 1671 0.88% 99.16% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 904 0.48% 99.64% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 416 0.22% 99.86% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 183 0.10% 99.96% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 76 0.04% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 33477 17.85% 17.85% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 4232 2.26% 20.11% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 73531 39.21% 59.32% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 73185 39.02% 98.34% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 1601 0.85% 99.19% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 889 0.47% 99.67% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 403 0.21% 99.88% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 147 0.08% 99.96% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 75 0.04% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 188895 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 187540 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 90 32.14% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 85 30.36% 62.50% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 105 37.50% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 61 21.11% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 125 43.25% 64.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 164414 42.44% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 148348 38.29% 80.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 74673 19.27% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 163127 42.29% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 148129 38.40% 80.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 74489 19.31% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 387435 # Type of FU issued
-system.cpu0.iq.rate 1.795335 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 280 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.000723 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 964068 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 404976 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 385522 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.FU_type_0::total 385745 # Type of FU issued
+system.cpu0.iq.rate 1.801713 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.000749 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 959350 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 402446 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 383893 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 387715 # Number of integer alu accesses
+system.cpu0.iq.int_alu_accesses 386034 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 71972 # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.forwLoads 71845 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 2476 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 2655 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 53 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 1617 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 63 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 1674 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1355 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 2123 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 464714 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 184 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 148895 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 75333 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 846 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewSquashCycles 1250 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 2043 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 463105 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 243 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 148776 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 75241 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 770 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 53 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 331 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 1113 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 1444 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 386358 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 148024 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 1077 # Number of squashed instructions skipped in execute
+system.cpu0.iew.memOrderViolationEvents 63 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 318 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 990 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 1308 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 384734 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 147791 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 1011 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 72999 # number of nop insts executed
-system.cpu0.iew.exec_refs 222560 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 76623 # Number of branches executed
-system.cpu0.iew.exec_stores 74536 # Number of stores executed
-system.cpu0.iew.exec_rate 1.790344 # Inst execution rate
-system.cpu0.iew.wb_sent 385902 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 385522 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 228646 # num instructions producing a value
-system.cpu0.iew.wb_consumers 231982 # num instructions consuming a value
+system.cpu0.iew.exec_nop 73033 # number of nop insts executed
+system.cpu0.iew.exec_refs 222131 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 76355 # Number of branches executed
+system.cpu0.iew.exec_stores 74340 # Number of stores executed
+system.cpu0.iew.exec_rate 1.796991 # Inst execution rate
+system.cpu0.iew.wb_sent 384301 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 383893 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 227714 # num instructions producing a value
+system.cpu0.iew.wb_consumers 230757 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 1.786470 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.985620 # average fanout of values written-back
+system.cpu0.iew.wb_rate 1.793063 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.986813 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 13812 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitSquashedInsts 13101 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 1206 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 186239 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 2.420760 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 2.150366 # Number of insts commited each cycle
+system.cpu0.commit.branchMispredicts 1100 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 185078 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 2.431116 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 2.149204 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 34563 18.56% 18.56% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 75593 40.59% 59.15% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 1959 1.05% 60.20% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 634 0.34% 60.54% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 503 0.27% 60.81% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 71729 38.51% 99.32% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 522 0.28% 99.60% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 250 0.13% 99.74% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 486 0.26% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 33718 18.22% 18.22% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 75423 40.75% 58.97% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 1935 1.05% 60.02% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 662 0.36% 60.37% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 535 0.29% 60.66% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 71534 38.65% 99.31% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 523 0.28% 99.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 265 0.14% 99.74% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 483 0.26% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 186239 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 450840 # Number of instructions committed
-system.cpu0.commit.committedOps 450840 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 185078 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 449946 # Number of instructions committed
+system.cpu0.commit.committedOps 449946 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 220135 # Number of memory references committed
-system.cpu0.commit.loads 146419 # Number of loads committed
+system.cpu0.commit.refs 219688 # Number of memory references committed
+system.cpu0.commit.loads 146121 # Number of loads committed
system.cpu0.commit.membars 84 # Number of memory barriers committed
-system.cpu0.commit.branches 75603 # Number of branches committed
+system.cpu0.commit.branches 75454 # Number of branches committed
system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 303990 # Number of committed integer instructions.
+system.cpu0.commit.int_insts 303394 # Number of committed integer instructions.
system.cpu0.commit.function_calls 223 # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass 72335 16.04% 16.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 158286 35.11% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 146503 32.50% 83.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 73716 16.35% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::No_OpClass 72186 16.04% 16.04% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 157988 35.11% 51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.16% # Class of committed instruction
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system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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-system.cpu0.idleCycles 26906 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.committedInsts 378421 # Number of Instructions Simulated
-system.cpu0.committedOps 378421 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 0.570267 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 0.570267 # CPI: Total CPI of All Threads
-system.cpu0.ipc 1.753565 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 1.753565 # IPC: Total IPC of All Threads
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system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
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system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
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system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks.
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system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu0.dcache.writebacks::total 1 # number of writebacks
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+system.cpu0.dcache.WriteReq_mshr_misses::total 177 # number of WriteReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6883000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6883000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8240500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8240500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 446500 # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::total 446500 # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15123500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 15123500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15123500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 15123500 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002411 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002411 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002407 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002407 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses
+system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002409 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.002409 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002409 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.002409 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37612.021858 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37612.021858 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46556.497175 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46556.497175 # average WriteReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17173.076923 # average SwapReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17173.076923 # average SwapReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42009.722222 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42009.722222 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42009.722222 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42009.722222 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 323 # number of replacements
-system.cpu0.icache.tags.tagsinuse 240.334366 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 6439 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 614 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 10.486971 # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements 315 # number of replacements
+system.cpu0.icache.tags.tagsinuse 241.042514 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 5949 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 607 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 9.800659 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 240.334366 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.469403 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.469403 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 0.568359 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 7852 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 7852 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 6439 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 6439 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 6439 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 6439 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 6439 # number of overall hits
-system.cpu0.icache.overall_hits::total 6439 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 799 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 799 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 799 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 799 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 799 # number of overall misses
-system.cpu0.icache.overall_misses::total 799 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40829000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 40829000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 40829000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 40829000 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 40829000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 40829000 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 7238 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 7238 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 7238 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 7238 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 7238 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 7238 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110390 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.110390 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110390 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.110390 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110390 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.110390 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51100.125156 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 51100.125156 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51100.125156 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 51100.125156 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51100.125156 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 51100.125156 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.042514 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470786 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.470786 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024 0.570312 # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses 7340 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 7340 # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst 5949 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 5949 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 5949 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 5949 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 5949 # number of overall hits
+system.cpu0.icache.overall_hits::total 5949 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 784 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 784 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 784 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 784 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 784 # number of overall misses
+system.cpu0.icache.overall_misses::total 784 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40365000 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 40365000 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 40365000 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 40365000 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 40365000 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 40365000 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 6733 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 6733 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 6733 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 6733 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 6733 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 6733 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116441 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.116441 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116441 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.116441 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116441 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.116441 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51485.969388 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 51485.969388 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51485.969388 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 51485.969388 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51485.969388 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 51485.969388 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 184 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst 184 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 184 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst 184 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 184 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 615 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 615 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 615 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 615 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 615 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 615 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31621000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 31621000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31621000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 31621000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31621000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 31621000 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.084968 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084968 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.084968 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.084968 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.084968 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.084968 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51416.260163 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51416.260163 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51416.260163 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 51416.260163 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51416.260163 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 51416.260163 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 176 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 176 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst 176 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 176 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst 176 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 176 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 608 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 608 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 608 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 608 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 608 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 608 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31177000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 31177000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31177000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 31177000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31177000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 31177000 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090302 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.090302 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.090302 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51277.960526 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 51277.960526 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 51277.960526 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 53963 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 50167 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 1346 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 46229 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 44971 # Number of BTB hits
+system.cpu1.branchPred.lookups 50039 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 46665 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 1271 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 42823 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 41749 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 97.278764 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 927 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.BTBHitPct 97.492002 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 914 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
-system.cpu1.numCycles 162372 # number of cpu cycles simulated
+system.cpu1.numCycles 161348 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 29926 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 299894 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 53963 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 45898 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 123960 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 2845 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.icacheStallCycles 31303 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 275372 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 50039 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 42663 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 121719 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 2699 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
-system.cpu1.fetch.PendingTrapStallCycles 1155 # Number of stall cycles due to pending traps
-system.cpu1.fetch.CacheLines 20576 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 472 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 156476 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 1.916550 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.231802 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps
+system.cpu1.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 21928 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 442 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples 155480 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.771109 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.178899 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 52995 33.87% 33.87% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 51987 33.22% 67.09% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 5834 3.73% 70.82% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 3448 2.20% 73.02% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 958 0.61% 73.64% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 34873 22.29% 95.92% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1256 0.80% 96.72% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 838 0.54% 97.26% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 4287 2.74% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 58088 37.36% 37.36% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 49421 31.79% 69.15% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 6835 4.40% 73.54% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 3518 2.26% 75.81% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 944 0.61% 76.41% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 30727 19.76% 96.18% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1228 0.79% 96.96% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 804 0.52% 97.48% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 3915 2.52% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 156476 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.332342 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 1.846956 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 18007 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 50929 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 83026 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 3082 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 1422 # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts 283749 # Number of instructions handled by decode
-system.cpu1.rename.SquashCycles 1422 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 18719 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 22929 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 13387 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 84356 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 15653 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 280426 # Number of instructions processed by rename
-system.cpu1.rename.IQFullEvents 13898 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full
+system.cpu1.fetch.rateDist::total 155480 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.310131 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 1.706696 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 17833 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 58352 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 74506 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 3430 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 1349 # Number of cycles decode is squashing
+system.cpu1.decode.DecodedInsts 260078 # Number of instructions handled by decode
+system.cpu1.rename.SquashCycles 1349 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 18539 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 27109 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 13862 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 76429 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 18182 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 256857 # Number of instructions processed by rename
+system.cpu1.rename.IQFullEvents 16651 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full
system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 198372 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 540599 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 420692 # Number of integer rename lookups
-system.cpu1.rename.CommittedMaps 183271 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 15101 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 1203 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 1280 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 20103 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 79058 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 37890 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 37399 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 32713 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 233810 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 5671 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 234514 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 14000 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 11968 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 653 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 156476 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 1.498722 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.383815 # Number of insts issued each cycle
+system.cpu1.rename.RenamedOperands 180872 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 489824 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 382391 # Number of integer rename lookups
+system.cpu1.rename.CommittedMaps 167019 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 13853 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 1180 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 1251 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 22657 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 71171 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 33454 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 33920 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 28372 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 213121 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 6586 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 214969 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 13076 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 10906 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 730 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 155480 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 1.382615 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.383057 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 56669 36.22% 36.22% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 19562 12.50% 48.72% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 37085 23.70% 72.42% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 36801 23.52% 95.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 3420 2.19% 98.12% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1602 1.02% 99.15% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 884 0.56% 99.71% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 239 0.15% 99.86% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 214 0.14% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 61906 39.82% 39.82% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 21977 14.13% 53.95% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 32894 21.16% 75.11% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 32429 20.86% 95.96% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 3365 2.16% 98.13% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1605 1.03% 99.16% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 896 0.58% 99.74% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 208 0.13% 99.87% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 200 0.13% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 156476 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 155480 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 87 24.58% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 58 16.38% 40.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 209 59.04% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 79 23.72% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 45 13.51% 37.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 209 62.76% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 114757 48.93% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 82569 35.21% 84.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 37188 15.86% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 106597 49.59% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 75532 35.14% 84.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 32840 15.28% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 234514 # Type of FU issued
-system.cpu1.iq.rate 1.444301 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 354 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.001510 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 625904 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 253521 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 232777 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.FU_type_0::total 214969 # Type of FU issued
+system.cpu1.iq.rate 1.332331 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 333 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.001549 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 585768 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 232822 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 213429 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 234868 # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses 215302 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 32465 # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads 28182 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 2830 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2653 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1669 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1503 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 1422 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 6958 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 277649 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 222 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 79058 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 37890 # Number of dispatched store instructions
+system.cpu1.iew.iewSquashCycles 1349 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 7989 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 73 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 254448 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 142 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 71171 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 33454 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 1130 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 43 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 481 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 1587 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 233397 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 77941 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 1117 # Number of squashed instructions skipped in execute
+system.cpu1.iew.memOrderViolationEvents 39 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 452 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 1051 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 213962 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 70077 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1007 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 38168 # number of nop insts executed
-system.cpu1.iew.exec_refs 115010 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 47577 # Number of branches executed
-system.cpu1.iew.exec_stores 37069 # Number of stores executed
-system.cpu1.iew.exec_rate 1.437421 # Inst execution rate
-system.cpu1.iew.wb_sent 233106 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 232777 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 132706 # num instructions producing a value
-system.cpu1.iew.wb_consumers 139339 # num instructions consuming a value
+system.cpu1.iew.exec_nop 34741 # number of nop insts executed
+system.cpu1.iew.exec_refs 102825 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 44094 # Number of branches executed
+system.cpu1.iew.exec_stores 32748 # Number of stores executed
+system.cpu1.iew.exec_rate 1.326090 # Inst execution rate
+system.cpu1.iew.wb_sent 213711 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 213429 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 120431 # num instructions producing a value
+system.cpu1.iew.wb_consumers 127039 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 1.433603 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.952397 # average fanout of values written-back
+system.cpu1.iew.wb_rate 1.322787 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.947984 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 14853 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 5018 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 1346 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 153761 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 1.708866 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 2.078798 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 13922 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 5856 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 1271 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 152910 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 1.572631 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 2.035068 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 61362 39.91% 39.91% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 44235 28.77% 68.68% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 5219 3.39% 72.07% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 5854 3.81% 75.88% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1519 0.99% 76.87% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 32513 21.15% 98.01% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 819 0.53% 98.54% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 953 0.62% 99.16% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1287 0.84% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 67472 44.13% 44.13% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 40678 26.60% 70.73% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 5251 3.43% 74.16% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 6680 4.37% 78.53% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1520 0.99% 79.52% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 28236 18.47% 97.99% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 823 0.54% 98.53% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 947 0.62% 99.15% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1303 0.85% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 153761 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 262757 # Number of instructions committed
-system.cpu1.commit.committedOps 262757 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 152910 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 240471 # Number of instructions committed
+system.cpu1.commit.committedOps 240471 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 112449 # Number of memory references committed
-system.cpu1.commit.loads 76228 # Number of loads committed
-system.cpu1.commit.membars 4303 # Number of memory barriers committed
-system.cpu1.commit.branches 46487 # Number of branches committed
+system.cpu1.commit.refs 100469 # Number of memory references committed
+system.cpu1.commit.loads 68518 # Number of loads committed
+system.cpu1.commit.membars 5139 # Number of memory barriers committed
+system.cpu1.commit.branches 43053 # Number of branches committed
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 181057 # Number of committed integer instructions.
+system.cpu1.commit.int_insts 165641 # Number of committed integer instructions.
system.cpu1.commit.function_calls 322 # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass 37276 14.19% 14.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 108729 41.38% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 80531 30.65% 86.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 36221 13.78% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::No_OpClass 33840 14.07% 14.07% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 101023 42.01% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead 73657 30.63% 86.71% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite 31951 13.29% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 262757 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 1287 # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads 429498 # The number of ROB reads
-system.cpu1.rob.rob_writes 557934 # The number of ROB writes
-system.cpu1.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 5896 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 46085 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 221178 # Number of Instructions Simulated
-system.cpu1.committedOps 221178 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 0.734124 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 0.734124 # CPI: Total CPI of All Threads
-system.cpu1.ipc 1.362168 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 1.362168 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 405088 # number of integer regfile reads
-system.cpu1.int_regfile_writes 189742 # number of integer regfile writes
+system.cpu1.commit.op_class_0::total 240471 # Class of committed instruction
+system.cpu1.commit.bw_lim_events 1303 # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads 405414 # The number of ROB reads
+system.cpu1.rob.rob_writes 511356 # The number of ROB writes
+system.cpu1.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 5868 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 45259 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 201492 # Number of Instructions Simulated
+system.cpu1.committedOps 201492 # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi 0.800766 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 0.800766 # CPI: Total CPI of All Threads
+system.cpu1.ipc 1.248804 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 1.248804 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 368266 # number of integer regfile reads
+system.cpu1.int_regfile_writes 172947 # number of integer regfile writes
system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 116634 # number of misc regfile reads
+system.cpu1.misc_regfile_reads 104453 # number of misc regfile reads
system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
system.cpu1.dcache.tags.replacements 0 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 25.592984 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 42361 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 1512.892857 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.tagsinuse 25.714463 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 38066 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 1312.620690 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.592984 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.049986 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.049986 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.714463 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050224 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.050224 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 326938 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 326938 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 44990 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 44990 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 35982 # number of WriteReq hits
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-system.cpu1.dcache.ReadReq_avg_miss_latency::total 18888.286334 # average ReadReq miss latency
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-system.cpu1.dcache.WriteReq_avg_miss_latency::total 24835.294118 # average WriteReq miss latency
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-system.cpu1.dcache.SwapReq_avg_miss_latency::total 11651.785714 # average SwapReq miss latency
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-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20490.491284 # average overall miss latency
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+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19382.936508 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 19382.936508 # average ReadReq miss latency
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+system.cpu1.dcache.WriteReq_avg_miss_latency::total 21059.375000 # average WriteReq miss latency
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+system.cpu1.dcache.demand_avg_miss_latency::total 19786.897590 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19786.897590 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 19786.897590 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1178,518 +1188,517 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu1.dcache.ReadReq_mshr_hits::total 303 # number of ReadReq MSHR hits
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-system.cpu1.dcache.WriteReq_mshr_hits::total 62 # number of WriteReq MSHR hits
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-system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
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system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
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-system.cpu1.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses
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-system.cpu1.dcache.demand_mshr_miss_latency::total 3884000 # number of demand (read+write) MSHR miss cycles
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-system.cpu1.dcache.overall_mshr_miss_latency::total 3884000 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003476 # mshr miss rate for ReadReq accesses
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-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12180.379747 # average ReadReq mshr miss latency
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-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14601.503759 # average overall mshr miss latency
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+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14125.448029 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14125.448029 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements 385 # number of replacements
-system.cpu1.icache.tags.tagsinuse 85.488179 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 19990 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 500 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 39.980000 # Average number of references to valid blocks.
+system.cpu1.icache.tags.replacements 383 # number of replacements
+system.cpu1.icache.tags.tagsinuse 84.275379 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 21349 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 496 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 43.042339 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 85.488179 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.166969 # Average percentage of cache occupancy
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-system.cpu1.icache.tags.occ_task_id_blocks::1024 115 # Occupied blocks per task id
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system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024 0.224609 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 21076 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 21076 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 19990 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 19990 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 19990 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 19990 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 19990 # number of overall hits
-system.cpu1.icache.overall_hits::total 19990 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 586 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 586 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 586 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 586 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 586 # number of overall misses
-system.cpu1.icache.overall_misses::total 586 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14253000 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 14253000 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 14253000 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 14253000 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 14253000 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 14253000 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 20576 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 20576 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 20576 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 20576 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 20576 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 20576 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028480 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.028480 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028480 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.028480 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028480 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.028480 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24322.525597 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 24322.525597 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24322.525597 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 24322.525597 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24322.525597 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 24322.525597 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked
+system.cpu1.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses 22424 # Number of tag accesses
+system.cpu1.icache.tags.data_accesses 22424 # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst 21349 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 21349 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 21349 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 21349 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 21349 # number of overall hits
+system.cpu1.icache.overall_hits::total 21349 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 579 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 579 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 579 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 579 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 579 # number of overall misses
+system.cpu1.icache.overall_misses::total 579 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 13955500 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 13955500 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 13955500 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 13955500 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 13955500 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 13955500 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 21928 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 21928 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 21928 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 21928 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 21928 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 21928 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026405 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.026405 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026405 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.026405 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026405 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.026405 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24102.763385 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 24102.763385 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24102.763385 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 24102.763385 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24102.763385 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 24102.763385 # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 86 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst 86 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst 86 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total 86 # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 500 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 500 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 500 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 500 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 500 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 500 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11778500 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 11778500 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11778500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 11778500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11778500 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 11778500 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024300 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024300 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024300 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.024300 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024300 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.024300 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23557 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23557 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23557 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 23557 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23557 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 23557 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 83 # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst 83 # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total 83 # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst 83 # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total 83 # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 496 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total 496 # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 496 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total 496 # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst 496 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total 496 # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11502500 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 11502500 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11502500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 11502500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11502500 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 11502500 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022619 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.022619 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.022619 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23190.524194 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 23190.524194 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 23190.524194 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.branchPred.lookups 40179 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 36730 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 1284 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 32851 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 31814 # Number of BTB hits
+system.cpu2.branchPred.lookups 42880 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 39445 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 1259 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 35521 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 34492 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 96.843323 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 891 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.BTBHitPct 97.103122 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 904 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
-system.cpu2.numCycles 162000 # number of cpu cycles simulated
+system.cpu2.numCycles 160976 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 38502 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 208114 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 40179 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 32705 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 119095 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 2725 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.icacheStallCycles 36449 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 226588 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 42880 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 35396 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 120624 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 2677 # Number of cycles fetch has spent squashing
system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
-system.cpu2.fetch.PendingTrapStallCycles 1151 # Number of stall cycles due to pending traps
-system.cpu2.fetch.CacheLines 29772 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 430 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples 160123 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.299713 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 1.967894 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.PendingTrapStallCycles 1157 # Number of stall cycles due to pending traps
+system.cpu2.fetch.CacheLines 27680 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 445 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples 159581 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.419893 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.036694 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 78817 49.22% 49.22% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 43234 27.00% 76.22% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 10666 6.66% 82.88% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 3447 2.15% 85.04% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 1063 0.66% 85.70% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 17019 10.63% 96.33% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 1193 0.75% 97.07% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 770 0.48% 97.56% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 3914 2.44% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 73772 46.23% 46.23% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 45044 28.23% 74.45% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 9695 6.08% 80.53% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 3476 2.18% 82.71% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 968 0.61% 83.32% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 20661 12.95% 96.26% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 1186 0.74% 97.01% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 799 0.50% 97.51% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 3980 2.49% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 160123 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.248019 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 1.284654 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 17927 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 88037 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 47537 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 5250 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 1362 # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts 193193 # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles 1362 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 18611 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 44936 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 13295 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 49321 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 32588 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 189743 # Number of instructions processed by rename
-system.cpu2.rename.IQFullEvents 29082 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents 12 # Number of times rename has blocked due to LQ full
+system.cpu2.fetch.rateDist::total 159581 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.266375 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 1.407589 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 17760 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 80804 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 54882 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 4787 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 1338 # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts 211151 # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles 1338 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 18439 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 40468 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 13548 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 56825 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 28953 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 208031 # Number of instructions processed by rename
+system.cpu2.rename.IQFullEvents 26065 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full
system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands 129905 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 340650 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 270570 # Number of integer rename lookups
-system.cpu2.rename.CommittedMaps 115581 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 14324 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 1221 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 1285 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 37412 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 47453 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 19802 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 23979 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 14667 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 152040 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 10334 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 157175 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 13577 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 11994 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.rename.RenamedOperands 143630 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 381000 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 300757 # Number of integer rename lookups
+system.cpu2.rename.CommittedMaps 129882 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 13748 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 1193 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 1262 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 33404 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 53977 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 23458 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 26723 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 18373 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 168634 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 9408 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 173236 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 12983 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 10808 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 781 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 160123 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 0.981589 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.305622 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::samples 159581 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.085568 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.335871 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 83163 51.94% 51.94% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 32837 20.51% 72.44% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 19129 11.95% 84.39% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 18742 11.70% 96.10% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 3350 2.09% 98.19% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 1588 0.99% 99.18% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 888 0.55% 99.73% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 222 0.14% 99.87% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 204 0.13% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 77748 48.72% 48.72% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 30232 18.94% 67.66% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 22868 14.33% 81.99% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 22470 14.08% 96.08% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 3364 2.11% 98.18% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 1606 1.01% 99.19% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 879 0.55% 99.74% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 214 0.13% 99.87% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 200 0.13% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 160123 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 159581 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 85 23.42% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 69 19.01% 42.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 209 57.58% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 79 23.94% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 42 12.73% 36.67% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 209 63.33% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 82729 52.63% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 55347 35.21% 87.85% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 19099 12.15% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 89318 51.56% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 61054 35.24% 86.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 22864 13.20% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 157175 # Type of FU issued
-system.cpu2.iq.rate 0.970216 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 363 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.002310 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 474890 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 175995 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 155491 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.FU_type_0::total 173236 # Type of FU issued
+system.cpu2.iq.rate 1.076160 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 330 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.001905 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 506398 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 191064 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 171727 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 157538 # Number of integer alu accesses
+system.cpu2.iq.int_alu_accesses 173566 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 14398 # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.forwLoads 18193 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 2822 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 2642 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 1616 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 1482 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 1362 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 11555 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 80 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 187117 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 206 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 47453 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 19802 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 1131 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewSquashCycles 1338 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 10563 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 81 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 205567 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 184 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 53977 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 23458 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 1137 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 44 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 462 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 1028 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 1490 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 156065 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 46210 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 1110 # Number of squashed instructions skipped in execute
+system.cpu2.iew.memOrderViolationEvents 39 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 430 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 1053 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 1483 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 172231 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 52840 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 1005 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 24743 # number of nop insts executed
-system.cpu2.iew.exec_refs 65197 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 33975 # Number of branches executed
-system.cpu2.iew.exec_stores 18987 # Number of stores executed
-system.cpu2.iew.exec_rate 0.963364 # Inst execution rate
-system.cpu2.iew.wb_sent 155796 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 155491 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 82775 # num instructions producing a value
-system.cpu2.iew.wb_consumers 89322 # num instructions consuming a value
+system.cpu2.iew.exec_nop 27525 # number of nop insts executed
+system.cpu2.iew.exec_refs 75615 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 36863 # Number of branches executed
+system.cpu2.iew.exec_stores 22775 # Number of stores executed
+system.cpu2.iew.exec_rate 1.069917 # Inst execution rate
+system.cpu2.iew.wb_sent 171997 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 171727 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 93200 # num instructions producing a value
+system.cpu2.iew.wb_consumers 99800 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 0.959821 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.926703 # average fanout of values written-back
+system.cpu2.iew.wb_rate 1.066786 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.933868 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 14525 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 9553 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 1284 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 157478 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.095639 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.783689 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 13823 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 8627 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 1259 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 157016 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.220837 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 1.865055 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 92218 58.56% 58.56% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 30640 19.46% 78.02% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 5207 3.31% 81.32% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 10311 6.55% 87.87% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 1532 0.97% 88.84% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 14554 9.24% 98.08% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 759 0.48% 98.57% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 956 0.61% 99.17% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 1301 0.83% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 86039 54.80% 54.80% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 33434 21.29% 76.09% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 5238 3.34% 79.43% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 9429 6.01% 85.43% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 1533 0.98% 86.41% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 18255 11.63% 98.03% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 831 0.53% 98.56% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 955 0.61% 99.17% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 1302 0.83% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 157478 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 172539 # Number of instructions committed
-system.cpu2.commit.committedOps 172539 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 157016 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 191691 # Number of instructions committed
+system.cpu2.commit.committedOps 191691 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 62817 # Number of memory references committed
-system.cpu2.commit.loads 44631 # Number of loads committed
-system.cpu2.commit.membars 8825 # Number of memory barriers committed
-system.cpu2.commit.branches 32966 # Number of branches committed
+system.cpu2.commit.refs 73311 # Number of memory references committed
+system.cpu2.commit.loads 51335 # Number of loads committed
+system.cpu2.commit.membars 7910 # Number of memory barriers committed
+system.cpu2.commit.branches 35845 # Number of branches committed
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 117894 # Number of committed integer instructions.
+system.cpu2.commit.int_insts 131277 # Number of committed integer instructions.
system.cpu2.commit.function_calls 322 # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass 23742 13.76% 13.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu 77155 44.72% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead 53456 30.98% 89.46% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite 18186 10.54% 100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::No_OpClass 26632 13.89% 13.89% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu 83838 43.74% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead 59245 30.91% 88.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite 21976 11.46% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total 172539 # Class of committed instruction
-system.cpu2.commit.bw_lim_events 1301 # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads 342655 # The number of ROB reads
-system.cpu2.rob.rob_writes 376773 # The number of ROB writes
-system.cpu2.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 1877 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 46457 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 139972 # Number of Instructions Simulated
-system.cpu2.committedOps 139972 # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi 1.157374 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 1.157374 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.864025 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.864025 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 255225 # number of integer regfile reads
-system.cpu2.int_regfile_writes 121437 # number of integer regfile writes
+system.cpu2.commit.op_class_0::total 191691 # Class of committed instruction
+system.cpu2.commit.bw_lim_events 1302 # number cycles where commit BW limit reached
+system.cpu2.rob.rob_reads 360642 # The number of ROB reads
+system.cpu2.rob.rob_writes 413593 # The number of ROB writes
+system.cpu2.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 1395 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 45631 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 157149 # Number of Instructions Simulated
+system.cpu2.committedOps 157149 # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi 1.024353 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 1.024353 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.976226 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.976226 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 286558 # number of integer regfile reads
+system.cpu2.int_regfile_writes 135654 # number of integer regfile writes
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 66781 # number of misc regfile reads
+system.cpu2.misc_regfile_reads 77226 # number of misc regfile reads
system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
system.cpu2.dcache.tags.replacements 0 # number of replacements
-system.cpu2.dcache.tags.tagsinuse 23.055357 # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs 24315 # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs 838.448276 # Average number of references to valid blocks.
+system.cpu2.dcache.tags.tagsinuse 23.071332 # Cycle average of tags in use
+system.cpu2.dcache.tags.total_refs 27978 # Total number of references to valid blocks.
+system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
+system.cpu2.dcache.tags.avg_refs 999.214286 # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.055357 # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045030 # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total 0.045030 # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
+system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.071332 # Average occupied blocks per requestor
+system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045061 # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_percent::total 0.045061 # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
-system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses 200189 # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses 200189 # Number of data accesses
-system.cpu2.dcache.ReadReq_hits::cpu2.data 31354 # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total 31354 # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data 17953 # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total 17953 # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits::cpu2.data 17 # number of SwapReq hits
-system.cpu2.dcache.SwapReq_hits::total 17 # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data 49307 # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total 49307 # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data 49307 # number of overall hits
-system.cpu2.dcache.overall_hits::total 49307 # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data 441 # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total 441 # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data 151 # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total 151 # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses::cpu2.data 65 # number of SwapReq misses
-system.cpu2.dcache.SwapReq_misses::total 65 # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data 592 # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total 592 # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data 592 # number of overall misses
-system.cpu2.dcache.overall_misses::total 592 # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 6519500 # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total 6519500 # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3142000 # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total 3142000 # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 710000 # number of SwapReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::total 710000 # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data 9661500 # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total 9661500 # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data 9661500 # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total 9661500 # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data 31795 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total 31795 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data 18104 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total 18104 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data 82 # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total 82 # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data 49899 # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total 49899 # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data 49899 # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total 49899 # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.013870 # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total 0.013870 # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.008341 # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total 0.008341 # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.792683 # miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::total 0.792683 # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data 0.011864 # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total 0.011864 # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data 0.011864 # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total 0.011864 # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14783.446712 # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 14783.446712 # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20807.947020 # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 20807.947020 # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10923.076923 # average SwapReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::total 10923.076923 # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 16320.101351 # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 16320.101351 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 16320.101351 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 16320.101351 # average overall miss latency
+system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id
+system.cpu2.dcache.tags.tag_accesses 226658 # Number of tag accesses
+system.cpu2.dcache.tags.data_accesses 226658 # Number of data accesses
+system.cpu2.dcache.ReadReq_hits::cpu2.data 34141 # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total 34141 # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits::cpu2.data 21749 # number of WriteReq hits
+system.cpu2.dcache.WriteReq_hits::total 21749 # number of WriteReq hits
+system.cpu2.dcache.SwapReq_hits::cpu2.data 19 # number of SwapReq hits
+system.cpu2.dcache.SwapReq_hits::total 19 # number of SwapReq hits
+system.cpu2.dcache.demand_hits::cpu2.data 55890 # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits::total 55890 # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits::cpu2.data 55890 # number of overall hits
+system.cpu2.dcache.overall_hits::total 55890 # number of overall hits
+system.cpu2.dcache.ReadReq_misses::cpu2.data 483 # number of ReadReq misses
+system.cpu2.dcache.ReadReq_misses::total 483 # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses::cpu2.data 156 # number of WriteReq misses
+system.cpu2.dcache.WriteReq_misses::total 156 # number of WriteReq misses
+system.cpu2.dcache.SwapReq_misses::cpu2.data 52 # number of SwapReq misses
+system.cpu2.dcache.SwapReq_misses::total 52 # number of SwapReq misses
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system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1698,517 +1707,517 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13207.530648 # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::total 13207.530648 # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13207.530648 # average overall miss latency
+system.cpu2.icache.demand_avg_miss_latency::total 13207.530648 # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13207.530648 # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::total 13207.530648 # average overall miss latency
+system.cpu2.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
-system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 68 # number of ReadReq MSHR hits
-system.cpu2.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits
-system.cpu2.icache.demand_mshr_hits::cpu2.inst 68 # number of demand (read+write) MSHR hits
-system.cpu2.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits
-system.cpu2.icache.overall_mshr_hits::cpu2.inst 68 # number of overall MSHR hits
-system.cpu2.icache.overall_mshr_hits::total 68 # number of overall MSHR hits
-system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 496 # number of ReadReq MSHR misses
-system.cpu2.icache.ReadReq_mshr_misses::total 496 # number of ReadReq MSHR misses
-system.cpu2.icache.demand_mshr_misses::cpu2.inst 496 # number of demand (read+write) MSHR misses
-system.cpu2.icache.demand_mshr_misses::total 496 # number of demand (read+write) MSHR misses
-system.cpu2.icache.overall_mshr_misses::cpu2.inst 496 # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_misses::total 496 # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6709500 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total 6709500 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6709500 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total 6709500 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6709500 # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total 6709500 # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.016660 # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.016660 # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.016660 # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total 0.016660 # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.016660 # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total 0.016660 # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13527.217742 # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13527.217742 # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13527.217742 # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 13527.217742 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13527.217742 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 13527.217742 # average overall mshr miss latency
+system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 71 # number of ReadReq MSHR hits
+system.cpu2.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits
+system.cpu2.icache.demand_mshr_hits::cpu2.inst 71 # number of demand (read+write) MSHR hits
+system.cpu2.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits
+system.cpu2.icache.overall_mshr_hits::cpu2.inst 71 # number of overall MSHR hits
+system.cpu2.icache.overall_mshr_hits::total 71 # number of overall MSHR hits
+system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 500 # number of ReadReq MSHR misses
+system.cpu2.icache.ReadReq_mshr_misses::total 500 # number of ReadReq MSHR misses
+system.cpu2.icache.demand_mshr_misses::cpu2.inst 500 # number of demand (read+write) MSHR misses
+system.cpu2.icache.demand_mshr_misses::total 500 # number of demand (read+write) MSHR misses
+system.cpu2.icache.overall_mshr_misses::cpu2.inst 500 # number of overall MSHR misses
+system.cpu2.icache.overall_mshr_misses::total 500 # number of overall MSHR misses
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6543500 # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total 6543500 # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6543500 # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total 6543500 # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6543500 # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total 6543500 # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.018064 # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_miss_rate::total 0.018064 # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_miss_rate::total 0.018064 # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13087 # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13087 # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13087 # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total 13087 # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13087 # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 13087 # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.branchPred.lookups 59537 # Number of BP lookups
-system.cpu3.branchPred.condPredicted 56113 # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect 1261 # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups 52336 # Number of BTB lookups
-system.cpu3.branchPred.BTBHits 51268 # Number of BTB hits
+system.cpu3.branchPred.lookups 58611 # Number of BP lookups
+system.cpu3.branchPred.condPredicted 55067 # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect 1279 # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups 51125 # Number of BTB lookups
+system.cpu3.branchPred.BTBHits 50131 # Number of BTB hits
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct 97.959340 # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS 894 # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.BTBHitPct 98.055746 # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS 906 # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
-system.cpu3.numCycles 161647 # number of cpu cycles simulated
+system.cpu3.numCycles 160611 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles 26901 # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts 335954 # Number of instructions fetch has processed
-system.cpu3.fetch.Branches 59537 # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches 52162 # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles 130682 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles 2681 # Number of cycles fetch has spent squashing
-system.cpu3.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu3.fetch.icacheStallCycles 27021 # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts 330369 # Number of instructions fetch has processed
+system.cpu3.fetch.Branches 58611 # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches 51037 # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles 129883 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles 2715 # Number of cycles fetch has spent squashing
+system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
-system.cpu3.fetch.PendingTrapStallCycles 1202 # Number of stall cycles due to pending traps
-system.cpu3.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR
-system.cpu3.fetch.CacheLines 18139 # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes 423 # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples 160153 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean 2.097707 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev 2.240976 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.PendingTrapStallCycles 1165 # Number of stall cycles due to pending traps
+system.cpu3.fetch.CacheLines 18269 # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes 450 # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.rateDist::samples 159439 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean 2.072071 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev 2.246890 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0 45773 28.58% 28.58% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1 56940 35.55% 64.13% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2 4846 3.03% 67.16% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3 3496 2.18% 69.34% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4 1060 0.66% 70.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5 42180 26.34% 96.34% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6 1201 0.75% 97.09% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7 768 0.48% 97.57% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8 3889 2.43% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0 47077 29.53% 29.53% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1 55913 35.07% 64.60% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2 4932 3.09% 67.69% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3 3522 2.21% 69.90% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4 934 0.59% 70.48% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5 40952 25.69% 96.17% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6 1272 0.80% 96.97% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7 798 0.50% 97.47% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8 4039 2.53% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total 160153 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate 0.368315 # Number of branch fetches per cycle
-system.cpu3.fetch.rate 2.078319 # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles 16971 # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles 42083 # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles 97172 # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles 2577 # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles 1340 # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts 322134 # Number of instructions handled by decode
-system.cpu3.rename.SquashCycles 1340 # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles 17645 # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles 17747 # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles 12855 # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles 98257 # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles 12299 # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts 318864 # Number of instructions processed by rename
-system.cpu3.rename.IQFullEvents 10783 # Number of times rename has blocked due to IQ full
+system.cpu3.fetch.rateDist::total 159439 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate 0.364925 # Number of branch fetches per cycle
+system.cpu3.fetch.rate 2.056951 # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles 16993 # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles 43740 # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles 94729 # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles 2610 # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles 1357 # Number of cycles decode is squashing
+system.cpu3.decode.DecodedInsts 315004 # Number of instructions handled by decode
+system.cpu3.rename.SquashCycles 1357 # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles 17735 # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles 17944 # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles 14128 # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles 95562 # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles 12703 # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts 311495 # Number of instructions processed by rename
+system.cpu3.rename.IQFullEvents 10931 # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full
system.cpu3.rename.FullRegisterEvents 2 # Number of times there has been no free registers
-system.cpu3.rename.RenamedOperands 225541 # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups 621446 # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups 481213 # Number of integer rename lookups
-system.cpu3.rename.CommittedMaps 211532 # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps 14009 # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts 1171 # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts 1234 # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts 16730 # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads 92339 # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores 45060 # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads 43467 # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores 39931 # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded 267326 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded 4600 # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued 267770 # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsExamined 12807 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined 10139 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved 551 # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples 160153 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean 1.671964 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev 1.354316 # Number of insts issued each cycle
+system.cpu3.rename.RenamedOperands 220426 # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups 606441 # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups 469854 # Number of integer rename lookups
+system.cpu3.rename.CommittedMaps 206787 # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps 13639 # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts 1207 # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts 1278 # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts 17457 # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads 89942 # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores 43802 # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads 42282 # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores 38692 # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded 261084 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded 4750 # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued 261694 # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined 12498 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined 9712 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved 614 # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples 159439 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean 1.641342 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev 1.359128 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0 48755 30.44% 30.44% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1 16655 10.40% 40.84% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2 44376 27.71% 68.55% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3 43948 27.44% 95.99% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4 3484 2.18% 98.17% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5 1651 1.03% 99.20% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6 861 0.54% 99.74% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7 222 0.14% 99.87% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8 201 0.13% 100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0 50249 31.52% 31.52% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1 16842 10.56% 42.08% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2 43259 27.13% 69.21% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3 42799 26.84% 96.05% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4 3393 2.13% 98.18% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5 1616 1.01% 99.20% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6 876 0.55% 99.75% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7 211 0.13% 99.88% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8 194 0.12% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total 160153 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total 159439 # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu 86 25.67% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead 40 11.94% 37.61% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite 209 62.39% 100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu 81 26.21% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead 19 6.15% 32.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite 209 67.64% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu 128178 47.87% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead 95149 35.53% 83.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite 44443 16.60% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu 125700 48.03% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead 92778 35.45% 83.49% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite 43216 16.51% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total 267770 # Type of FU issued
-system.cpu3.iq.rate 1.656511 # Inst issue rate
-system.cpu3.iq.fu_busy_cnt 335 # FU busy when requested
-system.cpu3.iq.fu_busy_rate 0.001251 # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads 696028 # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes 284773 # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses 266078 # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.FU_type_0::total 261694 # Type of FU issued
+system.cpu3.iq.rate 1.629365 # Inst issue rate
+system.cpu3.iq.fu_busy_cnt 309 # FU busy when requested
+system.cpu3.iq.fu_busy_rate 0.001181 # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads 683137 # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes 278366 # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses 260191 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses 268105 # Number of integer alu accesses
+system.cpu3.iq.int_alu_accesses 262003 # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads 39763 # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.forwLoads 38539 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads 2450 # Number of loads squashed
+system.cpu3.iew.lsq.thread0.squashedLoads 2394 # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores 1547 # Number of stores squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores 1484 # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles 1340 # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles 5357 # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts 316296 # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts 170 # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts 92339 # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts 45060 # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts 1094 # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewSquashCycles 1357 # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles 5389 # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles 51 # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts 309030 # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts 159 # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts 89942 # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts 43802 # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts 1148 # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents 40 # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect 466 # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect 1001 # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts 1467 # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts 266621 # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts 91475 # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts 1149 # Number of squashed instructions skipped in execute
+system.cpu3.iew.memOrderViolationEvents 34 # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect 441 # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect 1075 # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts 1516 # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts 260676 # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts 89042 # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts 1018 # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp 0 # number of swp insts executed
-system.cpu3.iew.exec_nop 44370 # number of nop insts executed
-system.cpu3.iew.exec_refs 135810 # number of memory reference insts executed
-system.cpu3.iew.exec_branches 53906 # Number of branches executed
-system.cpu3.iew.exec_stores 44335 # Number of stores executed
-system.cpu3.iew.exec_rate 1.649403 # Inst execution rate
-system.cpu3.iew.wb_sent 266372 # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count 266078 # cumulative count of insts written-back
-system.cpu3.iew.wb_producers 153535 # num instructions producing a value
-system.cpu3.iew.wb_consumers 160065 # num instructions consuming a value
+system.cpu3.iew.exec_nop 43196 # number of nop insts executed
+system.cpu3.iew.exec_refs 132177 # number of memory reference insts executed
+system.cpu3.iew.exec_branches 52784 # Number of branches executed
+system.cpu3.iew.exec_stores 43135 # Number of stores executed
+system.cpu3.iew.exec_rate 1.623027 # Inst execution rate
+system.cpu3.iew.wb_sent 260451 # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count 260191 # cumulative count of insts written-back
+system.cpu3.iew.wb_producers 149829 # num instructions producing a value
+system.cpu3.iew.wb_consumers 156442 # num instructions consuming a value
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate 1.646044 # insts written-back per cycle
-system.cpu3.iew.wb_fanout 0.959204 # average fanout of values written-back
+system.cpu3.iew.wb_rate 1.620007 # insts written-back per cycle
+system.cpu3.iew.wb_fanout 0.957729 # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitSquashedInsts 13497 # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls 4049 # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts 1261 # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples 157643 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean 1.920440 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev 2.127029 # Number of insts commited each cycle
+system.cpu3.commit.commitSquashedInsts 13144 # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls 4136 # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts 1279 # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples 156952 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean 1.884863 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev 2.121598 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0 52663 33.41% 33.41% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1 50442 32.00% 65.40% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2 5240 3.32% 68.73% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3 4903 3.11% 71.84% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4 1534 0.97% 72.81% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5 39716 25.19% 98.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6 903 0.57% 98.58% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7 957 0.61% 99.18% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8 1285 0.82% 100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0 54210 34.54% 34.54% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1 49323 31.43% 65.96% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2 5280 3.36% 69.33% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3 4930 3.14% 72.47% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4 1531 0.98% 73.45% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5 38585 24.58% 98.03% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6 839 0.53% 98.56% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7 955 0.61% 99.17% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8 1299 0.83% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total 157643 # Number of insts commited each cycle
-system.cpu3.commit.committedInsts 302744 # Number of instructions committed
-system.cpu3.commit.committedOps 302744 # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total 156952 # Number of insts commited each cycle
+system.cpu3.commit.committedInsts 295833 # Number of instructions committed
+system.cpu3.commit.committedOps 295833 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu3.commit.refs 133402 # Number of memory references committed
-system.cpu3.commit.loads 89889 # Number of loads committed
-system.cpu3.commit.membars 3344 # Number of memory barriers committed
-system.cpu3.commit.branches 52826 # Number of branches committed
+system.cpu3.commit.refs 129866 # Number of memory references committed
+system.cpu3.commit.loads 87548 # Number of loads committed
+system.cpu3.commit.membars 3423 # Number of memory barriers committed
+system.cpu3.commit.branches 51706 # Number of branches committed
system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu3.commit.int_insts 208356 # Number of committed integer instructions.
+system.cpu3.commit.int_insts 203693 # Number of committed integer instructions.
system.cpu3.commit.function_calls 322 # Number of function calls committed.
-system.cpu3.commit.op_class_0::No_OpClass 43625 14.41% 14.41% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu 122373 40.42% 54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult 0 0.00% 54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntDiv 0 0.00% 54.83% # Class of committed instruction
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-system.cpu3.quiesceCycles 46809 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts 255775 # Number of Instructions Simulated
-system.cpu3.committedOps 255775 # Number of Ops (including micro ops) Simulated
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-system.cpu3.cpi_total 0.631989 # CPI: Total CPI of All Threads
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-system.cpu3.ipc_total 1.582306 # IPC: Total IPC of All Threads
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system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
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system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
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+system.cpu3.dcache.overall_avg_miss_latency::total 17040.059347 # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -2217,389 +2226,391 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
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+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 374 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1141 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 357 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 6585 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 38848 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32000 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31744 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31744 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 32000 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 150784 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 1022 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 4941 # Request fanout histogram
+system.toL2Bus.pkt_size::total 150336 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 1026 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 4937 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
@@ -2828,29 +2851,29 @@ system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Re
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 4941 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 4937 100.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 4941 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 2489462 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 4937 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 2487961 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 921499 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 910999 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 506002 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 509492 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 751497 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 745995 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 425967 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 443468 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 748987 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.occupancy 752993 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 449462 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy 440464 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 748992 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy 747998 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 400481 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy 407479 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
index 5bb91ca76..d98aa0788 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
@@ -277,7 +277,6 @@ hot_lines=false
memory_size_bits=48
num_of_sequencers=8
phys_mem=Null
-random_seed=1234
randomization=false
[system.ruby.clk_domain]
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
index 38ddcde63..78111ddb3 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
@@ -5,76 +5,77 @@ warn: rounding error > tolerance
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-system.cpu3: completed 10000 read, 5348 write accesses @992702
-system.cpu6: completed 10000 read, 5382 write accesses @999346
-system.cpu1: completed 10000 read, 5624 write accesses @1005749
-system.cpu7: completed 10000 read, 5532 write accesses @1010533
-system.cpu2: completed 10000 read, 5663 write accesses @1013622
-system.cpu0: completed 10000 read, 5506 write accesses @1016642
-system.cpu4: completed 10000 read, 5607 write accesses @1016852
-system.cpu5: completed 10000 read, 5639 write accesses @1018259
-system.cpu6: completed 20000 read, 10715 write accesses @1997205
-system.cpu3: completed 20000 read, 10977 write accesses @1998029
-system.cpu0: completed 20000 read, 11023 write accesses @2011456
-system.cpu1: completed 20000 read, 11145 write accesses @2015637
-system.cpu5: completed 20000 read, 11208 write accesses @2025366
-system.cpu2: completed 20000 read, 11366 write accesses @2025566
-system.cpu4: completed 20000 read, 11146 write accesses @2028120
-system.cpu7: completed 20000 read, 11121 write accesses @2045222
-system.cpu6: completed 30000 read, 16197 write accesses @2978950
-system.cpu3: completed 30000 read, 16504 write accesses @2996143
-system.cpu5: completed 30000 read, 16638 write accesses @3014669
-system.cpu2: completed 30000 read, 16960 write accesses @3020410
-system.cpu1: completed 30000 read, 16646 write accesses @3022510
-system.cpu0: completed 30000 read, 16578 write accesses @3036538
-system.cpu4: completed 30000 read, 16862 write accesses @3064327
-system.cpu7: completed 30000 read, 16883 write accesses @3094105
-system.cpu6: completed 40000 read, 21871 write accesses @3965015
-system.cpu3: completed 40000 read, 22121 write accesses @4005328
-system.cpu1: completed 40000 read, 22099 write accesses @4020080
-system.cpu0: completed 40000 read, 21993 write accesses @4023329
-system.cpu5: completed 40000 read, 22121 write accesses @4034804
-system.cpu2: completed 40000 read, 22585 write accesses @4048347
-system.cpu4: completed 40000 read, 22400 write accesses @4056884
-system.cpu7: completed 40000 read, 22529 write accesses @4115622
-system.cpu6: completed 50000 read, 27583 write accesses @4990697
-system.cpu3: completed 50000 read, 27753 write accesses @5007438
-system.cpu0: completed 50000 read, 27487 write accesses @5025428
-system.cpu5: completed 50000 read, 27656 write accesses @5027517
-system.cpu1: completed 50000 read, 27616 write accesses @5030165
-system.cpu2: completed 50000 read, 28090 write accesses @5055177
-system.cpu4: completed 50000 read, 27929 write accesses @5090891
-system.cpu7: completed 50000 read, 27992 write accesses @5110188
-system.cpu6: completed 60000 read, 32899 write accesses @5986136
-system.cpu3: completed 60000 read, 33406 write accesses @6022857
-system.cpu0: completed 60000 read, 33044 write accesses @6031653
-system.cpu1: completed 60000 read, 33212 write accesses @6041161
-system.cpu5: completed 60000 read, 33442 write accesses @6056413
-system.cpu2: completed 60000 read, 33657 write accesses @6078013
-system.cpu4: completed 60000 read, 33587 write accesses @6112419
-system.cpu7: completed 60000 read, 33576 write accesses @6115149
-system.cpu6: completed 70000 read, 38416 write accesses @6987907
-system.cpu3: completed 70000 read, 38845 write accesses @7046740
-system.cpu1: completed 70000 read, 38729 write accesses @7054748
-system.cpu0: completed 70000 read, 38718 write accesses @7054971
-system.cpu5: completed 70000 read, 39001 write accesses @7079629
-system.cpu2: completed 70000 read, 39269 write accesses @7096675
-system.cpu7: completed 70000 read, 39115 write accesses @7118065
-system.cpu4: completed 70000 read, 39088 write accesses @7118300
-system.cpu6: completed 80000 read, 43855 write accesses @7989172
-system.cpu3: completed 80000 read, 44347 write accesses @8044375
-system.cpu1: completed 80000 read, 44281 write accesses @8052426
-system.cpu0: completed 80000 read, 44306 write accesses @8066104
-system.cpu5: completed 80000 read, 44603 write accesses @8080810
-system.cpu7: completed 80000 read, 44480 write accesses @8104479
-system.cpu4: completed 80000 read, 44600 write accesses @8110552
-system.cpu2: completed 80000 read, 44822 write accesses @8120410
-system.cpu6: completed 90000 read, 49504 write accesses @8982438
-system.cpu3: completed 90000 read, 49941 write accesses @9055578
-system.cpu0: completed 90000 read, 49850 write accesses @9059967
-system.cpu1: completed 90000 read, 49940 write accesses @9064061
-system.cpu5: completed 90000 read, 50040 write accesses @9082907
-system.cpu4: completed 90000 read, 50137 write accesses @9101079
-system.cpu7: completed 90000 read, 50039 write accesses @9112455
-system.cpu2: completed 90000 read, 50353 write accesses @9135660
-system.cpu6: completed 100000 read, 55063 write accesses @9995319
+warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+system.cpu0: completed 10000 read, 5465 write accesses @998393
+system.cpu1: completed 10000 read, 5568 write accesses @998560
+system.cpu6: completed 10000 read, 5642 write accesses @998656
+system.cpu2: completed 10000 read, 5573 write accesses @1004841
+system.cpu3: completed 10000 read, 5476 write accesses @1010347
+system.cpu4: completed 10000 read, 5603 write accesses @1011379
+system.cpu5: completed 10000 read, 5505 write accesses @1015197
+system.cpu7: completed 10000 read, 5844 write accesses @1020892
+system.cpu5: completed 20000 read, 10826 write accesses @1988283
+system.cpu0: completed 20000 read, 10919 write accesses @1991296
+system.cpu2: completed 20000 read, 11214 write accesses @2016414
+system.cpu4: completed 20000 read, 11078 write accesses @2020999
+system.cpu3: completed 20000 read, 10973 write accesses @2024874
+system.cpu7: completed 20000 read, 11506 write accesses @2025376
+system.cpu1: completed 20000 read, 11280 write accesses @2034256
+system.cpu6: completed 20000 read, 11147 write accesses @2037670
+system.cpu0: completed 30000 read, 16492 write accesses @3003033
+system.cpu5: completed 30000 read, 16298 write accesses @3011465
+system.cpu2: completed 30000 read, 16727 write accesses @3021562
+system.cpu7: completed 30000 read, 17173 write accesses @3033070
+system.cpu4: completed 30000 read, 16630 write accesses @3037868
+system.cpu6: completed 30000 read, 16672 write accesses @3038113
+system.cpu1: completed 30000 read, 16762 write accesses @3039811
+system.cpu3: completed 30000 read, 16588 write accesses @3051868
+system.cpu0: completed 40000 read, 21857 write accesses @4007879
+system.cpu2: completed 40000 read, 22234 write accesses @4028507
+system.cpu5: completed 40000 read, 21876 write accesses @4029649
+system.cpu6: completed 40000 read, 22097 write accesses @4032969
+system.cpu7: completed 40000 read, 22955 write accesses @4041622
+system.cpu1: completed 40000 read, 22471 write accesses @4049342
+system.cpu4: completed 40000 read, 22226 write accesses @4049383
+system.cpu3: completed 40000 read, 22078 write accesses @4062017
+system.cpu0: completed 50000 read, 27390 write accesses @5007193
+system.cpu7: completed 50000 read, 28594 write accesses @5029095
+system.cpu6: completed 50000 read, 27699 write accesses @5034544
+system.cpu5: completed 50000 read, 27508 write accesses @5037357
+system.cpu2: completed 50000 read, 27805 write accesses @5056032
+system.cpu1: completed 50000 read, 27932 write accesses @5062407
+system.cpu4: completed 50000 read, 27727 write accesses @5066868
+system.cpu3: completed 50000 read, 27598 write accesses @5095158
+system.cpu0: completed 60000 read, 33008 write accesses @6027788
+system.cpu7: completed 60000 read, 34229 write accesses @6038886
+system.cpu2: completed 60000 read, 33270 write accesses @6041019
+system.cpu5: completed 60000 read, 33038 write accesses @6044214
+system.cpu6: completed 60000 read, 33158 write accesses @6056522
+system.cpu1: completed 60000 read, 33437 write accesses @6060012
+system.cpu4: completed 60000 read, 33093 write accesses @6067283
+system.cpu3: completed 60000 read, 33046 write accesses @6099437
+system.cpu5: completed 70000 read, 38476 write accesses @7038412
+system.cpu0: completed 70000 read, 38672 write accesses @7049839
+system.cpu1: completed 70000 read, 38910 write accesses @7056694
+system.cpu2: completed 70000 read, 38729 write accesses @7056805
+system.cpu7: completed 70000 read, 39799 write accesses @7060220
+system.cpu4: completed 70000 read, 38525 write accesses @7063727
+system.cpu6: completed 70000 read, 38777 write accesses @7087878
+system.cpu3: completed 70000 read, 38653 write accesses @7104531
+system.cpu1: completed 80000 read, 44180 write accesses @8052473
+system.cpu4: completed 80000 read, 44107 write accesses @8058206
+system.cpu5: completed 80000 read, 44043 write accesses @8061949
+system.cpu2: completed 80000 read, 44449 write accesses @8062064
+system.cpu0: completed 80000 read, 44315 write accesses @8063955
+system.cpu7: completed 80000 read, 45316 write accesses @8089150
+system.cpu6: completed 80000 read, 44501 write accesses @8102611
+system.cpu3: completed 80000 read, 44234 write accesses @8131712
+system.cpu0: completed 90000 read, 49836 write accesses @9060237
+system.cpu1: completed 90000 read, 49611 write accesses @9070183
+system.cpu5: completed 90000 read, 49612 write accesses @9081515
+system.cpu4: completed 90000 read, 49785 write accesses @9092029
+system.cpu2: completed 90000 read, 50012 write accesses @9093129
+system.cpu6: completed 90000 read, 50151 write accesses @9110021
+system.cpu7: completed 90000 read, 50786 write accesses @9110647
+system.cpu3: completed 90000 read, 49787 write accesses @9134229
+system.cpu0: completed 100000 read, 55281 write accesses @10063247
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
index b71684a15..dc6e8bffa 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
@@ -277,7 +277,6 @@ hot_lines=false
memory_size_bits=48
num_of_sequencers=8
phys_mem=Null
-random_seed=1234
randomization=false
[system.ruby.clk_domain]
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
index 614ba1c08..ec7781619 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
@@ -5,76 +5,77 @@ warn: rounding error > tolerance
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-system.cpu6: completed 10000 read, 5570 write accesses @748299
-system.cpu5: completed 10000 read, 5647 write accesses @748339
-system.cpu7: completed 10000 read, 5495 write accesses @748944
-system.cpu1: completed 10000 read, 5568 write accesses @750499
-system.cpu0: completed 10000 read, 5483 write accesses @751080
-system.cpu3: completed 10000 read, 5619 write accesses @755896
-system.cpu4: completed 10000 read, 5746 write accesses @761190
-system.cpu2: completed 10000 read, 5739 write accesses @761633
-system.cpu7: completed 20000 read, 11020 write accesses @1491203
-system.cpu1: completed 20000 read, 11119 write accesses @1491567
-system.cpu0: completed 20000 read, 11060 write accesses @1496113
-system.cpu5: completed 20000 read, 11192 write accesses @1498026
-system.cpu2: completed 20000 read, 11268 write accesses @1499402
-system.cpu6: completed 20000 read, 11125 write accesses @1500210
-system.cpu4: completed 20000 read, 11177 write accesses @1507742
-system.cpu3: completed 20000 read, 11198 write accesses @1508349
-system.cpu1: completed 30000 read, 16685 write accesses @2235920
-system.cpu7: completed 30000 read, 16570 write accesses @2243071
-system.cpu3: completed 30000 read, 16661 write accesses @2246169
-system.cpu5: completed 30000 read, 16817 write accesses @2247226
-system.cpu6: completed 30000 read, 16630 write accesses @2251239
-system.cpu2: completed 30000 read, 17073 write accesses @2253746
-system.cpu0: completed 30000 read, 16607 write accesses @2257900
-system.cpu4: completed 30000 read, 16751 write accesses @2259082
-system.cpu1: completed 40000 read, 22443 write accesses @2985201
-system.cpu6: completed 40000 read, 22171 write accesses @2988819
-system.cpu5: completed 40000 read, 22360 write accesses @2994816
-system.cpu3: completed 40000 read, 22299 write accesses @2995156
-system.cpu2: completed 40000 read, 22516 write accesses @2995179
-system.cpu0: completed 40000 read, 22114 write accesses @2997980
-system.cpu4: completed 40000 read, 22133 write accesses @3004731
-system.cpu7: completed 40000 read, 22279 write accesses @3009795
-system.cpu1: completed 50000 read, 27939 write accesses @3723980
-system.cpu5: completed 50000 read, 27866 write accesses @3732543
-system.cpu2: completed 50000 read, 28007 write accesses @3736276
-system.cpu0: completed 50000 read, 27557 write accesses @3741693
-system.cpu6: completed 50000 read, 27758 write accesses @3746907
-system.cpu3: completed 50000 read, 28063 write accesses @3754651
-system.cpu4: completed 50000 read, 27711 write accesses @3755367
-system.cpu7: completed 50000 read, 27794 write accesses @3759179
-system.cpu1: completed 60000 read, 33413 write accesses @4481770
-system.cpu2: completed 60000 read, 33545 write accesses @4483814
-system.cpu5: completed 60000 read, 33400 write accesses @4486225
-system.cpu6: completed 60000 read, 33358 write accesses @4489305
-system.cpu0: completed 60000 read, 33272 write accesses @4495744
-system.cpu7: completed 60000 read, 33388 write accesses @4502600
-system.cpu3: completed 60000 read, 33518 write accesses @4505507
-system.cpu4: completed 60000 read, 33246 write accesses @4507884
-system.cpu6: completed 70000 read, 38763 write accesses @5228140
-system.cpu1: completed 70000 read, 38950 write accesses @5234719
-system.cpu5: completed 70000 read, 39075 write accesses @5237913
-system.cpu7: completed 70000 read, 38837 write accesses @5239204
-system.cpu2: completed 70000 read, 39142 write accesses @5242564
-system.cpu3: completed 70000 read, 39128 write accesses @5249855
-system.cpu0: completed 70000 read, 38875 write accesses @5253251
-system.cpu4: completed 70000 read, 38862 write accesses @5255205
-system.cpu6: completed 80000 read, 44316 write accesses @5978847
-system.cpu1: completed 80000 read, 44524 write accesses @5980771
-system.cpu5: completed 80000 read, 44534 write accesses @5982466
-system.cpu7: completed 80000 read, 44358 write accesses @5986610
-system.cpu0: completed 80000 read, 44270 write accesses @5996151
-system.cpu2: completed 80000 read, 44750 write accesses @6000893
-system.cpu3: completed 80000 read, 44691 write accesses @6004535
-system.cpu4: completed 80000 read, 44602 write accesses @6010875
-system.cpu6: completed 90000 read, 49845 write accesses @6717920
-system.cpu7: completed 90000 read, 50000 write accesses @6722062
-system.cpu1: completed 90000 read, 50241 write accesses @6726859
-system.cpu5: completed 90000 read, 50114 write accesses @6731510
-system.cpu0: completed 90000 read, 49747 write accesses @6741713
-system.cpu2: completed 90000 read, 50307 write accesses @6746697
-system.cpu3: completed 90000 read, 50421 write accesses @6748141
-system.cpu4: completed 90000 read, 50184 write accesses @6762059
-system.cpu1: completed 100000 read, 56005 write accesses @7477743
+warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+system.cpu7: completed 10000 read, 5629 write accesses @741490
+system.cpu2: completed 10000 read, 5483 write accesses @742929
+system.cpu5: completed 10000 read, 5467 write accesses @745712
+system.cpu6: completed 10000 read, 5704 write accesses @746130
+system.cpu1: completed 10000 read, 5548 write accesses @750324
+system.cpu3: completed 10000 read, 5605 write accesses @759134
+system.cpu4: completed 10000 read, 5617 write accesses @761737
+system.cpu0: completed 10000 read, 5610 write accesses @763525
+system.cpu6: completed 20000 read, 11106 write accesses @1481450
+system.cpu1: completed 20000 read, 11101 write accesses @1481864
+system.cpu2: completed 20000 read, 11175 write accesses @1493928
+system.cpu5: completed 20000 read, 11075 write accesses @1494219
+system.cpu7: completed 20000 read, 11191 write accesses @1494602
+system.cpu3: completed 20000 read, 11025 write accesses @1510005
+system.cpu4: completed 20000 read, 11155 write accesses @1515394
+system.cpu0: completed 20000 read, 11262 write accesses @1521161
+system.cpu1: completed 30000 read, 16596 write accesses @2213794
+system.cpu7: completed 30000 read, 16886 write accesses @2238208
+system.cpu2: completed 30000 read, 16749 write accesses @2249468
+system.cpu6: completed 30000 read, 16669 write accesses @2250299
+system.cpu5: completed 30000 read, 16592 write accesses @2250650
+system.cpu4: completed 30000 read, 16824 write accesses @2255563
+system.cpu3: completed 30000 read, 16603 write accesses @2258409
+system.cpu0: completed 30000 read, 16741 write accesses @2271167
+system.cpu1: completed 40000 read, 22131 write accesses @2952037
+system.cpu7: completed 40000 read, 22258 write accesses @2971365
+system.cpu4: completed 40000 read, 22385 write accesses @2992340
+system.cpu6: completed 40000 read, 22195 write accesses @2994415
+system.cpu2: completed 40000 read, 22365 write accesses @2995127
+system.cpu5: completed 40000 read, 22189 write accesses @2998059
+system.cpu0: completed 40000 read, 22190 write accesses @3008067
+system.cpu3: completed 40000 read, 22193 write accesses @3026200
+system.cpu1: completed 50000 read, 27565 write accesses @3685675
+system.cpu7: completed 50000 read, 27746 write accesses @3722444
+system.cpu4: completed 50000 read, 27966 write accesses @3737210
+system.cpu6: completed 50000 read, 27651 write accesses @3741340
+system.cpu2: completed 50000 read, 28025 write accesses @3751350
+system.cpu5: completed 50000 read, 27824 write accesses @3753408
+system.cpu0: completed 50000 read, 27788 write accesses @3764354
+system.cpu3: completed 50000 read, 27801 write accesses @3780460
+system.cpu1: completed 60000 read, 33120 write accesses @4430711
+system.cpu7: completed 60000 read, 33190 write accesses @4467208
+system.cpu4: completed 60000 read, 33493 write accesses @4471542
+system.cpu6: completed 60000 read, 33060 write accesses @4489453
+system.cpu0: completed 60000 read, 33163 write accesses @4498105
+system.cpu2: completed 60000 read, 33785 write accesses @4501427
+system.cpu5: completed 60000 read, 33616 write accesses @4507211
+system.cpu3: completed 60000 read, 33449 write accesses @4535522
+system.cpu1: completed 70000 read, 38615 write accesses @5182293
+system.cpu4: completed 70000 read, 39172 write accesses @5218522
+system.cpu7: completed 70000 read, 38708 write accesses @5235601
+system.cpu0: completed 70000 read, 38698 write accesses @5238798
+system.cpu6: completed 70000 read, 38663 write accesses @5239196
+system.cpu2: completed 70000 read, 39373 write accesses @5249164
+system.cpu5: completed 70000 read, 39147 write accesses @5262073
+system.cpu3: completed 70000 read, 38967 write accesses @5264376
+system.cpu1: completed 80000 read, 44079 write accesses @5932822
+system.cpu4: completed 80000 read, 44608 write accesses @5965802
+system.cpu0: completed 80000 read, 44082 write accesses @5973833
+system.cpu6: completed 80000 read, 44113 write accesses @5993004
+system.cpu7: completed 80000 read, 44313 write accesses @5994643
+system.cpu2: completed 80000 read, 44913 write accesses @5996066
+system.cpu5: completed 80000 read, 44640 write accesses @6007836
+system.cpu3: completed 80000 read, 44574 write accesses @6019565
+system.cpu1: completed 90000 read, 49658 write accesses @6686890
+system.cpu4: completed 90000 read, 50184 write accesses @6709227
+system.cpu0: completed 90000 read, 49596 write accesses @6710987
+system.cpu7: completed 90000 read, 49959 write accesses @6740828
+system.cpu2: completed 90000 read, 50425 write accesses @6744606
+system.cpu6: completed 90000 read, 49767 write accesses @6747581
+system.cpu3: completed 90000 read, 49994 write accesses @6761894
+system.cpu5: completed 90000 read, 50371 write accesses @6774603
+system.cpu4: completed 100000 read, 55545 write accesses @7450335
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
index f35fc603f..902cf6245 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
@@ -277,7 +277,6 @@ hot_lines=false
memory_size_bits=48
num_of_sequencers=8
phys_mem=Null
-random_seed=1234
randomization=false
[system.ruby.clk_domain]
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
index 4efa8f799..7f8bac20f 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
@@ -5,76 +5,77 @@ warn: rounding error > tolerance
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-system.cpu0: completed 10000 read, 5438 write accesses @570769
-system.cpu3: completed 10000 read, 5486 write accesses @571889
-system.cpu7: completed 10000 read, 5573 write accesses @579188
-system.cpu1: completed 10000 read, 5608 write accesses @581011
-system.cpu6: completed 10000 read, 5567 write accesses @582686
-system.cpu4: completed 10000 read, 5591 write accesses @584722
-system.cpu2: completed 10000 read, 5557 write accesses @586208
-system.cpu5: completed 10000 read, 5736 write accesses @589352
-system.cpu0: completed 20000 read, 11059 write accesses @1157243
-system.cpu6: completed 20000 read, 11078 write accesses @1162403
-system.cpu3: completed 20000 read, 10981 write accesses @1164669
-system.cpu1: completed 20000 read, 11264 write accesses @1166168
-system.cpu7: completed 20000 read, 11196 write accesses @1167284
-system.cpu4: completed 20000 read, 11109 write accesses @1177371
-system.cpu2: completed 20000 read, 11057 write accesses @1180619
-system.cpu5: completed 20000 read, 11381 write accesses @1181888
-system.cpu3: completed 30000 read, 16437 write accesses @1737096
-system.cpu6: completed 30000 read, 16668 write accesses @1737657
-system.cpu0: completed 30000 read, 16583 write accesses @1744758
-system.cpu7: completed 30000 read, 16677 write accesses @1750821
-system.cpu1: completed 30000 read, 16900 write accesses @1758970
-system.cpu4: completed 30000 read, 16637 write accesses @1759061
-system.cpu2: completed 30000 read, 16692 write accesses @1764462
-system.cpu5: completed 30000 read, 17012 write accesses @1766901
-system.cpu3: completed 40000 read, 21900 write accesses @2318433
-system.cpu6: completed 40000 read, 22213 write accesses @2326183
-system.cpu0: completed 40000 read, 22100 write accesses @2330415
-system.cpu7: completed 40000 read, 22210 write accesses @2340974
-system.cpu1: completed 40000 read, 22520 write accesses @2342642
-system.cpu4: completed 40000 read, 22243 write accesses @2344379
-system.cpu2: completed 40000 read, 22366 write accesses @2353655
-system.cpu5: completed 40000 read, 22618 write accesses @2355311
-system.cpu3: completed 50000 read, 27430 write accesses @2905853
-system.cpu0: completed 50000 read, 27644 write accesses @2909589
-system.cpu6: completed 50000 read, 27833 write accesses @2914500
-system.cpu1: completed 50000 read, 28151 write accesses @2927131
-system.cpu7: completed 50000 read, 27858 write accesses @2932955
-system.cpu5: completed 50000 read, 28068 write accesses @2933318
-system.cpu4: completed 50000 read, 27863 write accesses @2935763
-system.cpu2: completed 50000 read, 27944 write accesses @2939029
-system.cpu3: completed 60000 read, 33085 write accesses @3485958
-system.cpu0: completed 60000 read, 33127 write accesses @3493381
-system.cpu6: completed 60000 read, 33377 write accesses @3507979
-system.cpu2: completed 60000 read, 33438 write accesses @3515468
-system.cpu4: completed 60000 read, 33417 write accesses @3516729
-system.cpu1: completed 60000 read, 33739 write accesses @3518747
-system.cpu5: completed 60000 read, 33740 write accesses @3526984
-system.cpu7: completed 60000 read, 33559 write accesses @3532034
-system.cpu3: completed 70000 read, 38725 write accesses @4062982
-system.cpu0: completed 70000 read, 38646 write accesses @4078763
-system.cpu2: completed 70000 read, 39080 write accesses @4090901
-system.cpu6: completed 70000 read, 38952 write accesses @4094520
-system.cpu5: completed 70000 read, 39225 write accesses @4095937
-system.cpu4: completed 70000 read, 39045 write accesses @4099573
-system.cpu1: completed 70000 read, 39252 write accesses @4107563
-system.cpu7: completed 70000 read, 39300 write accesses @4124546
-system.cpu3: completed 80000 read, 44295 write accesses @4644973
-system.cpu0: completed 80000 read, 44378 write accesses @4658860
-system.cpu6: completed 80000 read, 44423 write accesses @4666482
-system.cpu2: completed 80000 read, 44600 write accesses @4677073
-system.cpu5: completed 80000 read, 44978 write accesses @4678763
-system.cpu4: completed 80000 read, 44603 write accesses @4687972
-system.cpu1: completed 80000 read, 44846 write accesses @4689031
-system.cpu7: completed 80000 read, 44628 write accesses @4707929
-system.cpu3: completed 90000 read, 49800 write accesses @5223450
-system.cpu6: completed 90000 read, 49915 write accesses @5243962
-system.cpu0: completed 90000 read, 50068 write accesses @5252685
-system.cpu2: completed 90000 read, 50165 write accesses @5258561
-system.cpu5: completed 90000 read, 50552 write accesses @5261845
-system.cpu1: completed 90000 read, 50370 write accesses @5279905
-system.cpu4: completed 90000 read, 50291 write accesses @5283589
-system.cpu7: completed 90000 read, 50405 write accesses @5296282
-system.cpu3: completed 100000 read, 55379 write accesses @5815635
+warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+system.cpu2: completed 10000 read, 5534 write accesses @569178
+system.cpu4: completed 10000 read, 5465 write accesses @574915
+system.cpu3: completed 10000 read, 5497 write accesses @574937
+system.cpu0: completed 10000 read, 5565 write accesses @574960
+system.cpu5: completed 10000 read, 5652 write accesses @581034
+system.cpu1: completed 10000 read, 5555 write accesses @582035
+system.cpu6: completed 10000 read, 5449 write accesses @585160
+system.cpu7: completed 10000 read, 5566 write accesses @590115
+system.cpu2: completed 20000 read, 11022 write accesses @1126531
+system.cpu4: completed 20000 read, 10939 write accesses @1142499
+system.cpu0: completed 20000 read, 11310 write accesses @1159134
+system.cpu1: completed 20000 read, 11166 write accesses @1161343
+system.cpu6: completed 20000 read, 10890 write accesses @1161677
+system.cpu5: completed 20000 read, 11181 write accesses @1166462
+system.cpu3: completed 20000 read, 11040 write accesses @1167366
+system.cpu7: completed 20000 read, 11027 write accesses @1170049
+system.cpu2: completed 30000 read, 16703 write accesses @1710014
+system.cpu4: completed 30000 read, 16637 write accesses @1736174
+system.cpu6: completed 30000 read, 16254 write accesses @1736781
+system.cpu0: completed 30000 read, 16824 write accesses @1741663
+system.cpu1: completed 30000 read, 16729 write accesses @1746318
+system.cpu3: completed 30000 read, 16380 write accesses @1746864
+system.cpu5: completed 30000 read, 16699 write accesses @1749543
+system.cpu7: completed 30000 read, 16593 write accesses @1755317
+system.cpu2: completed 40000 read, 22220 write accesses @2299827
+system.cpu4: completed 40000 read, 22137 write accesses @2310891
+system.cpu0: completed 40000 read, 22226 write accesses @2313874
+system.cpu3: completed 40000 read, 21851 write accesses @2325087
+system.cpu1: completed 40000 read, 22363 write accesses @2328426
+system.cpu6: completed 40000 read, 21890 write accesses @2332432
+system.cpu5: completed 40000 read, 22240 write accesses @2338721
+system.cpu7: completed 40000 read, 22061 write accesses @2344897
+system.cpu2: completed 50000 read, 27819 write accesses @2881934
+system.cpu4: completed 50000 read, 27895 write accesses @2900734
+system.cpu0: completed 50000 read, 27815 write accesses @2900790
+system.cpu3: completed 50000 read, 27422 write accesses @2903532
+system.cpu6: completed 50000 read, 27382 write accesses @2918034
+system.cpu1: completed 50000 read, 27840 write accesses @2920513
+system.cpu5: completed 50000 read, 27748 write accesses @2927060
+system.cpu7: completed 50000 read, 27652 write accesses @2929759
+system.cpu2: completed 60000 read, 33490 write accesses @3464091
+system.cpu0: completed 60000 read, 33375 write accesses @3480817
+system.cpu4: completed 60000 read, 33517 write accesses @3486603
+system.cpu3: completed 60000 read, 33057 write accesses @3493116
+system.cpu6: completed 60000 read, 33095 write accesses @3508756
+system.cpu1: completed 60000 read, 33334 write accesses @3509528
+system.cpu5: completed 60000 read, 33334 write accesses @3510074
+system.cpu7: completed 60000 read, 33249 write accesses @3510130
+system.cpu2: completed 70000 read, 38895 write accesses @4051519
+system.cpu0: completed 70000 read, 39000 write accesses @4061632
+system.cpu4: completed 70000 read, 39030 write accesses @4069905
+system.cpu3: completed 70000 read, 38509 write accesses @4083701
+system.cpu1: completed 70000 read, 38918 write accesses @4095424
+system.cpu7: completed 70000 read, 38836 write accesses @4097039
+system.cpu5: completed 70000 read, 38933 write accesses @4099052
+system.cpu6: completed 70000 read, 38530 write accesses @4100439
+system.cpu2: completed 80000 read, 44484 write accesses @4637728
+system.cpu0: completed 80000 read, 44611 write accesses @4638049
+system.cpu4: completed 80000 read, 44541 write accesses @4643818
+system.cpu3: completed 80000 read, 44193 write accesses @4673647
+system.cpu5: completed 80000 read, 44336 write accesses @4673863
+system.cpu7: completed 80000 read, 44217 write accesses @4679114
+system.cpu1: completed 80000 read, 44372 write accesses @4685942
+system.cpu6: completed 80000 read, 44195 write accesses @4694933
+system.cpu2: completed 90000 read, 50176 write accesses @5226302
+system.cpu4: completed 90000 read, 50158 write accesses @5229556
+system.cpu0: completed 90000 read, 50290 write accesses @5238793
+system.cpu5: completed 90000 read, 49829 write accesses @5251555
+system.cpu3: completed 90000 read, 49657 write accesses @5262428
+system.cpu1: completed 90000 read, 49892 write accesses @5268645
+system.cpu7: completed 90000 read, 49892 write accesses @5270670
+system.cpu6: completed 90000 read, 49840 write accesses @5284950
+system.cpu4: completed 100000 read, 55681 write accesses @5804619
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
index 71ed7021a..dfaa8805c 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
@@ -277,7 +277,6 @@ hot_lines=false
memory_size_bits=48
num_of_sequencers=8
phys_mem=Null
-random_seed=1234
randomization=false
[system.ruby.clk_domain]
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
index fb4f3b04a..54948ce1e 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
@@ -5,76 +5,77 @@ warn: rounding error > tolerance
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-system.cpu2: completed 10000 read, 5682 write accesses @468618
-system.cpu0: completed 10000 read, 5397 write accesses @470518
-system.cpu4: completed 10000 read, 5666 write accesses @470555
-system.cpu7: completed 10000 read, 5549 write accesses @473660
-system.cpu1: completed 10000 read, 5645 write accesses @474596
-system.cpu6: completed 10000 read, 5628 write accesses @480303
-system.cpu5: completed 10000 read, 5664 write accesses @480328
-system.cpu3: completed 10000 read, 5553 write accesses @482516
-system.cpu1: completed 20000 read, 11276 write accesses @941108
-system.cpu0: completed 20000 read, 10999 write accesses @944640
-system.cpu2: completed 20000 read, 11272 write accesses @946991
-system.cpu7: completed 20000 read, 10999 write accesses @947826
-system.cpu4: completed 20000 read, 11411 write accesses @948779
-system.cpu6: completed 20000 read, 11144 write accesses @953193
-system.cpu5: completed 20000 read, 11173 write accesses @954235
-system.cpu3: completed 20000 read, 11228 write accesses @961631
-system.cpu1: completed 30000 read, 16818 write accesses @1419188
-system.cpu0: completed 30000 read, 16479 write accesses @1420336
-system.cpu5: completed 30000 read, 16548 write accesses @1421142
-system.cpu2: completed 30000 read, 16790 write accesses @1421818
-system.cpu7: completed 30000 read, 16464 write accesses @1422123
-system.cpu4: completed 30000 read, 17005 write accesses @1422259
-system.cpu6: completed 30000 read, 16812 write accesses @1431146
-system.cpu3: completed 30000 read, 16876 write accesses @1437656
-system.cpu2: completed 40000 read, 22285 write accesses @1891081
-system.cpu5: completed 40000 read, 22160 write accesses @1896261
-system.cpu7: completed 40000 read, 21953 write accesses @1897179
-system.cpu1: completed 40000 read, 22536 write accesses @1897207
-system.cpu0: completed 40000 read, 21989 write accesses @1898643
-system.cpu6: completed 40000 read, 22334 write accesses @1898811
-system.cpu4: completed 40000 read, 22788 write accesses @1906823
-system.cpu3: completed 40000 read, 22523 write accesses @1907448
-system.cpu2: completed 50000 read, 27730 write accesses @2357928
-system.cpu5: completed 50000 read, 27750 write accesses @2363043
-system.cpu1: completed 50000 read, 28041 write accesses @2368230
-system.cpu6: completed 50000 read, 27966 write accesses @2376268
-system.cpu0: completed 50000 read, 27789 write accesses @2380452
-system.cpu3: completed 50000 read, 27901 write accesses @2382173
-system.cpu7: completed 50000 read, 27437 write accesses @2383988
-system.cpu4: completed 50000 read, 28553 write accesses @2384309
-system.cpu2: completed 60000 read, 33436 write accesses @2836829
-system.cpu5: completed 60000 read, 33223 write accesses @2839619
-system.cpu6: completed 60000 read, 33442 write accesses @2843227
-system.cpu1: completed 60000 read, 33632 write accesses @2850331
-system.cpu3: completed 60000 read, 33335 write accesses @2850932
-system.cpu0: completed 60000 read, 33499 write accesses @2853510
-system.cpu7: completed 60000 read, 33083 write accesses @2863799
-system.cpu4: completed 60000 read, 34211 write accesses @2865957
-system.cpu5: completed 70000 read, 38796 write accesses @3309970
-system.cpu2: completed 70000 read, 39076 write accesses @3312829
-system.cpu6: completed 70000 read, 38982 write accesses @3317982
-system.cpu3: completed 70000 read, 38893 write accesses @3320658
-system.cpu1: completed 70000 read, 39042 write accesses @3326984
-system.cpu0: completed 70000 read, 39160 write accesses @3330466
-system.cpu4: completed 70000 read, 39705 write accesses @3336097
-system.cpu7: completed 70000 read, 38681 write accesses @3351133
-system.cpu2: completed 80000 read, 44448 write accesses @3784665
-system.cpu5: completed 80000 read, 44282 write accesses @3786578
-system.cpu6: completed 80000 read, 44649 write accesses @3794509
-system.cpu3: completed 80000 read, 44408 write accesses @3795252
-system.cpu1: completed 80000 read, 44488 write accesses @3798206
-system.cpu0: completed 80000 read, 44824 write accesses @3800842
-system.cpu4: completed 80000 read, 45327 write accesses @3814610
-system.cpu7: completed 80000 read, 44370 write accesses @3836498
-system.cpu2: completed 90000 read, 50112 write accesses @4258356
-system.cpu5: completed 90000 read, 49726 write accesses @4263981
-system.cpu1: completed 90000 read, 49878 write accesses @4270068
-system.cpu6: completed 90000 read, 50189 write accesses @4270506
-system.cpu3: completed 90000 read, 50062 write accesses @4274971
-system.cpu0: completed 90000 read, 50500 write accesses @4278576
-system.cpu4: completed 90000 read, 51009 write accesses @4290694
-system.cpu7: completed 90000 read, 50035 write accesses @4314863
-system.cpu5: completed 100000 read, 55296 write accesses @4735173
+warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+system.cpu0: completed 10000 read, 5501 write accesses @467078
+system.cpu7: completed 10000 read, 5585 write accesses @472925
+system.cpu6: completed 10000 read, 5702 write accesses @473859
+system.cpu2: completed 10000 read, 5570 write accesses @475598
+system.cpu5: completed 10000 read, 5606 write accesses @476119
+system.cpu1: completed 10000 read, 5578 write accesses @479229
+system.cpu4: completed 10000 read, 5573 write accesses @479674
+system.cpu3: completed 10000 read, 5640 write accesses @487499
+system.cpu0: completed 20000 read, 10981 write accesses @938964
+system.cpu7: completed 20000 read, 11056 write accesses @947871
+system.cpu6: completed 20000 read, 11411 write accesses @949459
+system.cpu2: completed 20000 read, 11228 write accesses @952214
+system.cpu1: completed 20000 read, 11065 write accesses @953211
+system.cpu3: completed 20000 read, 11304 write accesses @953777
+system.cpu4: completed 20000 read, 11256 write accesses @958238
+system.cpu5: completed 20000 read, 11225 write accesses @963838
+system.cpu0: completed 30000 read, 16484 write accesses @1401349
+system.cpu7: completed 30000 read, 16587 write accesses @1415642
+system.cpu6: completed 30000 read, 17110 write accesses @1421193
+system.cpu2: completed 30000 read, 16781 write accesses @1426752
+system.cpu4: completed 30000 read, 16747 write accesses @1427872
+system.cpu3: completed 30000 read, 16939 write accesses @1428046
+system.cpu5: completed 30000 read, 16611 write accesses @1429067
+system.cpu1: completed 30000 read, 16662 write accesses @1439258
+system.cpu0: completed 40000 read, 22150 write accesses @1869298
+system.cpu7: completed 40000 read, 22057 write accesses @1896002
+system.cpu5: completed 40000 read, 22232 write accesses @1898974
+system.cpu3: completed 40000 read, 22443 write accesses @1899719
+system.cpu4: completed 40000 read, 22301 write accesses @1902954
+system.cpu2: completed 40000 read, 22327 write accesses @1903835
+system.cpu6: completed 40000 read, 22829 write accesses @1906722
+system.cpu1: completed 40000 read, 22218 write accesses @1911204
+system.cpu0: completed 50000 read, 27765 write accesses @2351180
+system.cpu7: completed 50000 read, 27538 write accesses @2370464
+system.cpu5: completed 50000 read, 27786 write accesses @2373992
+system.cpu6: completed 50000 read, 28263 write accesses @2376222
+system.cpu4: completed 50000 read, 27975 write accesses @2380027
+system.cpu2: completed 50000 read, 28023 write accesses @2381328
+system.cpu3: completed 50000 read, 27880 write accesses @2381446
+system.cpu1: completed 50000 read, 27838 write accesses @2385886
+system.cpu0: completed 60000 read, 33279 write accesses @2819366
+system.cpu5: completed 60000 read, 33244 write accesses @2835967
+system.cpu7: completed 60000 read, 32998 write accesses @2836623
+system.cpu6: completed 60000 read, 33822 write accesses @2850173
+system.cpu4: completed 60000 read, 33518 write accesses @2855957
+system.cpu3: completed 60000 read, 33583 write accesses @2858859
+system.cpu2: completed 60000 read, 33714 write accesses @2861156
+system.cpu1: completed 60000 read, 33518 write accesses @2869518
+system.cpu0: completed 70000 read, 38798 write accesses @3293451
+system.cpu7: completed 70000 read, 38547 write accesses @3309641
+system.cpu5: completed 70000 read, 38890 write accesses @3314464
+system.cpu6: completed 70000 read, 39365 write accesses @3323971
+system.cpu3: completed 70000 read, 39171 write accesses @3326960
+system.cpu2: completed 70000 read, 39322 write accesses @3333015
+system.cpu4: completed 70000 read, 39148 write accesses @3335631
+system.cpu1: completed 70000 read, 39115 write accesses @3343424
+system.cpu0: completed 80000 read, 44502 write accesses @3773676
+system.cpu7: completed 80000 read, 44178 write accesses @3784689
+system.cpu5: completed 80000 read, 44522 write accesses @3798601
+system.cpu6: completed 80000 read, 45044 write accesses @3801812
+system.cpu2: completed 80000 read, 44852 write accesses @3805475
+system.cpu3: completed 80000 read, 44704 write accesses @3805485
+system.cpu4: completed 80000 read, 44724 write accesses @3811165
+system.cpu1: completed 80000 read, 44691 write accesses @3816230
+system.cpu0: completed 90000 read, 50144 write accesses @4257479
+system.cpu7: completed 90000 read, 49707 write accesses @4267140
+system.cpu3: completed 90000 read, 50073 write accesses @4274290
+system.cpu2: completed 90000 read, 50440 write accesses @4275160
+system.cpu6: completed 90000 read, 50729 write accesses @4275803
+system.cpu5: completed 90000 read, 50235 write accesses @4277870
+system.cpu4: completed 90000 read, 50337 write accesses @4285144
+system.cpu1: completed 90000 read, 50416 write accesses @4290707
+system.cpu0: completed 100000 read, 55755 write accesses @4723747
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
index ac16b5115..f67ca278f 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
@@ -277,7 +277,6 @@ hot_lines=false
memory_size_bits=48
num_of_sequencers=8
phys_mem=Null
-random_seed=1234
randomization=false
[system.ruby.clk_domain]
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
index d407a62fd..76ce9faa1 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
@@ -5,76 +5,77 @@ warn: rounding error > tolerance
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-system.cpu3: completed 10000 read, 5525 write accesses @760625
-system.cpu5: completed 10000 read, 5663 write accesses @765664
-system.cpu1: completed 10000 read, 5656 write accesses @767292
-system.cpu4: completed 10000 read, 5509 write accesses @775011
-system.cpu6: completed 10000 read, 5563 write accesses @775672
-system.cpu0: completed 10000 read, 5617 write accesses @776185
-system.cpu2: completed 10000 read, 5515 write accesses @776720
-system.cpu7: completed 10000 read, 5487 write accesses @777568
-system.cpu3: completed 20000 read, 11028 write accesses @1517020
-system.cpu4: completed 20000 read, 10944 write accesses @1530984
-system.cpu6: completed 20000 read, 11090 write accesses @1531354
-system.cpu1: completed 20000 read, 11154 write accesses @1539725
-system.cpu2: completed 20000 read, 10831 write accesses @1540287
-system.cpu7: completed 20000 read, 11114 write accesses @1543700
-system.cpu5: completed 20000 read, 11175 write accesses @1554030
-system.cpu0: completed 20000 read, 11186 write accesses @1559187
-system.cpu3: completed 30000 read, 16598 write accesses @2283007
-system.cpu1: completed 30000 read, 16605 write accesses @2291164
-system.cpu4: completed 30000 read, 16704 write accesses @2303776
-system.cpu6: completed 30000 read, 16727 write accesses @2310983
-system.cpu5: completed 30000 read, 16800 write accesses @2319374
-system.cpu0: completed 30000 read, 16827 write accesses @2322838
-system.cpu2: completed 30000 read, 16435 write accesses @2325373
-system.cpu7: completed 30000 read, 16664 write accesses @2329585
-system.cpu3: completed 40000 read, 22203 write accesses @3054702
-system.cpu1: completed 40000 read, 22271 write accesses @3064092
-system.cpu4: completed 40000 read, 22104 write accesses @3064313
-system.cpu0: completed 40000 read, 22287 write accesses @3078243
-system.cpu2: completed 40000 read, 22034 write accesses @3081341
-system.cpu6: completed 40000 read, 22288 write accesses @3087106
-system.cpu7: completed 40000 read, 22139 write accesses @3090483
-system.cpu5: completed 40000 read, 22456 write accesses @3115167
-system.cpu3: completed 50000 read, 27685 write accesses @3816500
-system.cpu0: completed 50000 read, 27819 write accesses @3832053
-system.cpu4: completed 50000 read, 27741 write accesses @3843043
-system.cpu6: completed 50000 read, 27737 write accesses @3846249
-system.cpu1: completed 50000 read, 27853 write accesses @3847483
-system.cpu2: completed 50000 read, 27474 write accesses @3847984
-system.cpu7: completed 50000 read, 27784 write accesses @3859638
-system.cpu5: completed 50000 read, 27985 write accesses @3881373
-system.cpu3: completed 60000 read, 33240 write accesses @4586843
-system.cpu0: completed 60000 read, 33283 write accesses @4597223
-system.cpu4: completed 60000 read, 33280 write accesses @4612495
-system.cpu6: completed 60000 read, 33333 write accesses @4617744
-system.cpu7: completed 60000 read, 33161 write accesses @4621422
-system.cpu1: completed 60000 read, 33491 write accesses @4624484
-system.cpu2: completed 60000 read, 33073 write accesses @4629780
-system.cpu5: completed 60000 read, 33544 write accesses @4644282
-system.cpu4: completed 70000 read, 38779 write accesses @5369467
-system.cpu0: completed 70000 read, 38963 write accesses @5378485
-system.cpu3: completed 70000 read, 38978 write accesses @5379251
-system.cpu6: completed 70000 read, 38932 write accesses @5401655
-system.cpu1: completed 70000 read, 39086 write accesses @5406571
-system.cpu2: completed 70000 read, 38592 write accesses @5406836
-system.cpu5: completed 70000 read, 39048 write accesses @5413732
-system.cpu7: completed 70000 read, 38996 write accesses @5416693
-system.cpu4: completed 80000 read, 44330 write accesses @6131353
-system.cpu3: completed 80000 read, 44590 write accesses @6147147
-system.cpu0: completed 80000 read, 44469 write accesses @6155707
-system.cpu2: completed 80000 read, 44132 write accesses @6161312
-system.cpu1: completed 80000 read, 44704 write accesses @6173967
-system.cpu6: completed 80000 read, 44443 write accesses @6181977
-system.cpu5: completed 80000 read, 44606 write accesses @6182931
-system.cpu7: completed 80000 read, 44440 write accesses @6186571
-system.cpu4: completed 90000 read, 49946 write accesses @6904148
-system.cpu3: completed 90000 read, 50248 write accesses @6916525
-system.cpu0: completed 90000 read, 49962 write accesses @6927054
-system.cpu2: completed 90000 read, 49754 write accesses @6935410
-system.cpu6: completed 90000 read, 49929 write accesses @6947145
-system.cpu1: completed 90000 read, 50385 write accesses @6951341
-system.cpu5: completed 90000 read, 50139 write accesses @6962538
-system.cpu7: completed 90000 read, 50280 write accesses @6972720
-system.cpu4: completed 100000 read, 55350 write accesses @7662866
+warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+system.cpu0: completed 10000 read, 5584 write accesses @762508
+system.cpu4: completed 10000 read, 5574 write accesses @764238
+system.cpu2: completed 10000 read, 5499 write accesses @766606
+system.cpu3: completed 10000 read, 5407 write accesses @769966
+system.cpu6: completed 10000 read, 5627 write accesses @771429
+system.cpu7: completed 10000 read, 5581 write accesses @773439
+system.cpu5: completed 10000 read, 5758 write accesses @783372
+system.cpu1: completed 10000 read, 5719 write accesses @784929
+system.cpu0: completed 20000 read, 11047 write accesses @1530543
+system.cpu7: completed 20000 read, 11107 write accesses @1533180
+system.cpu3: completed 20000 read, 10950 write accesses @1534683
+system.cpu6: completed 20000 read, 11194 write accesses @1535502
+system.cpu2: completed 20000 read, 11001 write accesses @1542405
+system.cpu5: completed 20000 read, 11318 write accesses @1544896
+system.cpu4: completed 20000 read, 11200 write accesses @1550910
+system.cpu1: completed 20000 read, 11300 write accesses @1556665
+system.cpu3: completed 30000 read, 16397 write accesses @2295657
+system.cpu2: completed 30000 read, 16594 write accesses @2305853
+system.cpu6: completed 30000 read, 16817 write accesses @2307161
+system.cpu0: completed 30000 read, 16652 write accesses @2307391
+system.cpu4: completed 30000 read, 16735 write accesses @2311189
+system.cpu7: completed 30000 read, 16751 write accesses @2314182
+system.cpu5: completed 30000 read, 16940 write accesses @2314755
+system.cpu1: completed 30000 read, 16881 write accesses @2333727
+system.cpu3: completed 40000 read, 22068 write accesses @3066226
+system.cpu4: completed 40000 read, 22266 write accesses @3071105
+system.cpu2: completed 40000 read, 22243 write accesses @3071593
+system.cpu5: completed 40000 read, 22338 write accesses @3072991
+system.cpu0: completed 40000 read, 22234 write accesses @3074112
+system.cpu6: completed 40000 read, 22357 write accesses @3078814
+system.cpu7: completed 40000 read, 22306 write accesses @3082874
+system.cpu1: completed 40000 read, 22431 write accesses @3111031
+system.cpu6: completed 50000 read, 27886 write accesses @3834085
+system.cpu3: completed 50000 read, 27514 write accesses @3834389
+system.cpu4: completed 50000 read, 27846 write accesses @3838179
+system.cpu2: completed 50000 read, 27730 write accesses @3839105
+system.cpu7: completed 50000 read, 27761 write accesses @3841365
+system.cpu5: completed 50000 read, 28029 write accesses @3855011
+system.cpu0: completed 50000 read, 27884 write accesses @3855221
+system.cpu1: completed 50000 read, 28029 write accesses @3872616
+system.cpu3: completed 60000 read, 32929 write accesses @4596558
+system.cpu4: completed 60000 read, 33251 write accesses @4604359
+system.cpu2: completed 60000 read, 33251 write accesses @4609070
+system.cpu6: completed 60000 read, 33602 write accesses @4611658
+system.cpu5: completed 60000 read, 33552 write accesses @4623475
+system.cpu7: completed 60000 read, 33412 write accesses @4626557
+system.cpu0: completed 60000 read, 33422 write accesses @4628259
+system.cpu1: completed 60000 read, 33486 write accesses @4645474
+system.cpu4: completed 70000 read, 38743 write accesses @5365823
+system.cpu3: completed 70000 read, 38597 write accesses @5375393
+system.cpu2: completed 70000 read, 38711 write accesses @5386294
+system.cpu6: completed 70000 read, 39263 write accesses @5390216
+system.cpu5: completed 70000 read, 39043 write accesses @5395080
+system.cpu7: completed 70000 read, 38983 write accesses @5398310
+system.cpu0: completed 70000 read, 38989 write accesses @5399705
+system.cpu1: completed 70000 read, 39150 write accesses @5425218
+system.cpu4: completed 80000 read, 44094 write accesses @6130494
+system.cpu3: completed 80000 read, 44230 write accesses @6148777
+system.cpu6: completed 80000 read, 44684 write accesses @6157555
+system.cpu5: completed 80000 read, 44551 write accesses @6161202
+system.cpu2: completed 80000 read, 44139 write accesses @6164119
+system.cpu0: completed 80000 read, 44724 write accesses @6175294
+system.cpu7: completed 80000 read, 44671 write accesses @6179013
+system.cpu1: completed 80000 read, 44749 write accesses @6192724
+system.cpu4: completed 90000 read, 49488 write accesses @6869712
+system.cpu6: completed 90000 read, 50150 write accesses @6920477
+system.cpu2: completed 90000 read, 49757 write accesses @6931420
+system.cpu3: completed 90000 read, 50041 write accesses @6935428
+system.cpu0: completed 90000 read, 50304 write accesses @6951052
+system.cpu5: completed 90000 read, 50260 write accesses @6951232
+system.cpu7: completed 90000 read, 50274 write accesses @6961816
+system.cpu1: completed 90000 read, 50419 write accesses @6968220
+system.cpu4: completed 100000 read, 54873 write accesses @7628407
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
index b3780e14b..8c46bff97 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
@@ -154,7 +154,6 @@ hot_lines=false
memory_size_bits=48
num_of_sequencers=1
phys_mem=Null
-random_seed=1234
randomization=true
[system.ruby.clk_domain]
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
index df3120f37..95197b990 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
@@ -154,7 +154,6 @@ hot_lines=false
memory_size_bits=48
num_of_sequencers=1
phys_mem=Null
-random_seed=1234
randomization=true
[system.ruby.clk_domain]
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
index 9c27c2144..fa6d969d1 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
@@ -154,7 +154,6 @@ hot_lines=false
memory_size_bits=48
num_of_sequencers=1
phys_mem=Null
-random_seed=1234
randomization=true
[system.ruby.clk_domain]
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
index 4dcf159bb..3e7f75c5f 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
@@ -154,7 +154,6 @@ hot_lines=false
memory_size_bits=48
num_of_sequencers=1
phys_mem=Null
-random_seed=1234
randomization=true
[system.ruby.clk_domain]
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
index 45a39afd9..a8da47f38 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
@@ -154,7 +154,6 @@ hot_lines=false
memory_size_bits=48
num_of_sequencers=1
phys_mem=Null
-random_seed=1234
randomization=true
[system.ruby.clk_domain]
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 19:54:35 +0000